CA2014407C - Apparatus and method for efficiently coupling digital signals to a communications medium in information packets - Google Patents
Apparatus and method for efficiently coupling digital signals to a communications medium in information packetsInfo
- Publication number
- CA2014407C CA2014407C CA002014407A CA2014407A CA2014407C CA 2014407 C CA2014407 C CA 2014407C CA 002014407 A CA002014407 A CA 002014407A CA 2014407 A CA2014407 A CA 2014407A CA 2014407 C CA2014407 C CA 2014407C
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0435—Details
- H04Q11/0471—Terminal access circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/40—Network security protocols
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/28—Timers or timing mechanisms used in protocols
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
- H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
- H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
- H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/214—Phase shifted impulses; Clock signals; Timing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/216—Code signals; Framing (not synchronizing)
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/296—Packet switching
Abstract
An improved Packet Assembler/Disassembler (PAD) optimizes the assembling of characters into packets for transmission over a packet network. The PAD is arranged to operably connect to and receive character asynchronous data from one or more terminal instruments operating in either a block transfer mode or an echoplexing mode. Characters received by the PAD from a terminal instrument operating in an echoplexing mode are forwarded with no PAD delay.
Characters received by the PAD from a terminal instrument operating in a block transfer mode are similarly forwarded with no PAD delay and in full packets withthe exception of the last few characters of each block of characters which only partially fill their respective packets. And these partially filled packets are quickly forwarded in a time period which just exceeds the period required for the reception of a single character at the rate of data reception from the terminal instrument.
Characters received by the PAD from a terminal instrument operating in a block transfer mode are similarly forwarded with no PAD delay and in full packets withthe exception of the last few characters of each block of characters which only partially fill their respective packets. And these partially filled packets are quickly forwarded in a time period which just exceeds the period required for the reception of a single character at the rate of data reception from the terminal instrument.
Description
Price-Richal~soll 3-2 ~- `~ 2014407 APPARATUS AND METHOD FOR EFFICIENTLY COUPLING
DIGITAL SIGNALS TO A COMMUNICATIONS MEDIUM
IN INFORMATION PA(~
R^cl~ ,md of the I~
1. Technical ~ield The invention relates generally to data tran~mi~sion and more particularly to a process for optimi7in~ the assembling of asynchronous characters into data packets for tran~mi~sion through a packet network.
Description of the Prior Art In accordance with recently developing needs to quiclcly access or provide info~ ation, there has been a proliferation of various terminal in~llull,enls installed in the business co-""~ni~y that receive and transmit data through a character asynchronous format. These instruments include among others: termin~
printers, personal coll~u~e,~ operating as t~rmin~l em~ tors~ and host colll~ule,~. A
15 co"",-"niç~3tions link for transferring the data between these termin~l instruments is generally provided by telephone transmission systems. These sy~lellls are increasing becoming digital in operation employing packet switching networks which use a bit synchronous format for tran~mi~sion of the data. Operation of a packet switching* network is such that messages longer than 1000 bits, for example, are typically 20 broken up into separate messages or "packets" before being tran~mitte l Thesepackets also contain some additional bits added for address and ~rlministrative purposes. And various adapter arrangements are used for pelrolll~ing the packet - assembly operation and interfacing the asynchronous te~nin~l insllulllellts to the packet switching network.
Transmissi-)n costs in a packet switching network are primarily a function of the number of packets transmitte~ through the network during each period of communication between terminal in~l- umenls. It is important in most operations, therefore, to minimi7~ the number of packets transmi~ l by the network by collec~ing as many characters as possible into each packet. But data throughput 30 and responsiveness are affected by the delay encountered by each character intransferring through the network and existing packeti_ing arrangements cause a major component of that delay.
Terminal instruments transmit asynchronous data in two basic modes, echoplexing and block transfer. Echoplexing occurs when a user types in a character 35 which is tran~mitte~ to and then is echoed back by the far-end terminal in~llu.llenl.
By way of example, the characters may be comm~n-l~ to a screen editor provided to manipulate an image on a screen. Block transfers are contained in a spurt of data Price-Riclla,~son 3-2 that occurs during a file transfer between termin~l in~llullællts or in ~ ons~ to a users comm~nd to a far-end termin~l in~llulllent to display a large amount of data.
There are conflicting packet assembly re~uihG.l,en~ for echoplexing and block ll~ulsr~`~. For echoplexing, the packet assembly operation should be as rapid S as possible to minimi7P delays for the user. Assembling the characters into the largest possible packets is of secondary interest because of the relatively slow rate that the characters are usually tr~n~mitted from the terminal instrument, e. g., a user typing. During echoplexing operation, the need for the user to get rapid feedback of character echo from the far-end termin~l in~Llumellt far outweighs the need to 10 assemble large p~c~ t~.
For block transfers, the packet assembly operation is such that the characters are assembled into the largest possible packets to minimi7P the number of packets and therefore costs. The packet assembly operation should also be as fast as possible, however, since the time it takes to send the last partially filled packet in a 15 data spurt is critical for operation with many file Iransfer protocols. In these protocols, a subsequent block transfer will not occur until the previous block transfer has been received and acknowledged by the far end terminal in~LIulllent.
For interfacing asynchronous terminal instruments or the like to a packet switching network, an adapter arrangement such as a Packet Assembler/Disassembler (PAD) is typically used to insure that all packets tr~n~mitted to the network will be in a specific format. The PAD serves as a concentrator that collects individual characters from one or more terminal insl,ul"ents and periodically outputs a properly fi)rm~tte~ packet containing the most recent character harvest. The International Telegraph and Telephone Con~lllt~tive Committee (CCIIT) Recommendations X.3,X.28 and X.29 define the CCITT PAD
interfaces. X.3 defines the PAD parameters, X.28 defines the termin~l-PAD
interface and X.29 defines the PAD-computer (data termin~l e~luipmellt) interface.
In accordance with the above indicated conflicting packet assembly requirements, the PAD must optimize the number of characters it accumlll~tes before 30 forwarding a packet, such as occurs when the associated terminal insl~ ulllent is operating in a block transfer mode. And it must also minimi7~ the delay caused by waiting for more characters, such as occurs when the associated terrninal instrument is operating in an echoplexing mode. In an effort to optimize the assembling of characters for each mode before forwarding a packet, an idle timer defined in 35 CCll~, Reco,.-.~-~-n~ tion X.3is currently employed in PADs. In operation, this timer provides a data forwarding time-out signal or is reset with each new character received. Thus after the reception of a character by the PAD, if no new characters Price-Richardson 3-2 are received before the idle timer expires, a partially ~led packet is rol~v~(led. If new characters are received by the PAD at a sp~cing less than the idle timer value, however, the idle timer is reset with each ch~a~ter received and folwar~ g occurs only upon the mtoeting of some other data rOl vvdr~illg con~ition such as when the 5 packet is full or upon receipt of a data fol ~Ivdlding character.
In accordance with CCITT Reco-----u n-l~tion X.3, the range in time for this idle timer may be set between 50 milli~econds and 12.75 seconds in 50 millisecon~ls intervals. This idle timer does not minimi7P the delay caused by the PAD waiting for more characters, particularly at the faster asynchronous data speeds.
10 Due to its inability to distinguish between the reception of an i~ol~ted character and the beginning of a data spurt, it waits a ,~ini..~ of 50 milli~econds before sending an isolated character. The idle timer is also unable to dct~llline when the end of the data spurt, or the end of a block transfer in the data spurt, occurs and again waits a miniml-m of 50 milli~econfl~ before folvvalding an unfill~d packet of characters.
It is there~ore desirable to have the asynchronous data received from associated terminal in~llu~enls quickly and efficiPntly assembled by an adapter arrangement, irrespective of whether a termin~l in~llumellt is operating in a block transfer mode or an echoplexing mode, without the noted disadvantages of existing adapter arrangements.
20 Summary of the Invention In accordance with the invention, there is provided an improved Packet Assembler/Disassembler (PAD) for assembling characters or groups of identifiabledigits into packets for tr~n~mi~sion over a co,-~ ni~tions m~ m such as a packetnetwork. The PAD optimizes the assembling of the characters when receiving 25 character asynchronous data from a termin:~l in~llu~ent operating in either a block transfer mode or an echoplexing mode. The hll~u~e~ ,nt to the PAD is obtained through employing a process or program that advantageously addresses the re(lui~ ents of data throughput and responsiveness by autom~tin~lly optimizing for each mode the arnount of data in each packet tr~n~mitte(l from the PAD to the 30 network. In accordance with the invention, a "minimllm" timer is used by the process in achieving the sm~llçst possible delay time before data is forwarded to the network. This minimum timer is variable and adjusted according to a rate of datareceived from the terminal instrument. In operation, the timer is adjusted to have a expiration period just greater than the tr?n~mi~sion time of a single character at the 35 rate of data received from the terminal instrument. If new characters are received by the PAD within a time period less than that provided by the minimllm timer, the timer is reset to its initial value with the reception of each new character.
Price-Richardson 3-2 In the operation of the process, a buffer n~~ ly associated with the PAD is periodically sc~nn~d in order to detect receipt of characters therein from an associated terminal insL.ulllcnt. In response to this interrogation, the process then makes a decision as to how to process these characters based upon certain 5 illustratively defined p~ ,tcls such as: the presence or absence of characters in the buffer memory at the time of the scan; a relative measure of the time interval for receipt of each character in the buffer memory; a time period over which the characters are received by the buffer memory; and the number of characters received by the buffer memory in the time period.
In accordance with the illustratively defined p~llelel~, the pr~!cessing of characters received into the buffer memory may be illustrated by a number of conditions. If in a first illustrative condition, a single character arrives in the buffer memory after a time interval greater than that provided by the timer, the process ~sum~.s that an isolated character has arrived and this single character is sent15 immP~ tely in a packet. If in a second illustrative condition, multiple characters arrive in the buffer memory after a time interval greater t-han that provided by the timer, the process ~csllmt~s that the data received is the start of a data spurt and these characters will not be packetized imm~i~tely. Rather, these characters and the ones that imm~li~tely follow are assembled into full packets before being sent to the20 packet network. If in the second illustrative condition, other characters do not follow immsfli~tely in sequence, the timer will expire with any gap or break in the receipt of data just greater than the tr~n~mission time of a single character from the termin~l instrument. Upon the expiration of the timer, these characters are sent immt tli~tely as a packet. If in a third illustrative condition, multiple characters arriving in the 25 buffer memory are being assembled into full packets and the timer expires, the process assumes that the gap or break in the reception of data represents the end of a block of data in a data spurt or, alternatively, the end of the data spurt. Once the timer expires in this or any of the other illustrative conditions, any data in the buffer memory is sent imm~ tely as a packet.
Thus operation of the process upon receipt of data from a terminal instrument operating in an echoplexing mode is such that characters are rolwalded in unfilled packets but with essenti~lly no PAD delay. Operation of the process upon receipt of data from a terminal instrument operating in a block transfer mode is such that characters are fol ~v~ded in full packets with the exception of a last partially 35 filled packet which reflects either the end of a data spurt or a block transfer in the data spurt. And this partially filled packet is forwarded in a time period which just exceeds the period required for the reception of one character from the terminal Price-Richa~soll 3-2 ~ 201~ lO7 in~llull~ellt. The process is applicable in any system that receives a~nc~unous data for packetizing and for tran~mitting over a packet network. It is easily employed in a packet assembly ~rrangçm.~nt disposed between an asynchronous termin~l and a packet l~lwolL
5 Brief Description of the D~ d~.;l.~
The invention and its mode of operation will be more clearly understood from the following det~il~l descli~lion when read with the appended drawing in which:
FIG. 1 is a functional system block l~leselltation of an asynchronous 10 termin~l instrument and data module arranged to interface with a packet switching network operative in accordance with the principles of the present invention;
FIG. 2 is a hardwal~; block diagram of the data module in accordance with the invention;
FIG. 3 is an illustration depicting data structures and data flow performed by the data module of FIG. 1 in accordance with the invention;
FIG. 4 depicts a flow chart illustrating some of the proces~ing pelrolllled by the data module of FIG. 1 in accordance with the invention; and FIG. 5iS a table showing time periods that are ~si~n~ble to a minimnm c~ timer in accordance with a rate of data being provided from the data t~rmin~l to the data module.
Throughout the drawing, the same elements when shown in more than one figure are desi~n~tecl by the same reference numerals.
Detailed Description Referring now to FIG. 1 of the drawing, in accordance with the present invention there is shown a functional block representation of an asynchronous terminal instrument 100 and a data module 200 arranged to interface data betweenthe terminal 100 and a tr~n~mi~ion system illustratively shown as a packet switching network 150. The data module 200 may also be a voice/data telephone and may be arranged to simlll~neously accommodate more than one terminal 30 instrument.
Data between the terminal instrument 100 and the data module 200 is provided in a character asynchronous format typically via an EIA RS-232-C
interface. And data to and from the packet switching network is provided in a bit synchronous format typically in packets of data. The data module 200 serves as an 35 interface adapter for these two data formats. The packet assembly/ lis~semblyoperation is conveniently performed by a PAD cont~in~l in the data module 200 which is illustratively shown as providing data to an interface for an Integrated Price-Richardson 3-2 Service Digital Network (ISDN) system. It is to be understood, however, that thedata module may be arranged to interface with other tr~n~mi~si~ n sy~ .s such asthose defined by the CCITT X.25 r,~,lwo.k access protocol. A number of such tr~n~mi~sion ~y~lell~s network architect lres are described by Andres S. Tanenbaum 5 in ComputerNetworks, Prentice-Hall, Inc., Englewood Cliffs, New Jersey, 1981, and by Michael J. Miller and Syed V. Ahamed in Digital Transmissions Systems and Networks, Computer Science Press, Inc., 1988. In this latter reference, a review of the ISDN concept and its potential services are also described.
Referring next to FIG. 2, there is shown a functional hal~lw~e block 10 diagram of circuitry suitable for providing the packet assembly/disasse.l-blyoperation performed by the data module 200. This ci~uilly comprises a processor 210 and associated random access memory (RAM) 300 and read only memory (ROM) 212. Processor 210 may be one of many processors such as the 8088 microprocessor available from Intel Corporation. Also included as part of this 15 ciluuilly is an universal asynchronous receiver tr~n~mitter (UART) 213 which provides an asynchronous int~ e for data coupled between the data module 200 and the terminal instrument 100 over line 101. An asynchronous interface suitable for use as UART 213 is described in U.S. patent 4,761,800 issued to G. Lese et al. on ~; August 2, 1988, this patent and this pending application being commonly assigned to 20 the same assignee. The circuit of FIG. 2 further includes a high level Data Link Control (HDLC) formatter 220 and an ISDN line interface 230. The HDLC
form~tt~r 220 receives the outgoing data from the processor 210 and formats thisdata into packets according to the protocol defined by CCll-l Recomm~ndation X.25. The packets of data are provided to the ISDN line interface 230 which 25 provides the a~pio~-iate header and signals for the data to be suitably interfaced into the ISDN system.
Referring next to FIG. 3. There is illustratively depicted the data structures and the flow of data in some of the ci-uuiLI.y of FIG. 2. Asynchronous data received by the UAP~T 213 is separated into 8-bit bytes. These bytes are placed into a 30 first-in first-out UART buffer memory 310 in RAM 300. In accordance with the invention a process or program, shown in a flow chart in FIG. 4 and fully described later herein, examines the bytes in this UART buffer memory 310 and decides whento transfer them to a packet buffer memory 320 where they are packetized. Once in the packet buffer memory, the process also decides when to send the packetized data 35 to the HDLC formatter 220 for formatting and tr~n~mitting to the ISDN system.
Price-Richaldsol~ 3-2 `:
For proper operation of the process, a "...ini....,."" timer 330 is provided by the ~lucessol 210 in order to pl~,pelly determine when to p~ ti7~ the data in the packet buffer ~l~moly 320. The timer 330 is set with a selçct~ble initial starting value and then allowed to count down over time to ~ero. A range of initial starting S values for the timer are illustratively shown in the table of FIG. 5. When thetimer 330 reaches _ero, it triggers an event in the flow chart, shown in FIG. 4, which is provided to the processor 210. A one-bit "was-idle" flag 340 is set by the timer 330 and also provides inroll~alion to the processor 210 as part of the flow chart shown in FIG. 4.
Referring now to FIG. 4, there is shown the flow chart illustrating the processing performed by the cir~;uil,y of FIG. 2. This processing operation will be more easily understood if the cil~uiL.y of FM. 2 and the table in FIG. 5 are both referenced in combination with this flow chart. This processing task is advantageously det~rmine-l by a process or program stored in ROM 212 and 15 processed by processor 210. The processing task is one of many performed by the processor 210 and is therefore entered approximately once every 1.5 milliceconds. A
1.5 millicecond cycling rate is sufficiently fast for satisfactorily interrogating the fastest character asynchronous data of 19.2 K bits per second expected to be received # from a terminal instrument. It is to be understood, however, that the process is 20 functional as is with data rates in excess of 19.2 K bits per second. If desired a faster cycling rate, and thereby a more precise interrogation, is easily achieved by reducing the number of tasks for the processor so that it may enter this task more frequently, or if the situation dictates, a de(1ir~tf d processor may be used.
The processing task is entered at decicion 401 where it checks for data 25 in the UART buffer memory 310. If there is no data in the UART buffer memory 310, the process advances to decision 402 where it checks to see if the timer 330 has expired. In accordance with existing conditions during the previous cycle, the timer may or may not have been reset at that time. If the timer has not expired and there is no data in the UART buffer memory, the processing task is 30 exited. If the timer has expired at ~lecicion 402, the procescing task advances to step 403 where the "was idle" flag 340 is set to true for reflecting that data was provided to the UART 213 by the terminal ins~.ulllellt 100 since the last sc~nning cycle. This is useful in that the next time the processing task is entered, the processor 212 will be able to determine that UART 213 has been idle for the 35 minimum time determined by the timer 330.
. . ; 3 . `.~
Price-Richardson 3-2 The plocessing task next advances to ~eçicion 404 where it ~lele~ nes whether the packet buffer memory 320 is empty. If this buffer memory is empty, the task is exited. If data is in the packet buffer ~ ly at this point, however, this reflects that no additional data has been received in the UART buffer 310 within the 5 n~ l". time det~rmin~d by the timer 330. The processing task thus advances to step 405 where the data in the packet buffer memory 320 is processed to add protocol headers and then sent to the HDLC form~tter 220. The task is then exited.
Referring once again to decision 401, if any data was found in the UART buffer memory 310, the processing task advances to step 406. In step 406, 10 the data in the UART buffer memory 310 is moved into the packet buffer memory 320. The processing task next advances to decision 407 which monitors theamount of data entering the packet buffer memory 320. If the packet buffer memory is found to be full (typically 128 bytes) by decision 407, the processing task advances to step 408 where the data in the buffer memory is processed as in step 404 15 and then sent to the HDLC formatter 220.
If the packet buffer memory was found not to be full at decision 407 the processing task advances to decision 409. At this decision, the "was idle" flag 340 is examined and the number of characters moved into the packet buffer memory 320 .~ from the UART buffer memory 310 also determined. If the "was idle" flag 340 is set 20 to true and if only one character was moved into the packet buffer memory, the processing task advances to step 408 where the single character is sent to the HDLC
fonn:~tter 220.
The goal of a very responsive system to receipt of a single character is thereby achieved. If only one character is received, as just illustrated, the process 25 assumes that it is an isolated character and will imm~ tely send out a packet with just that one character from the terminal in~ll Ulll~llt. This operation provides the desired high performance in an echoplexing environment where typically only one character is received in a time period that exceeds the time period provided by the timer 330. A single character may be received, by way of example, where a user is 30 typing on a keyboard. Each time the user types a character in the present system, that character is able to quickly go to the far-end tennin~l instrument and return so that the user is timely provided with the echo of the typed character on his or her screen.
Referring once again to decision 409, this decision provides an 35 indication that data was either received the last time this processing task was entered (the "was idle" flag 340 is set to false) or that there were two or more characters moved into the packet buffer memory since the last time the processing task was Price-Richardson 3-2 201~407 entered. The processor int~JIet~ this as one of three possible con~ition~: the start of a data spurt; the middle of the data spurt; or the end of either the data spurt or a block transfer in the data spurt. For each of these conditions, the proces~ing task advances to step 410 where the "was idle" flag is set to false when previously set at true, or S kept at false when previously set at false. From this step 410 the ~ ces,;~g task advances to step 411 where, if necessziry~ the timer 330 is reset according to the asynchronous data speed received from the tçrminz~l and shown in the table in FIG. 5. Operating under the above conditions, the processor thus waits for more data to acc-lm.llz-ite before sending the packet to the HDLC fo. . .~ 220.
The processing task, through decision 409, is thus able to quickly - clelel i.. ine the beginning of a data spurt or, alternatively, either the end of a data spurt or a block of data. Yet the processing task, through decision 409, also advantageously provides the desired minim~lm delay allowing time for additional characters to arrive during the middle of a data spurt which does not fill the packet 15 buffer, as determin~d by decision 407.
The need to efficiently respond to a spurt of data from the terminz~l insllu~ nt is important in achieving a responsive system. During reception of a spurt of data from the terminal insLlulllent, the received data should be packetiæd into the largest possible packets since a packet switching network essentiz~lly charges 20 as a function of how many packets are sent, not of how many characters are in each packet. The desired efficiency is achieved since the PAD packetiæs spurts of data into the largest possible packets for sending over the packet switching network.Depending upon such factors as the sarnpling rate of the processor and the data reception rate from a terminal in~LIument, however, a first received character in a 25 data spurt may be sent in a single packet. Any cost penalty associated with sending this single character is far outweighed by the automatic operation provided to the PAD. Any requirement to alter options in the PAD to accommodate data received from a terminzll instrument while operating in either an echoplexing mode or a block transfer rnode is elimin~tecl by employing the process of the present invention.File transfer efficiency is also improved during block transfers. File transfer from a terminal instrument generally comprises fixed size blocks of data which are ~nsmitted within a data spurt. The number of bytes in a block of data,however, rarely equals the number of bytes in a packet of data. Once a block of data has been sent by the termin~l instrument, it then waits for the far-end terminal35 in~llument to acknowledge receipt of that entire block of data before the next block of data is sent. In a long data spurt, filled packets will be transmitted quickly, but partially filled packets containing the last bytes of data in each block will always Price-Rich~ lsol~ 3-2 have some minim~l delay while the processor is waiting for additional data from the data spurt to fill these packets.
Use of the process of this invention avoids the delay traditionally associated with the near-end termin~l instrument waiting for the far-end termin~l S in~llulllent to acknowledge receipt of a block of data. Through the above processing task, the processor quickly recognizes a gap in the receipt of data from the termin~l in~lulllent and sends the data then accllm~ tG~l in the packet buffer memory. This allows the far-end terminal instrument to acknowledge sooner the receipt of thatblock of data. The file transfer is made even more efficient when the far-end 10 tçrmin~l in~llunlellt also employs the process of this invention in its packet assembly operation.
With further reference to the table shown in FM. 5, the period of time for the timer 330 is determined in accordance with the speed provided to the asynchronous inte.rf~-~e by an associated terminal instrument. A relatively long time 15 period is necessary for receipt of characters at very low speeds. Thus the timer is set for a time period that just exceeds a character receipt time period at each data reception rate and allowed to expire before deciding that the asynchronous interface is idle and that a packet of data should be sent. By way of example, with a datareception rate at 300 baud, the time to receive each character is approximately 33 20 milliseconds. At this data reception rate, the minimllm timer is set to expire at 40 milliseconds awaiting this amount of time before deciding that there has been a gap between characters appearing on the asynchronous interface. At very high speeds,however, the character receipt time period is proportionally very small and the timer is assigned a collGsponding shorter time that just exceeds a character receipt time 25 period for the selected data reception rate.
DIGITAL SIGNALS TO A COMMUNICATIONS MEDIUM
IN INFORMATION PA(~
R^cl~ ,md of the I~
1. Technical ~ield The invention relates generally to data tran~mi~sion and more particularly to a process for optimi7in~ the assembling of asynchronous characters into data packets for tran~mi~sion through a packet network.
Description of the Prior Art In accordance with recently developing needs to quiclcly access or provide info~ ation, there has been a proliferation of various terminal in~llull,enls installed in the business co-""~ni~y that receive and transmit data through a character asynchronous format. These instruments include among others: termin~
printers, personal coll~u~e,~ operating as t~rmin~l em~ tors~ and host colll~ule,~. A
15 co"",-"niç~3tions link for transferring the data between these termin~l instruments is generally provided by telephone transmission systems. These sy~lellls are increasing becoming digital in operation employing packet switching networks which use a bit synchronous format for tran~mi~sion of the data. Operation of a packet switching* network is such that messages longer than 1000 bits, for example, are typically 20 broken up into separate messages or "packets" before being tran~mitte l Thesepackets also contain some additional bits added for address and ~rlministrative purposes. And various adapter arrangements are used for pelrolll~ing the packet - assembly operation and interfacing the asynchronous te~nin~l insllulllellts to the packet switching network.
Transmissi-)n costs in a packet switching network are primarily a function of the number of packets transmitte~ through the network during each period of communication between terminal in~l- umenls. It is important in most operations, therefore, to minimi7~ the number of packets transmi~ l by the network by collec~ing as many characters as possible into each packet. But data throughput 30 and responsiveness are affected by the delay encountered by each character intransferring through the network and existing packeti_ing arrangements cause a major component of that delay.
Terminal instruments transmit asynchronous data in two basic modes, echoplexing and block transfer. Echoplexing occurs when a user types in a character 35 which is tran~mitte~ to and then is echoed back by the far-end terminal in~llu.llenl.
By way of example, the characters may be comm~n-l~ to a screen editor provided to manipulate an image on a screen. Block transfers are contained in a spurt of data Price-Riclla,~son 3-2 that occurs during a file transfer between termin~l in~llullællts or in ~ ons~ to a users comm~nd to a far-end termin~l in~llulllent to display a large amount of data.
There are conflicting packet assembly re~uihG.l,en~ for echoplexing and block ll~ulsr~`~. For echoplexing, the packet assembly operation should be as rapid S as possible to minimi7P delays for the user. Assembling the characters into the largest possible packets is of secondary interest because of the relatively slow rate that the characters are usually tr~n~mitted from the terminal instrument, e. g., a user typing. During echoplexing operation, the need for the user to get rapid feedback of character echo from the far-end termin~l in~Llumellt far outweighs the need to 10 assemble large p~c~ t~.
For block transfers, the packet assembly operation is such that the characters are assembled into the largest possible packets to minimi7P the number of packets and therefore costs. The packet assembly operation should also be as fast as possible, however, since the time it takes to send the last partially filled packet in a 15 data spurt is critical for operation with many file Iransfer protocols. In these protocols, a subsequent block transfer will not occur until the previous block transfer has been received and acknowledged by the far end terminal in~LIulllent.
For interfacing asynchronous terminal instruments or the like to a packet switching network, an adapter arrangement such as a Packet Assembler/Disassembler (PAD) is typically used to insure that all packets tr~n~mitted to the network will be in a specific format. The PAD serves as a concentrator that collects individual characters from one or more terminal insl,ul"ents and periodically outputs a properly fi)rm~tte~ packet containing the most recent character harvest. The International Telegraph and Telephone Con~lllt~tive Committee (CCIIT) Recommendations X.3,X.28 and X.29 define the CCITT PAD
interfaces. X.3 defines the PAD parameters, X.28 defines the termin~l-PAD
interface and X.29 defines the PAD-computer (data termin~l e~luipmellt) interface.
In accordance with the above indicated conflicting packet assembly requirements, the PAD must optimize the number of characters it accumlll~tes before 30 forwarding a packet, such as occurs when the associated terminal insl~ ulllent is operating in a block transfer mode. And it must also minimi7~ the delay caused by waiting for more characters, such as occurs when the associated terrninal instrument is operating in an echoplexing mode. In an effort to optimize the assembling of characters for each mode before forwarding a packet, an idle timer defined in 35 CCll~, Reco,.-.~-~-n~ tion X.3is currently employed in PADs. In operation, this timer provides a data forwarding time-out signal or is reset with each new character received. Thus after the reception of a character by the PAD, if no new characters Price-Richardson 3-2 are received before the idle timer expires, a partially ~led packet is rol~v~(led. If new characters are received by the PAD at a sp~cing less than the idle timer value, however, the idle timer is reset with each ch~a~ter received and folwar~ g occurs only upon the mtoeting of some other data rOl vvdr~illg con~ition such as when the 5 packet is full or upon receipt of a data fol ~Ivdlding character.
In accordance with CCITT Reco-----u n-l~tion X.3, the range in time for this idle timer may be set between 50 milli~econds and 12.75 seconds in 50 millisecon~ls intervals. This idle timer does not minimi7P the delay caused by the PAD waiting for more characters, particularly at the faster asynchronous data speeds.
10 Due to its inability to distinguish between the reception of an i~ol~ted character and the beginning of a data spurt, it waits a ,~ini..~ of 50 milli~econds before sending an isolated character. The idle timer is also unable to dct~llline when the end of the data spurt, or the end of a block transfer in the data spurt, occurs and again waits a miniml-m of 50 milli~econfl~ before folvvalding an unfill~d packet of characters.
It is there~ore desirable to have the asynchronous data received from associated terminal in~llu~enls quickly and efficiPntly assembled by an adapter arrangement, irrespective of whether a termin~l in~llumellt is operating in a block transfer mode or an echoplexing mode, without the noted disadvantages of existing adapter arrangements.
20 Summary of the Invention In accordance with the invention, there is provided an improved Packet Assembler/Disassembler (PAD) for assembling characters or groups of identifiabledigits into packets for tr~n~mi~sion over a co,-~ ni~tions m~ m such as a packetnetwork. The PAD optimizes the assembling of the characters when receiving 25 character asynchronous data from a termin:~l in~llu~ent operating in either a block transfer mode or an echoplexing mode. The hll~u~e~ ,nt to the PAD is obtained through employing a process or program that advantageously addresses the re(lui~ ents of data throughput and responsiveness by autom~tin~lly optimizing for each mode the arnount of data in each packet tr~n~mitte(l from the PAD to the 30 network. In accordance with the invention, a "minimllm" timer is used by the process in achieving the sm~llçst possible delay time before data is forwarded to the network. This minimum timer is variable and adjusted according to a rate of datareceived from the terminal instrument. In operation, the timer is adjusted to have a expiration period just greater than the tr?n~mi~sion time of a single character at the 35 rate of data received from the terminal instrument. If new characters are received by the PAD within a time period less than that provided by the minimllm timer, the timer is reset to its initial value with the reception of each new character.
Price-Richardson 3-2 In the operation of the process, a buffer n~~ ly associated with the PAD is periodically sc~nn~d in order to detect receipt of characters therein from an associated terminal insL.ulllcnt. In response to this interrogation, the process then makes a decision as to how to process these characters based upon certain 5 illustratively defined p~ ,tcls such as: the presence or absence of characters in the buffer memory at the time of the scan; a relative measure of the time interval for receipt of each character in the buffer memory; a time period over which the characters are received by the buffer memory; and the number of characters received by the buffer memory in the time period.
In accordance with the illustratively defined p~llelel~, the pr~!cessing of characters received into the buffer memory may be illustrated by a number of conditions. If in a first illustrative condition, a single character arrives in the buffer memory after a time interval greater than that provided by the timer, the process ~sum~.s that an isolated character has arrived and this single character is sent15 immP~ tely in a packet. If in a second illustrative condition, multiple characters arrive in the buffer memory after a time interval greater t-han that provided by the timer, the process ~csllmt~s that the data received is the start of a data spurt and these characters will not be packetized imm~i~tely. Rather, these characters and the ones that imm~li~tely follow are assembled into full packets before being sent to the20 packet network. If in the second illustrative condition, other characters do not follow immsfli~tely in sequence, the timer will expire with any gap or break in the receipt of data just greater than the tr~n~mission time of a single character from the termin~l instrument. Upon the expiration of the timer, these characters are sent immt tli~tely as a packet. If in a third illustrative condition, multiple characters arriving in the 25 buffer memory are being assembled into full packets and the timer expires, the process assumes that the gap or break in the reception of data represents the end of a block of data in a data spurt or, alternatively, the end of the data spurt. Once the timer expires in this or any of the other illustrative conditions, any data in the buffer memory is sent imm~ tely as a packet.
Thus operation of the process upon receipt of data from a terminal instrument operating in an echoplexing mode is such that characters are rolwalded in unfilled packets but with essenti~lly no PAD delay. Operation of the process upon receipt of data from a terminal instrument operating in a block transfer mode is such that characters are fol ~v~ded in full packets with the exception of a last partially 35 filled packet which reflects either the end of a data spurt or a block transfer in the data spurt. And this partially filled packet is forwarded in a time period which just exceeds the period required for the reception of one character from the terminal Price-Richa~soll 3-2 ~ 201~ lO7 in~llull~ellt. The process is applicable in any system that receives a~nc~unous data for packetizing and for tran~mitting over a packet network. It is easily employed in a packet assembly ~rrangçm.~nt disposed between an asynchronous termin~l and a packet l~lwolL
5 Brief Description of the D~ d~.;l.~
The invention and its mode of operation will be more clearly understood from the following det~il~l descli~lion when read with the appended drawing in which:
FIG. 1 is a functional system block l~leselltation of an asynchronous 10 termin~l instrument and data module arranged to interface with a packet switching network operative in accordance with the principles of the present invention;
FIG. 2 is a hardwal~; block diagram of the data module in accordance with the invention;
FIG. 3 is an illustration depicting data structures and data flow performed by the data module of FIG. 1 in accordance with the invention;
FIG. 4 depicts a flow chart illustrating some of the proces~ing pelrolllled by the data module of FIG. 1 in accordance with the invention; and FIG. 5iS a table showing time periods that are ~si~n~ble to a minimnm c~ timer in accordance with a rate of data being provided from the data t~rmin~l to the data module.
Throughout the drawing, the same elements when shown in more than one figure are desi~n~tecl by the same reference numerals.
Detailed Description Referring now to FIG. 1 of the drawing, in accordance with the present invention there is shown a functional block representation of an asynchronous terminal instrument 100 and a data module 200 arranged to interface data betweenthe terminal 100 and a tr~n~mi~ion system illustratively shown as a packet switching network 150. The data module 200 may also be a voice/data telephone and may be arranged to simlll~neously accommodate more than one terminal 30 instrument.
Data between the terminal instrument 100 and the data module 200 is provided in a character asynchronous format typically via an EIA RS-232-C
interface. And data to and from the packet switching network is provided in a bit synchronous format typically in packets of data. The data module 200 serves as an 35 interface adapter for these two data formats. The packet assembly/ lis~semblyoperation is conveniently performed by a PAD cont~in~l in the data module 200 which is illustratively shown as providing data to an interface for an Integrated Price-Richardson 3-2 Service Digital Network (ISDN) system. It is to be understood, however, that thedata module may be arranged to interface with other tr~n~mi~si~ n sy~ .s such asthose defined by the CCITT X.25 r,~,lwo.k access protocol. A number of such tr~n~mi~sion ~y~lell~s network architect lres are described by Andres S. Tanenbaum 5 in ComputerNetworks, Prentice-Hall, Inc., Englewood Cliffs, New Jersey, 1981, and by Michael J. Miller and Syed V. Ahamed in Digital Transmissions Systems and Networks, Computer Science Press, Inc., 1988. In this latter reference, a review of the ISDN concept and its potential services are also described.
Referring next to FIG. 2, there is shown a functional hal~lw~e block 10 diagram of circuitry suitable for providing the packet assembly/disasse.l-blyoperation performed by the data module 200. This ci~uilly comprises a processor 210 and associated random access memory (RAM) 300 and read only memory (ROM) 212. Processor 210 may be one of many processors such as the 8088 microprocessor available from Intel Corporation. Also included as part of this 15 ciluuilly is an universal asynchronous receiver tr~n~mitter (UART) 213 which provides an asynchronous int~ e for data coupled between the data module 200 and the terminal instrument 100 over line 101. An asynchronous interface suitable for use as UART 213 is described in U.S. patent 4,761,800 issued to G. Lese et al. on ~; August 2, 1988, this patent and this pending application being commonly assigned to 20 the same assignee. The circuit of FIG. 2 further includes a high level Data Link Control (HDLC) formatter 220 and an ISDN line interface 230. The HDLC
form~tt~r 220 receives the outgoing data from the processor 210 and formats thisdata into packets according to the protocol defined by CCll-l Recomm~ndation X.25. The packets of data are provided to the ISDN line interface 230 which 25 provides the a~pio~-iate header and signals for the data to be suitably interfaced into the ISDN system.
Referring next to FIG. 3. There is illustratively depicted the data structures and the flow of data in some of the ci-uuiLI.y of FIG. 2. Asynchronous data received by the UAP~T 213 is separated into 8-bit bytes. These bytes are placed into a 30 first-in first-out UART buffer memory 310 in RAM 300. In accordance with the invention a process or program, shown in a flow chart in FIG. 4 and fully described later herein, examines the bytes in this UART buffer memory 310 and decides whento transfer them to a packet buffer memory 320 where they are packetized. Once in the packet buffer memory, the process also decides when to send the packetized data 35 to the HDLC formatter 220 for formatting and tr~n~mitting to the ISDN system.
Price-Richaldsol~ 3-2 `:
For proper operation of the process, a "...ini....,."" timer 330 is provided by the ~lucessol 210 in order to pl~,pelly determine when to p~ ti7~ the data in the packet buffer ~l~moly 320. The timer 330 is set with a selçct~ble initial starting value and then allowed to count down over time to ~ero. A range of initial starting S values for the timer are illustratively shown in the table of FIG. 5. When thetimer 330 reaches _ero, it triggers an event in the flow chart, shown in FIG. 4, which is provided to the processor 210. A one-bit "was-idle" flag 340 is set by the timer 330 and also provides inroll~alion to the processor 210 as part of the flow chart shown in FIG. 4.
Referring now to FIG. 4, there is shown the flow chart illustrating the processing performed by the cir~;uil,y of FIG. 2. This processing operation will be more easily understood if the cil~uiL.y of FM. 2 and the table in FIG. 5 are both referenced in combination with this flow chart. This processing task is advantageously det~rmine-l by a process or program stored in ROM 212 and 15 processed by processor 210. The processing task is one of many performed by the processor 210 and is therefore entered approximately once every 1.5 milliceconds. A
1.5 millicecond cycling rate is sufficiently fast for satisfactorily interrogating the fastest character asynchronous data of 19.2 K bits per second expected to be received # from a terminal instrument. It is to be understood, however, that the process is 20 functional as is with data rates in excess of 19.2 K bits per second. If desired a faster cycling rate, and thereby a more precise interrogation, is easily achieved by reducing the number of tasks for the processor so that it may enter this task more frequently, or if the situation dictates, a de(1ir~tf d processor may be used.
The processing task is entered at decicion 401 where it checks for data 25 in the UART buffer memory 310. If there is no data in the UART buffer memory 310, the process advances to decision 402 where it checks to see if the timer 330 has expired. In accordance with existing conditions during the previous cycle, the timer may or may not have been reset at that time. If the timer has not expired and there is no data in the UART buffer memory, the processing task is 30 exited. If the timer has expired at ~lecicion 402, the procescing task advances to step 403 where the "was idle" flag 340 is set to true for reflecting that data was provided to the UART 213 by the terminal ins~.ulllellt 100 since the last sc~nning cycle. This is useful in that the next time the processing task is entered, the processor 212 will be able to determine that UART 213 has been idle for the 35 minimum time determined by the timer 330.
. . ; 3 . `.~
Price-Richardson 3-2 The plocessing task next advances to ~eçicion 404 where it ~lele~ nes whether the packet buffer memory 320 is empty. If this buffer memory is empty, the task is exited. If data is in the packet buffer ~ ly at this point, however, this reflects that no additional data has been received in the UART buffer 310 within the 5 n~ l". time det~rmin~d by the timer 330. The processing task thus advances to step 405 where the data in the packet buffer memory 320 is processed to add protocol headers and then sent to the HDLC form~tter 220. The task is then exited.
Referring once again to decision 401, if any data was found in the UART buffer memory 310, the processing task advances to step 406. In step 406, 10 the data in the UART buffer memory 310 is moved into the packet buffer memory 320. The processing task next advances to decision 407 which monitors theamount of data entering the packet buffer memory 320. If the packet buffer memory is found to be full (typically 128 bytes) by decision 407, the processing task advances to step 408 where the data in the buffer memory is processed as in step 404 15 and then sent to the HDLC formatter 220.
If the packet buffer memory was found not to be full at decision 407 the processing task advances to decision 409. At this decision, the "was idle" flag 340 is examined and the number of characters moved into the packet buffer memory 320 .~ from the UART buffer memory 310 also determined. If the "was idle" flag 340 is set 20 to true and if only one character was moved into the packet buffer memory, the processing task advances to step 408 where the single character is sent to the HDLC
fonn:~tter 220.
The goal of a very responsive system to receipt of a single character is thereby achieved. If only one character is received, as just illustrated, the process 25 assumes that it is an isolated character and will imm~ tely send out a packet with just that one character from the terminal in~ll Ulll~llt. This operation provides the desired high performance in an echoplexing environment where typically only one character is received in a time period that exceeds the time period provided by the timer 330. A single character may be received, by way of example, where a user is 30 typing on a keyboard. Each time the user types a character in the present system, that character is able to quickly go to the far-end tennin~l instrument and return so that the user is timely provided with the echo of the typed character on his or her screen.
Referring once again to decision 409, this decision provides an 35 indication that data was either received the last time this processing task was entered (the "was idle" flag 340 is set to false) or that there were two or more characters moved into the packet buffer memory since the last time the processing task was Price-Richardson 3-2 201~407 entered. The processor int~JIet~ this as one of three possible con~ition~: the start of a data spurt; the middle of the data spurt; or the end of either the data spurt or a block transfer in the data spurt. For each of these conditions, the proces~ing task advances to step 410 where the "was idle" flag is set to false when previously set at true, or S kept at false when previously set at false. From this step 410 the ~ ces,;~g task advances to step 411 where, if necessziry~ the timer 330 is reset according to the asynchronous data speed received from the tçrminz~l and shown in the table in FIG. 5. Operating under the above conditions, the processor thus waits for more data to acc-lm.llz-ite before sending the packet to the HDLC fo. . .~ 220.
The processing task, through decision 409, is thus able to quickly - clelel i.. ine the beginning of a data spurt or, alternatively, either the end of a data spurt or a block of data. Yet the processing task, through decision 409, also advantageously provides the desired minim~lm delay allowing time for additional characters to arrive during the middle of a data spurt which does not fill the packet 15 buffer, as determin~d by decision 407.
The need to efficiently respond to a spurt of data from the terminz~l insllu~ nt is important in achieving a responsive system. During reception of a spurt of data from the terminal insLlulllent, the received data should be packetiæd into the largest possible packets since a packet switching network essentiz~lly charges 20 as a function of how many packets are sent, not of how many characters are in each packet. The desired efficiency is achieved since the PAD packetiæs spurts of data into the largest possible packets for sending over the packet switching network.Depending upon such factors as the sarnpling rate of the processor and the data reception rate from a terminal in~LIument, however, a first received character in a 25 data spurt may be sent in a single packet. Any cost penalty associated with sending this single character is far outweighed by the automatic operation provided to the PAD. Any requirement to alter options in the PAD to accommodate data received from a terminzll instrument while operating in either an echoplexing mode or a block transfer rnode is elimin~tecl by employing the process of the present invention.File transfer efficiency is also improved during block transfers. File transfer from a terminal instrument generally comprises fixed size blocks of data which are ~nsmitted within a data spurt. The number of bytes in a block of data,however, rarely equals the number of bytes in a packet of data. Once a block of data has been sent by the termin~l instrument, it then waits for the far-end terminal35 in~llument to acknowledge receipt of that entire block of data before the next block of data is sent. In a long data spurt, filled packets will be transmitted quickly, but partially filled packets containing the last bytes of data in each block will always Price-Rich~ lsol~ 3-2 have some minim~l delay while the processor is waiting for additional data from the data spurt to fill these packets.
Use of the process of this invention avoids the delay traditionally associated with the near-end termin~l instrument waiting for the far-end termin~l S in~llulllent to acknowledge receipt of a block of data. Through the above processing task, the processor quickly recognizes a gap in the receipt of data from the termin~l in~lulllent and sends the data then accllm~ tG~l in the packet buffer memory. This allows the far-end terminal instrument to acknowledge sooner the receipt of thatblock of data. The file transfer is made even more efficient when the far-end 10 tçrmin~l in~llunlellt also employs the process of this invention in its packet assembly operation.
With further reference to the table shown in FM. 5, the period of time for the timer 330 is determined in accordance with the speed provided to the asynchronous inte.rf~-~e by an associated terminal instrument. A relatively long time 15 period is necessary for receipt of characters at very low speeds. Thus the timer is set for a time period that just exceeds a character receipt time period at each data reception rate and allowed to expire before deciding that the asynchronous interface is idle and that a packet of data should be sent. By way of example, with a datareception rate at 300 baud, the time to receive each character is approximately 33 20 milliseconds. At this data reception rate, the minimllm timer is set to expire at 40 milliseconds awaiting this amount of time before deciding that there has been a gap between characters appearing on the asynchronous interface. At very high speeds,however, the character receipt time period is proportionally very small and the timer is assigned a collGsponding shorter time that just exceeds a character receipt time 25 period for the selected data reception rate.
Claims (25)
1. An apparatus for coupling digital signals to a communications medium in information packets, the apparatus comprising:
signal receiving means for receiving data from an asynchronous signal source, the data being arranged in a plurality of groups of identifiable digits;
processor means for converting the asynchronous signal data from the signal receiving means into information packets;
buffer memory means for storing data from the asynchronous signal source, the data to the buffer memory means being provided by the signal receiving means;
timing means for comparing the time period for receipt of each group of identifiable digits of data into the buffer memory means with a predetermined time period;
sampling means for periodically interrogating the buffer memory means for data stored therein;
counting means for counting the number of groups of identifiable digits of data provided to the buffer memory means between sampling periods provided by the sampling means; and the sampling means being responsive to both the timing means and the counting means for determining the time for receipt and the number of groups of identifiable digits of data stored in the buffer memory means between sampling periods, the data in the buffer memory means being coupled by the processor means to the communications medium in an information packet when both a) the time period for receipt of a group of identifiable digits of data exceeds the predetermined time period and b) only one group of identifiable digits of data is stored in the buffer memory means.
signal receiving means for receiving data from an asynchronous signal source, the data being arranged in a plurality of groups of identifiable digits;
processor means for converting the asynchronous signal data from the signal receiving means into information packets;
buffer memory means for storing data from the asynchronous signal source, the data to the buffer memory means being provided by the signal receiving means;
timing means for comparing the time period for receipt of each group of identifiable digits of data into the buffer memory means with a predetermined time period;
sampling means for periodically interrogating the buffer memory means for data stored therein;
counting means for counting the number of groups of identifiable digits of data provided to the buffer memory means between sampling periods provided by the sampling means; and the sampling means being responsive to both the timing means and the counting means for determining the time for receipt and the number of groups of identifiable digits of data stored in the buffer memory means between sampling periods, the data in the buffer memory means being coupled by the processor means to the communications medium in an information packet when both a) the time period for receipt of a group of identifiable digits of data exceeds the predetermined time period and b) only one group of identifiable digits of data is stored in the buffer memory means.
2. The apparatus as in claim 1 wherein the data in the buffer memory means is retained in the buffer memory means until the next sampling period in response to the receipt of multiple groups of identifiable digits of data in the buffer memory means.
3. The apparatus as in claim 1 wherein subsequently received data in the buffer memory means is coupled to the communications medium in an information packet when said one group of identifiable digits of data is stored in the buffer memory means and a variable time period, occurring prior to the receipt of said one group of identifiable digits of data, exceeds the predetermined time period.
4. The apparatus of claim 3 further including means for determining the predetermined time period, the signal receiving means being configurable for measuring a rate of data reception from the asynchronous signal source, the processor means in response to the signal receiving means adjusting the predetermined timeperiod to be proportional to the time period for receipt of said one group of identifiable digits of data.
5. The apparatus of claim 4 wherein the processor means proportionally adjusts the predetermined time period in a manner to just exceed the time required for one group of identifiable digits of data to be received from the asynchronous signal source and provided to the buffer memory means, said data being received at the measured rate of data reception from the asynchronous signal source.
6. The apparatus of claim 5 wherein the predetermined time period is provided by an adjustable count down timer reset to its initial starting value upon the receipt of each group of identifiable digits of data provided to the buffer memory means.
7. The apparatus as in claim 6 wherein the buffer memory means comprises a first and second buffer memory, the first buffer memory receiving the data from the signal receiving means and the second buffer memory receiving the data from the first buffer memory for processing by the processor means.
8. The apparatus as in claim 5 wherein the plurality of groups of identifiable digits are digital representations of characters.
9. The apparatus as in claim 5 wherein the communications medium is a packet switching network.
10. The apparatus as in claim 9 wherein the processor means further includes means for formatting and interfacing the information packets to the packet switching network.
11. An apparatus for coupling digital signals to a communications medium in information packets, the apparatus comprising:
signal receiving means for receiving data from an asynchronous signal source, the data being arranged in a plurality of groups of identifiable digits;
processor means for converting the data from the signal receiving means into information packets;
buffer memory means for storing data from the asynchronous signal source, the data to the buffer memory means being provided by the signal receiving means;
timing means for comparing the time for receipt of each group of identifiable digits of data into the buffer memory means with a predetermined time period;
sampling means for periodically interrogating the buffer memory means for data stored therein;
counting means for counting the number of groups of identifiable digits of data provided to the buffer memory means between sampling periods provided by the sampling means; and the sampling means being responsive to both the timing means and the counting means for periodically determining the time for receipt and the number of groups of identifiable digits of data stored in the buffer memory means between sampling periods, the data in the buffer memory means being coupled by the processor means to the communications medium in an information packet when the time period for receipt of a group of identifiable digits of data exceeds the predetermined time period after the receipt of multiple groups of identifiable digits of data in the buffer memory means.
signal receiving means for receiving data from an asynchronous signal source, the data being arranged in a plurality of groups of identifiable digits;
processor means for converting the data from the signal receiving means into information packets;
buffer memory means for storing data from the asynchronous signal source, the data to the buffer memory means being provided by the signal receiving means;
timing means for comparing the time for receipt of each group of identifiable digits of data into the buffer memory means with a predetermined time period;
sampling means for periodically interrogating the buffer memory means for data stored therein;
counting means for counting the number of groups of identifiable digits of data provided to the buffer memory means between sampling periods provided by the sampling means; and the sampling means being responsive to both the timing means and the counting means for periodically determining the time for receipt and the number of groups of identifiable digits of data stored in the buffer memory means between sampling periods, the data in the buffer memory means being coupled by the processor means to the communications medium in an information packet when the time period for receipt of a group of identifiable digits of data exceeds the predetermined time period after the receipt of multiple groups of identifiable digits of data in the buffer memory means.
12. The apparatus of claim 11 further including means for determining the predetermined time period, the signal receiving means being configurable for measuring a rate of data reception from the asynchronous signal source, the processor means in response to the signal receiving means adjusting the predetermined timeperiod to be proportional to the time period for receipt of said one group of identifiable digits of data.
13. The apparatus of claim 12 wherein the processor means proportionally adjusts the predetermined time period in a manner to just exceed the time required for one group of identifiable digits of data to be received from the asynchronous signal source and provided to the buffer memory means, said data being received at the measured rate of data reception from the asynchronous signal source.
14. The apparatus of claim 13 wherein the predetermined time period is provided by an adjustable count down timer reset to its initial starting value upon the receipt of each group of identifiable digits of data provided to the buffer memory means.
15. The apparatus as in claim 14 wherein the plurality of groups of identifiable digits are digital representations of characters.
16. A method of processing data for transmission over a packet network, the method comprising the steps of:
receiving data from an asynchronous signal source, the data being arranged in a plurality of groups of identifiable digits;
storing said data from the asynchronous signal source in a buffer memory;
comparing the time period for receipt of each group of identifiable digits of data into the buffer memory with a predetermined time period;
sampling periodically the buffer memory for interrogating the data stored therein;
counting the number of groups of identifiable digits of data provided to the buffer memory between sampling periods provided by the sampling step;
determining the time period for receipt and the number of groups identifiable digits of data stored in the buffer memory between sample periods;
converting the data into information packets; and transmitting the data in the buffer memory to the packet network in an information packet when both the time for receipt of a group of identifiable digits of data exceeds the predetermined time period and only one group of identifiable digits of data is stored in the buffer memory.
receiving data from an asynchronous signal source, the data being arranged in a plurality of groups of identifiable digits;
storing said data from the asynchronous signal source in a buffer memory;
comparing the time period for receipt of each group of identifiable digits of data into the buffer memory with a predetermined time period;
sampling periodically the buffer memory for interrogating the data stored therein;
counting the number of groups of identifiable digits of data provided to the buffer memory between sampling periods provided by the sampling step;
determining the time period for receipt and the number of groups identifiable digits of data stored in the buffer memory between sample periods;
converting the data into information packets; and transmitting the data in the buffer memory to the packet network in an information packet when both the time for receipt of a group of identifiable digits of data exceeds the predetermined time period and only one group of identifiable digits of data is stored in the buffer memory.
17. The method of processing data for transmission over a packet network as in claim 16 wherein the transmitting step further includes the step of retaining the data in the buffer memory until the next sampling period in response to receipt of multiple groups of identifiable digits of data in the buffer memory.
18. The method of processing data for transmission over a packet network as in claim 16 wherein the transmitting step further includes the step of transmittingsubsequently received data in the buffer memory to the packet network in an information packet when said one group of identifiable digits of data is stored in the buffer memory and a variable time period, occurring prior to the receipt of said one group of identifiable digits of data, exceeds the predetermined time period.
19. The method of processing data for transmission over a packet network as in claim 18 further comprising the step of obtaining the predetermined time period, this step including the steps of measuring a rate of data reception from the asynchronous signal source and adjusting the predetermined time period to be proportional to the time period for receipt of said one group of identifiable digits of data.
20. The method of processing data for transmission over a packet network as in claim 19 wherein the step of proportionally adjusting the predetermined time period comprises adjusting said period in a manner to just exceed the time required for one group of identifiable digits of data to be received from the asynchronous signal source and provided to the buffer memory, said data being received at the measured rate of data reception from the asynchronous signal source.
21. A method of processing data for transmission over a packet network, the method comprising the steps of:
receiving data from an asynchronous signal source, the data being arranged in a plurality of groups of identifiable digits;
storing data from the asynchronous signal source in a buffer memory;
comparing the time period for receipt of each group of identifiable digits of data into the buffer memory with a predetermined time period;
sampling periodically the buffer memory for interrogating the data stored therein;
counting the number of groups of identifiable digits of data provided to the buffer memory between sampling periods provided by the sampling step;
determining the time period for receipt and the number of groups of identifiable digits of data stored in the buffer memory between sample periods;
converting the data into information packets; and transmitting the data in the buffer memory to the packet network in an information packet when the time period for receipt of a group of identifiable digits exceeds the predetermined time period after the receipt of multiple groups of identifiable digits of data in the buffer memory.
receiving data from an asynchronous signal source, the data being arranged in a plurality of groups of identifiable digits;
storing data from the asynchronous signal source in a buffer memory;
comparing the time period for receipt of each group of identifiable digits of data into the buffer memory with a predetermined time period;
sampling periodically the buffer memory for interrogating the data stored therein;
counting the number of groups of identifiable digits of data provided to the buffer memory between sampling periods provided by the sampling step;
determining the time period for receipt and the number of groups of identifiable digits of data stored in the buffer memory between sample periods;
converting the data into information packets; and transmitting the data in the buffer memory to the packet network in an information packet when the time period for receipt of a group of identifiable digits exceeds the predetermined time period after the receipt of multiple groups of identifiable digits of data in the buffer memory.
22. An apparatus for coupling data to a communications medium in information packets, the apparatus comprising:
means for receiving data from an asynchronous signal source, the data being arranged in a plurality of groups of identifiable digits;
means for determining from a range of time periods a first time period for receipt of each group of identifiable digits received from the asynchronous signal source;
means for determining a predetermined time period from the first time period, the predetermined time period being varied as a function of the determined first time period so that it just exceeds the first time period; and means for coupling to the communications medium an information packet containing one group of identifiable digits when the group of identifiable digits received from the asynchronous signal source is preceded by a time period at least equal to the predetermined time period.
means for receiving data from an asynchronous signal source, the data being arranged in a plurality of groups of identifiable digits;
means for determining from a range of time periods a first time period for receipt of each group of identifiable digits received from the asynchronous signal source;
means for determining a predetermined time period from the first time period, the predetermined time period being varied as a function of the determined first time period so that it just exceeds the first time period; and means for coupling to the communications medium an information packet containing one group of identifiable digits when the group of identifiable digits received from the asynchronous signal source is preceded by a time period at least equal to the predetermined time period.
23. An apparatus for coupling data to a communications medium in information packets, the apparatus comprising:
means for receiving data from an asynchronous signal source, the data being arranged in a plurality of groups of identifiable digits; and means for determining a time period for receipt of each one of multiple groups of identifiable digits received from the data receiving means, and for coupling to the communications medium an information packet containing the multiple groups of identifiable digits when the time period for receipt of one group of identifiable digits exceeds a predetermined time period after the receipt of the multiple groups of identifiable digits from the asynchronous signal source, said predetermined time period being varied as a function of the received time period detected by said determining means so that it just exceeds said received time period.
means for receiving data from an asynchronous signal source, the data being arranged in a plurality of groups of identifiable digits; and means for determining a time period for receipt of each one of multiple groups of identifiable digits received from the data receiving means, and for coupling to the communications medium an information packet containing the multiple groups of identifiable digits when the time period for receipt of one group of identifiable digits exceeds a predetermined time period after the receipt of the multiple groups of identifiable digits from the asynchronous signal source, said predetermined time period being varied as a function of the received time period detected by said determining means so that it just exceeds said received time period.
24. A method of processing data for transmission over a packet network, the method comprising the steps of:
receiving data from an asynchronous signal source, the data being arranged in a plurality of groups of identifiable digits;
determining from a range of time periods a first time period for receipt of eachgroup of identifiable digits received from the asynchronous signal source;
determining a predetermined time period from the first time period, the predetermined time period being varied as a function of the determined first time period so that it just exceeds the first time period; and coupling to the communications medium an information packet containing one group of identified digits when the group of identifiable digits received from the asynchronous signal source is preceded by a time period at least equal to the predetermined time period.
receiving data from an asynchronous signal source, the data being arranged in a plurality of groups of identifiable digits;
determining from a range of time periods a first time period for receipt of eachgroup of identifiable digits received from the asynchronous signal source;
determining a predetermined time period from the first time period, the predetermined time period being varied as a function of the determined first time period so that it just exceeds the first time period; and coupling to the communications medium an information packet containing one group of identified digits when the group of identifiable digits received from the asynchronous signal source is preceded by a time period at least equal to the predetermined time period.
25. A method of processing data for transmission over a packet network, the method comprising the steps of:
receiving data from an asynchronous signal source, the data being arranged in a plurality of groups of identifiable digits;
determining a time period for receipt of each one of multiple groups of identifiable digits received from the data receiving means, and for coupling to the communications medium an information packet containing the multiple groups of identifiable digits when the time period for receipt of one group of identifiable digits exceeds a predetermined time period after the receipt of the multiple groups of identifiable digits from the asynchronous signal source, said predetermined time period being varied as a function of the received time period detected by said determining means so that it just exceeds said received time period.
receiving data from an asynchronous signal source, the data being arranged in a plurality of groups of identifiable digits;
determining a time period for receipt of each one of multiple groups of identifiable digits received from the data receiving means, and for coupling to the communications medium an information packet containing the multiple groups of identifiable digits when the time period for receipt of one group of identifiable digits exceeds a predetermined time period after the receipt of the multiple groups of identifiable digits from the asynchronous signal source, said predetermined time period being varied as a function of the received time period detected by said determining means so that it just exceeds said received time period.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/345,912 US5056088A (en) | 1989-05-01 | 1989-05-01 | Apparatus and method for efficiently coupling digital signals to a communications medium in information packets |
| US345,912 | 1989-05-01 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2014407A1 CA2014407A1 (en) | 1990-11-01 |
| CA2014407C true CA2014407C (en) | 1996-11-12 |
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|---|---|---|---|
| CA002014407A Expired - Lifetime CA2014407C (en) | 1989-05-01 | 1990-04-11 | Apparatus and method for efficiently coupling digital signals to a communications medium in information packets |
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| US (1) | US5056088A (en) |
| EP (1) | EP0396309B1 (en) |
| JP (1) | JP2588488B2 (en) |
| KR (1) | KR0149860B1 (en) |
| CA (1) | CA2014407C (en) |
| DE (1) | DE69022278T2 (en) |
| HK (1) | HK78296A (en) |
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| US5274762A (en) * | 1989-12-15 | 1993-12-28 | Ncr Corporation | Method for high speed data transfer |
| JPH03214841A (en) * | 1990-01-19 | 1991-09-20 | Fujitsu Ltd | Modem pool system dependent upon packet communication procedure |
| JPH0828756B2 (en) * | 1990-04-17 | 1996-03-21 | ヤマハ株式会社 | Data transfer method |
| JP2556923B2 (en) * | 1990-05-10 | 1996-11-27 | 三菱電機株式会社 | Packet data amount control method, packet transmission method, and data transmission device |
| JPH0490645A (en) * | 1990-08-03 | 1992-03-24 | Mitsubishi Electric Corp | Voice packet assembly/diassembly equipment |
| FR2674650A1 (en) * | 1991-03-29 | 1992-10-02 | Albertin Pierre | Process for constructing a fault-tolerant X 25 packet switch which can be expanded in service and has parallel MIMD processors |
| US5463623A (en) * | 1991-07-31 | 1995-10-31 | At&T Ipm Corp. | Integrated wireless telecommunication and local area network system |
| JP3037476B2 (en) * | 1991-08-28 | 2000-04-24 | 富士通株式会社 | ATM cell assembly / disassembly method |
| US5384770A (en) * | 1992-05-08 | 1995-01-24 | Hayes Microcomputer Products, Inc. | Packet assembler |
| US5631935A (en) * | 1993-05-06 | 1997-05-20 | Run-Rad Unlimited Networking, Ltd. | Method and apparatus for governing information transfer using an efficient transport protocol |
| WO1995026089A1 (en) * | 1994-03-18 | 1995-09-28 | Research In Motion Limited | Method and apparatus for maximizing the transmission of data in a wireless data communication network |
| US5553075A (en) * | 1994-06-22 | 1996-09-03 | Ericsson Ge Mobile Communications Inc. | Packet data protocol for wireless communication |
| US5450411A (en) * | 1994-09-02 | 1995-09-12 | At&T Global Information Solutions Company | Network interface for multiplexing and demultiplexing isochronous and bursty data streams in ATM networks |
| KR100418848B1 (en) * | 1994-12-09 | 2004-07-27 | 브렌트 타운젠드 | High speed decoder and decoding method |
| US5970103A (en) * | 1996-09-06 | 1999-10-19 | Townshend; Brent | High speed communications system for analog subscriber connections |
| US5574858A (en) * | 1995-08-11 | 1996-11-12 | Dell U.S.A., L.P. | Method and apparatus for, upon receipt of data from a mouse, requiring the remainder of data needed to constitute a packet to be received within one second |
| KR100251712B1 (en) * | 1997-07-11 | 2000-04-15 | 윤종용 | X.25 network interfacing apparatus for x.25 protocol communication in electronic switching system |
| JP3319367B2 (en) * | 1997-10-14 | 2002-08-26 | ケイディーディーアイ株式会社 | Network connection device |
| US6256323B1 (en) * | 1997-12-08 | 2001-07-03 | Cisco Technology, Inc. | Method and apparatus for efficiently transporting asynchronous characters over an ATM network |
| US6477143B1 (en) | 1998-01-25 | 2002-11-05 | Dror Ginossar | Method and apparatus for packet network congestion avoidance and control |
| US7319860B2 (en) * | 2002-11-07 | 2008-01-15 | Research In Motion Limited | Pseudo-interactive input processing in wireless environments |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU591057B2 (en) * | 1984-06-01 | 1989-11-30 | Digital Equipment Corporation | Local area network for digital data processing system |
| US4737950A (en) * | 1985-05-31 | 1988-04-12 | Rockwell International Corp. | Multifunction bus to user device interface circuit |
| GB8526620D0 (en) * | 1985-10-29 | 1985-12-04 | British Telecomm | Communications network |
| JPS6354844A (en) * | 1986-08-26 | 1988-03-09 | Nec Corp | Code independent type packet forming system for semi-duplex communication |
| FR2616025B1 (en) * | 1987-05-26 | 1989-07-21 | Lespagnol Albert | METHOD AND SYSTEM FOR PACKET FLOW CONTROL |
| US4893306A (en) * | 1987-11-10 | 1990-01-09 | Bell Communications Research, Inc. | Method and apparatus for multiplexing circuit and packet traffic |
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1989
- 1989-05-01 US US07/345,912 patent/US5056088A/en not_active Expired - Lifetime
-
1990
- 1990-04-11 CA CA002014407A patent/CA2014407C/en not_active Expired - Lifetime
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- 1990-04-25 EP EP90304435A patent/EP0396309B1/en not_active Expired - Lifetime
- 1990-04-30 KR KR1019900006078A patent/KR0149860B1/en not_active IP Right Cessation
- 1990-05-01 JP JP11189090A patent/JP2588488B2/en not_active Expired - Lifetime
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1996
- 1996-05-02 HK HK78296A patent/HK78296A/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| US5056088A (en) | 1991-10-08 |
| KR900019424A (en) | 1990-12-24 |
| JP2588488B2 (en) | 1997-03-05 |
| EP0396309B1 (en) | 1995-09-13 |
| CA2014407A1 (en) | 1990-11-01 |
| EP0396309A2 (en) | 1990-11-07 |
| JPH02305041A (en) | 1990-12-18 |
| HK78296A (en) | 1996-05-10 |
| DE69022278D1 (en) | 1995-10-19 |
| DE69022278T2 (en) | 1996-05-15 |
| EP0396309A3 (en) | 1992-12-23 |
| KR0149860B1 (en) | 1999-05-15 |
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