CA2016755A1 - Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-configured logic arrays - Google Patents
Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-configured logic arraysInfo
- Publication number
- CA2016755A1 CA2016755A1 CA2016755A CA2016755A CA2016755A1 CA 2016755 A1 CA2016755 A1 CA 2016755A1 CA 2016755 A CA2016755 A CA 2016755A CA 2016755 A CA2016755 A CA 2016755A CA 2016755 A1 CA2016755 A1 CA 2016755A1
- Authority
- CA
- Canada
- Prior art keywords
- substitutes
- user
- mask
- transistors
- integrated circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318541—Scan latches or cell details
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318516—Test of programmable logic devices [PLDs]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318544—Scanning methods, algorithms and patterns
- G01R31/31855—Interconnection testing, e.g. crosstalk, shortcircuits
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Abstract
A structure and method for producing mask-configured integrated circuits which are pin compatible substitutes for user-configured logic arrays is disclosed. Mask-defined routing lines having resistive/capacitive characteristics simulating those of user-configurable routing paths in the user-configurable logic array are used in the mask-defined substitutes to replace the user-configurable routing paths. Scan testing networks are formed in the metal-configured substitutes to test the operability of logical function blocks formed on such chips. The scan testing networks comprise a plurality of test blocks each including three field effect pass transistors formed of four adjacent diffusion regions. Proper connection of the gates of these pass transistors to control lines controlling the transistors is tested by trans-mitting alternating high/low signals through serial conduction paths including the gate electrodes of these transistors.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/351,888 | 1989-05-15 | ||
US07/351,888 US5068603A (en) | 1987-10-07 | 1989-05-15 | Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-configured logic arrays |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2016755A1 true CA2016755A1 (en) | 1990-11-15 |
CA2016755C CA2016755C (en) | 1994-08-09 |
Family
ID=23382850
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002016755A Expired - Fee Related CA2016755C (en) | 1989-05-15 | 1990-05-14 | Structure and method for producing mask-programmed integrated circuits which are pin compatible substitutes for memory-configured logic arrays |
Country Status (5)
Country | Link |
---|---|
US (1) | US5068603A (en) |
EP (1) | EP0398605A3 (en) |
JP (1) | JPH03183154A (en) |
CA (1) | CA2016755C (en) |
DE (1) | DE398605T1 (en) |
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US4635261A (en) * | 1985-06-26 | 1987-01-06 | Motorola, Inc. | On chip test system for configurable gate arrays |
JPS6218732A (en) * | 1985-07-15 | 1987-01-27 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Integrated circuit and individualization thereof |
US4821233A (en) * | 1985-09-19 | 1989-04-11 | Xilinx, Incorporated | 5-transistor memory cell with known state on power-up |
US4746822A (en) * | 1986-03-20 | 1988-05-24 | Xilinx, Inc. | CMOS power-on reset circuit |
ES2012483B3 (en) * | 1986-05-14 | 1990-04-01 | American Telephone & Telegraph Company | INTEGRATED CIRCUIT WITH CHANNEL LENGTH INDICATOR. |
ATE87755T1 (en) * | 1986-06-06 | 1993-04-15 | Siemens Ag | METHOD OF SIMULATING AN OPEN TIME FAULT IN A LOGIC CIRCUIT USING FIELD EFFECT TRANSISTORS AND ARRANGEMENTS FOR CARRYING OUT THE METHOD. |
US4907180A (en) * | 1987-05-04 | 1990-03-06 | Hewlett-Packard Company | Hardware switch level simulator for MOS circuits |
US4902910A (en) * | 1987-11-17 | 1990-02-20 | Xilinx, Inc. | Power supply voltage level sensing circuit |
US4835418A (en) * | 1987-11-17 | 1989-05-30 | Xilinx, Inc. | Three-state bidirectional buffer |
US4963824A (en) * | 1988-11-04 | 1990-10-16 | International Business Machines Corporation | Diagnostics of a board containing a plurality of hybrid electronic components |
US4980636A (en) * | 1989-08-10 | 1990-12-25 | The United States Of America As Represented By The Administrator, National Aeronautics And Space Administration | Universal nondestructive MM-wave integrated circuit test fixture |
-
1989
- 1989-05-15 US US07/351,888 patent/US5068603A/en not_active Expired - Lifetime
-
1990
- 1990-05-14 CA CA002016755A patent/CA2016755C/en not_active Expired - Fee Related
- 1990-05-14 DE DE199090305142T patent/DE398605T1/en active Pending
- 1990-05-14 EP EP19900305142 patent/EP0398605A3/en not_active Withdrawn
- 1990-05-15 JP JP2123233A patent/JPH03183154A/en active Pending
Also Published As
Publication number | Publication date |
---|---|
EP0398605A2 (en) | 1990-11-22 |
US5068603A (en) | 1991-11-26 |
DE398605T1 (en) | 1991-07-25 |
CA2016755C (en) | 1994-08-09 |
EP0398605A3 (en) | 1993-10-06 |
JPH03183154A (en) | 1991-08-09 |
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