CA2018855A1 - Burst demodulator for establishing carrier and clock timing from a sequence of alternating symbols - Google Patents

Burst demodulator for establishing carrier and clock timing from a sequence of alternating symbols

Info

Publication number
CA2018855A1
CA2018855A1 CA2018855A CA2018855A CA2018855A1 CA 2018855 A1 CA2018855 A1 CA 2018855A1 CA 2018855 A CA2018855 A CA 2018855A CA 2018855 A CA2018855 A CA 2018855A CA 2018855 A1 CA2018855 A1 CA 2018855A1
Authority
CA
Canada
Prior art keywords
signal
burst
preamble
carrier
digital samples
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2018855A
Other languages
French (fr)
Other versions
CA2018855C (en
Inventor
Shousei Yoshida
Hizuru Nawata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP1152623A external-priority patent/JPH0732408B2/en
Priority claimed from JP1152624A external-priority patent/JPH0744576B2/en
Priority claimed from JP29033589A external-priority patent/JP2513330B2/en
Priority claimed from JP1304292A external-priority patent/JPH0720146B2/en
Application filed by NEC Corp filed Critical NEC Corp
Publication of CA2018855A1 publication Critical patent/CA2018855A1/en
Application granted granted Critical
Publication of CA2018855C publication Critical patent/CA2018855C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/32—Carrier systems characterised by combinations of two or more of the types covered by groups H04L27/02, H04L27/10, H04L27/18 or H04L27/26
    • H04L27/34—Amplitude- and phase-modulated carrier systems, e.g. quadrature-amplitude modulated carrier systems
    • H04L27/38—Demodulator circuits; Receiver circuits
    • H04L27/3845—Demodulator circuits; Receiver circuits using non - coherent demodulation, i.e. not using a phase synchronous carrier
    • H04L27/3854—Demodulator circuits; Receiver circuits using non - coherent demodulation, i.e. not using a phase synchronous carrier using a non - coherent carrier, including systems with baseband correction for phase or frequency offset
    • H04L27/3872—Compensation for phase rotation in the demodulated signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Abstract

ABSTRACT OF THE DISCLOSURE

In a burst demodulator, an APSK burst signal containing a preamble of alternating "1" and "-1" symbols, followed by a data field is received and quasi-coherently demodulated into a baseband complex signal, which is converted to digital form such that each symbol of the complex signal yields N digital samples, with N being selected such that at least one of the N digital samples is closest to a signal point of the burst signal.
A clock recovery circuit is responsive to the arrival of the burst for estimating the symbol timing of the burst signal from digital samples of the preamble. A digital sample is extracted from every N samples of the preamble in response to the estimated symbol timing so that it is most likely to be closest to the signal point. A carrier recovery circuit responds to the estimated symbol timing by estimating the carrier frequency and phase of the burst signal from the extracted digital samples to produce a complex carrier signal, which is multiplied with the extracted digital samples to recover the original signal. Memories are preferably provided to store the received burst signal. By repeatedly reading the preamble from the memories, the same symbols of the preamble can be used for clock timing and carrier phase recovery operations.
CA002018855A 1989-06-14 1990-06-13 Burst demodulator for establishing carrier and clock timing from a sequence of alternating symbols Expired - Fee Related CA2018855C (en)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
JP1-152624 1989-06-14
JP1152623A JPH0732408B2 (en) 1989-06-14 1989-06-14 Burst detector
JP1152624A JPH0744576B2 (en) 1989-06-14 1989-06-14 Burst signal demodulator
JP1-152623 1989-06-14
JP29033589A JP2513330B2 (en) 1989-11-07 1989-11-07 Burst demodulator
JP1-290335 1989-11-07
JP1-304292 1989-11-22
JP1304292A JPH0720146B2 (en) 1989-11-22 1989-11-22 Burst signal demodulator

Publications (2)

Publication Number Publication Date
CA2018855A1 true CA2018855A1 (en) 1990-12-14
CA2018855C CA2018855C (en) 1993-09-21

Family

ID=27473168

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002018855A Expired - Fee Related CA2018855C (en) 1989-06-14 1990-06-13 Burst demodulator for establishing carrier and clock timing from a sequence of alternating symbols

Country Status (3)

Country Link
US (1) US5170415A (en)
AU (1) AU624251B2 (en)
CA (1) CA2018855C (en)

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US7209433B2 (en) * 2002-01-07 2007-04-24 Hitachi, Ltd. Channel estimation and compensation techniques for use in frequency division multiplexed systems
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Also Published As

Publication number Publication date
AU624251B2 (en) 1992-06-04
AU5716590A (en) 1990-12-20
US5170415A (en) 1992-12-08
CA2018855C (en) 1993-09-21

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