CA2031054A1 - Inverse multiplexer and demultiplexer techniques - Google Patents

Inverse multiplexer and demultiplexer techniques

Info

Publication number
CA2031054A1
CA2031054A1 CA2031054A CA2031054A CA2031054A1 CA 2031054 A1 CA2031054 A1 CA 2031054A1 CA 2031054 A CA2031054 A CA 2031054A CA 2031054 A CA2031054 A CA 2031054A CA 2031054 A1 CA2031054 A1 CA 2031054A1
Authority
CA
Canada
Prior art keywords
subsectional
data rate
signal
time slots
time domain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2031054A
Other languages
French (fr)
Other versions
CA2031054C (en
Inventor
James J. Castellano
John H. Leshchuk
Michael Louis Steinberger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of CA2031054A1 publication Critical patent/CA2031054A1/en
Application granted granted Critical
Publication of CA2031054C publication Critical patent/CA2031054C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
    • H04J2203/0094—Virtual Concatenation

Abstract

An Inverse Multiplexer is disclosed which first demultiplexes a first data rate input signal into a plurality of second lower data rate subsectional signals, where each subsectional signal is provided with a periodic synchronization marker and includes a data rate which is less than the channel data rate used to transmit that subsectional signal to a remote terminal. Programmable Multiplexers (PMUXs) thenoperate to each take one or more subsectional signals that are (1) clock synchronized to a PMUX clock, and (2) a rational fraction of the channel data rate, and map contiguously assigned time slots in a capacity domain frame for each subsectional signal to time slots of a time domain frame format using a 2-step or 3-step digit reverse technique. The resultant time domain format has the input subsectional capacity domain time slots substantially uniformly distributed over the time domain frame. At the receiving end, an Inverse Demultiplexer performs the reverse operation to recover the original first data rate input signal.
CA002031054A 1990-01-02 1990-11-28 Inverse multiplexer and demultiplexer techniques Expired - Fee Related CA2031054C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US460,209 1990-01-02
US07/460,209 US5065396A (en) 1990-01-02 1990-01-02 Inverse multiplexer and demultiplexer techniques

Publications (2)

Publication Number Publication Date
CA2031054A1 true CA2031054A1 (en) 1991-07-03
CA2031054C CA2031054C (en) 1997-05-06

Family

ID=23827780

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002031054A Expired - Fee Related CA2031054C (en) 1990-01-02 1990-11-28 Inverse multiplexer and demultiplexer techniques

Country Status (6)

Country Link
US (1) US5065396A (en)
EP (1) EP0436293B1 (en)
JP (1) JPH0761055B2 (en)
AU (1) AU618694B2 (en)
CA (1) CA2031054C (en)
DE (1) DE69016634T2 (en)

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Also Published As

Publication number Publication date
EP0436293B1 (en) 1995-02-01
US5065396A (en) 1991-11-12
JPH0761055B2 (en) 1995-06-28
DE69016634D1 (en) 1995-03-16
AU6795890A (en) 1991-07-04
JPH04211534A (en) 1992-08-03
CA2031054C (en) 1997-05-06
AU618694B2 (en) 1992-01-02
EP0436293A3 (en) 1991-10-30
DE69016634T2 (en) 1995-05-24
EP0436293A2 (en) 1991-07-10

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