CA2040848C - Pll frequency synthesizer - Google Patents
Pll frequency synthesizerInfo
- Publication number
- CA2040848C CA2040848C CA002040848A CA2040848A CA2040848C CA 2040848 C CA2040848 C CA 2040848C CA 002040848 A CA002040848 A CA 002040848A CA 2040848 A CA2040848 A CA 2040848A CA 2040848 C CA2040848 C CA 2040848C
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- CA
- Canada
- Prior art keywords
- frequency
- output
- phase
- signal
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
- H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
- H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S331/00—Oscillators
- Y10S331/02—Phase locked loop having lock indicating or detecting means
Abstract
A phase locked loop (PLL) frequency synthesizer capable of switching the output frequency thereof at high speed. The frequency synthesizer has a second phase/frequency comparator and a second variable frequency divider in addition to a first phase/frequency comparator which is included in a PLL. The synthesizer switches over the time constant of a loop filter by the output of the second phase/frequency comparator, i. e., independently of the PLL which is responsive to the output of the first phase/frequency comparator. As a result, the time constant of the loop filter is switched over at an advanced timing to thereby reduce PLL tuning time.
Description
PLL FREQUENCY SYNTHESIZER
BACKGROUND OF THE INVENTION
The present invention relates to a frequency synthesizer using a phase locked loop (PLL) and, more particularly, to a PLL synthesizer capable of switching the output frequency thereof 5 at high speed.
A conventional PLL synthesizer has a reference frequency oscillator, a fixed frequency divider for dividing the output frequency of the oscillator, a voltage controlled oscillator (VCO), a variable frequency divider for dividing the output 10 frequency of the VCO, a phase/frequency comparator for comparing the outputs of the fixed and variable frequency dividers to output a difference therebetween, a charge pump to which the difference or deviation is applied, and a loop filter receiving and smoothing the output of the charge pump and 15 feeding bacl~ the output thereof to the VCO as a control voltage.
It is a common practice with this type of PLL synthesizer to cause the loop filter to select either one of a greater and a smaller time constant in order to enhance high-speed frequency switching and to stabilize the frequency. More specifically, the 2 0 time constant of the loop filter is reduced at the time of 20408~8 frequency switching so as to promote rapid tuning. After the frequency switching, a lock signa~ is fed from the phase/frequency comparator to the loop filter to increase the time constant of the filter, thereby stabilizing the frequency. In practice, however, at the time when the switching operation is completed, the control voltage applied to the VCO has been deviated from an expected value due to the delay particular to detection and switching. Therefore, the initial frequency just after the switching is different from predetermined one with the result that the switchover of the time constant of the loop filter is delayed. This in turn delays the tuning ti~e of the PLL and prevents the frequency to be switched over at high speed.
SUMMARY OF THE INV~:NTION
It is therefore an object of the present invention to provide a PLL frequency synthesizer capable of switching the output frequency thereof at high speed.
It is another obiect of the present invention to provide a generally improved PLL frequency synthesizer.
A PLL synthesizer for switching an output frequency at high speed of the present invention cmprises a reference frequency oscillator, a VCO, a first and a second variable frequency divider for dividing the output of the ~,TCO independentlY of each other, and each being provided with a particular divisor for 2 5 frequency division, a first phase/frequency comparator for 20408~8 comparing the output of the reference frequency oscillator and the output of the first variable frequency divider, a second phase/frequency comparator for comparing the output of the reference frequency oscillator and the output of the second 5 variable frequency divider, and a loop filter for smoothing the output of the first phase/frequency comparator to feed back a smoothed output thereof the VCO and switching over the time constant thereof in response to the output of the second - phase/frequency comparator.
A synthesizer of the present invention comprises a reference oscillator for generating a reference oscillation signal, a VCO for generating a VCO oscillation signal, the frequency of the VCO
oscillation signal being varied with a control signal, first and second variable frequency dividers for frequency dividing the 15 VCO signal in accordance with first and second divisors, respectively, first and second comparators for phase/frequency comparing the reference oscillation signal with the outputs of the first and second dividers, respectively, a filter for filtering the output of the first comparator to produce a filtered output and 20 supply it to the VCO as the control si~nal, the time constant of the filter being changed in response to the output of the second comparator.
A method of generating an oscillation signal in response to a divisor signal in accordance with the present invention comprises 2 5 the steps of (a) generating a first oscillation signal, (b~
4 2~408~8 generating a second oscillation signal whose frequency changes in response to a control signal, (c) responsive to first and second divisor signals, frequency dividing the second oscillation signal to produce first and second divided signals, respectively, (d) frequency and phase comparing the reference oscillation signal with the first and second divided signals to produce first and second comparison signal, respectively; and (e) filtering the first comparison signal to produce a filtered signal and supplying the filtered signal to the generating step (b) as the control signal, the tlme constant of the filterin~ step (e) being changed in response to the second comparison signal.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other obiects, features and advantages of the present invention will become more apparent from the following detailed description taken with the accompanying drawings in which:
Fig. 1 is a block diagram schematically showing a conventional PLL frequency synthesizer;
Fig. 2 is a schematic block diagram showing a PLL frequency synthesizer embodying the present invention; and Fig. 3 is a circuit dia$ram modeling a loop filter included in the embodiment.
DESCRIPTION OF THE PREFERRED EMBODIMENT
To better understand the present invention, a brief reference will be made to a prior art PLL frequency synthesizer, shown in Fig. 1. As shown, the prior art frequency synthesizer, 5 generally 10, has a reference frequency oscillator 12, a fixed frequency divider 14, a VCO 16, a variable frequency divider 18, a phase/frequency comparator 20, a charge pump 22, and a loop filter 24. The fixed frequency divider 14 divides the output of the reference frequency oscillator while the variable 10 frequency divider 18 divides the output of the VCO 16. The phase frequency comparator 20 compares the outputs of the frequency dividers 14 and 18 to produce an output representative of a phase or frequency difference therebetween. The loop filter 24 smoothes the output of the charge pump 22 and then feeds it 15 back to the VCO 16 as a control voltage C. Divisor data is applied to the variable frequency divider 18 via an input terminal 26. A lock signal L is fed from the comparator 20 to the loop filter 24 to switch over the time constant of the latter.
The loop filter 24 has two different time constants one of 20 which is selected at the time of switching and the other is selected after the switching. This is to promote rapid switching and to stabilize the frequency. Specifically, at the time when the frequency is switched over, the loop filter 24 selects a smaller time constant to effect rapid tuning. After the switchover, the 25 loop filter 24 selects a greater time constant in response to the lock signal L fed from the phase/frequency comparator 2 0, thereby stabilizing the frequency. In practice, however, at the time when the switching operation is completed, the control voltage C applied to the VCO 16 has been deviated from an 5 expected value due to the delay particular to detection and switching, as stated earlier. Therefore, the initial frequency iust after the switching is different from predetermined one with the result that the switchover of the time constant of the loop filter 24 is delayed. This in turn delays the tuning time of the 10 PLL and prevents the frequency to be switched over at high speed.
Referring to Fig. 2, a PLL frequency synthesizer embodying the present invention is shown and generally designated by the reference numeral 30. In Fig. 2, blocks functionally equivalent 15 to the blocks of Fig. 1 are designated by the same reference numerals, and redundant description will be avoided for simplicity. Let the phase/frequency comparator 2 0 and the variable frequency divider 18 shown in Fig. 1 be referred to as a first phase/frequency comparator and a first variable frequency 2 0 divider, respectively.
As shown in Fig. 2, the frequency synthesizer 3 O has a second phase/frequency comparator 32 and a second variable frequency divider 34 in addition to the first phase/frequency comparator 2 0 and first variable frequency divider 18 . The 25 second variable frequency divider 34 divides the output of a VCO
20~0~48 16 while a fixed frequency divider 14 divides the output of a reference frequency oscillator 12. The second phase/frequencY
comparator 3 2 compares the outputs of the two frequency dividers 14 and 34. A loop filter 24 switches over the time constant thereof on the basis of the result of comparison outputted by the comparator 3 2 . Particular divisor data is applied to each of input terminals 26 and 36. The output of the frequency synthesizer 30 appears on an output terminal 38.
In operation, the first variable frequency divider 1~ divides the output of the VCO 16 by a particular divisor applied thereto via the input terminal 26. The fixed frequency divider 14 divides the output of the reference frequency oscillator 12. The first phase/frequency comparator 20 compares the outputs of the frequency dividers 18 and 14 and delivers ~he output thereof representative of their difference to a charge pumP 2 2 . In response, the charge pump 2 2 controls the loop filter 2 0 such that a capacitor included in the loop filter 2 0 is charged or discharged. The resulting output voltage of the loop filter 20 is fed back to the VCO 16 to effect necessary frequency control.
2 0 The output of the VCO 16 is also applied to the second variable frequency divider 34. The frequency divider 34, therefore, divides the output of the VCO 16 by a divisor applied to the input terminal 36. The second phase/frequency comparator 3 2 compares the output of the variable frequency 2 5 divider 3 4 with the output of the fixed frequency divider 14.
20~0848 When the d;fference between the two frequencies becomes smaller than a pedetermined value, the comparator 32 feeds a switching signal SW to the loop filter 24 to switch over the time constant of the latter. Specifically, in the initial stage of frequency 5 switching operation, the loop filter 2 4 selects a smaller time constant since the difference or deviation determined by the comparator 32 is greater than the predetermined value. As the switching operation proceeds, the deviation is sequentially reduced. When the deviation becomes smaller than the 10 predetermined value, the comparator 32 causes the loop filter 24 to select a greater time constant by the switching signal SW. At the same time, the switching signal SW is supplied to the first variable frequency divider 18 and fixed frequency divider 14 to reset them and also to the first phase/frequency comparator 20 15 to initialize it.
Assume that the divisors for frequency division applied to the input terminals 2 6 and 3 6 are respectively Dl and D2, and that the divisor initially set in the first variable frequency divider 18 is Do. It is to be noted that the divisors Dl and D2 are stored in 20 a ROM, not shown, and each is fed to one of the input terminals 2 6 and 3 6 via a buffer. Also, assume that the predetermined deviation to be detected by the second phase/frequency comparator 3 2 is tl, and that the time necessary for the loop filter 24 to be switched over is t2. Further, assume that the 25 control voltages ~rl and V2 are supplied to the ~JCO 16 when the loop including the second variable phase/frequency comparator 32 is stabilized with the divisors D~ and D2 applied to the second variable frequency divider 3 4, respectively, and that the maximum voltage which the charge pump 22 can output is Vmax.
5 As shown in Fig. 3, let the loop filter 24 be modeled as a filter made up of resistors R, and R2, a capacitor C, an input terminal 4 0, and an output terminal 4 2 .
When the control voltage Do is lower than the control voltage Dl, there holds an equation:
Vl - V~!lax tl + t2 = - (R, + R2) Cln V2 ~ V~,ax Assuming that the voltage appearing on the output terminal 42 is lS initially VO. then V (t) = V?aX + R, / R, + R2 (VO - V~rax) e-t/(Rl+R2)C
When t" t2, R" R2, C and V, are given, V2 is obtained and, 20 therefore, optimum D2 is produced. Preferably, a frequency intermediate between the frequencies Do and D, set in the first variable frequency divider 18 before and at the time of switching, respectively, should be set in the second variable frequency divider 34. Then, the second phase/frequency 25 comparator 32 will output the switching signal SW to switch over the loop filter 24 before the PLL is established in response to the output of the first phase/frequency comparator 2 0 . This is successful in reducing the tuning time of the PLL despite the delay particular to the detection and switching.
In summary, in accordance with the present invention, a PLL frequency synthesizer has a second phase/frequency comparator and a second variable frequency divider in addition to a first phase/frequency comparator which is included in a PLL. The synthesizer switches over the time constant of a loop filter by the output of the second phase/frequency comparator, i. e., independently of the PLL which is responsive to the output of the first phase/frequency comparator. As a result, the time constant of the loop filter is switched over at an advanced timing to thereby reduce the PLL tuning time.
Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.
BACKGROUND OF THE INVENTION
The present invention relates to a frequency synthesizer using a phase locked loop (PLL) and, more particularly, to a PLL synthesizer capable of switching the output frequency thereof 5 at high speed.
A conventional PLL synthesizer has a reference frequency oscillator, a fixed frequency divider for dividing the output frequency of the oscillator, a voltage controlled oscillator (VCO), a variable frequency divider for dividing the output 10 frequency of the VCO, a phase/frequency comparator for comparing the outputs of the fixed and variable frequency dividers to output a difference therebetween, a charge pump to which the difference or deviation is applied, and a loop filter receiving and smoothing the output of the charge pump and 15 feeding bacl~ the output thereof to the VCO as a control voltage.
It is a common practice with this type of PLL synthesizer to cause the loop filter to select either one of a greater and a smaller time constant in order to enhance high-speed frequency switching and to stabilize the frequency. More specifically, the 2 0 time constant of the loop filter is reduced at the time of 20408~8 frequency switching so as to promote rapid tuning. After the frequency switching, a lock signa~ is fed from the phase/frequency comparator to the loop filter to increase the time constant of the filter, thereby stabilizing the frequency. In practice, however, at the time when the switching operation is completed, the control voltage applied to the VCO has been deviated from an expected value due to the delay particular to detection and switching. Therefore, the initial frequency just after the switching is different from predetermined one with the result that the switchover of the time constant of the loop filter is delayed. This in turn delays the tuning ti~e of the PLL and prevents the frequency to be switched over at high speed.
SUMMARY OF THE INV~:NTION
It is therefore an object of the present invention to provide a PLL frequency synthesizer capable of switching the output frequency thereof at high speed.
It is another obiect of the present invention to provide a generally improved PLL frequency synthesizer.
A PLL synthesizer for switching an output frequency at high speed of the present invention cmprises a reference frequency oscillator, a VCO, a first and a second variable frequency divider for dividing the output of the ~,TCO independentlY of each other, and each being provided with a particular divisor for 2 5 frequency division, a first phase/frequency comparator for 20408~8 comparing the output of the reference frequency oscillator and the output of the first variable frequency divider, a second phase/frequency comparator for comparing the output of the reference frequency oscillator and the output of the second 5 variable frequency divider, and a loop filter for smoothing the output of the first phase/frequency comparator to feed back a smoothed output thereof the VCO and switching over the time constant thereof in response to the output of the second - phase/frequency comparator.
A synthesizer of the present invention comprises a reference oscillator for generating a reference oscillation signal, a VCO for generating a VCO oscillation signal, the frequency of the VCO
oscillation signal being varied with a control signal, first and second variable frequency dividers for frequency dividing the 15 VCO signal in accordance with first and second divisors, respectively, first and second comparators for phase/frequency comparing the reference oscillation signal with the outputs of the first and second dividers, respectively, a filter for filtering the output of the first comparator to produce a filtered output and 20 supply it to the VCO as the control si~nal, the time constant of the filter being changed in response to the output of the second comparator.
A method of generating an oscillation signal in response to a divisor signal in accordance with the present invention comprises 2 5 the steps of (a) generating a first oscillation signal, (b~
4 2~408~8 generating a second oscillation signal whose frequency changes in response to a control signal, (c) responsive to first and second divisor signals, frequency dividing the second oscillation signal to produce first and second divided signals, respectively, (d) frequency and phase comparing the reference oscillation signal with the first and second divided signals to produce first and second comparison signal, respectively; and (e) filtering the first comparison signal to produce a filtered signal and supplying the filtered signal to the generating step (b) as the control signal, the tlme constant of the filterin~ step (e) being changed in response to the second comparison signal.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other obiects, features and advantages of the present invention will become more apparent from the following detailed description taken with the accompanying drawings in which:
Fig. 1 is a block diagram schematically showing a conventional PLL frequency synthesizer;
Fig. 2 is a schematic block diagram showing a PLL frequency synthesizer embodying the present invention; and Fig. 3 is a circuit dia$ram modeling a loop filter included in the embodiment.
DESCRIPTION OF THE PREFERRED EMBODIMENT
To better understand the present invention, a brief reference will be made to a prior art PLL frequency synthesizer, shown in Fig. 1. As shown, the prior art frequency synthesizer, 5 generally 10, has a reference frequency oscillator 12, a fixed frequency divider 14, a VCO 16, a variable frequency divider 18, a phase/frequency comparator 20, a charge pump 22, and a loop filter 24. The fixed frequency divider 14 divides the output of the reference frequency oscillator while the variable 10 frequency divider 18 divides the output of the VCO 16. The phase frequency comparator 20 compares the outputs of the frequency dividers 14 and 18 to produce an output representative of a phase or frequency difference therebetween. The loop filter 24 smoothes the output of the charge pump 22 and then feeds it 15 back to the VCO 16 as a control voltage C. Divisor data is applied to the variable frequency divider 18 via an input terminal 26. A lock signal L is fed from the comparator 20 to the loop filter 24 to switch over the time constant of the latter.
The loop filter 24 has two different time constants one of 20 which is selected at the time of switching and the other is selected after the switching. This is to promote rapid switching and to stabilize the frequency. Specifically, at the time when the frequency is switched over, the loop filter 24 selects a smaller time constant to effect rapid tuning. After the switchover, the 25 loop filter 24 selects a greater time constant in response to the lock signal L fed from the phase/frequency comparator 2 0, thereby stabilizing the frequency. In practice, however, at the time when the switching operation is completed, the control voltage C applied to the VCO 16 has been deviated from an 5 expected value due to the delay particular to detection and switching, as stated earlier. Therefore, the initial frequency iust after the switching is different from predetermined one with the result that the switchover of the time constant of the loop filter 24 is delayed. This in turn delays the tuning time of the 10 PLL and prevents the frequency to be switched over at high speed.
Referring to Fig. 2, a PLL frequency synthesizer embodying the present invention is shown and generally designated by the reference numeral 30. In Fig. 2, blocks functionally equivalent 15 to the blocks of Fig. 1 are designated by the same reference numerals, and redundant description will be avoided for simplicity. Let the phase/frequency comparator 2 0 and the variable frequency divider 18 shown in Fig. 1 be referred to as a first phase/frequency comparator and a first variable frequency 2 0 divider, respectively.
As shown in Fig. 2, the frequency synthesizer 3 O has a second phase/frequency comparator 32 and a second variable frequency divider 34 in addition to the first phase/frequency comparator 2 0 and first variable frequency divider 18 . The 25 second variable frequency divider 34 divides the output of a VCO
20~0~48 16 while a fixed frequency divider 14 divides the output of a reference frequency oscillator 12. The second phase/frequencY
comparator 3 2 compares the outputs of the two frequency dividers 14 and 34. A loop filter 24 switches over the time constant thereof on the basis of the result of comparison outputted by the comparator 3 2 . Particular divisor data is applied to each of input terminals 26 and 36. The output of the frequency synthesizer 30 appears on an output terminal 38.
In operation, the first variable frequency divider 1~ divides the output of the VCO 16 by a particular divisor applied thereto via the input terminal 26. The fixed frequency divider 14 divides the output of the reference frequency oscillator 12. The first phase/frequency comparator 20 compares the outputs of the frequency dividers 18 and 14 and delivers ~he output thereof representative of their difference to a charge pumP 2 2 . In response, the charge pump 2 2 controls the loop filter 2 0 such that a capacitor included in the loop filter 2 0 is charged or discharged. The resulting output voltage of the loop filter 20 is fed back to the VCO 16 to effect necessary frequency control.
2 0 The output of the VCO 16 is also applied to the second variable frequency divider 34. The frequency divider 34, therefore, divides the output of the VCO 16 by a divisor applied to the input terminal 36. The second phase/frequency comparator 3 2 compares the output of the variable frequency 2 5 divider 3 4 with the output of the fixed frequency divider 14.
20~0848 When the d;fference between the two frequencies becomes smaller than a pedetermined value, the comparator 32 feeds a switching signal SW to the loop filter 24 to switch over the time constant of the latter. Specifically, in the initial stage of frequency 5 switching operation, the loop filter 2 4 selects a smaller time constant since the difference or deviation determined by the comparator 32 is greater than the predetermined value. As the switching operation proceeds, the deviation is sequentially reduced. When the deviation becomes smaller than the 10 predetermined value, the comparator 32 causes the loop filter 24 to select a greater time constant by the switching signal SW. At the same time, the switching signal SW is supplied to the first variable frequency divider 18 and fixed frequency divider 14 to reset them and also to the first phase/frequency comparator 20 15 to initialize it.
Assume that the divisors for frequency division applied to the input terminals 2 6 and 3 6 are respectively Dl and D2, and that the divisor initially set in the first variable frequency divider 18 is Do. It is to be noted that the divisors Dl and D2 are stored in 20 a ROM, not shown, and each is fed to one of the input terminals 2 6 and 3 6 via a buffer. Also, assume that the predetermined deviation to be detected by the second phase/frequency comparator 3 2 is tl, and that the time necessary for the loop filter 24 to be switched over is t2. Further, assume that the 25 control voltages ~rl and V2 are supplied to the ~JCO 16 when the loop including the second variable phase/frequency comparator 32 is stabilized with the divisors D~ and D2 applied to the second variable frequency divider 3 4, respectively, and that the maximum voltage which the charge pump 22 can output is Vmax.
5 As shown in Fig. 3, let the loop filter 24 be modeled as a filter made up of resistors R, and R2, a capacitor C, an input terminal 4 0, and an output terminal 4 2 .
When the control voltage Do is lower than the control voltage Dl, there holds an equation:
Vl - V~!lax tl + t2 = - (R, + R2) Cln V2 ~ V~,ax Assuming that the voltage appearing on the output terminal 42 is lS initially VO. then V (t) = V?aX + R, / R, + R2 (VO - V~rax) e-t/(Rl+R2)C
When t" t2, R" R2, C and V, are given, V2 is obtained and, 20 therefore, optimum D2 is produced. Preferably, a frequency intermediate between the frequencies Do and D, set in the first variable frequency divider 18 before and at the time of switching, respectively, should be set in the second variable frequency divider 34. Then, the second phase/frequency 25 comparator 32 will output the switching signal SW to switch over the loop filter 24 before the PLL is established in response to the output of the first phase/frequency comparator 2 0 . This is successful in reducing the tuning time of the PLL despite the delay particular to the detection and switching.
In summary, in accordance with the present invention, a PLL frequency synthesizer has a second phase/frequency comparator and a second variable frequency divider in addition to a first phase/frequency comparator which is included in a PLL. The synthesizer switches over the time constant of a loop filter by the output of the second phase/frequency comparator, i. e., independently of the PLL which is responsive to the output of the first phase/frequency comparator. As a result, the time constant of the loop filter is switched over at an advanced timing to thereby reduce the PLL tuning time.
Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.
Claims (6)
1. A phase locked loop (PLL) synthesizer for switching an output frequency at high speed, comprising:
a reference frequency oscillator;
a voltage controlled oscillator (VCO);
a first and a second variable frequency divider for dividing an output of said VCO independently of each other, and each being provided with a particular divisor for frequency division;
a first phase/frequency comparator for comparing an output of said reference frequency oscillator and an output of said first variable frequency divider;
a second phase/frequency comparator for comparing the output of said reference frequency oscillator and an output of said second variable frequency divider; and a loop filter for smoothing an output of said first phase/frequency comparator to feed back a smoothed output thereof to said VCO and switching over a time constant thereof in response to an output of said second phase/frequency comparator.
a reference frequency oscillator;
a voltage controlled oscillator (VCO);
a first and a second variable frequency divider for dividing an output of said VCO independently of each other, and each being provided with a particular divisor for frequency division;
a first phase/frequency comparator for comparing an output of said reference frequency oscillator and an output of said first variable frequency divider;
a second phase/frequency comparator for comparing the output of said reference frequency oscillator and an output of said second variable frequency divider; and a loop filter for smoothing an output of said first phase/frequency comparator to feed back a smoothed output thereof to said VCO and switching over a time constant thereof in response to an output of said second phase/frequency comparator.
2. A PLL frequency synthesizer as claimed in claim 1, wherein said divisor of said second variable frequency divider is intermediate between divisors of said first variable frequency divider before and at the time of switching, respectively.
3. A phase-locked loop (PLL) synthesizer comprising:
reference oscillator means for generating a reference oscillation signal;
voltage-controlled oscillator (VCO) means for generating a VCO oscillation signal, the frequency of said VCO oscillation signal being varied with a control signal;
first and second variable frequency divider means for frequency dividing said VCO signal in accordance with first and second divisors, respectively;
first and second comparator means for phase/frequency comparing said reference oscillation signal with the outputs of said first and second divider means, respectively;
filter means for filtering the output of said first comparator means to produce a filtered output and supply it to said VCO
means as said control signal, the time constant of said filter means being changed in response to the output of said second comparator means.
reference oscillator means for generating a reference oscillation signal;
voltage-controlled oscillator (VCO) means for generating a VCO oscillation signal, the frequency of said VCO oscillation signal being varied with a control signal;
first and second variable frequency divider means for frequency dividing said VCO signal in accordance with first and second divisors, respectively;
first and second comparator means for phase/frequency comparing said reference oscillation signal with the outputs of said first and second divider means, respectively;
filter means for filtering the output of said first comparator means to produce a filtered output and supply it to said VCO
means as said control signal, the time constant of said filter means being changed in response to the output of said second comparator means.
4. A PLL synthesizer as claimed in claime 3, wherein said second divisor is so selected that the frequency difference between said reference oscillation signal and the output of said second divider means is smaller than the frequency difference between said reference oscillation signal and the output of said first divider means.
5. A PLL synthesizer as claimed in claim 3, further comprising third divider means for frequency dividing said reference oscillation signal in accordance with a predetermined divisor.
6. A method of generating an oscillation signal in response to a divisor signal, comprising the steps of:
(a) generating a first oscillation signal;
(b) generating a second oscillation signal whose frequency changes in response to a control signal;
(c) responsive to first and second divisor signals, frequency dividing said second oscillation signal to produce first and second divided signals, respectively;
(d) frequency and phase comparing said reference oscillation signal with said first and second divided signals to produce first and second comparison signal, respectively; and (e) filtering said first comparison signal to produce a filtered signal and supplying said filtered signal to the generating step (b) as said control signal, the time constant of the filtering step (e) being changed in response to said second comparison signal.
(a) generating a first oscillation signal;
(b) generating a second oscillation signal whose frequency changes in response to a control signal;
(c) responsive to first and second divisor signals, frequency dividing said second oscillation signal to produce first and second divided signals, respectively;
(d) frequency and phase comparing said reference oscillation signal with said first and second divided signals to produce first and second comparison signal, respectively; and (e) filtering said first comparison signal to produce a filtered signal and supplying said filtered signal to the generating step (b) as said control signal, the time constant of the filtering step (e) being changed in response to said second comparison signal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2103414A JP2841693B2 (en) | 1990-04-19 | 1990-04-19 | PLL frequency synthesizer |
| JP2-103414 | 1990-04-19 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2040848A1 CA2040848A1 (en) | 1991-10-20 |
| CA2040848C true CA2040848C (en) | 1996-04-23 |
Family
ID=14353388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002040848A Expired - Fee Related CA2040848C (en) | 1990-04-19 | 1991-04-19 | Pll frequency synthesizer |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US5113152A (en) |
| EP (1) | EP0453280B1 (en) |
| JP (1) | JP2841693B2 (en) |
| AU (1) | AU632024B2 (en) |
| CA (1) | CA2040848C (en) |
| DE (1) | DE69112477T2 (en) |
Families Citing this family (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0548450A (en) * | 1991-08-08 | 1993-02-26 | Fujitsu Ltd | Pll synthesizer circuit |
| DE4200816A1 (en) * | 1992-01-15 | 1993-07-22 | Bosch Gmbh Robert | FREQUENCY AND PHASE MODULATOR FOR DIGITAL MODULATORS OR DIGITAL TRANSMISSION, IN PARTICULAR FOR RADIO TRANSMISSION |
| JPH05291950A (en) * | 1992-04-15 | 1993-11-05 | Mitsubishi Electric Corp | Phase locked loop frequency synthesizer |
| US5307071A (en) * | 1992-04-17 | 1994-04-26 | Hughes Aircraft Company | Low noise frequency synthesizer using half integer dividers and analog gain compensation |
| US5315623A (en) * | 1992-08-04 | 1994-05-24 | Ford Motor Company | Dual mode phase-locked loop |
| US5420545A (en) * | 1993-03-10 | 1995-05-30 | National Semiconductor Corporation | Phase lock loop with selectable frequency switching time |
| EP0691746A1 (en) * | 1993-03-18 | 1996-01-10 | Kabushiki Kaisha Toshiba | Frequency synthesizer |
| US5703539A (en) * | 1993-12-17 | 1997-12-30 | Motorola, Inc. | Apparatus and method for controlling the loop bandwidth of a phase locked loop |
| US5794130A (en) * | 1994-04-26 | 1998-08-11 | Funai Electric Engineering Company Limited | Wireless communication system having improved PLL circuits |
| JPH0879074A (en) * | 1994-09-05 | 1996-03-22 | Mitsubishi Electric Corp | Phase locked loop circuit |
| US5610955A (en) * | 1995-11-28 | 1997-03-11 | Microclock, Inc. | Circuit for generating a spread spectrum clock |
| US5815694A (en) * | 1995-12-21 | 1998-09-29 | International Business Machines Corporation | Apparatus and method to change a processor clock frequency |
| US5943382A (en) * | 1996-08-21 | 1999-08-24 | Neomagic Corp. | Dual-loop spread-spectrum clock generator with master PLL and slave voltage-modulation-locked loop |
| JPH10233816A (en) * | 1997-02-21 | 1998-09-02 | Sharp Corp | Digital satellite receiver |
| US6373912B1 (en) * | 1997-06-16 | 2002-04-16 | Legerity, Inc. | Phase-locked loop arrangement with fast lock mode |
| JPH1139806A (en) * | 1997-07-14 | 1999-02-12 | Oki Electric Ind Co Ltd | Clock multiplying circuit |
| GB2341285B (en) * | 1998-09-02 | 2001-12-19 | Nec Technologies | Frequency synthesisers |
| JP3532861B2 (en) * | 2001-02-06 | 2004-05-31 | 松下電器産業株式会社 | PLL circuit |
| JP4504580B2 (en) * | 2001-02-20 | 2010-07-14 | ルネサスエレクトロニクス株式会社 | Multiplication PLL circuit |
| US6501307B1 (en) | 2001-11-12 | 2002-12-31 | Pericom Semiconductor Corp. | Spread-spectrum clock buffer/driver that modulates clock period by switching loads |
| JP4236998B2 (en) * | 2003-02-19 | 2009-03-11 | 株式会社神戸製鋼所 | Oscillator |
| US6864753B2 (en) * | 2002-06-11 | 2005-03-08 | The Regents Of The University Of California | Stabilization technique for phase-locked frequency synthesizers |
| FR2846164A1 (en) * | 2002-10-17 | 2004-04-23 | St Microelectronics Sa | METHOD AND DEVICE FOR GENERATING A SIGNAL HAVING A FREQUENCY EQUAL TO THE PRODUCT OF A REFERENCE FREQUENCY BY A REAL NUMBER |
| US6714085B1 (en) | 2002-10-24 | 2004-03-30 | General Dynamics Decision Systems, Inc | Prepositioned frequency synthesizer and method therefor |
| US7542483B1 (en) * | 2003-06-25 | 2009-06-02 | Cisco Technology, Inc. | Recoverable reference clock architecture for SONET/SDH and ethernet mixed bidirectional applications |
| US6980060B2 (en) * | 2003-10-23 | 2005-12-27 | International Business Machines Corporation | Adaptive method and apparatus to control loop bandwidth of a phase lock loop |
| US7586344B1 (en) * | 2007-10-16 | 2009-09-08 | Lattice Semiconductor Corporation | Dynamic delay or advance adjustment of oscillating signal phase |
| US8024120B2 (en) * | 2008-05-16 | 2011-09-20 | Turner Larry A | Complex phase locked loop |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3421105A (en) * | 1967-02-28 | 1969-01-07 | Nasa | Automatic acquisition system for phase-lock loop |
| US3956710A (en) * | 1974-11-20 | 1976-05-11 | Motorola, Inc. | Phase locked loop lock detector and method |
| US4745371A (en) * | 1985-08-02 | 1988-05-17 | Libera Developments Limited | Phase-locked digital synthesizer |
| US4771249A (en) * | 1987-05-26 | 1988-09-13 | Motorola, Inc. | Phase locked loop having a filter with controlled variable bandwidth |
| US5027087A (en) * | 1990-02-02 | 1991-06-25 | Motorola, Inc. | Fast-switching frequency synthesizer |
| CA2043054C (en) * | 1990-05-23 | 1994-12-06 | Osamu Ichiyoshi | Phase-lock loop device operable at a high speed |
| DE69130046T2 (en) * | 1990-10-22 | 1999-05-06 | Nec Corp | Frequency synthesizer with PLL, which enables a frequency change of the output at high speed |
-
1990
- 1990-04-19 JP JP2103414A patent/JP2841693B2/en not_active Expired - Fee Related
-
1991
- 1991-04-18 DE DE69112477T patent/DE69112477T2/en not_active Expired - Fee Related
- 1991-04-18 EP EP91303462A patent/EP0453280B1/en not_active Expired - Lifetime
- 1991-04-18 AU AU75149/91A patent/AU632024B2/en not_active Ceased
- 1991-04-18 US US07/687,329 patent/US5113152A/en not_active Expired - Lifetime
- 1991-04-19 CA CA002040848A patent/CA2040848C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CA2040848A1 (en) | 1991-10-20 |
| JP2841693B2 (en) | 1998-12-24 |
| AU632024B2 (en) | 1992-12-10 |
| US5113152A (en) | 1992-05-12 |
| EP0453280A1 (en) | 1991-10-23 |
| EP0453280B1 (en) | 1995-08-30 |
| AU7514991A (en) | 1991-10-24 |
| JPH042218A (en) | 1992-01-07 |
| DE69112477D1 (en) | 1995-10-05 |
| DE69112477T2 (en) | 1996-05-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |