CA2041507A1 - A high performance pipelined emulator - Google Patents

A high performance pipelined emulator

Info

Publication number
CA2041507A1
CA2041507A1 CA2041507A CA2041507A CA2041507A1 CA 2041507 A1 CA2041507 A1 CA 2041507A1 CA 2041507 A CA2041507 A CA 2041507A CA 2041507 A CA2041507 A CA 2041507A CA 2041507 A1 CA2041507 A1 CA 2041507A1
Authority
CA
Canada
Prior art keywords
emulator
instruction
chip
source
vector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2041507A
Other languages
French (fr)
Other versions
CA2041507C (en
Inventor
Steven S. Smith
Arnold J. Smith
Amy E. Gilfeather
Richard P. Brown
Thomas F. Joyce
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Steven S. Smith
Arnold J. Smith
Amy E. Gilfeather
Richard P. Brown
Thomas F. Joyce
Bull Hn Information Systems Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Steven S. Smith, Arnold J. Smith, Amy E. Gilfeather, Richard P. Brown, Thomas F. Joyce, Bull Hn Information Systems Inc. filed Critical Steven S. Smith
Publication of CA2041507A1 publication Critical patent/CA2041507A1/en
Application granted granted Critical
Publication of CA2041507C publication Critical patent/CA2041507C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30174—Runtime instruction translation, e.g. macros for non-native instruction set, e.g. Javabyte, legacy code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set

Abstract

The emulator includes first and second pipelined stages connected through a bidirectional bus for executing source instructions normally executed by a different/source computer in a highly overlapped manner. The first stage includes an emulator chip which performs the function of fetching and decoding each source instruction stored in cache memory resulting in the generation of a number of vector addresses required for executing the instruction by the second stage. The second stage includes a high performance microprocessor chip having on-chip instruction and data caches for storing a plurality of emulation subroutines and data fetched during subroutine execution. In pipelined fashion, the emulator chip fetches and decodes each source instruction which generates a vector branch address which is loaded into the branch vector register while the microprocessor chip fetches and executes emulation subroutines specified by the vector address transferred via the bus for each previously decoded source instruction.
CA002041507A 1990-06-29 1991-04-30 A high performance pipelined emulator Expired - Fee Related CA2041507C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/546,348 US5430862A (en) 1990-06-29 1990-06-29 Emulation of CISC instructions by RISC instructions using two pipelined stages for overlapped CISC decoding and RISC execution
US546,348 1990-06-29

Publications (2)

Publication Number Publication Date
CA2041507A1 true CA2041507A1 (en) 1991-12-30
CA2041507C CA2041507C (en) 1999-04-06

Family

ID=24180022

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002041507A Expired - Fee Related CA2041507C (en) 1990-06-29 1991-04-30 A high performance pipelined emulator

Country Status (4)

Country Link
US (1) US5430862A (en)
EP (1) EP0464494B1 (en)
CA (1) CA2041507C (en)
DE (1) DE69129565T2 (en)

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Also Published As

Publication number Publication date
EP0464494A3 (en) 1993-12-08
EP0464494A2 (en) 1992-01-08
US5430862A (en) 1995-07-04
DE69129565D1 (en) 1998-07-16
EP0464494B1 (en) 1998-06-10
CA2041507C (en) 1999-04-06
DE69129565T2 (en) 1999-03-18

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