CA2050129A1 - Dynamic bus arbitration with grant sharing each cycle - Google Patents

Dynamic bus arbitration with grant sharing each cycle

Info

Publication number
CA2050129A1
CA2050129A1 CA2050129A CA2050129A CA2050129A1 CA 2050129 A1 CA2050129 A1 CA 2050129A1 CA 2050129 A CA2050129 A CA 2050129A CA 2050129 A CA2050129 A CA 2050129A CA 2050129 A1 CA2050129 A1 CA 2050129A1
Authority
CA
Canada
Prior art keywords
arbitration
bus
cycle
bus master
external devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2050129A
Other languages
French (fr)
Other versions
CA2050129C (en
Inventor
George Bohoslaw Marenin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CA2050129A1 publication Critical patent/CA2050129A1/en
Application granted granted Critical
Publication of CA2050129C publication Critical patent/CA2050129C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Abstract

Apparatus and method for optimizing bus arbitration during direct memory access (DMA) data transfers across a nondedicated bus between a memory and/or a plurality of external devices each master having an arbitration priority. At least two nonoverlapping clocks are provided per transfer cycle and there is at least one transfer cycle per arbitration cycle. Arbitration priority requests are transmitted from each external device to an arbitration bus only at the rise of the first clock. At the end of the last clock, the priority code of the external device having the highest priority is determined to designate the external device which is to become bus master. Addresses and data are transferred between the designated bus master and the memory or another of the external devices via the nondedicated bus during the next cycle after a then active bus master relinquishes control. The priorities of the external devices can be changed dynamically. Arbitration cycles are pipelined in such manner that there is no loss of address or data transfer cycles. The then active bus master may extend the number of cycles during which it communicates with one or more external devices. A device designated as next in line as bus master may be preempted under a certain condition.
CA002050129A 1990-09-21 1991-08-28 Dynamic bus arbitration with grant sharing each cycle Expired - Fee Related CA2050129C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US58634990A 1990-09-21 1990-09-21
US07/586,349 1990-09-21

Publications (2)

Publication Number Publication Date
CA2050129A1 true CA2050129A1 (en) 1992-03-22
CA2050129C CA2050129C (en) 1996-05-14

Family

ID=24345380

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002050129A Expired - Fee Related CA2050129C (en) 1990-09-21 1991-08-28 Dynamic bus arbitration with grant sharing each cycle

Country Status (18)

Country Link
US (1) US5195185A (en)
EP (1) EP0476990B1 (en)
JP (1) JPH0810445B2 (en)
KR (1) KR950014505B1 (en)
CN (1) CN1037553C (en)
AU (1) AU639589B2 (en)
BR (1) BR9103929A (en)
CA (1) CA2050129C (en)
CZ (1) CZ282214B6 (en)
DE (1) DE69132344T2 (en)
FI (1) FI914429A (en)
HU (1) HU215867B (en)
MX (1) MX173460B (en)
NO (1) NO913707L (en)
PL (1) PL167608B1 (en)
PT (1) PT99006A (en)
RU (1) RU2110838C1 (en)
SG (1) SG42853A1 (en)

Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5559962A (en) * 1989-10-09 1996-09-24 Yamaha Corporation Data transmission system selecting both source and destination using addressing mechanism
US5461723A (en) * 1990-04-05 1995-10-24 Mit Technology Corp. Dual channel data block transfer bus
FR2675286B1 (en) * 1991-04-15 1993-06-18 Bull Sa INTEGRATED CIRCUIT ARBITRATOR OF MCA BUS AND USES OF SUCH A CIRCUIT.
US5454082A (en) * 1991-09-18 1995-09-26 Ncr Corporation System for preventing an unselected controller from transferring data via a first bus while concurrently permitting it to transfer data via a second bus
JPH05165762A (en) * 1991-12-13 1993-07-02 Toshiba Corp Dma controller
EP0559409B1 (en) * 1992-03-04 1998-07-22 Motorola, Inc. A method and apparatus for performing a bus arbitration protocol in a data processing system
DE69320508T2 (en) * 1992-03-04 1999-03-04 Motorola Inc Method and device for performing bus arbitration with an arbiter in a data processing system
US5341480A (en) * 1992-04-09 1994-08-23 Apple Computer, Inc. Method and apparatus for providing a two conductor serial bus
JPH05342178A (en) * 1992-06-10 1993-12-24 Hitachi Ltd Arbitration circuit and data processor using the circuit
US5313591A (en) * 1992-06-25 1994-05-17 Hewlett-Packard Company Computer bus arbitration for N processors requiring only N unidirectional signal leads
US5596749A (en) * 1992-09-21 1997-01-21 Texas Instruments Incorporated Arbitration request sequencer
US5553248A (en) * 1992-10-02 1996-09-03 Compaq Computer Corporation System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal
US5553310A (en) * 1992-10-02 1996-09-03 Compaq Computer Corporation Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems
US5535395A (en) * 1992-10-02 1996-07-09 Compaq Computer Corporation Prioritization of microprocessors in multiprocessor computer systems
US5299196A (en) * 1992-11-12 1994-03-29 International Business Machines Corporation Distributed address decoding for bus structures
JPH06282528A (en) * 1993-01-29 1994-10-07 Internatl Business Mach Corp <Ibm> Method and system for transfer of data
US5546548A (en) * 1993-03-31 1996-08-13 Intel Corporation Arbiter and arbitration process for a dynamic and flexible prioritization
EP0619547A1 (en) * 1993-04-05 1994-10-12 Motorola, Inc. A method of requesting data and apparatus therefor
CA2115731C (en) * 1993-05-17 2000-01-25 Mikiel Loyal Larson Dynamically programmable bus arbiter with provisions for historical feedback and error detection and correction
US5517671A (en) * 1993-07-30 1996-05-14 Dell Usa, L.P. System for designating a plurality of I/O devices to a plurality of I/O channels and connecting and buffering the plurality of I/O channels to a single system bus
US5600839A (en) * 1993-10-01 1997-02-04 Advanced Micro Devices, Inc. System and method for controlling assertion of a peripheral bus clock signal through a slave device
US6163848A (en) * 1993-09-22 2000-12-19 Advanced Micro Devices, Inc. System and method for re-starting a peripheral bus clock signal and requesting mastership of a peripheral bus
US5524215A (en) * 1993-10-05 1996-06-04 Motorola, Inc. Bus protocol and method for controlling a data processor
EP0654743A1 (en) * 1993-11-19 1995-05-24 International Business Machines Corporation Computer system having a DSP local bus
US5519838A (en) * 1994-02-24 1996-05-21 Hewlett-Packard Company Fast pipelined distributed arbitration scheme
US6026455A (en) * 1994-02-24 2000-02-15 Intel Corporation Architecture and method for providing guaranteed access for a retrying bus master to a data transfer bridge connecting two buses in a computer system
US5533205A (en) * 1994-03-30 1996-07-02 International Business Machines Corporation Method and system for efficient bus allocation in a multimedia computer system
US5526496A (en) * 1994-04-22 1996-06-11 The University Of British Columbia Method and apparatus for priority arbitration among devices in a computer system
US5572687A (en) * 1994-04-22 1996-11-05 The University Of British Columbia Method and apparatus for priority arbitration among devices in a computer system
US6256694B1 (en) * 1994-06-30 2001-07-03 Compaq Computer Corporation Distributed early arbitration
US5758106A (en) * 1994-06-30 1998-05-26 Digital Equipment Corporation Arbitration unit which requests control of the system bus prior to determining whether such control is required
US5568614A (en) * 1994-07-29 1996-10-22 International Business Machines Corporation Data streaming between peer subsystems of a computer system
US5598542A (en) * 1994-08-08 1997-01-28 International Business Machines Corporation Method and apparatus for bus arbitration in a multiple bus information handling system using time slot assignment values
US5634060A (en) * 1994-08-09 1997-05-27 Unisys Corporation Method and apparatus for high-speed efficient bi-directional communication between multiple processor over a common bus
US5559969A (en) * 1994-08-09 1996-09-24 Unisys Corporation Method and apparatus for efficiently interfacing variable width data streams to a fixed width memory
US6434638B1 (en) 1994-12-09 2002-08-13 International Business Machines Corporation Arbitration protocol for peer-to-peer communication in synchronous systems
KR0155269B1 (en) * 1995-01-16 1998-11-16 김광호 Bus arbitrating method and its apparatus
JP3320233B2 (en) * 1995-02-06 2002-09-03 キヤノン株式会社 Recording device
US5701313A (en) * 1995-02-24 1997-12-23 Unisys Corporation Method and apparatus for removing soft errors from a memory
US5511164A (en) 1995-03-01 1996-04-23 Unisys Corporation Method and apparatus for determining the source and nature of an error within a computer system
US5740383A (en) * 1995-12-22 1998-04-14 Cirrus Logic, Inc. Dynamic arbitration priority
KR100201325B1 (en) * 1996-03-30 1999-06-15 유기범 Method of rising frequency of bus clock in a multiprocessor system
US5842025A (en) * 1996-08-27 1998-11-24 Mmc Networks, Inc. Arbitration methods and apparatus
US5822766A (en) * 1997-01-09 1998-10-13 Unisys Corporation Main memory interface for high speed data transfer
US5970253A (en) * 1997-01-09 1999-10-19 Unisys Corporation Priority logic for selecting and stacking data
US5859986A (en) * 1997-02-20 1999-01-12 International Business Machines Corporation Bandwidth efficient method and means for resynchronizing a master and slave over a clocked, arbitrated, bidirectional multistate parallel bus using local data recirculation, wait states, and cycle stealing
US5862353A (en) * 1997-03-25 1999-01-19 International Business Machines Corporation Systems and methods for dynamically controlling a bus
US5996037A (en) * 1997-06-03 1999-11-30 Lsi Logic Corporation System and method for arbitrating multi-function access to a system bus
US6006303A (en) * 1997-08-28 1999-12-21 Oki Electric Industry Co., Inc. Priority encoding and decoding for memory architecture
JP4019333B2 (en) * 1998-02-13 2007-12-12 富士通株式会社 Head IC circuit and recording apparatus
US6047336A (en) * 1998-03-16 2000-04-04 International Business Machines Corporation Speculative direct memory access transfer between slave devices and memory
US6182112B1 (en) 1998-06-12 2001-01-30 Unisys Corporation Method of and apparatus for bandwidth control of transfers via a bi-directional interface
US6199135B1 (en) 1998-06-12 2001-03-06 Unisys Corporation Source synchronous transfer scheme for a high speed memory interface
US6330646B1 (en) * 1999-01-08 2001-12-11 Intel Corporation Arbitration mechanism for a computer system having a unified memory architecture
US6519666B1 (en) 1999-10-05 2003-02-11 International Business Machines Corporation Arbitration scheme for optimal performance
US8834864B2 (en) * 2003-06-05 2014-09-16 Baxter International Inc. Methods for repairing and regenerating human dura mater
KR101034493B1 (en) * 2004-01-09 2011-05-17 삼성전자주식회사 Image transforming apparatus, dma apparatus for image transforming, and camera interface supporting image transforming
JP2006155387A (en) * 2004-11-30 2006-06-15 Yamaha Corp Computer system
US8260993B2 (en) * 2006-06-27 2012-09-04 Thomson Licensing Method and apparatus for performing arbitration
GB2473505B (en) * 2009-09-15 2016-09-14 Advanced Risc Mach Ltd A data processing apparatus and a method for setting priority levels for transactions
US8713277B2 (en) * 2010-06-01 2014-04-29 Apple Inc. Critical word forwarding with adaptive prediction
CN111478840A (en) * 2020-04-15 2020-07-31 联合华芯电子有限公司 Double-rate arbitration relay device for bus system
CN113821470A (en) * 2020-06-19 2021-12-21 平头哥(上海)半导体技术有限公司 Bus device, embedded system and system on chip
RU2749911C1 (en) * 2020-12-25 2021-06-21 Акционерное Общество "Крафтвэй Корпорэйшн Плс" Hardware implementation of mechanism for using the same memory by multiple devices

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4481580A (en) * 1979-11-19 1984-11-06 Sperry Corporation Distributed data transfer control for parallel processor architectures
US4453211A (en) * 1981-04-28 1984-06-05 Formation, Inc. System bus for an emulated multichannel system
EP0340347B1 (en) * 1983-09-22 1994-04-06 Digital Equipment Corporation Bus arbitration system
US4967344A (en) * 1985-03-26 1990-10-30 Codex Corporation Interconnection network for multiple processors
US4837677A (en) * 1985-06-14 1989-06-06 International Business Machines Corporation Multiple port service expansion adapter for a communications controller
US4924427A (en) * 1985-11-15 1990-05-08 Unisys Corporation Direct memory access controller with direct memory to memory transfers
US4949301A (en) * 1986-03-06 1990-08-14 Advanced Micro Devices, Inc. Improved pointer FIFO controller for converting a standard RAM into a simulated dual FIFO by controlling the RAM's address inputs
JPS6366654A (en) * 1986-09-08 1988-03-25 Matsushita Electric Ind Co Ltd Synchronous bus
US4947368A (en) * 1987-05-01 1990-08-07 Digital Equipment Corporation Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfers
DE3782500T2 (en) * 1987-12-23 1993-05-06 Ibm SHARED STORAGE INTERFACE FOR DATA PROCESSING SYSTEM.
US5001625A (en) * 1988-03-24 1991-03-19 Gould Inc. Bus structure for overlapped data transfer
US5016162A (en) * 1988-03-30 1991-05-14 Data General Corp. Contention revolution in a digital computer system
US4987529A (en) * 1988-08-11 1991-01-22 Ast Research, Inc. Shared memory bus system for arbitrating access control among contending memory refresh circuits, peripheral controllers, and bus masters
US5006982A (en) * 1988-10-21 1991-04-09 Siemens Ak. Method of increasing the bandwidth of a packet bus by reordering reply packets

Also Published As

Publication number Publication date
DE69132344D1 (en) 2000-09-07
EP0476990B1 (en) 2000-08-02
SG42853A1 (en) 1997-10-17
EP0476990A2 (en) 1992-03-25
KR920006858A (en) 1992-04-28
CA2050129C (en) 1996-05-14
HUT58931A (en) 1992-03-30
BR9103929A (en) 1992-05-26
PL291778A1 (en) 1992-06-01
JPH04246758A (en) 1992-09-02
NO913707L (en) 1992-03-23
EP0476990A3 (en) 1993-08-04
CZ282214B6 (en) 1997-06-11
JPH0810445B2 (en) 1996-01-31
MX173460B (en) 1994-03-04
CS287491A3 (en) 1992-04-15
RU2110838C1 (en) 1998-05-10
PT99006A (en) 1993-10-29
HU215867B (en) 1999-03-29
AU8261291A (en) 1992-03-26
FI914429A0 (en) 1991-09-20
HU913024D0 (en) 1992-01-28
KR950014505B1 (en) 1995-12-02
CN1037553C (en) 1998-02-25
AU639589B2 (en) 1993-07-29
PL167608B1 (en) 1995-09-30
CN1060166A (en) 1992-04-08
FI914429A (en) 1992-03-22
NO913707D0 (en) 1991-09-20
US5195185A (en) 1993-03-16
DE69132344T2 (en) 2001-02-15

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