CA2050657A1 - Multifunction high performance graphics rendering processor - Google Patents

Abstract

MULTIFUNCTION HIGH PERFORMANCE
GRAPHICS RENDERING PROCESSOR

ABSTRACT
Disclosed is a multifunction cogenerator or graphics processor (10) for use in agraphics rendering processor. The graphics processor (10) comprises dual graphics engines operating in parallel, with one of the engines having higher operating priority than the other. The graphics processor (10) comprises a conics, vector, and area fill generator (43), a symbol generator (45), a bit block transfer operator (47), and a block texturing and complex clip mask processor (30) synchronously controlled by a multi-process scheduler (46). Included in the graphics processor (10) is a large display mem-ory (26) for receiving and storing program instructions and data generated by an exter-nal host processor (14), internal generators and processors, and a bit mapped memory (22) of a graphics display (24). The graphics processor (10) provides hardware specif-ic graphics functions and externally programmable general purpose processing.

Description

20~0~7 i.

MULTIFUNCTJON IIIGH rERI; ORMANCE
GRAP~ITCS RENl)ERlNG PROCESSOR

Cl'cOSS REFERENCE: TO REI,ATED ArrLICAl`IONS
The present npplica~ion is relate~l to contemporaneously filed pntent applications:
Serial No. _ ~11ed on , 1990, entilled, "Dual Programmable Block Tex-turing and Complex Clipping and Graphics Rendering Processor," Serial No.
filed on _, 199(), entitled "Dtlal llardwnre Chanllels nnd Tlnrdware Context S Switching in a Graphics Rendering Processor," Serial No. ~lled on 1990, enti~led "Concllrrent General Pllrpose nnd I)MA ProcessinL~ in a Grapllics Ren-dering Processor," Serial No. filed on , 1990, entitle(l "Integrnted l-lar(lwnre aenerntor for Areu l~ill, Collics nn(l Vec~ors in a Grnpllics Processor", Seriul No. _ filed on _, 1990, cntilled "I lnr(~wnre Bit 1310ck 'I ransfer Ol~crator 1() in ll Graphics Renderill~ Processor," Seriul No. - _ filed on , 19')(), enli-tled "}lardwllre Symbolo~y and Text aenerll~or in a Grapllics Processor," an(l Sérial No. filed on , 1990, elllille(l "I-lar(lwarc Multiproce:is Sche(llller in u Gruphics Renderill~ Processor," nll l)y Jolln M. I'euslee and Jeffrey C. Msllacarne, whose teuchill~s are incorporate(l hercill by reference.
nACK(. ROUND
The present invenlion relates generally to digil~ll grupllic display processors, and more particularly, to a multifilnction graphics rendering processor whicll provides botl multiple hardware based graphics generating capability and programmable general pur-2() pose processing.

2~06~7 Real time digital electronic displays are llsed in many applicalions sl-ch as mili-tary command and control workstations and air-traffic control systems. In these dis-plays, the displayed information typically comprises real-time processed data generated by a host processor adapted to receive real-time information from one or more radars, 5 communications systems and/or other data processors. These data are combined with one or more graphic primitives, such as polylines, vectors, circles, ellipses or poly-gons, along with generated alphanumerics, mask areas and texture patterns to provide a relatively easily llnderstood comprehensive graphic display on an OUtpllt device sllch as cathode-ray tube. In contemporary syslems, the various components of the grilpllics 1() displuy such as the graphic primitives, mask win(lows, fill textllrin~ and the like are provided either by a general purpose cnmputer based grapl ics generator or by a h,lrd-ware specific graphics generator. Of Ihese, general purpnse graphics generators offer system versatility but usua]ly mllst sacrifice some degree of system performance for ease of programming. On the other hand, llardware specific grapllics generators, called 15 cogenerators, provide good system performance and sacrifice progr.lmmability.Increasing demnnds on military command and control systems, militnry an(l civ-il nir-tr;lmc control systems and the like llave created n need for n higll performance mllltifunction graphics cogenerator wllich, in addition, provides a versatile and ensily implemented programming capnbility. It is tllerefore an ohjective of the invention to 2n provide a mllltifilnction cogenerator tllnt is n lligll performance two dimensionnl grapll-ics engine providing n modlllar SOIll~iOll tO n wide vuriety of graphic system npplica-tions. The multifilnction cogenerator is implemel)te(l as a in~egrate l circllit chi~ sh~g large scale integrated circlli~ logic. l he mullifllllclion cogenerator comhines botll gen-erul pllrl)ose processing cnl)nl)ilily wilh hardwllle il~lplelllellte(l grnl)llics nluolilllms cre-25 nting nll inllovative grapllics engille. I he mllltifllllclion cogenerntor performs n cOm-plete set of grnphic pl imitives or operllliotls ns well aS perfOrnlS getlCrlll pllrl)OSe pro-CeSSirlg fl~llCtiOllS. l`his Collll~inlllioll illlOWS a llser ~o perfnrm colllplex grnl-llics opera-liolls Wilh Illillin~al re~lllired plOgrllll~ 5. A Unilllle reatnre Or the mllltifllnCliOIl CO-generntor is provisioll of two separnte drslwillg chllnllels in pnrllllel witllin the snllle de-3() vice. rnch chnnnel provi(les n Coll~l~lllll I inl)llt register all(l cnn service a sep;ll;lle h -st processor if desired. The mllltifullctioll cogcllelntor selvices one chanllel at a higller priorily ~llnn ~he other solving mnlly plol)lems associnte(l wilh high perfmmnllce L~raPIlics displays.

35SUMMARY Ol; TIIE INVENTION
In the broader aspects, the invention is a multifilnction grapllics processor orcogenerator. The cogenerator is provided with input registers for receiving inpllt data 2050~7 and program instmctions from a hos~ processor. A large display memory is provided for storing inpllt data and program i~structions. Also provided is a large context regis-ter amdy for receiving and storing system attribute signals determining the cogenerator operating characteristics. Included are a plurality of internal primitive processors for generating primitive signal sets including primitives sllch as polylines, vectors, poly-gons, rectangles, circles, ellipses, symbols, alphanumerics, perfonning bit block trans-fers, and generating texture patterns and complex clip masks. A display list processor which includes a display memory interfilce unit is provided to control input and o~ltput of data, primitive signal sets, attribute signals, and program instruc~ions to and from tlle It) display memory and received from and output to Ihe host processor, primitive proces-sors, and the bit mapped memory of a graphic display.
In specifie embodiments of the invention, the primitive processors include a symbol generator for generatinU syn-l)ols such as alphanllmerics, a bit block transfer operator for moving and transferring hlocks of data, a conics and area fill generator for generating primitives such as circles, ellipses and polygons in both filled and ~Infilled formats, and a bloek texturing and complex clipping processor for generating texture patterns and performing a variety of complex clipping and masking fllnctions.

I~RIE:F DESCRJPT~ON Ol; Tlll~ DRAWlNGS
The various features and advantages of the present invention may be more rend-ily understood with reference to the following detailed deseription taken in con~jllnction with the accompanyin6 drnwings, wherein like reference nnmerals desi6nnte like strllc-tural elements, nnd in whicll:
l~ig. ! is a bnsic block dillurllln of a system thlll incorl~rllles n (lnal ch~ lel 2~5 mllltifllnclioll eogenerator of which the p resent invelltioll forms n pllrt;
Fig. 2 is a détuiled block diauraln of ~he mnllifilnc~ioll cogeller,l~or of Ihe present inven~ion;
Fig. 3 is a block din~rllm of ~h-: dlllll challllel Flr;O controller of the couenerator of r;i~. 2;
3() Fig. 4 is a block dia~rnm of the displ;ly memory interface nnit of the co~enera-tor of Fig. 2;
Fig. 5 is a block dia~ram of the display list processor of the cogenerator of Fig.
2;
Fig. 6 is a bloek diagram of the context registers of the cogenerator of Fig. 2;Pig. 7 is a block dia6ram of the block textllring and complex clippin~ processorof tlle cogenerator of Fig. 2;

20506~7 Figs. 8 and 9 are block diagrams of the mllltiprocess schedlller of the cogenera-tor of l~ig. 2;
Fig. 10 is a block diagram of the command generator of the eogenerator of Fig.
2;
Fi~. I l is a block diagram of ~he area fill conic and vector generl~tor of the co-generator of Fig. 2;
l~ig. 12 is a block diagram of ~he symbol generator of the cogenerator of F~ig. 2;
and Fig. 13 is a block diagram of the BITBI T ad(lress generator of the cogenerlltor1 () of Fig. 2.

DE:TAll,l~n l~ESCl~lPTlON
Referring to the drnwings F;l(~. I is a hlock diaL~rllm of a generalized graphicdisplay syslem including a dual channel mullifilnction cogenerator 10 of whicll the pre-sent invention forms a pnrt. The cogenerator 10 is a dllal channel hardware bused de-vice whicll operates in conjllnctioo wi~h one or more general purpose data processing systems sucl~ as a military comman(l and conlrol system. Briefly Ihe system com-prises one or more real time dllta processors 14 all(l o~her real lime datfl acculll~llatillg devices sllch as a radar system 1 fi an(l olller cogenerators 17. The host processor 14 2() an(l the ra(lar scan converter l 6 for example fecd d;lta into the co~enerntor 1() via a mullifilnction blls 18 where it is combined witll 6rapllics data gellerat~l hy the cogell-eralor I (). ri1`he cogenerator I () OlltplltS u complete set of data for ~enerll~inll Or " gra~
ics display via a 64-l)it bidircclionill inl~rconllect image luls 2() into ~ )it mal) mel~1-)ry 22 all(l Ihell hy way of a vide~- hlls 2:3 lo a disl)lay sys~elll 2-1. 1 lle co~ellenllol I () nlny incllldc variol~s otller inplll devices sllcll as Illnllllal inl)nl onllllll devices mllllil)le reill hne plocessors, hlllk memory dcvices all(l Ihc liiie.
Witll refclellce to l;la. 2 Ille c-)~ellelalor 1() is a hil ll perlorlllallce single chi gral)llics rellllerillg processt)l. Il ~encrllles mnllil)le ~rnl)llics prilllilives all(l perfolllls gellelal pllrpose processing l`nnctiolls. I he cogcnernlor accel)ls gral)llic comnlllll(ls 3() over n Illirty two bit bidirectional llosl inl)~t port from a processor sucll as Ihe hosl pro-cessor l 4 of FIG. I . The cogeneralor I () processes Ihese commall(ls and thell dl aws into the bit mapped memory 22. The cogellerlltor 1() draws into the hit mappe(l mem-ory 22 over ~he image blls 20. I)mwill~ is pcrforme(l I-y en~eril~ inary one an(i zero signals tdrnwilll3 ones and drawillg zelos hereill) into indivi(lllal mel11ory 10Ca~;OI1S nf the bit mapped memory 22. Typically ~he l it mappe(l mernory 22 l111S multiple mem-ory layers with the layers corresponding to color and inlensity of graphic display pix-els. The image hus 20 is a 64 bit bidirectional mlll~i-user l lls. The cogenerator 10 can 2 0 ~ 0 6 ~ 7 s draw graphic primitives such as symbols, polylines, rectangles, circles, ellipses, arcs, polygon fills, and per~orm bit block transfers (BITBLT) between the cogenerator 10, the host processor 14, and the bit mapped memory 22.
Directly associated with the cogenerator 10 is a tri-ported display memory 26.
S The display memory 26 stores all commands and parameters and includes appropriate logic required for the cogenerator 10 to filnction properly. The memory address space in a working embodiment is 4 megabytes by 32 bits. l`he cogenera~or 10 interfaces with either DRAMS, SRAMS, and/or P,ROMS. The display memory 26 is accessible by ~he cogenerator 10 display list processor 28, the cogenerator 10 internal graphics generator 34, and the host processor 14. Stored in the display memory 26 are two ~Irst in, first out (FIFO) memory buffers one of the buffers being assigned a higher opera-tional priority than the other and there being one buffer memory for each of two draw-ing channels. An address stack is provided for each FIFO buffer to store subroutines calls. An attribute stack stores all internal cogenerator attributes for hardware context 15 switching, a sin/cosine table for drawing graphics, and up to 128 font tables to draw stroked and/or dot matrix symbols and characters. A large display list region is also provided.
The display memory 26 is comprised of up to four million words of RAM or-ganized as 32 bit data words and appropriate buffer logic. The contents of the display 20 memory 26 may be organized ns shown in Table I below. The host processor 14 has the ability to perform random rends nnd writes nt nny address within the display mem-ory 26 address space. The cogenerntor 10 monitors the input of da~a from the host pro-cessor 14 to the display memory ~6 to synchronize llpdnting of dntn from the host p ro-cessor 14 with the output of ~6rnphics si~nnls therefrom.
TAnlJE I
MEMORY DATA
~B~

} DISPLAY l.lST

rONT TABLE

SINE/COSINE TABLE

35 ) Al-rRlBUTE STACK

20~0657 FIFO I

} SUBROUTINE STACK 2 INTeRRUl~ TABl,r #

I () ) UNUSED
n A d~ l channel I~IFO bnffer controller 38 4() interfaces the co~enerator I () tothe host processor 14 and is shown in Fig. 3. The Fll;O buffer eontroller 38 4û are responsible for performing all interfacing duties suell as proper halld shakin)3 whell the bus 18 is perforrning data transfers The host proeessor 14 is ahle to both read and write to the cogenerator 10 and the disl-lay memory 2fi. When the host processor 14 reads or writes to the display memory 2fi the ~Ir~o buffer eontroller 38 4() actunlly performs the read or write operations to the display memory 26 for the host processor ] 4. The FII~O buffer eon~Toller 38 4n is also responsil)le for arbilratill~ hi~ll nnd low priority channels to the cogeneratc)r 1() An address stnck is provided internally within the display memory 2fi to s~ore subroll~ine calls an at~ribll~es stnel~ IO store nll in~ernal ttributes reqllired by lho co~enerator 1() ~o perform har(lware context switcllinL~ a sine/eosine table of drawin~ eonies and primitives up to 128 font tnl)les to draw both stroked and dot matrix symhols nnd cl~nracters nl)(l n Inr~e disl)lay list re~ion Pig 3 shows n bloek (lin~rnl)) of the ~ O controller 3X 4n. l`he dll.ll clu.lnllel r~l~o con~roller 3~ 40 rec~:ives n con~n~nn(l fron~ e hc st proeessor 14. 1 h~ ch;lnnel 2 interfilce Irnnseeiver 7() accerl~s the dnln s~ddress nl~(l provides proller hnndshakill~
witll the hosl proeessor 14 ~o complel-: Ihe hlls ~rnnsler l`he chnnnel 2 in~elf;lee Irnns-ceiver 7() thell nctivates a clu.lllnel 2 reqllest~ A priorily con~rl)ller 71 mo~ ors holh 3t) chanllel 1 reg~est and channel 2 req~es~ aclivi~y. In ~his cnse channel I is idle an(l channel 2 has reeeived n eomrn.lnd for l ll ()2 The function of the cluanllel 2 hlterfnee transceiver 70 is to set priority nnd determine what kind of memory cycle to perform.
When the chal-nel 2 interface transeeiver 7() de~errnines ~he cyele type it tells the dis-play memory cyele requestor 72 to perforrn the cycle The priority controller 71 re-ceives a channel 2 request and loads the input da~a re~is~er 73 with the data sent from the host proeessor 14. The input data register 73 sends it s contents ~o the display memory cycle requestor 72. An address decoder 74 decodes the cllrrent host processor ~05~65~

address. The priority controller 71 uses this informalion to deterrnine what the host processor 14 is attempting to do. In ~his case a write to F~F02 is occurring. The prior-ity controller 71 selects the FIF02 write pointer from a F~FO controller 75. The priority controller 71 controls an address multiplexer 76 and selec~s the FIF()2 ~rrite pointer.
S The address multiplexer 76 sends the FTF02 write pointer value to the display memory cycle requestor 72. Now the priority requestor 71 commallds the display memory cycle requestor 72 to perfonn a write cycle to PTF02. The display memory cycle reqllestor 72 has the proper address and clata. Il now issues a cycle request ~o lhe displ;ly me-n-ory interface unit 35.
The cll;lnnel I transceiver 68 operates in mucll lhe same mnlll1er as the ch;llll1el 2 transceiver 7(). The Outp~lt data regisler 69 is used when the host processor 14 is read-ing data from the multifilnclion co~enerator I(). Tlle host processor 14 can read data from the rmlltifllnction cogenerator 10 or the display memory 26. In either case the dat;l that is to be sent to the host processor 14 durillg a host read cycle is stored in the olltpllt data register 69 before being sent to the host processor 14. The read cycle is completed wllen the data is sent from lhe Olltpllt data register 69 to either tlle clllll1l1el 1 or channel 2 transceiver 68 70. The transceivers fiR 7n then plDce the data onto the bus 18 thlls completing tl1e read cycle.
A display memory interface llnit 35 perfonms the actllal dislllay memory mem-2n ory cycles llnd is shown in l~ig 4. lt is essentially a tri-port memory controller A
display list processor 28 perfonns nll of tlle cogellerator 1 û comn1nlld nnd display list processing and is sllown in ~ig S. Commnn(ls nre sent to tlle cogener~ltor In from the host processor 14 The display list plocessor 28 Illlll(lles the variolls ways ~hal com-mnn(ls call be sellt ,0 the cogenern~or I n. rhc displ;~y list processor 2R in~erf;lces to tlle display memory 2fi usillg tho display nlClllory inlerfnce llnit 35 rca(ls comlll;lll(ls rrom the ~IPO bllPfers ns well as performs otller functiolls~ Wllen n COlllm;lll(l iS givell to tlle displlly lixt processor 28 it processes lhc comll1llll(l all(l deterl11illes what ~lctinn tn take 'I'lle cogenerator 10 provi(les mslny dil'rerellt cOIlllllands an(l se(luellces. 'I'lle llosl pro-cessor 14 can send comm~ln(ls to tlle nlllltifilllcli n cogwler;ltor I () lhrollgll I~II;Ol 3() ~ O2 or Ille display list region of llle disI)hly memory ~6. Tlle lisplay list processor 28 processes commands fTom any of lhese localiolls. Tlle display list processor 28 is also responsible for controlling ttle allribule slack in llle display memory 26 during con-text switches. Also the display list processor 28 conlrols bolh tlle cll.lnnel I an(l ch;ln-nel 2 subrolltine stacks also located in Ihe display memory 26.
Referring to l~ig. S a block diaL~ram of lhe display list processor 28 of lhe pre-sent invenlioll is shown The display list processor 28 comprises al) input data register 91 that is collpled to a command decoder 92 a display memory cycle requestor 98 and 2050~7 an address multiplexer and generator 99 for coupling of data there~o. The input data register 98 also has control lines coul)led to the command decoder 92 a display list command interpreter 93 first and second subrolltil1e stack address geneMtors 94 95 an attribute stack address genera~o~ 96 an intermpt h.lndler address generator 97 II-e dis-5 play memory cycle requestor 98 and the address mulliplexer and generator 99. The dis-play list command interpreter 93 is coupled to the 1~ 0 controller 38 4n by way of FIFO read request and status lines coupled to external computers such as the host pro-cessor 14 by way of interrupt lines and to the context register 42 and readback ~mllli-plexer 44 by way of attribute and data select lines. The data memory cycle re(luestor 98 10 is coupled to the display memory intcrrace unit 35 which in turn is coupled to Ille dis-play memory 26. The operation of the display list processor 28 is described in more detail below with reference to Table 1 and l~igs. 4-fi.
The display list command interpreter 93 provides the fiulctions of a concllrrentprocessing circllit an interrupt input circuit un(i a restore control circllit. The interrllpt 15 handler address generator 97 provides the functiolls of an intemlpt input circuit a nest-ed intermpt input circllit a reslore exccutiorl circuit and n multilevel nested hlterrllpt circuit. The first and secon(l subrolltille stack nddless generators 94 95 filnctioll as nested subrolltine circllit and pllsh down stacks. Tlle operation of these circuits is dis-cussed in more detnil helow.
2() Context registers 42 slore all of Ihe cogeneralor atlribll~es llnd are shown in ~ig. 6. These attributes define the currellt stnte of ~he cogenerator ln. The culrent state may inclu(lc ~1 lar~e nllmber of parllllletels sucl) ns: co~cnerlltor operlltiollal mod~; draw pointer posilion; fore~roull(l color; b;lcl;~rollll(l color; clipl)illL~ win(low dilllensiolls;
ctc. Tlle con~ellls of Ihe conlexl rel is~els 12 ale hllpor~an~ as they define Ihe l~rsonali~y 25 of the co~enelnlor 1~ t ally ~iven thllc an(l nll nt~ril)ll~es nre uscr l~ro~sramlllnl)le. I his L~ives ~1 llser consi(ierable flexil)ility h~ opera~illg Ihe disl)lay system.
Referring to T-i~. 6 a dcl~lilc(l hlock dill~lanl Or Ihe contexl rc~is~ers 12 isshown. t`he context r~l3isters 42 are compris~:(l of 21 altrit)llle r~gislers 1()1-1 lo I()l-21 alld anribllte re~ister load con~roller 1()2 all(l an a~tribllte mlllliplexer 1()3. I he con-3() text registers 42 are couple(l to the disl)lay melllory interf;lce unit 35 to the display listprocessor 28 and the readl)ack mlll~it)lexer 44 as in(lica~cd in l~ig 6.
To start a context switch the cogenerator 1 () processes a PUSI-1 at~rihlltes command. The display list processor 28 reads in a commian(l fiom the displuy memory 2fi A PUSH command is placed in~o either the 1~ 0 I-uffers or a displlly list. The 35 command decoder 92 (FIG. 5) detects a PUSI-I command and informs a display list command interpreter 93 that selects the attribute data bus input to the readback multi-plexer 44. This bus runs from the context registers 42 to the readback multiplexer 44 20506~7 as shown in Fig. 2. The output of tlle readback multiplexer 44 is sent to the display memory interface unit 35. The display list processor 28 selects the attribute blls for in-put to the display memory interface Ullit 35 so all the cogenerator attributes are sequen-~ially loaded into tlle attribute stack located in the display memory 26. The attribute S stack is a IK block of memory broken up into 32 tables each having 32 entries. Each table holds one cogenerator context or state lypically with some llnused entries.
Once the attribute bus is selected for input to the display memory interface unit 35 the command interpreter in the display list processor 28 sends the attribute selec~
code to the context registers 42. The interpreter cycles througl1 21 codes to extract all 21 attribute register values out of tlle context registers 42. This l1appens sequentially to perform the PUST~ operntion. Tlle attrihute select code connects to Ihe attribllte mlllti-plexer 93 in the context re~isters 42. I`he first code sent selects attribtlte re~ister I for outpllt. Tlle attribute mllltiplexer 93 drives ~he data to lhe readback multiplexer 44. The first attribllte value is at the input to the display memory interface unit 35. The com-15 mal1d interpreter in the display list processor 28 controls the attribute stack address ~en-erator 96.
Also provided is a readback mllltiplexer 44 whicllis a large datn multiplexer. It is used to mllltiplex data to the display memory interface unit 35 wi1ich is directed to either the display memory 2fi or back to the host processor 14 via bns 1~. Three read-2() hack dat~l sollrces are the context re~islers 42 a ~rapllics ~enernlor 34de~1lle(1wil1lin the dashed I lnck in I~IG. 2 and n blocl; lexturin~ and complex clippin~ processor 3n.
If the data is intended for the host processor 14 it will he sent throlllsh the l~lr O buffer controller 3~,4n by the displny mel1l-)ry interface llnit 35. The grllpllics generlltor 34 is connected lo lhe readlmck mllltil)lexel )4 for variolls cogenerlltor 1() drawillg 0pcrll-lions. The block textllring an(l com~ x clipping proccssor 3n IIISO SCn(lS dllttl to the readbllck multiplexer 44 for vnriolls co~ellerator 1() nperntions. I)ctails of Ihc hlock tex~urillg alld complex clipping processor 3() ale sllowll in l-ig. 7.
Referling now lo ~IG. 7 thc l)lock lexlllrill~ nn(l coml)lcx clipl)ing plocessor3() is shown in more delllil in conjllllclioll wilh relalc(l portiolls nr the cogener;llor 1().
3() l`llel)locklexlllrill~an(lcolllplexclil)l)illg processor 3() compriscs Ihlcc fiu1cliollal sec-lions: a textme generating seclion I I () a reclanglllar clip seclion 1 11 and a comhina-tional lo~ic section 1 12.
Inclll(led withill the lexture gener;lting seclion 1 1() is a m;ll)pillg processor 1 13 al1d an address processor 114. l`o perform a texturillg filnction tlle next bit mapped memory 22 x y address is applied to the map processor 113 this address being thenext address in the bit mapped n emory 22 to be written to by the cogenerator 1(). Si-multalleously a programmable texlure pattern size si~nal and the display memory 26 2 ~ 7 ]o address of a desired text~lre pattern are entered into the mapping processor 113 and ad-dress processor 114, respectively. The texture pa~tern size is specified as a rectanglllar parameter measured in pixels and in a working embodiment must be defined as a square pattern having pixel dimensions that are multiples of 16, i.e., 16 by 16, 32 by 32.
In a working embodiment, the mapping processor 113 and tl-e address proces-sor 114 are provided in dllplicate enabling the implementation of two texture patterns at any one time. With the texture pattenn sizes and texture pattern addresses specified, ~ile mapping processor 113 is coupled throllgh the ~1~0 buffers 32, 33, display memory interfuce llnit 35 and display list processor 28 to the appropriate address or addresses in the display memory 26 which contain the textllre patterns. The display memory may contain any desired nllmber of textllre patterlls. These patterns can be down loaded into the display memory 26 from the host processor 14 or otherwise programmed into the display memory 26. However, at any one time, only two texture patterns are directly addressed by the mapping processor 113, this being accomplished through nppropriate address pointers. The area fill, conic and vector generator 43 symbol generator 45, or BITBLT generator 47 generate all primitive profiles, area fill, and associated clip mask signals. These signals are applied via a data bus to one input of an AND logic filnction 1 15 in the combinational logic section 112. The texture pattern signals are OUtpllt from ~i tlle display memory 26 throllgh the (lisplay memory interface Ullit 35 to other inpnts of 2() tlle AND filnction I lfi. The result of the logical comhinntion of prill1ilive, prhl1ilive clip rmask and ~extnre signals by the logic section 112 is n textllred primitive signnl set.
If only one texture pattern is regtleste 1, the primitive or symbol will be comhill-ed with Ihe single textllre pattem. lf two text~lre pnttcrlls huve heen specifie(l, the tcx-tllre pllllerl-s cnn ~x imlllement :d sel)al nlely or Ihey can be colnl-ine(l. I;or exall-ple, if oné textllre pattern comprises horiznlltal lines an(l the secon(l c~mlprises vertical lines, these two lextllre pallerns cml be npl-lie(l indivi(lnally t o differellt primilives to pr~lllce prillliliVeS hllVil)~ a llorizolltlll linc texlllle pn~lern all(l l)rilnilives havin~ a ver~ical linc lexlllre pallern. l`he two text~lre patlcrlls can also lle coml-inc l. I his will pl xluce a prill1ilive willl a checkel~Klnr(l lexlnlt:(l pJlllerll. A plilllilive call nlso l e ren(leled wilh 3() no lextllre palterll lllerel)y provi(lillg nl) to fo~lr texlurcs llsing two dircctly accesse(l texlllre pattelns. rt will Ix furlher al)l)leciale(l Ih;lt the ontpllts fiom the are.l fill, conics, and the vector generator 43 symbol gellel ator 45 and BlT131. T gener.llor 47 inclllde clip mask signals which ne~ate ontpllt Sigl als or pixel sigllals outside of Ihe ~enera~e(l prhnitive. Th~ls, the textllre paltern will appear only wilhh~ Ihe ~lrimilive or syml ol.
It will filrther ~x appreciated Ih.lt if tl e conic, vector and nrea f ll genel alor 43 outpllts an o~ltline primitive, that is, a primitive that is only an olltline and not a solid, Ihe texture pattern will be applied to only this ou~lille. ~or example, if the conic genera-I l 2 ~ 7 tor 43 generates an ellipse outline primitive tllis primitive combined wilh a textllre pat-tern comprising horizontal lines resu]ls in an ellipse drawn as a series of broken lines.
The cogenerator 10 has the ahility to render any primidve into ~he display mem-ory 26 as a series of ones or zeros. This capability enables the use of textllre patterns to 5 create arbitrarily shaped or "complex" clip masks. Complex clipping is the ability to clip images to randomly shaped regions such as circles pie shapes polygons and the like as well as rectanglllar regions. This capability solves the prohlem of overlapping various ranAomly placed display windows on a display. Complex clipping provides a way to update non-rectanglllar regions in one operation.
I() Another fi~nction of lhe block lexturing and complex clipping processor 42 is reclang~ r clipping 'l'he block textllring and coml-lex clipping processor 42 provides two modes of rectan61l1ar clipping. These are insi(le clipping and olltside clipping.
Tl1erectangularclipsection 111 inclndesasetofregisters 116a 116b 117a 117h used to programmably define the size and localion of ~he rectanglllar clip window sllch as the window. The rectanglllar clip window is defined hy two points the llpper left hand corner and the lower right han(l corner. This specifies the rectanglllar re~ion ~hat ral1ges from () to 4 ()95 pixels in bo~ e x an~l y direclions Tlle cogener;l~or 1() UlltO-matic~lly inpllts the next bit mapped meIllory 22 ad(lress into the rectullglllar clip regis-ters 86-92 If réctunglllar clipping hus becn uctivuled a rectall~lllllr mask generutor 118 controlled l-y the cogenerutor 1() untol1laliclllly clips us it druws any primilive As Ihe drawing u(l(lress chul1ges lhe co~el1era(or 1() con~ l;llly perforlns coml)arisol1s he-lween Ihe cllrrenl l)it Inappe(l n~elllory 22 lld(lless un(l x y llixcl nd(lrcsscs (Icfincd hy Ihe clippill~ win(low bonll(lury If tll~ pixels nrc n1cl11l)ers nf Ihe rcgion IO hc clipl)e(l tpixels insi~le ll~e clip window) Ihc co~cl)erlllor 1() will sinll)ly iL~nOl'C IhCSC pixcls illld conlilllle processing. If Ihe pixels nre mell1l)ers of Ihe clipl)e(l rcgion Ihc co~cncrnlor 1() Ihell wriles int(~ the bil n1al)l)e(1 mcll~ory 22 unII conlinllcs processing Ihe prin~ilive~
Il will he seen Ihut it is possible for u druwing opcrllli-)n pcrforl1lc(1 l-y Ihe coL~cllerulor I () to enler ul1(1 exit u clipping win(low n1lll~il)le lin1es. 'I'<> pcrfolln Ihis fnllclioll Ihe 3() reclunglllur clip sigl1als olllpllt fiom Ihe rcclullglllar mask generator 1 18 are thell com-bined with the textl~red primilive sigl1~l1 set ontl)llt from Ihe texture generating section 11() in the AND logic funclion 115 'I llis resnlts in Ihe rectanglllar clip window over-laying a textured primitive.
As a furtl1er feature of the invention Ihe clipping f~lnctinn al1(1 Ihe reclanglllar clip functiol1s are performed both in the conventional manner of oulside clipping in whicl1 pixels exterior of a primitive are clipped or in Ihe reverse manner of inside clip-ping in which pixels inside Ihe primilive are clipped. This is effected by a program-2 ~ 7 mable clip in/clip out control attribute which reverses ~he masking filnction for the rect-angular clip function or by reversing ~he genera~ion of drawing ones and drawing ze-rc)es patterns as described above for complex clip windows.
To provide for "picking" the rec~angl~lar clip filnction fur~her includes means for 5 comparing primitives and clip window boundaries. As tl)e cogenera~or 10 processes a primi~ive and simultaneously performs rectangular clip mask func~ions ~he cogenera~or 10 de~ermines whether a particular primitive lies within a clip window. This function can be used to automatically expanA or contract clip windows to match primitive dimen-sions and is indicated by ~he outpu~ of s~a~lls regis~er 119.
1 n The gruphics generator 34 genera~es cogenerutor primitives and symbols nnd performs bit block transfers (BlTBl~Ts) The grnphics genera~or 34 includes u ml~process schedlller 4~ shown in l~igs. 8 and 9 a commllnd ~eneril~or 41 showll in Fi~.
1 () an aren fill conic and vec~or genera~or 43 shown in Fig. I 1 a symbol generaîor 45 shown in Fig. 12 and a BIT131 T ad(lress genera~or 47 shown in l~ig. 13. The area fill 15 conics and vec~or generator 43 crea~es digi~al signllls representing grapllics l)rimi~ives snch as r)olylines rec~nngles circles ellipses ulld poly~ons und uleil fills. These primi-~ive signals nre next combined wilh other digi~al signuls represell~in~ alpllanlnneric and o~her symbols which are genera~ed in u symhol generu~or 45 un(l wi~h ye~ u ~hir(l se~
of signals generated by block textllrin~ und complex clipping processor 3n to pro(lllce 20 lhe final se~ of signals which is ~hen ~runsferretl hy ~he BlTBl~T ud(lress generll~nr 47 in~o specified pixel ad(lresses in ~he hi~ mal)pe(l melll(Iry 22. 'I'ypicully ~he l-i~ nl;lplIed memory 22 has mllltiple memory luy~rs wllich set the color alld h~ llsily for ~he ~rapll-ics displlly dcfille(l for eucll pixel loc;llioll lh~leill.
'l'lle nlllllil)rocess sclle(llllel lfi conlrols dalil ~ransr(ns l~lweell el~lnellls Of lll~
25 cogellerlllor l (). Tlle mllllil)rocess scll(:(llller 4fi llses u hrllnclle(l sclle(llllel ul)l)loll( ll lo conlrol lhe several operlllions an(l ul)l)ly cerlnin chara( lerislics of ~l sor~wllre ol)erlllill~
sys~ erel(I.'I'l~i~l)lolllol~ r~l"(~io,~,~lil,(l~l,c"(l~,~c~ w~ellvlllio~lsco~ rll~or It) S~ S 1111(1 I-lovi(l~s Il Illt:Clllllli~lll ror i"~ "~i~ (o~ ;llioll.
'l'h(: filnc~iolllll chllrllc~elis~ics oF lhe har(Jwllre nlllllirlrocess scll-:tllllel ~lfi of llle 3~) present invention ale showll gellerlllly in l~ . As sh(lwll lhcrein ~he sche(llller 4~
con~rols ~he flow of (lutll to and ~hroll~llollt ~he severul d.l~a ~enera~illg/l)rocessill~ und conlrol snhsystems comprisill~ L~ral)llics ~enerator 34 und ~he block tex~nrin~ und clip mllsk ~eneru~or 30. 'I'his involves sclled~llillg (enlll)lill~ ) one or more of ~he six cOn-tlolle(l s~lhsystems when ull require(l inpll~s ;Ire ;Ivuil;ll)le for cllrren~ operulioll all(l 35 blocking (disnbling) ~he con~rolled snl)sys~em(s) when some o~her snbsys~em is utili~-ing its (their) current ou~put.

2~6~7 Tn operation, instmctions received from Ille cogenerator I n keep the hllrdware scheduler 46 cognizant as to what operation is required by each of the controlled sub-systems and when. E~ach of these s~lbsystems is allowed to begin operation as soon as its local inpllt requirements are met and its culTent outr)llt is no longer needed. Tl1is S serves to decollple each of the individllal controlled units from the overall tasl~, thlls al-]owing the operation of each of the six parallel controlled subsystems to proceed as soon as it is able. This approach removes ~he need for synchronous reguest/acknowl-edge handsllaking and its associated overhea(i dnring data transfer between operalionS.
Tnstead, the hardware multiprocess schedlller 46 of the present invention folms ll com-10 binational logie function lhat respon(ls immediately Witl1 enable and load strohes when-éver new input data are needed by one of tl1e controlled subsysten1s.
To fucilitflte eommand and eon~rol hl Ihe emlx)diment illuslrate(l, the hllrdw;lre seheduler 46 comprises a control inlerface blls 121 which curries command and control signals from an instruction deeoder 122 and stalus infom1ation transmitted from un im-15 age bus command generator 41, the conics/vector/fill generator 43, the symbol genera-tor 45, the BITBLT generiator 47, the dllal hlock texturil1~ and clipl)in~ filnctions of texturin~ elipper 30, and six task eonlrol units 123. Command and control is applied by means of eueh of the task control fin~elions lltilizhlg similur S~UI~S words for euell of the filnctions controlled, with flags indicating eilher each funclion's readiness to accept 20 new inpllt, or the availubility of new Olltpllt therefroll-. Complex l)arullelisnl is UCCO111-plished by ereatinL~ an environment in whicll Ihe segllenced fin~ctions ure free to per-fom1 their locul processing until a trunsfer operatiol1 tn or rrom anolher cogener;llor filnction is required. In the present inventioll it is not neeessary to nccollllt for every possible combinlltioll of the stntes of every se(lllence(l fnnction to ensllre thllt nll of Ihe 25 conlr(llled filnclions work togetller.
As fimclionally illuslrllled in l~ig. 9, eacll of the six tusk conlrol unils 123 com-prises fonl sepnrllle suhfilllctiolls whicll, whell tukell us u whole collslitllt(: tlle control mellns implell1ellte(1 Iher~l)y. 'I`hese sllbrllllcliolls coml)rise SOIIICC stntlls, deslill;ltion s~ullls, done slnllls nn(l mncrosegllellce Sl;ltllS. ~ source StUtllS mollitor 124 hl(lic;ltes 3() the avllilllbility of valid inputs to the conlrolle(l sllhsyslem for filrther processing, n des-tinution stalus monitor 125 indic;ltes whelller or not the destin;ltioll is reu(ly to receive the processed datu, and a dolle status nlol1itor 126 indicutes whetller or not the current processing operation in the controlled subsystem hus been completed. Ttlese three sta-tllS conditions are eornbined in an OUtpllt logic unit 127 to enable the particlllar grapllics 35 subsystem under control. When mlllliple input or OUtpllt operations are required, a macrosegllence state register 128 keeps truck of these operations to prevent lmder or over processing of the data.

2~306~7 In practice, whenever a controlled ~ask filnction is to receive new data, the scheduler 46 determines if a valid inpllt ready signal has been received from the af-fected cogenerator subsystem If this is the case, the unit is enabled and the data are in-put from the bus 18, or from other diata interfaces hetween sllbsystems. At the con-S clusion of the data inpllt cycle, the controlled subsystem starts processing the d.lta re-ceived, in accordance with the particuliar instmctions received by way of the data bus 121 and the instmction decoder 122. When Olllpllts that reslllt from processed inpllt data are ready to he passed to anothel sllhsystem, the processing UlIit transmits an "out-pllt ready" flag. Several inputs, whelller received concllnrently or in sequence, may be 10 reqllired to create a single olltput. When all reqllired ontl)llts for a given sllbsystem Ini-croseqllence operation are complete(l, the processing unit transmits a "done" flag. Mul-liple s~lbsystem microseqnences may he reqllired to coml)lete the macroseqllelIce for the currellt cogenerator instrllction.
When the unit to whicll the data are dilected llas emilte(l a vllli(l inplll rea(ly sta-15 tllS, the recipient snbsystem is asynchrollously enabled by the the appropriate task con^trol nnit 123 wilh zero clock delaly lo receive theln and, if necessary, process it. If Ihe recil)ient ullit does not show a valid inl)llt ready statlls, then the correspon(lin~ taslc control filnction captllres tlle olltpnt rea(ly filnction plllse in a macrostate register 128 to indicate Ihat a data transfer is penditlg In either case, whenever llle receiving nllit 2(1 sends a valid input ready statlls, it is asyncllrollollsly enal)led and ll~e waliting dilta are then transferred thcreto. Tlle inl)llt rea(ly signal acts as a ~lag to in(licate tlle cnnrent readiness slatlls of ~lle controllcd llnil~
Referring to Fig. In, a hlock diagrallI of the image bns (113US) comlIullld gen-erator41 is shown. ThecollIlllall(l gcllerator41 is resl)0nsil)1e forperforllling 1130~
25 comtlIlln(J cycles. 'I`hese conlllIall(l cyclcs arc perf(lnlIe(l hy tlle cogcllellltor 1() over the imllge blls 2() all(l sent lo the hit mlll) nlellIory 22. 'I'h(:sc comllIall(l cycles are perforlll-ed to initinlize ~m(l start nl) thc hil map mellloly 22. 'I'hey arc perrorlllc(l hy Ihe co~ener-atOI 1() al Ihe reqllcsl of Ille host processor 14. 'I'his allows Ihc hosl plo(:~:sso~ 1~1 to configllle Ihe bit map metIloly 22 to a sllllcture Illat works in hnnn(lny wilh tlle pallicll-3() lar grnl)llics system in nse. Tlle comlllall(l ~enerlllor 41 receives comltlan(l dala frolnthe display memory interface llnit 35. ï'he data is loaded into the input registcr 77. The commllnd sequence controller 78 ncknowledges that the data has heen received to the display memory interface llnit 35. The commallll sequence controller 78 thell sends comtnand type information the the OUtpllt multiplexerhegister 79. the inpllt register 77 35 sends the command data to the olltpllt register 79. The command data an(l command type infonmation are comhined at the olltput register 79 an(l senl lo InUS interface 55 20~0~

(Fig. 2). the command sequence conlrol 7~ Ihell instnlcts the T13l~S interface 55 to per-forsn tlle command cycle over the image bIls 20.
Referring now to Fig. I l the area ~111 conic and vector generator 43 calculatesmathematical solutions for drawing geometric primitives. Tn overview the area fill 5 conic and vector generator 43 is a single circllit whicll generates vectors reclangles circles ellipses and polygon area fills. The basic buildil1g hlock of the generator is a digital differential analyzer (DDA) 131 wllicll in operation accumlllates fract;onal (subpixel) components of x/y coordinate data and signals when tlle accumI~ ion over-flows one or anolher pixel boundary. I nis occurrence causes tlle syslem to increment 1() or decrement tlle x and y coordinates Ihat in(licale Ihe pixel address lo be lou(le(i or druwn in Ihe bit mup memory 22. In ils most ~enerul form tlle analyzer 131 llas a general purpose architecture comprixing inpllt nealls wllicll feeds input datll an(l in-structions into at least two digital differential multiplexers or comparators 132 an arith-metic logic llnit (ALU) 133 and a regis~er file 134 comprising two registers and coun-ters 134a 134b.
In operation the compuralors 132 acIlllire x all(l y duta l y wuy of Ihe co~encr;l-lor 1() and compare these to x and y pixel posilion dllta stored in regislers 134. Whell-ever eitller the x or y data stored in the registers 1 34a and coullters 1 34b in(lic;lte thllt a pixel bollndary l1US been crossed the l)DA 131 olltpllts move directioll conlrols for Ihe 2() next pixel ad(lress This process is conlilllle(l ulllil Ihe primilive sln.ll)e is completed In îllrlllernllce of tllis fIlnctioll Ille area Rll generalor 43 also compriscs us conslilllellt purts thereof u paran1etric collntcr 135 a sin/cos fetch llnit 13fi ~In a(l(lress collnler 137 nn(l a horizontal line generalor 13X 11l Ille configllrlllioll illllslraled in l-i~ 11 Ille sys-lel11 PrOV;(ICS ft)r COnS;(ICrIII)Ie VCrSUI;I;IY ;11 SCII;I1L~ IIP SI)IIII;OI1S f )r IhC SIIbIIII1CI;OI1S
25 llse(l lo col1lpllle Ihe variolls geoll1ell ic t (IllaliOllS llSe(l Willlill IhC syslcnl.
Tlle symbol gellerator 45 gellelules all)lla nllll1cric symlx)ls. A delaile(l blockdiagrlln1 ol the syml)ol an(l lexl gener;llor 45 is :;l1I)WI1 in l~ig 12. I he busic filnclioll Or Ihe syml~l alld text ~eneratnr 45 is lo nccel)t syml)ol collllllllllIls froll1 Ihe (lisl)l;ly nlcln-ory interf~lce llnit 35 (Pig 2) ulld generate tlle synllu)ls all(l/or lext ch.lrncters. I`hese 3() are refe~red to as simply symbols heleillnrter~ As Ihe syml)ols nre drllwn they are sent to Ille block texturiIlg and complex clipl)er processor 3n. Inilially when Ihe symbol generator starls to clraw a symbol il accesses an appropriale font lable in the cogenerator 1() displuy mel11ory 26 l he display nlemory 2fi conluills the necessuly inronnalion to draw a desired syml~ol The cogeneru~or 10 accesses display memory 2fi throllgh dis-35 play memory interface Ullit 35 Referring again to Fig. 12 tlle symbol generator s inpllt data register 150 is usedto store all incoming duta from the display memory interface unit 35. This data includes 2Q~0~5~

symbol commands symbol generator programming data symbol data fetched from the display memory 26 and font table definition at~riblltes. This register lSn temporarily llolds this inforrnation llntil it is rouled to the proper part of the symbol generator 45.
The display memory address generator 151 is used by the symbol generator 45 S to address the display memory 26. Tlle symhol generator 45 performs read cycles from the font tables in display memory 26 when drawing symhology. The display memory address generator ISI contains an address counter. Tlle address is forrned from the current font value and u symbol entry colmter. The font value is input to the disl)lay memory uddress generator ISl from a font selection controller 84. As mentioned ear-10 lier when the symbol generator 45 is lold to (lraw a symhol from a new font tahle itreads in new fo~lt table defil1ition atll-il)lltes. The display memory address gener;ltor ISI is used to address these values as Ihey nre rend into the symbol generator 45. The symbol entry counter is simply the cllrrent posilion that tlle symhol generator 45 is at when drawing a symbol. The symbol generator 45 performs multiple reads from dis-15 play memory 26 when drawing n synll ol. When n symhol is drawll the sylnbol gener-ator 45 addresses the symbol data starling at the first location of that symbol all(l se-entially read in symbol data llntil the syml)ol is complete~l. I`he sy~ ol enlry coullter is incremented for each symbol dala vallle rend.
The font selection controller I S2 contains registers and conlr)urators. It s main 2() filnclion is lo store Ihe cllrrent font tal)le anIl sen(l it to the disl)lay melllory a(l/lless gen-eralor 151. Also it mllst compare ally new font tal)le that is sent to the syml ol gellera-tor 28. If Ihe new font t~lhle code dil`rers from the cllrrent co<le Ihe f nt sele( tion Coll-troller 84 inforll1s n synll~l controller~ l`his Wlly the new font defillition may hc read inlo Ihe syml)ol gelleralor 4.~ hefore synll)ols call he drawll fronl the new font tal)le.
25 I`he rOI~l seleclion conllollcr 152 reccives ~Illrihllles from Ihe colltcxt reL~istels 4~ wllicl provi~es f~nt tnl)le infom~utioll.
I`he typewrilercl)nlroller 154 conlllills louic 10 COlltl~l Iheco~elleralor 1() Iyl)e-wriler fmlctions. l he context registers 42 store the coL~el1erator 1 () attril)lltes alld send the typewriler informlllion lo thc tyl)ewriter conlroller 154. l his informalioll inclll(les 3(1 sllch Ihin6s as Ihe cllrrent typewrite m(~le the carrin6e retllrll c~le line feed c-xle allto line feed code typewl iter direction allto symlx l spacinL~ etc. ï`he typewriter controller 88 monitors incoming symbol data when each new symhol is to be drawn. If a carriage returll or u line feed code is detecte(l it informs the syml ol controller 153. It tells the symbol controller 153 what the typewriter direction is. When a symbol is completed it 35 tells the symbol controller lSS what symbol spacing to use for the next symbol. The typewriter controller 154 helps the symbol controller 86 posidon lhe symhols properly to provide all the typewriter feanlres mentioned earlier 2~3~7 A color mllltiplexer 155 receives back~roulld and foreground color information from the context registers 42. The color multiplexer l.S5 is controlled by the symbol controller 153. The OUtpllt of the color multiplexer ] 55 is sent to a bit map memory OUtpIlt data re~ister 156. This value is used as the colnr value for Ihe symbol whell it is 5 drawn. As mentioned earlier the cogenerator l() can (Iraw two color symbols. Tlle color multiplexer 155 allows the symbol controller 153 to select either background or foreground color depending upon wllether a symt ol is being drawn or a background cell is being drawn. Also when inverse video symhols are drawn and foregronlld and background colors are reversed by the symbol conlroller usillg lhe color multil)lexer 1() 155.
Tlle symbol a(l(lress generalor 157 is whele Ihe symhols are aclually rendered.
Ttle symbol address ~eneralor 157 drllws bolh dot matrix synll ols and stroke codell symbols depen(ling on what is required. The syml)ol address generator 157 contllins re~isters, coul)ters, comparators and controllers. It is controlled hy the symbol con-troller 153. l'he symbol controller 153 tells the syml)ol nddress ~enerator l.S7 whell to drllw symbols and backgroun(l cells 157 and when to space syml)ols, perfol-llI a car-riage retIlrn and/or a line feed. The symbol atldress L~enerator 157 provides feedback to Ihe symbt)l controller 153 abollt its current state. l'he symbol nddress ~enerator 94 is told whilt Ihe typewriler direction is hy lhe typewriter controller 15~1. The syn~lx l all-2() dress genelil~or 157 also perfolms IhC sculing ~In(l rot;l~ion of lhe syml)ols if ~his is re-tlllire(l~
rhe symlx~l controller 153 is Ihe m~lill colllrollcr of Ihc syml)ol L~encr;l~or 45. It must insule lhnl all lhe ful-clions of lhe symhol nll(l lexl generalor 45 work in h;lrlllolly lo prod~lce symhols. It oplimi~es lhC performilncc of the symtx)l llnd Icxt g(,ncra~or 4.S
2.S hy keepinL~ all Ihe pil)cline s~ages full lln(l nll the l;lnclions llclivcly perrnllllilltd lasks. It londs the inp~lt dlltll rcgister 15(). It conlrols lhe displ~ly memory lld(llcss gcllclallor 151. It conlrols the symht)l n(l(lress ~senerlltor 157 llnd color mlll~il)lexer ~)(). It lon(ls the displlly memory outl~llt register I Sfi. It mllst hlln(lsllilke with Ixoth the mllllil)rocess sche(llller 46 nll(l the texturing/clipl)cr processor 3(). It monitors StlltllS from all lh~
3() l;lnclions in Ihe symhol ~enernlor 157 It allso hns inpuls from Ihe conlext re~islers 42 wllicll are symbol altril)lltes derlning nl.lny filnclions lI~at need lo he performed in line wilh the current cogenerator 10 state.
Tlle outl)llt register 156 is the final pipeline stage of the symbol gener.ltor 45.
As symbols are drawn, the display memory OUtpllt register 156 is loaded by the symbol 35 controller 153. It stores pixel address and color infolmlltion which is sent to the textur-ing/clipper processor 30. Eventually this information is sent over the image bus 20 by 2~5a~7 the cogenerator 10 and drawn into bit mapped memory 22. rrom tllere it is clisplayedon video display 24 as symbols and/or characters Witll all the features descrihed earlier The BITBLT address generator 47 provides a general purpose mechanism for moving rectangular blocks of image data in the bit map memory 2 alld tlle display S memory ~6. Fig. 13 shows a top level block diagram of tlle hit bollndary block trans-fer address generator 47 or BIT131,T operator 47 of the presen~ invelltion. As showll, the Blll~LT operator 47 comprises three major fimctional blocks; a read/write com-mand sequencer 161 comprising data maniplllation means, an address generator 16,and a 64-bit data path 163. Functionally, the read/write command seqllencer 161 ~en-I() erates all requests for external memory cycles to the display memory '~o and the bitmapped memory 22. While n word ali~ned block trallsfer may in~/olve only siml)le READ/WRlTe cycles, non-wor(l aligne(l lransf~rs muy involve l-onn(lary exceptions an(l thus req~lire altdilional cycles lo collecl or o~llp~ll lhe necessary dala ~nr example, dat" from lwo source words may be req~lired lo form lhe first deslinalioll word of each 15 horizontally scanned line. The macrosequence whicll controls lhe individual microse-q~lellces for each READ and WRlTr CYCLE control ~eneration then l ecomes READ/
RE~Al)/Wl~lTe Also, a given sit~lalioll may reqllire tllat the dal;l from one so~lrce word be read into two destination words all(l, in this event, tlle m;lcrose(lllellce hecollles READ/WRlTE/WRI'rE. As a praclical maller, nll pe~rnlltalions of one or lwo re;l(is nnd 20 writes nre required to sllpport slrbilrary l)it bollndary mappin~s belween sollrce nlld des-tinalion dala To provide lhis Cllp;lhilily~ lhe read/wrile command se(luellcer 161 inl)llls two flugs from lhe nddress L~enerntor 1~53 lhal in(lic;lle whell)er lwo snllrce or Iwo desli-nalioll wor(ls are reql~ire(l for lhe cnrl~llt m;lcro cycle Detailed descril)lit ns of thc al)ove-(lescril~e(l porlinlls of Ihc cn~eller;lll)r 1() are 2.~ givell in copen(lill~ corllll1ollly nssiglle(l IJlliled .Slan:s l)atelll nl)plicalions Scli;ll No.
rlledon , 19')(),enlille(l,"I)n;ll l'ro~lnllllll;ll)le l~ k'I`cxllllinL alldComl)lex ClipI)illf, all(t Gl;ll)llics R(:n(lerill~ l'rocessor~ Scrial No ~ d on __, 199(), entille(l "l~lal llar(lw;lle Challllels al1d llar(lware Context Swilcllin~ in " arul-hics Renderillg Processor," Seli;ll No. _ filed on ___, 1')9(), ~nlille(l3() "Conc~lrlellt aenerlll Pllrpose an(i I~MA Processin~ in a Cral)l~ics Ren(lerillg Proces-sor," Seriul No filed on _, 199(), entilled "Tnte~r;lle(l llardw;lre Gener-ator for ~rea Fill, Conics alld Vecl--ls in a Gr;ll)hics Processor", Seli.ll No __ __ file(l 011 , 19~0, enlilled "llardw;lre l~il 1310ck 'I`rallsfer Or)ernlor in a Ciral)hics Rendering Processor," Serial No _ filed on , 1~9(), enlilled "llardware 35 Symholo~y and Text Generator in a Grnpllics Processor," and Serial No r~led on , 1990, enlitled "llardw;lre Mllltiprocess Sche(llller in a Graphics Ren-2~$~7 dering Processor," all by John M. Peaslee and Jeffrey C. Malacarne, whose teachings are incorporated herein by reference.
From the above description it will now be æen that the multifunction cogenera-tor 10 of the present invention provides a novel and unique system for use in a graph-S ics rendering processor. The multifunction cogenerator 10 includes a plurality of pro-cessors for generating graphics primitives, symbols, alphanumerics, and the like, a bit block transfer operator, and a block texturing and complex c1ip mask processor. All of these functions are synchronously controlled by a multiprocess scheduler. All of these processors are hardware specific thereby providing very high speed performance. Si-I0 multaneously, the cogenerator 10 is provided with a large programmable memory, dualchannel input buffers, and context registers which enables the cogenerator 10 to be easily externally programmed to perform a wide variety of programmable functions.
The cogenerator 10 also provides general purpose programming capability. The cogen-erator 10 is also provlded with dual channel capability whereby it is able to handle the I S input of data and programming instructions in parallel with one of the channels being designated a higher priority channel tllan the other thus enhancing the performance of the cogenerator 10 when used in contraction with high speed graphics systems such as used in military command and control systems and air traffic control systems.
Thus there has been described a new and improved graphics processor capable 20 of performing hardware specific high speed graphics rendering funcdons as well as general purpose programmable graphics rendering functions. It is to be understood that the above-described embodiment is merely illustrative of some of the many specific embodiments which represent applications of the principles of the present invention.
Clearly, numerous and other arrangements cJm be rendily devised by those skilled in the 25 nrt withollt depnrting from the scope of the invendon.

Claims (20)

What is claimed is:

1. A multifunction graphics processor (10) for use with a host processor (14) and a graphics display (24), said processor (10) characterized by:
interface means (38,40) for receiving input data and program instructions from the host processor (14);
context register means (42) for receiving and storing programmable processor attribute signals that determine the processor operating characteristics;
processor means (34) for generating a plurality of graphic signal sets;
display memory means for receiving and storing the input data and program in-structions from the interface means (38, 40), the host processor (14), and the processor means (34);
display list processor means (28) coupled to the input register means, the dis-play memory, and the processor means (34) for controlling the input and output of data, program instructions, and graphic signal sets therebetween.

2. The graphics processor (10) of Claim I wherein the processor means (34) is characterized by a conics and area fill generating means (43) for generating signal sets for the generation of open and filled conic graphics.

3. The graphics processor (10) of Claim 2 wherein the processor means (34) further is characterized by a symbol and text generator means (45) for generating alpha-numeric graphic symbols.

4. The graphics processor (10) of Claim 3 wherein the processor means (34) further is characterized by a bit block transfer operator means (47) for transferring rect-angular blocks of data between the display memory and the bit mapped memory of the graphics display.

5. The graphics processor (10) of Claim 4 wherein the processor means (34) further is characterized by block texturing and complex clip mask processor means (30) for generating block texture signal sets and complex clip mask signal sets.

6. The graphics processor (10) of Claim 5 wherein the processor means (34) is further characterized by a multiprocess scheduler (46) for synchronously controlling the operation of the conics and area fill generating means (43), the symbol generator means (45), the bit block transfer operator means (47), and the block texturing and complex clip mask processor means (30).

7. The graphics processor (10) of Claim 1 wherein the interface means (38,40) is characterized by two operating channels, one of the channels having a higher operat-ing priority than the other channel, and wherein the channels operate in parallel.

8. The graphics processor (10) of Claim 7 wherein the display list processor means (28) is characterized by a display memory interface unit (35) coupled between the host processor (14), the processor means (34), the interface means (38,40), and the display memory means (26).

9. The graphics processor (10) of Claim 8 wherein the display memory means (26) is characterized by a tri-ported memory having input ports connected to the host processor (14), the interface means (38,40), and the processor means (34).

10. The graphics processor (10) of Claim 9 further characterized by readback muliplexer means (44) operatively coupled between the display memory interface unit (35) and a bit mapped memory (22) of the graphics display (24) for transferring data therebetween.

11. The graphics processor (10) of Claim 1 wherein the processor means (34) is characterized by two hardware channels with high and low priority, the high priority channel adapted to interrupt operation of the low priority channel and process instruc-tions immediately.

12. The graphics processor (10) of Claim 11 further characterized by context switching means (42) adapted to save the current operational state of the graphics pro-cessor (10), alter the state of the graphics processor (10), perform a completely inde-pendent task, and then restore the previous operating state.

13 The graphics processor (10) of Claim 12 wherein nested context switching is characterized by storing and retrieving a multitude of attribute context register values stored in an attribute stack located in the display memory (26).

14. The graphics processor (10) of Claim 12 that is adapted to perform both general purpose and graphics primitive processing derived from a display list stored in the display memory (26).

15. The graphics processor (10) of Claim 14 that is adapted to perform concur-rent DMA processing on the display list wherein the graphics processor (10) starts processing the display list before the display list is completely build in the display mem-ory (26) by the host processor (14) this reducing the processing latency time between building the display list and processing it.

16. The graphics processor (10) of Claim 4 wherein the bit block transfer op-erator means (47) is adapted to perform a complete BITBLT operation between a plu-rality of source and destination locations.

17. The graphics processor (10) of Claim 16 wherein the plurality of source and destination locations is characterized by bit map memory (22) to bit map memory (22) display memory (26) to bit map memory (22). bit map memory (22) to display memory (26) host processor (14) to display memory (26) display memory (20) to host processor (14) host processor (14) to bit map memory (22) and bit map memory (22) to host processor (14).

18. The graphics processor (10) of Claim 3 wherein the symbol and text gen-erator means (45) is adapted to create a plurality of symbols comprising two color sym-bols inverse video, symbol scaling, symbol rotation, and typewriter operation.

19. The graphics processor (10) of Claim 5 wherein the block texturing and complex clip mask processor means (30) provides for simultaneous image texturingusing up to two texture patterns and for clipping images to rectangular and complex shapes.

20. The graphics processor (10) of Claim 5 further characterized by a multipro-cess scheduler (46) adapted to control concurrent processes in the graphics processor (10) to allow for simultaneous concurrent operation of the primitive generators com-prising the processor means (34) and block texturing and complex clipping operations of the block texturing and complex clip mask processor means (30).