CA2055396C - Delay distortion suppressing system for asynchronous transfer mode (atm) communication system - Google Patents

Abstract

A delay distortion suppressing system for use in an asynchronous transfer mode communication system which includes at least a transmitting end and a receiving end which are connected via transmission paths. The delay distortion suppressing system includes a first part provided in the transmitting end for transmitting information in the form of cells in an asynchronous transfer mode, a second part provided in the receiving end for delaying each cell which is received via a transmission path by a predetermined delay time relative to a reference point, a third part provided in the receiving end for varying the reference point depending on an arrival time of the cell which is received at the receiving end via the transmission path, so that a delay distortion of the cells is suppressed, and a fourth part including a decoding part for decoding the cells output from the second part.

Description

CA 020~396 1998-01-07 - l - 27879-89 TITLE OF THE INVENTION
DELAY DISTORTION SUPPRESSING SYSTEM FOR ATM
COMMUNICATION SYSTEM

BACKGROUND OF THE INVENTION
The present invention generally relates to delay distortion suppressing systems, and more particularly to a delay distortion suppressing system for use in an asynchronous transfer mode (ATM) communication system.
In the ATM communication system, each of various kinds of information such as audio signals, image signals and data is divided into cells which have a constant length, and the cells are multiplexed via a buffer and transmitted. When the number Of transmitted cells increases, the cells remain in the buffer for a longer time. On the other hand, the cells remain in the buffer for a shorter time when the number of transmitted cells decreases. Accordingly, a delay ZO distortion is introduced in the cells which are multiplexed and transmitted. At the receiving end, a receiving buffer made up of a first-in-first-out (FIFO) buffer is provided in order to suppress or absorb the delay distortion. It is desirable that the receiving end have a large delay distortion suppressing range and that the absolute delay time is small.
FIG.1 shows an essential part of an example of a conventional ATM communication system. A transmitting end includes a coding part 41, a cell forming part 42, a signal detecting part 43 and a multiplexing part 45 which has a buffer 44. On the other hand, a receiving end includes a demultiplexing part 46, a receiving buffer 47, a cell disassem~ling part 48 and a decoding part 49. The transmitting end and the receiving end are coupled via a transmission line 50, an ATM exchange and the like which are not shown.
At the transmitting end, the signal detecting :, CA 020~396 1998-01-07 2 ~ ~ ~ 3 ~ ~

part 43 detects whether an input signal is an audio signal or a modem signal. The signal detecting part 43 controls the coding part 41 and the cell forming part 42 depending on the detected result, so that the input signal is subjected to an appropriate coding process in the coding part 41 and subjected to an appropriate cell forming process in the cell forming part 42. Each cell which is output from the cell forming part 42 has a length of 53 bytes which is made up of a 5-byte header and a 48-byte information field. The cells output from the cell forming part 42 are multiplexed via the buffer 44 of the multiplexing part 45 and transmitted to the transmission line 50.
Generally, with respect to the audio signal, the cell forming part 42 judges whether or not each cell is a voiced cell which includes voice or an unvoiced cell which includes no voice, and the cell forming part 42 supplies only the voiced cells to the multiplexing part 45. When transmitting the cells, the multiplexing part 45 can add a cell number, a cell transmission time and the like to the header.
At the receiving end, the demultiplexing part 46 demultiplexes the multiplexed cells received from the transmission line 50. The demultiplexed cells are supplied to the cell disassembling part 48 via the receiving buffer 47, and each cell is disassembled into the header and the information field. The information field is supplied to the decoding part 49. The cell disassembling part 48 also judges whether or not each cell is related to an audio signal or a modem signal, and controls the decoding part 49 depending on the result of the judgement. Hence, the decoding part 49 carries out a decoding process in correspondence with the kind of information, that is, the audio signal or the modem signal.
As the number of cells input to the multiplexing part 45 from several channels increases, CA 020~396 1998-01-07 7 ~ ~ ~ 3 ~ ~

the waiting time of the cells in the buffer 44 becomes longer. On the other hand, when the number- of cells input to the multiplexing part 45 decreases, the waiting time of the cells in the buffer 44 becomes shorter. As a r-esult, the delay time of the cells which are multiplexed in the multiplexing part 45 and transmitted to the transmission line 50 changes, and a delay distortion of the cells occurs. When such a delay distortion occurs for the audio ~ignal cells, the quality of the reproduced audio signal at the receiving end deteriorates. Accordlngly, the receiving buffer 47 is provided on the receiving end so as to suppress the delay distortion.
The receiving buffer 47 is made up of a FIFO memory having a memory capacity which is, for example, twice the delay distortion suppressing range. The cell which arrives first is written at the center of the FIFO memory and is read out by successively shifting the cell within the FIFO memory. If the second cell arrives at the time a reference delay time elapses, this second cell likewise is written at the center of the FIFO
memory. If the second cell arrives after the reference delay time elapses, this next cell is written on the output side from the center of the FIFO memory. On the other hand, if the next cell arrives before the reference delay time elapses, this next cell is written on the input side frorn the center of the FIFO memory. As a result, the delay distortion is suppressed when the cells are output from the FIFO memory, that is, the receiving buffer 47.
However, in order to suppress the delay distortion, the FIFO memory requires a memory capacity which is twice the delay distortlon suppressing range. However when the delay distortion ,A, ~

CA 020~396 1998-01-07 suppressing range ls set large, the cells remain ln the FIFO
memory for a relatively long time and there is a problem in that the absolute delay time becomes large. On the other hand, there is active research in broad-band integrated services digital networks (B-ISDNs) whlch enables communication of broad-band inforrnation such as images. The ATM is suitable for use in this broad-band ISDN. In this case, the cells are multiplexed at each node within the network, but generally, the cells are delayed if congestion occurs on the line. A difference inevltably occurs among the delay times of the cells, thereby causing a delay distortlon.
FIG. 2 shows an essential part of an example of a conventlonal ISDN employing the ATM. In FIG. 2, those parts which are basically the same as those corresponding parts in FIG. 1 are desi~nated by the same reference numerals, and a de~cription thereof will be omitted. In this example, a terminal 510 is telephone set, but varlous other kinds of terminals may be used as the terminal 510. The multiplexed cells are transmitted to the transmisslon llne ~not shown) via a switch 5201 of an ATM switch 520, and this AT~I switch 520 carries out a switching operation so that the rnultiplexed cells are transmitted to an ATM switch (not shown) which is connected to a destlnatlon terminal (not shown) via the transmission line. On the other hand, the multiplexed cells which are received from the transmission line are supplied to the demultiplexer part 46 via a switch 5202 of the ATM switch 520.
After the cells are generated in the cell forming part 42, the cells are delayed when congestion occurs in the path, A

CA 020~396 1998-04-17 which path includes the multiplexing part 45, the ATM switch 520 and the transmission line, and particularly in the multiplexing part 45, which includes the buffer, and in the ATM switch 520. In this case, the cells in most cases arrive at the receiving end with different delays, and such different delays are often referred to as the delay distortion. The voice cannot be reproduced correctly if the delay distortion occurs, and there is a problem in that the contents of the communication cannot be understood by the listener when the delay distortion occurs.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful delay distortion suppressing system in which the problems described above are eliminated.
Another and more specific object of the present invention is to provide a delay distortion suppressing system for an asynchronous transfer mode communication system which includes at least a transmitting end and a receiving end which are connected via transmission paths, said delay distortion suppressing system comprising first means, provided in the transmitting end, for transmitting information in the form of cells in an asynchronous transfer mode, second means, provided in the receiving end, for delaying each cell, as received via a transmission path by a predetermined delay time relative to a reference point, third means, provided in the receiving end and coupled to the second means, for varying the reference CA 020~396 1998-04-17 6a determining that a difference between the cell transmission time and the cell reception time is smaller than the predetermined time. According to the delay distortion suppressing system of the present invention it is possible to ' CA 020~396 1998-04-17 point depending on an arrival time of the cell which is received at the receiving end via the transmission path, so that a delay distortion of the cell is suppressed, and fourth means, provided in the receiving end and coupled to the second means, including decoding means for decoding the cells output from the second means. According to the delay distortion suppressing system of the present invention, it is possible effectively to suppress the delay distortion. Therefore, it is possible to prevent discontinuity of voice in the case where the information is a continuous audio information.
Still another object of the present invention is to provide the delay distortion suppressing system of the type described above where each cell comprises a header and an information field, the first means includes means for inserting a cell transmitting time in the header of each cell, the second means includes storage means for storing each cell received from the transmission path, inserting means for inserting a cell reception time in the header of each cell received from the transmission path, and control means for controlling write and read operations of the storage means based on the cell transmission time and the cell reception time included in the header of each cell which is read out from the storage means, a delay distortion suppressing range and the predetermined time so that the cell which arrives first is written into the storage means and read out after a time which corresponds to the delay distortion suppressing range, and the third means varies the reference point upon CA 020~396 1998-01-07 "~ ' 9 ~

suppress the delay distortion effectively by suitably and automatically ad~ustlng the reference polnt. Therefore, lt is possible to prevent discontinuity of voice in the case where the information is continuous audio information.
A further obiect of the present inventlon ls to provide the delay distortion suppressing system of the type descrlbed above, whereln the flrst means includes priority cell generating means for generating a priority cell from a head of the information, the priority cell being transmitted over a transmission path which causes a minimum delay while other cells following the priority cell are transmitted over other transmission paths having normal delays, the third means includes means for setting a reception time of the priority cell as the reference point and means for statistically obtainlng a maximum delay time of the cells following the priority cell, and the second means delays each cell by the predetermined time which is set independently for each cell so that a total delay time of each cell becomes the maximum delay time. According to the delay distortion suppressing system of the present invention, it is possible to suppress the delay distortlon effectively by using the priority cell. Therefore, it is possible to prevent discontinuity of voice in the case where the lnformation is continuous audlo information.
In accordance with the present invention there is provided a delay distortion suppressing system for an asynchronous transfer mode communication system which includes at least a transmitting end and a receiving end which are 2787g-8g CA 020~396 1998-01-07 3 ~ ~
.~" ,....
- 7a -connected vla transmission paths, said delay distortion suppressing system comprising:
first means, provided in the transmitting end, for transmitting information in the form of cells in an asynchronous transfer mode;
second means, provided in the receiving end, for delaying each cell which is received via a transmission path by a predetermined delay time relative to a reference point;
third means, provided in the receiving end and coupled to said second means, for varying the reference point depending on an arrival time of the cell which is received at the receiving end via the transmission path, so that a delay distortion of the cells is suppressed;
fourth means, provided in the receiving end and coupled to said second means, including decoding means for decoding the cells output from said second means;
wherein each cell is made up of a header and an information field;
said first means includes means for inserting a cell ~0 transmitting time in the header of each cell;
said second means includes storage means for storing each cell received via the transmission path, lnsertlng means for inserting a cell reception time in the header of each cell received via the transmission path, and control means for controlling write and read operations of said storage means based on cell transmission time and the cell reception time included in the header of each cell which is read out from CA 020~396 1998-01-07 7. ~
.~
- 7b -said storage means, a delay distortion suppressing range and the predetermlned delay time so that the cell which arrlves first is written into said storage means and read out after a time which corresponds to the delay distortion suppressing range;
said third means varies the reference point when a difference between the cell transmission and the cell reception time is smaller than the predetermined delay time;
and 1~ the predetermined delay time is a minimum delay time of each cell which is recelved at the receiving end.
In accordance with another aspect of the present invention there is provided a delay dlstortion suppresslng system for an asynchronous transfer mode communication system which includes at least a transmitting end and a receiving end which are connected via transmission paths, said delay distortion suppressing system comprislng:
first means, provided in the transmitting end, for transmitting information in the form of cells in an asynchronous transfer mode;
second means, provided in the receiving end, for delaying each cell which is received via a transmission path by a predetermined delay time relative to a reference point;
thlrd means, including means for setting an arrival time of the priority cell as the reference point and means for statistically obtaining a maximum delay time of the cells following the priority cell; and --7 (~

,"~,. .
- 7c -fourth means, provided in the receiving end and coupled to said second means, including decoding means for decoding the cells output from said second means;
wherein said first means includes priority cell generating means for generating a priority cell from a head of the information, said priority cell being transmitted via a transmission path which causes a minimum delay while other cells following the prlority cell are transmitted vla other transmission paths having normal delays; and said second means delays each cell by the predetermined delay time which is set independently for each cell so that a total delay time of each cell becomes the maximum delay time.

~- 27879-89 CA 020~396 1998-01-07 ~ ~7 ~

7 ~ 27879-89 Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanylng drawlngs.

BRIEF DE~CRIPTION OF THE DRAWINGS
FIG. 1 ls a system block dlagram showlng an essential part of an exal-nple of a conventional ATM communication system;
FIG. 2 is a system block diagram showlng an essentlal part of an example of a conventlonal I~DN employing the ATM;
FIG. 3 is a system block dlagram showing an essential part of a first embodiment of a delay distortion suppressing system according to the present invention;
FIG. 4 is a timing chart for explaining the operation of the first embodiment;
FIG. 5 is a system block diagram for explaining the operating principle of a second embodiment of the delay distortion suppressing system according to the present invention;
FIG. 6 is a system block diagram showing the second embodiment;
FIG. 7 is a timing chart for explaining the operation of the second embodlment;
FIG. 8 is a system block diagram showing an embodiment of a receiving process part shown in FIG. 6;
FIG. 9 is a system block diagram showing an embodiment of an insertion control part shown in FIG. 6;
FIG. 10 is a timing chart for explaining the CA 020~396 1998~ 7 2 0 S 5 3 9 6 1 operations of the receiving process part and the insertion control part shown in FIGS.8 and 9;
FIG.11 is a system block diagram showing an embodiment of a judgement and read control part shown in FIG.6;
FIG.12 is a timing chart for explaining the operation of the judgement and read control part shown in FIG.ll;
FIG.13 is a system block diagram showing a modification of the second embodiment;
FIG.14 is a timing chart for explaining the operation of the modification shown in FIG.13;
FIG.15 is a system block diagram for explaining the operating principle of a third embodiment of the delay distortion suppressing system according to the present invention;
FIG.16 is a diagram for explaining the delay distortion suppressing operation with reference to FIG.15;
FIGS.17A and 17B are system block diagrams showing the third embodiment;
FIG.18 is a system block diagram showing the vicinity of a multiplexing part shown in FIGS.17A and 17B;
FIG.19 is a system block diagram showing the vicinity of a demultiplexing part shown in FIGS.17A and 17B;
FIG.20 is a diagram showing a cell format; and FIG.21 is a system block diagram showing an embodiment of a cell forming part.

DESCRIPTION OF THE PREFERRED EMBODIMENTS
First, a description will be given of a first embodiment of a delay distortion suppressing system according to the present invention, by referring to FIG.4. In this embodiment, the absolute delay time is reduced by writing the received cell into a FIFO memory CA 020~396 1998-01-07 3 ~ ~
. _ ~ 27879-89 and immedlately readlng out the cell for decoding.
The system shown in FIG. 3 includes a FIFO memory 51, a timer 52, a read control part 53, a set control part 54, a register 55, a recelving process part 56 and a decoding part 57.
All parts except a decoding part in FIG. 3 reallze the functlon of the cell disassembling part 48 shown in FIGS. 1 and 2.
The receivlng process part 56 detects the header of the received cell, and detects the virtual path identlfier VPI and the virtual channel identifier VCI of the header. The receiving process part 5~ supplies to the FIFO memory 51 only the received cells intended for this channel. The receiving process part 56 supplies a write clock signal WCK to the FIFO memory 51 upon determining that no overflow flag OV is received from the FIFO
rnemory 51, so as to write the received cells into the FIFO memory 51. Hence, each recelvlng process part 56 has the functlon of demultlplexing the received cells intended for lts own channel.
The read control part 53 supplies to the FIFO memory 51 a read clock signal RCK for reading out the received cells upon determining that no empty flag EP is recelved from the FIFO memory 51, that is, upon determining that the received cells are written into the FIFO memory 51. The read control part 53 outputs a timing pulse TP based on a cell header pulse HP of the received cell which ls read out from the FIFO memory 51 ln response to the read clock signal RCK. Thls tlming pulse TP is used to set in the register 55 a cell transmlsslon tlme ST whlch ls added to the header of the received cell. The cell transmlssion time ~T which ls set in the register 55 ls supplied to the set control part 54.

_ 7 f~ ~ ~ 3 ~ ~

~a 27879-89 The information field of the received cell which is read out from the FIFO memory 51 is supplied to the decoding part 57 wherein a decoding process is carried out based on a decodlng clock signal CLK. The timer 52 counts pulses of the decoding clock signal CLK, ~ . .

CA 020~396 1998-01-07 ~ 7 ~

and a counted value TT is supplied to the set control part 54, and the set control part 54 compares the cell transmission time ST and the counted value TT. The set control part 54 supplies a control signal RS to the read control part 53 so that a difference between the cell transmission time ST and the counted value TT becomes constant. The set control part 54 carries out other control operations such as controlling the timing of the read cloc~ signal RCK which is supplied to the FIFO
10 memory 51.
FIG.4 is a timing chart for explaining the operation of the first embodiment shown in FIG. 3. In FIG.4, (a) shows the cell transmission time ST which is added to the header of the received cell, and (b) shows the timing of cells Cl through Cll which are written into the FIFO memory 51, where Ca shows a case where the cell is an unvoiced cell and is therefore not transmitted. In addition, in FIG.4, (c) shows an empty flag EP, and (d) shows the headers of the cells read out 20 from the FIFO memory 51 by bold lines and the decoding times of the cells C1 through Cll, where TD denotes the decoding time of one cell. Furthermore, in FIG.4, (e) shows the read waiting time, (f) shows the counted value TT of the timer 52, and (g) shows the difference between the cell receiving time and the cell transmission time ST.
The cells Cl through Cll having the cell transmission times ST = 0 to 130 arrive at intervals different from the intervals of the cell transmission 30 times ST. When the cell Cl having the cell transmission time ST = 0 in (a) is written into the FIF0 memory 51 with the timing shown in (b), the empty flag EP changes from "1" to "0" as shown in (c). In addition, the counted value TT of the timer 52 which counts the pulses of the decoding clock signal CLK increases with a constant period as shown in (f). Moreover, when the A empty flag EP is "0", the header of the cell is read out CA 020~396 1998-01-07 20~5396 from the FIF0 memory 51 at a constant period as shown in (d), and the cell transmission time ST is set in the register 55. This transmission tim~ which is set in the register 55 and the counted value TT of the timer 52 are 5 compared in the set control part 54, and the read clock signal RCK output from the read control part 53 is controlled so that the difference between the cell transmission time ST and the counted value TT becomes constant.
~uring the decoding time TD of the first cell Cl, the cell C2 having the cell transmission time ST =
lo is written into the FIFO memory 51, and this cell C2 is read out from the FIFO memory 51 and decoded when the counted value TT of the timer 52 is "10". Similarly, the cell C3 having the cell transmission time ST = 20 and the cell C4 having the cell transmission time ST =
30 are respectively read out from the FIF0 memory 51 and decoded when the counted value TT of the timer 52 is "20" and "30".
Since the next cell Ca is an unvoiced cell and is not transmitted, the cell C5 having the next cell transmission time ST = 50 is written into the FIFO
memory 51, and a header H5 of the cell C5 is read out as shown in (d) of FIG.4 when the counted value TT of the timer 52 is "40". The cell transmission time ST added to this header H5 is "50", and thus, TT < ST. During the read waiting time shown in (e) of FIG.4 until the relationship TT = ST is obtained, no read clock signal RCK is supplied to the FIFO memory 51 and the supply of the information field of the cell C5 to the decoding part 57 is waited.
The information field of the cell C5 is supplied from the FIF0 memory 51 to the decoding part 57 and decoded when the counted value TT of the timer 52 becomes "50". The cells C6 and C7 are decoded similarly. In this case, the difference between the cell transmission time ST and the counted value TT of CA 020~396 1998-01-07 the timer 52 becomes "0" as shown in (g) of FIG. 4.
The cell Ca next to the cell C7 is an unvoiced cell.
When the delay time of the next cell C8 is lar~e, the FIFO memory 51 becomes empty upon completion of the decoding of the cell C7 ends, and the empty flag EP becomes "1". In this case, the reproduced audio output is interrupted because the codlng ls interrupted for a time longer than the interval of the unvoiced cell Ca.
When the cell C8 having the cell transmission time ST = 90 arrives at a point A, this cell C8 is written into the FIFO memory 51 and the empty flag EP ~ecomes "0". The header of thls cell C8 is read out from the FIF0 memory 51 and the cell transmission time ST = 90 is set in the register 55. The set control part 54 compares the cell transmission tlme ST in the register 55 and the counted value TT of the tirner 52, and in this case, a reference point of the minimum delay time is changed because (,5T - TT) c 0. In addition, the information field of the cell C8 ls supplled from the FIF0 memory 51 to the decoding part 57 and decoded. The cells C9 and ClQ which arrive after the cell C8 are read out from the FIFO memory 51 so that the difference between the counted value TT of the timer 52 and the cell transmission time ST becomes "15" and constant.
When the cell C11 havlng the cell transmission time ST = 130 arrlves at a point B when the counted value TT of the timer 52 is "150", the reference point of the minimum delay time is changed because (ST - TT) c -15. In addition, the informatlon read out from the FIFO memory 51 is controlled so that the difference between the counted value TT of the timer 52 and the 3 ~ ~
12a 27879-89 cell transmission time ST thereafter becomes "20".
Accordlng to the first embodiment, the cell is read out immediately from the FIFO 51 and decoded ln correspondence wlth the cell transmission time .ST thereof when the cell is written into the FIFO memory 51. For this reason, the absolute delay time can be CA 020~396 1998-01-07 ~ ' 2 ~ ~ ~ 3 ~ ~

made small by making the time in which the cell remains in the FIF0 memory 51 short.
~ iowever, the distribution of the cells which arrive from the minimum delay time to the time which is the delay distortion suppressing range after, is such that the number of cells arriving in the vicinity of the minimum delay time is large while the number of cells arriving thereafter rapidly decreases. But that depends on an application, so it is unclear whether or not the arrival of the first cell is in the vicinity of the reference point of the minimum delay time, and it is necessary to change the reference point for the delay distortion suppression as indicated by the point A or B
in FIG.4 until the following cells fall within the delay distortion suppressing range. Consequently, the coding process is interrupted during a time when the counted value TT of the timer 52 is "80" to "150", for example, and there is a problem in that the quality of the sound deteriorates because a time discontinuity occurs in the reproduced audio output.
Accordingly, a description will be given of a second embodiment of the delay distortion suppressing system according to the present invention, in which the problem of the first embodiment is eliminated.
First, a description will be given of the operating principle of the second embodiment, by referring to FIG.5. In this embodiment, a FIF0 memory is used to suppress the delay distortion of the received cells as in the first embodiment.
In the ATM communication system shown in FIG.5, only the information field of the received cell which is read out from a FIF0 memory 1 is supplied to a decoding part 2. A timer 3 counts pulses of a decoding clock signal which is supplied to the decoding part 2.
These two contents are the same as in the first embodiment. A reception time inserting part 4 inserts A the content of the timer 3 into the header of the CA 020~S396 l998-0l-07 2 0 ~ 5 3 9 6 1 received cell as a cell reception time and supplies it to the FIFO memory 1. A judgement and read control part 5 controls the read operation of the FIFO 1 based on the minimum delay time, the delay distortion suppressing range, the cell reception time and the cell transmission time added to the header of the received cell which is read out from the FIFO memory 1. After writing into the FIFO memory 1 the received cell which arrives first, the judgement and read control part 5 then reads this received cell from the FIFo memory 1 after a time corresponding to the delay distortion suppressing range. Thereafter, the judgement and read control part 5 changes the reference point of the minimum delay time when it is judged that the difference between the cell transmission time and the cell reception time is smaller than the minimum delay time. Thus, since the decoding is first started by a delay time corresponding to the delay distortion suppressing range, the reproduced audio output will not be interrupted too long when the reference point of the minimum delay time is thereafter shifted a little depending on the size of the delay distortion.
In addition, the judgement and read control part 5 reads out the header of the received cell from the FIFO ~emory 1 every time the decoding process of the decoding part 2 ends, and judges whether or not the difference between the cell reception time and the cell transmission time added to the header is smaller than the minimum delay time. If the difference between the cell reception time and the cell transmission time is smaller than the minimum delay time, the judgement and read control part 5 changes the reference point of the minimum delay time and reads the information field of this reception cell according to this reference. The read information field is supplied to the decoding part 2.
Next, a more detailed description will be CA 020~5396 1998-01-07 glven of the second embodiment, by referrlng to FIGS. 6 and 7.
FIG. 6 shows an essential part of the second embodlment; and FIG.
7 is a timlng chart for explaining the operatlon of the second embodlment.
The systel-n shown in FIG. 6 includes a ~IFO memory 11, a timer 12, an inserting circuit 13, an insertlon control part 14, a iudgment and read control part 15, a reglster 16, a receiving process part 17 and a decoding part 18.
When the received cell arrlves at the recelving process part 17, the recelvlng process part 17 ~udges the vlrtual path identifier VPI and the virtual channel ldentlfler VCI ln the header of the recelved cell. The recelvlng process part 17 supplies only the received cell of its own channel to the FIFO
memory 11 vla the lnserting circuit 13. The recelvlng process part 17 also supplles a write clock signal WCK to the FIF0 memory 11 when no over flow flag OV is recelved from the FIF~ memory 11.
The received cell is written into the FIF0 memory 11 in response to the wrlte clock slgnal WCK.
The timer 12 counts pulses of a decoding clock signal CLK which ls supplled to the decodlng part 18, and supplles a counted value TT to the insert.lon control part 14. The insertion control part 14 controls the inserting circult 13 so as to lnsert the counted value TT at a predetermlned positlon of the ~leader of the recelved cell based on a cell header pulse HPl. The lnsertlng circuit 13 inserts the counted value TT as a cell receptlon time.
Accor~lngly, the header of the recelved cell lncludes the cell transmlssion time, which ls added at the transmitting end, and the cell reception tlme, whlch ls lnserted ln the inserting circult ~.
~.

CA 020~5396 1998-01-07 13. Then the header ls written into the FIFO memory 11.
A delay dlstortion suppressing range is set in the judgement and read control part 15. Thl~ delay dlstortion suppressing range can be switched depending on whether the cell is an audlo slgnal cell or a modem slgnal cell. The ~udgement and read control part 15 iudges whether or not this part supplies a read clock signal RCK to the FIF0 memory 11 upon determining that no empty flag EP is received from the FIF0 memory 11. This empty flag EP indicates that the FIF0 memory 11 is empty. The jud~ement and read control part 15 also outputs a timing slgnal TP, which is used to set in the register 16 the cell transmission time ST and the cell reception time TT which has never been added in the header of the received cell read out from the FIFO memory 11.
This timing slgnal TP is transmitted in response to a cell header pulse HP2 of the received cell whlch is read out from the FIF0 memory 11. With respect to the reduced cell which arrlved first, the ~udgement and re~d control part 15 reads the cell transmission time ST and the cell reception time TT, whlch are set in the reglster 16, and supplies the read clock slgnal RCK to the FIF0 memory 11 after the tlme corresponding to the set delay distortion suppresslng range elapses. Hence, the lnformation field of thls first received cell is read out from the FIFO memory 11 and is supplled to the decoding part 18. Thereafter, the ~udgement and read control part 15 ~udges whether or not the reference polnt of the minlmum delay tlme should be changed depending on whether or not the difference between the cell transmission time ST and the cell receptlon tlme TT ls smaller than the mlnlmum delay time, and controls the supply of the read clock slgnal RCK to the FIFO

CA 020~396 1998-01-07 memory 11.
FIG. 7 is a timing c}-lart for explaining the operation of the second embodiment shown ln FIG. 6. In FIG. 7, (a) shows the cell transmission time ~T which is added to the header of the received cell, and !b) shows the timing of cells Cl through Cll which are written into the FIF0 memory 11, where Ca shows that the cell is an unvoiced cell and is therefore not transmitted. In addition, in FIG. 7, ~c) s}-,ows the difference between the cell receiving time TT and the cell transmission time ST, and (d) ~hows the counted value TT of the tirner 12, that is, the cell reception time TT, where TD denotes the decoding time of one cell. In FIG.
7, (e) shows an empty flag EP, and (f) shows the decoding tlmes of the recelved cells Cl through Cll, where the bold lines lndlcate the headers Hl through Hll of the received cells Cl through Cll, which are read out from the FIF0 memory 51, and Fd lndlcates the delay distortion suppressing range. Furthermore, in FIG. 7, the tlme base of (f) matches the time bases of (a) through (e) only initially and the tirne base in (f) thereafter ls shlfted by the amount whlch ls shortened by the delay distortion suppressing range Fd. Furtherrrlore, in FIG. 7, (g) S}-IOWS an initial state 30 of the reference point of the minimum delay tlme and changed points 31 through 35.
When the first received cell Cl having the cell transmission time ST = 0 arrives, the receiving process part 17 supplles the write clock signal WCK to the FIFO memory 11 because no overflow flag OV is received from the FIFO memory 11. If the counted value of the timer 12 in this state is the cell reception time TT = 0, the lnsertlng clrcuit 13 lnserts this cell receptlon .~ ~ t~

CA 020~396 1998-01-07 tlme TT = 0 lnto the predetermlned positlon of the header under the control of the insertion control part 14 depending on the cell header pulse HP1, which is received from the receiving process part 17. The received cell C1, which is inserted with the cell reception time TT = 0, is then written into the FIFO memory 11.
Since the empty flag EP from the FIFO rnernory 11 changes from "1" to "0" as shown in (e) of FIG. 7, the ~udgement and read control part 15 supplies the read clock slgnal RCK to the FIFO
memory ll to read out the header Hl of the received cell C1. In addition, the iudgement and read col-ltrol part 15 supplles the tlmlng pulse TP to the reglster 16 in response to the cell header pulse HP2, which is recelved from the FIFO memory 11, so as to set the cell transmission time ST = 0 and the cell reception tlme TT =
0 in the register 16. Because the received cell C1 is the first cell, the ~udgement and read control part 15 supplies the read clock signal RCK to the FIF0 mernory 11 after the delay distortion suppressing range Fd, so as to read out the informatlon fleld of the recelved cell C1 as shown in ~f~ of FIG. 7 and to su~ply the information field to the decoding part 18 to be decoded into the audio signal. During this time, the received cells C2, C3, C4 and C5 respectively having the cell transmission times ST = 10, 20, 30 and 50 arrive when the counted value TT of the tirner 12 is 5, 12, 20 and 32 respectively there are cells successlvely written into the FIFO mernory 11 as shown in !b~ of FIC. 7.
The header H2 of the next received cell C2 is read out from the FIF0 rnernory 11 after the decoding tlme of the received cell C1. As in the case of the recelved cell Cl descrlbed above, the cell transmission time ST = 10 and the cell reception time A

CA 020~396 1998-01-07 ,,,,,,~_ .

18a 27879-89 TT = 5 of the recelved cell C2 are set in the reglster 16. The judgement and read control part 15 obtains D2 = TT-ST = -5 and compares D2 wlth Dl = TT-ST = ~ for the previou~ received cell C1.
In this case, Dl > D2, and thus, the judgement and read control part 15 changes the reference point of the minimum delay time.
The inforrnation field of the received cell C2 is read out from the FIFO memory 11 to be decoded in the decoding part 18, after a time corresponding to D1-D2. ~imilarly, the header H3 of the next recelved cell C3 is read out from the FIF0 memory 11 after the decoding time of the received cell C2. The cell transmission tirne ST = 20 and the cell re~eption time TT = 12 of this received cell C3 are set in the register 16. The ~udgement and read control part 15 obtains D3 = TT-ST = -8. In this case, D2 > D3, and thus, the iudgement and read control part 15 changes the reference point of the A

1 minimum delay time. The information field of the received cell C3 is read out from the FIF0 memory 11 to be decoded after a time corresponding to D2-D3.
The next received cell C4 has the cell transmission time ST = 30 and the cell reception time TT
= 20. Hence, D4 = TT-ST = -10, and D3 > D4. For this reason, the reference point of the minimum delay time is changed, and the information field of the received cell C4 is read out from the FIF0 memory 11 to be decoded after a time corresponding to D3-D4.
An unvoiced cell Ca exists after the received cell C4, and the received cell C5 exists after this unvoiced cell Ca. The received cell C5 has the cell transmission time ST = 50 and the cell reception time TT
= 32. Hence, D5 = TT-ST = -18, and D4 > D5.
Accordingly, the reference point of the minimum delay time is changed, and the information field of the received cell C5 is read out from the FIF0 memory 11 to be decoded after a time corresponding to D4-D5. For the next received cell C6, D6 = -20 and D5 > D6, and the reference point of the minimum delay time is also changed in this case. For the next received cell C7, D7 = -18 and D6 < D7. In this case, the information field of the received cell C7 is read out from the FIF0 memory 11 without changing the reference point of the minimum delay time. Therefore, the reference point of the minimum delay time is changed at the changed points 31 through 35 in (g) of FIG.7.
D8 = -15 and D6 < D8 for the received cell C8. Hence, the reference point of the minimum delay time is not changed, but it can be detected from the cell transmission time ST that an unvoiced cell Ca exists next to the received cell C7. Thus, the information field of the received cell C8 is read out from the FIF0 memory 11 to be decoded after a time TD
corresponding to one cell decoding.
The judgement and read control part 15 CA 020~396 1998-01-07 .3 ~ ~

thereafter ~udges whether or not this point changes the reference point of the minimum delay time, similarly as described above, and controls the read out from the FIFO memory 11. In this way, the reference point of the minirnum delay time is adiusted smoothly.
As a result, it is possible to prevent discontinuity in the reproduced sound, and the delay distortion is suppressed satisfactorily.
FIG. 8 shows an embodiment of the receiving process part 17 shown in FIG. 6, and FI~. 9 shows an embodiment of the insertion control part 14 shown in FIG. 6.
In FIG. 8, the receiving process part 17 includes a serial-to-parallel (~tP) converter 171, a VPI/VCI reading part 172, a cell header pulse generator 173, a comparator 174, a VPI/VCI generator 175f an ena~le signal generator 176 and an AND
circuit 177, which are connected as shown.
The S/P converter 171 converts the received cell shown in ~a) of FIG. 10 into parallel data based on a bit clock signal BCLK and a word clock signal WCLK of the received cell data. The VPI/VCI reading part 172 reads the VPI and VCI from the header of the parallel data output from the ~tP converter 171. The parallel data from the S/P converter 171 is also supplied to the lnserting circuit 13 shown in FIG. 6. On the other ~,and, the cell header pulse generator 173 generates the cell header pulse HP1 shown in ~) of FIG. 10 ~ased on outputs of a comparator 174. The cell header pulse HP1 is supplied to the insertion control part 14.
The VPI and VCI which are read in the VPI/VCI reading part 172 are supplied to the comparator 174 which also receives A the ~PI and VCI of its own channel generated from the VPI/VCI

CA 020~396 1998-01-07 ,.,,",_ .

generator 175. If the VPIs and the VCIs compared ln the comparator 174 match, it is detected that the recelved cell is intended for this channel. In this case, the enable slgnal generator 176 generates an enable slgnal EN amountlng to one cell based on the output of the comparator 174. This enable slgnal EN
shown in ~c) of FIG. 10 ls supplled to the AND circuit 177, whlch also receives the word cl~ck signal WCLK, and an output slgnal of the AND circuit 177 is supplied to the FIFO memory 11 shown in FIG. 6 as the write clock signal WCK. The enable signal generator 176 is reset respons~ve to the overflow signal OV from the FIFO
memory 11.
In FIG. 9, the insertion control part 14 lncludes an insertion pulse generator 141 and a delay flip-flop 142, which are connected as shown. The cell header pulse HPl from the receivlng process part 17 is sl~pplled to the insertion pulse generator 141 and to a clock terminal CK of the flip-flop 142. The lnsertion pulse generator 141 generates an insertlon pulse IP shown in (e) of FIG. 10 based on the cell header pulse HPl and the word cloGk signal WCLK. This insertion pul~e IP is supplied to the inserting circuit 13. On the other hand, the counted value TT (parallel data) from the timer 12 shown in FIG. 6 is supplied to a data termlnal D of t.he flip-flop, and a data DT is output from an output terminal Q of the flip-flop 142. The counted value TT
tparallel data~ is shown in ~d~ of FIG. 10, and the data TT is shown in (f) of FIG. 10. The data TT from the flip-fl~p 142 ls supplied to the inserting cirGuit 13, and the data DT in ~f) of FIG. 10 is supplled to the FIFO ll ln FIG. 6.

, ,.~ ~_ ~ FIG. 11 shows an embodlmerlt of the judgement and read CA 020~396 1998-01-07 ,,,__ .
7 ~

control part 15 shown ln FIG. 6. The judgement and read control part 15 shown in FIG. 11 includes a HP2~ST/TT read enable signal generator 150, and AND circuit 151, and OR circuit 152, a ST~TT
latch pulse generator 153, su~tracting clrcuits 154 and 159, registers 155 and 156, a buffer 157, a comparator 158, a delay distortion suppressing range setting circuit 160, an adding circult 161, counters 162 and 163, a set-reset flip-flop 164 and an AND circuit 165 which are connected as shown.
The w~rd clock signal WCLK of the cell data which is output from the FIFO 11 shown in FIG. 6 is supplied to the HP2/ST/TT read enable signal generator 150 and the AND circuits 151 and 165. The HP2/ST/TT read enable signal generator 150 also receives the empty flag EP from the FIFO memory 11, and supplies to the AND circuit 151 a read enable signal RENl for enabling reading of the cell header pulse HP2, the cell transmission time ST and the cell reception tirne TT. The empty flag EP is also supplied to the AND circuit 151. An OlltpUt signal of the AND
circuit 151 is supplied to an OR clrcult 152, which outputs the read clock signal RCK, which is supplied to the FIFO memory 11.
The OR circuit 152 also receives an output signal of the AND
circuit 165, which wlll be described later.
The ST/TT latch pulse generator 153 receives the cell header pulse HP2 from the FIFO memory 11, and generates a ST/TT
latch pulse (timing signal~ TP. The timing signal TP for setting the cell transmission time ST and the timing signal TP for setting the cell reception tlrne TT are supplied to the register 16 shown in FIG. 6.
The suhtracting circuit 154 subtracts the cell ,. .

, ; .. .-CA 0205~396 1998-01-07 7 ~ J ~ ~ ~

transmlssion tlme ST, whlch ls recelved from the reglster 16, from the cell reception time TT, which is also received from the reglster 16. An output of the subtracting circuit 154 is supplied to the register 155. An output of t~-le register 155 is supplled to the subtractlng clrcult l5g on one hand, and ls supplled to the register 156 through the buffer 157 on the other. However, the buffer 157 is enabled by an OUtpllt of the comparator 158 only if the comparator 158 iudges that the content of the register 156, which stores the minimum value, is greater than the content stored in the register 155. The content of the register 155 is subtracted from the content of the register 156 ln a subtractlng circuit 15~. An output of the subtracting circuit 159 is supplied to an adding circuit 161, which receives the delay dlstortlon suppressing range Fd from the delay distortion suppressing range setting circuit 160. For example, the delay distortion suppressing range setting circult 160 may be a register, whlch recelves the delay dlstortlon suppresslng range Fd from outside the judgement and read control part 15.
An output of the adding circuit 161 is supplled to the counter 162 as a load value, and thls load value is loaded in response to the cell header pulse HP2, ~hich is recelved from the FIF0 memory 11. An output carry slgnal of the counter 162 ls supplied to the counter 163 and the fllp-flop 164. The counter 163 counts the number of data words wlthln the cell in respect to the output carry slgnal of the counter 162, and supplies a carry signal to the flip-flop 164. Hence, the flip-flop 164 is set and reset responslve to the output carry signals of the counters 162 and 163 and an output signal of t~le flip-flop 164 ls supplied to i ~i CA 020~396 1998-01-07 24 2787g-89 the AND circult 165 as a coded data read enable signal REN2. The AND circuit 165 receives the empty flag EP, the word clock signal WCLK and the coded data read enable signal REN. The AND circuit 165 supplies an output signal to the OR circuit 152, which outputs the read clock signal RCK.
FIG. 12 is a timing chart showing signals at various parts of the judgement and read control part 15 shown in FIG. ll.
In FIG. 12, (a~ shows the empty flag EP from the FIFO memory 11, ~b) shows the read enable si~nal REN 1 from the HP2/ST/TT read enable signal generator 150, (c) shows the cell header pulse HP 2 from the FIFO memory ll, and (d) shows the cell transmission time ~T and the cell reception tirne TT from the FIFO memory 11. The timing pulse TP for setting the cell transmission time ST ls shown in (e) of FIG. 12, and the timing pulse TP for setting the cell reception time TT is shown in (f) of FIG. 12. In FIG. 12, tg) shows the renewal timing of the rninimum value (TT-ST), (h) shows the output carry signal of the counter 62, and (i) shows the coded data read enable signal REN 2 from the flip-flop 164.
Next, a description will be given of a modification of the second embodiment, by referring to FIG. 13. In FIG. 13, those parts which are the same as those corresponding parts in FIGs. 6 and 11 are designated by the same reference numerals, and a description thereof wlll be omltted. In this embodlment, a random access rnel-nory (RAM) is used in place of the FIFO memory.
The system shown in FIG. 13 includes the recelving process part 17, a buffer 211, an inverter 212, a RAM 213, a timing pulse generator 214, a control part 215, registers 216 and 218, a delay circuit 217, a selector 219, a timer 220, a write A

CA 020~5396 1998-01-07 address generator 221, and a circuit part 222. The clrcuit part 222 is identical to the corresponding circuit part shown in FIG. 11.
In FIG. 13, the received cell shown in ~a) of FIG. 14 is input to the receiving process part 17. The cell data is supplied to a bus 225 via the buffer 211. The cell header pulse HP1 from the receiving process part 17 is supplied to the timing pulse generator 214 whlch generates the timing pulse TP. The timin~
pulse TP causes the cell transmission time ST from the receiving process part 17 to be supplied to the register 216. The cell header pulse HPl is shown in ib! of FIG. 14. The cell transmission time ST is set in the register 216 in response to the timing pulse TP from the tirning pulse generator 214. The cell transmission time ST is supplied to the subtracting circult 154 of the circuit part 222.
On the other hand, the enable signal EN from the receiving process part 17 is supplied to the buffer 211 and to the RAM 213 through the inverter 212. The enable signal EN is shown in (c~ of FIG. 14. Hence, the cell data is supplied to the RAM
213 through the buffer 211 if the buffer is enabled by the enable signal EN. On the other hand, if the buffer 211 is disabled by the enable signal EN, then an output signal of the inverter 212 enables output from the RAM 213. In other words, the cell data can be written into the RAM 213 as long as the buffer 211 is enabled. The stored cell data can be read out from the RAM 213 as long as the buffer 211 is disabled. The RAM 213 also receives the write clock signal WCK from the receiving process part 17.
On the other hand, the enable signal EN is also supplied to the control part 215 which ou~puts a control si~nal CNT shown ! ~ ~
~ ~.

CA 020~396 1998-01-07 2~ 27879-89 ln (d) of FIG. 14. The control slgnal CNT ls sllpplled to the delay circuit 217 and the selector 219. The selector 219 is switched to selectively OlltpUt the read address during a low-level perlod of the control slgnal CNT and to selectlvely output the ~rlte address durlng a hlgh-level perlod of the control slgnal CNT. The read or ~rite address output from the selector 219 ls supplled to the RAM 2l3.
The read address of the RAM 213 ls supplied from the tlmer 220, whlch generates the read address based on the decodlng clock signal CLK. On the other hand, the wrlte address of the RAM
213 is supplled from the wrlte address generator 221. An lnltlal value of the wrlte address generator 221 is supplied from the adding circuit 161. The wrlte address generator 221 counts up based on the write clock slgnal WCK which is received from the receivlng process part 17. In FIG. 14, (e~ shows the wrlte clock signal WCK, and the initial value of the write address is determined durlng a time T.
The decoding clock slgnal CLK ls also supplied to the delay clrcuit 217. Hence, lf the decodlng clock slgnal CLK rlses during the high-level period of the control slgnal CNT, then the supply of the rislng edge of the decodlng clock signal CLK to the register 218 is delayed by the delay circuit 217 until the read address is selectively supplied from the selector 219 and supplied to the RAM 213. As a result, the cell data read out frorn the RAM
based on the read address is set in the reglster through the bus 225 in response to the decoding clock signal CLK, which ls received from the delay circuit 217. The content of the register 218 is decoded ~y the decodlng part 18 responsive to the decoding i ~

CA 020~396 1998-01-07 ~ . .

clock signal CLK.
Next, a descriptlon will be given of the operating prlnclple of a thlrd embodlment of the delay dlstortlon suppresslng system according to the present lnventlon, by referring to FIG. 15.
The system shown in FIG. 15 lncludes a coding part 101, a cell formlng part 102 whlch includes a prlorlty cell generatlng part 910, a flrst multiplexing part 103, a second multlplexlng part 104, a transmisslon llne 105; a demultlplexlng part 106, a cell dlsassembllng part 107, which includes a distortion time detecting part 950 and a distortlon suppressing time calculatlng part 951, a dlstortlon suppressing part 108, and a decoding part 109, whlch are connected as shown.
In this embodlment, the transmltting end regards a first cell of a slgnal such as an audlo slgnal as a priorlty cell, and transmlts thls prlorlty cell over a path, which has a mlnimum cell delay. The cells, whlch follo~ the first cell, are transmitted over a normal path. At the receiving end, the delay times of the cells, which follow the priority cell, are obtalned based on the arrlval times of the prlorlty cell and the cells followlng the prlorlty cell. A maxlmum delay time of the cells which follow the prlorlty cell ls obtained statlstlcally, and the delay tlmes of the cells whlch follow the prlority cell are ad~usted so as to become the maximum delay time, thereby suppressing the delay distortion.
At the transmitting end, an origlnal slgnal such as an audlo slgnal is dlgitized ln the codlng part lOl and cells are formed in the cell forming part 102. The first informatlon of .~
~.

CA 020~S396 1998-01-07 the original signal ls lnput to the prlority cell generatlng part 910 wherein a prlorlty cell ls generated. An ldentlflcation code, whlch lndlcates the prlority cell, ls added withln the lnformation and supplied to the second multiplexlng part 104. The prlorlty cell does not pass through a buffer of the first multiplexlng part lQ3, and ls thus not sub~ect to the cell dlsposal. Hence, the prlority cell has a mlnlmum cell delay, and ls processed at the recelvlng end as having a minlmum delay dlstortlon, that ls, a zero dlstortion time.
The cells whlch follow the prlorlty cell are input to the flrst multlplexlng part 103 from the cell formlng part 102.
At the flrst multiplexlng part 103 f the cells, are multlplexed wlth the normal cells which are received from cell forming parts 102, whlch correspond to other termlnals. The multlplexed cells from the first multlplexlng part 103 are lnput to the second multlplexlng part 104. The second multlplexing part 104 multlplexes the cells, whlch are recelved from a plurallty of first multlplexlng parts 103 and the priority cells, whlch are recelved from a plurallty of cell formlng parts 102. The multlplexed cells from the second multlplexlng part are transmltted to a node ~exchange} at the other end vla the transmlsslon llne 105, whlch corlnects to the destlnatlon. In actual practlce, the multlplexed cells are flrst subiected to a swltchlng ln unlts of cells in an ATM switch (not shown~ before belng transmltted to the transmlsslon llne 105.
At the node on the other end ~receiving end), the multlplexed cells recelved over the transmisslon llne 105 are lnput to the demultiplexing part 106. In actual practlce, the .

CA 020~396 1998-01-07 3 ~ ~
~ 9 27879-89 multlplexed cells are subiected to a swltchlng ln the ATM swltch before ~elng input to the dernultiplexlng part 106. The multlplexed cells are demultlplexed lnto the cells, which correspond to each of the terminals. The demultiplexed cells are input to the cell dlsassembllng part 107. When the cell disassernbling part 107 detects the priorlty cell, the dlstortion time detecting part g50 measures the timlng with reference to the arrival time of the priorlty cell. The arrival of the following cells is awaited and the cells are dlsassembled. The dlsassembled cells are supplied to the decoding part 109 through the distortion suppressing part 108.
The delay distortion suppresslng operation carried out at the recelvlng end wlll now be descrlbed wlth reference to FIG.
16. When the first one of the cells following the priority cell arrives at the receivlng end, the dlstortlon tlme detectlng part 950 measures arrival time of this flrst cell wlth reference to the arrival time of the priority cell. The arrival times of the other following cells are measured similarly by the dlstortion time detectlng part 950 so as to detect the delay tlme of each cell.
The time intervals with which the norrnal cells, that ls, the cells other than the priorlty cell, are generated, ls known at the receivlng end because the cell generation intervals at the transmlttlng end ls known. Hence, the delay tlme of each cell can be calculated by deterl-nining the difference between the actual reception time of the cell and the predlcted receptlon tlme of the cell with respect to the reception time of the priority cell.
The ~istortlon tlme I shown in FIG. 16 can be obtained for each cell by obtaining the delay time for each cell. The distortion ., CA 020~396 1998-01-07 ~ 27879-89 times for a predetermined number of cells are measured, and a rnaximum distortion time ImaX shown in FI~. 16 is obtained from the measured distortion times. In FIG. 16, tx denotes the reception time of the priority cell.
~ hen the maximurn distortion time ImaX is obtained, the distortlon time detecting part 950 of the cell disassembling part 107 supplies the distortion times I of each of the following cells to the distortion suppressing time calculating part g51. The distortion suppressing tirne calculating part g51 calculates the difference between the maxlmum distortion time ImaX and the distortion time of each cell, that is, calculates ImaX-I = y shown in FIG. 16 for each cell. The calculation result y for each cell is supplied to the distortion suppressing part 108 which delays each cell by the corresponding delay time y. As a result, each cell is delayed by the constant time ImaX in total, and the delay distortion is effectively suppressed.
It was described above that the cell forming part 102 at the transmitting end generates the priority cell from the priority cell generating part 910 only when the first information of the original signal is detected. However, the cell forming part ln2 may be designed to generate the priority cell frorn the priority cell generatlng part ~flO for every predetermined period of the original signal. In this case, the reference time can be obtained at the receiving end for every predetermined time. The maximum distortion time can be appropriately changed depending on the state of the communication path.
Next, a more detalled description of the third embodiment wlll be given with reference to FIGS. 17 through 20.

CA 020~396 1998-01-07 ~ 1 2787g-89 FIGS. 17A and 17B show the thlrd embodlment, FIG. 18 shows the constructlon ln the viclnlty of the multiplexing part 103~ FIG. 19 shows the constructlon ln the vlclnity of the demultlplexlng part 10~ and FIG. 20 shows the cell format. In FIG,S. 17A, 17B, 18 and 19, those parts, whlch are the same as those correspondlng parts in FIG. 15, are designated by the same reference numerals, and a descrlptlon thereof wlll be omltted.
FIGS. 17A and 17B shows the structure provided between two termlnals, whlch are connected to two exchanges (swltchlng systems). In FIG~. 17A and 17B, the second multlplexing part 104 is shown as an OR (loglcal sum~ clrcult. However, a control circuit (not shown) is actually provided to control the OR clrcult so that the plurallty of slgnals lnput to the OR circult do not overlap when obtaining the logical sum of the signals. A hybrid clrcult 111 swltches the subscrlber llne whlch connect to each terminal between the transmitting side and the receiving side of the ATM swltch.
FIG. 18 shows the viclnlty of the rnultiplexing part 103 shown ln FIG. 17A. In FIG. 18, the orlglnal signal, such as the audlo slgnal, which is transmitted from the terminal, is supplied to the cell formlng part 102 through the coding part 101 ~hown in FIG. 17A. The cell forming part 102 includes a head detector 121, which detects the head of the audio signal or the like. When the head detector 121 detects the head, the priority cell generating part 910 is started in response to an output of the head detector 121. The priority cell generating part 910 adds a speclflc lndlcatlon to the head (flrst) cell, whlch corresponds to the head of a series of continuous voice information~ and supplies this ~.. ...

CA 020~396 1998-01-07 7 ~
.,_ I , . . . .

~ 2 27879-89 cell as the prlorlty cell to the second multlplexing part 104 directly, i.e. not through the first multiplexing part 103. The serles of continuous voice lnformation is divlded lnto a plurallty of cells. The second multlplexing part 104 multlplexes the priorlty cell from the priorlty cell generatlng part 910 wlth the other cells, whlch are recelved from the flrst multlplexlng part 103. The multlplexed cells are output from the second multl~lexing ~art 104 and transmltted to the transmission line 105 through a switching part (not shown).
As shown in FIG. 20, each cell is made up of 53 bytes.
The first 5 bytes of the cell form an ATM header in whlch varlous prescrlbed lnformation such as VPI~ ~CI and HEC are set. The 48 bytes followlng the 5-byte ATkl header form the lnformatlon fleld, and a 3-byte adaptation header is provlded ln the first 3 bytes of the information field. The 3-byte adaptatlon header includes a 15-bit segment number SN, a l-bit segment identifler SID, a 3-blt rate code RT, and a 5-blt cyclic redundancy check code CRC. The segrnent number SN lndicates the position (number) of the cell.
The orlglnal lnformatlon is dlvlded lnto a plurallty of cells based on the SN. The segment identifier SID indicates the identification lnformation of the segment. In this embodlment, the specific indicator for lndicating the priority cell ls lnserted ln one blt of the adaptation header. For example, one bit within the 15-bit segment number SN is used as the specific lndicator bit. The priorlty cell ls lndlcated lf the speclflc indicator blt is "1". The cells following the priority cell are indicated if the specific indlc~tor blt is "0".
FI~. 21 shows an em~odiment of the cell forming part CA 020~396 1998-01-07 33 ~787g-89 102. In FIG. 21, the priority cell generating part 9lO includes a first circuit part 910A for settlng the speciflc indicator bit to "1" in the adaptation header of the cell in response to the output of the head detector 121 if the head detector 121 detects the head of the original signal; and a second circuit part 910B for resetting the speciflc indicator bit to "O" in the adaptation header of the cell in response to the output of the head detector 121 if the head detector 121 detects no head of the orlginal signal. The priority cell OUtpllt from the first circult part 910A
is supplied to the second rnultiplexing part 104, while the normal cell output from the second clrcult part 9lOB ls sllpplled to the first multiplexing part 103.
FIG. 19 shows the vicinity of the demultiplexing part 106 shown in FIG. 17B. In FIG. l9, the multlplexed cells, which are received from the transmission line 105 through the switching part (not shown), is lnput to the demultiplexing part 106, ~herein the multlplexed cells are demultiplexed into cells by destination.
Each demultiplexed cell is supplied to the corresponding cell disassembling part 107 by destination. The cell disassembling part 107 has the distortlon time detecting part 950 and the suppressing til-ne calculating part 951 in addition to a mechanism for disassembling the cells.
If the cell disassembling part 107 shown in FIG. 19 detects the arrival of the priority cell, a timer 710 of the time detecting part 950 is started. The cell disassembling part 107 detects the arrival of the priority cell by a detecting circult 107A, which detects whether or not the specific indicator bit ~within the adaptation header of the received cell has the value CA 020~396 1998-01-07 "1". If the cell following the prlorlty cell arrlves, the measured value T of the timer 710 is input to a subtractlng circult 712. The subtractlng circuit 712 also receives a tlme value t from a prediction circult 711. This time value t describes a predicted cell lnterval dependln~ on the klnd of original signal. As a result, the subtracting clrcult 712 calculates T-t = I, and supplies the result I to the dlstortlon suppressing time calculating part 951. The timer 710 of the suppressing tlme detecting part 950 ls reset to start a new tlmer operation immediately after the timer 710 supplies the measured value T to the subtracting circuit 712 in response to the arrival of the cell. Hence, the suppressing tlme I is successively supplied to the distortion suppressing time calculating part 951.
A maximum distortion time detector 720 of the distortion suppresslng tlme calculating part 951 detects an~ hol~s a maximum suppressing time ImaX out of a predetermined number of suppressing times I, which are received from the suppressing tlme detecting part g50. Thereafter, the suppressing time detecting part 951 is started to calculate ImaX-I = y with respect to the suppressing time I, w~lich is received from the suppressing time detecting part 950. In other words a subtracting circult 721 subtracts the suppressing time I received from t}-'e suppressing time detecting part 950 from the maximum suppressing time ImaX received from the maximum suppressing time detector 720. The resulting y output from the subtracting circuit 721 is supplied to the distortion suppressing part 108. The distortion suppressing part 108 delays the disassembled cell ~that is, only the data of the information field) in a ~elay circuit 180 in response to the output slgnal of , y ~, the dlstortion suppresslng tlme calculatlng part 951 lndlcatlng the calculated result y. The output data of the dlstortion suppressing part 108 ls supplled to the decodlng part 109, whlch decodes the cell delayed by a predetermlned delay tirne and therefore ellminates the delay dlstortlon. The decoded data output from the decodlng part 109 is transmitted to the terminal via the hybrld clrcult 111.
Further, the present lnventlon is not limlted to these embodlments, but varlous variations and modificatlons may be made without departing from the scope of the present lnvention.

Claims (11)

1. A delay distortion suppressing system for an asynchronous transfer mode communication system which includes at least a transmitting end and a receiving end which are connected via transmission paths, said delay distortion suppressing system comprising:
first means, provided in the transmitting end, for transmitting information in the form of cells in an asynchronous transfer mode;
second means, provided in the receiving end, for delaying each cell which is received via a transmission path by a predetermined delay time relative to a reference point;
third means, provided in the receiving end and coupled to said second means, for varying the reference point depending on an arrival time of the cell which is received at the receiving end via the transmission path, so that a delay distortion of the cells is suppressed;
fourth means, provided in the receiving end and coupled to said second means, including decoding means for decoding the cells output from said second means;
wherein each cell is made up of a header and an information field;
said first means includes means for inserting a cell transmitting time in the header of each cell;
said second means includes storage means for storing each cell received via the transmission path, inserting means for inserting a cell reception time in the header of each cell received via the transmission path, and control means for controlling write and read operations of said storage means based on cell transmission time and the cell reception time included in the header of each cell which is read out from said storage means, a delay distortion suppressing range and the predetermined delay time so that the cell which arrives first is written into said storage means and read out after a time which corresponds to the delay distortion suppressing range;
said third means varies the reference point when a difference between the cell transmission time and the cell reception time is smaller than the predetermined delay time;
and the predetermined delay time is a minimum delay time of each cell which is received at the receiving end.

2. The delay distortion suppressing system as claimed in claim 1, wherein said second means further includes timer means for counting a decoding clock signal which is supplied to said decoding means, and said inserting means inserts a counted value of said timer means as the cell reception time.

3. The delay distortion suppressing system as claimed in claim 1, wherein said control means controls said storage means so that said decoding means receives only the - 38 ~

information field of each cell read out from said storage means.

4. The delay distortion suppressing system as claimed in claim 1, wherein said storage means includes a first-in-first-out memory.

5. The delay distortion suppressing system as claimed in claim 1, wherein said storage means includes a random access memory.

6. The delay distortion suppressing system as claimed in claim 1, wherein said control means controls said storage means to read out the header of the cell from said storage means every time a decoding operation of said decoding means ends, and said control means controls said storage means to read out the information field of the cell from said storage means to be supplied to said decoding means when said third means changes the reference point.

7. A delay distortion suppressing system for an asynchronous transfer mode communication system which includes at least a transmitting end and a receiving end which are connected via transmission paths, said delay distortion suppressing system comprising:
first means, provided in the transmitting end, for transmitting information in the form of cells in an asynchronous transfer mode;
second means, provided in the receiving end, for delaying each cell which is received via a transmission path by a predetermined delay time relative to a reference point;
third means, including means for setting an arrival time of the priority cell as the reference point and means for statistically obtaining a maximum delay time of the cells following the priority cell; and fourth means, provided in the receiving end and coupled to said second means, including decoding means for decoding the cells output from said second means;
wherein said first means includes priority cell generating means for generating a priority cell from a head of the information, said priority cell being transmitted via a transmission path which causes a minimum delay while other cells following the priority cell are transmitted via other transmission paths having normal delays; and said second means delays each cell by the predetermined delay time which is set independently for each cell so that a total delay time of each cell becomes the maximum delay time.

8. The delay distortion suppressing system as claimed in claim 7, wherein each cell is made up of a header and an information field which includes an adaptation header, and said priority cell generating means inserts a specific indication in the adaptation header of the cell to indicate that the cell is the priority cell.

9. The delay distortion suppressing system as claimed in claim 8, wherein the adaptation header includes a segment number, a segment identifier, a rate code and a cyclic redundancy check code, and a specific indication bit.

10. The delay distortion suppressing system as claimed in claim 7, wherein said priority cell generating means transmits the priority cell with a predetermined period.

11. The delay distortion suppressing system as claimed in claim 1, wherein said first means includes means for multiplexing the cells before transmission to the transmission path, and said second means includes means for demultiplexing the multiplexed cells received from the transmission path.