CA2055845A1 - Method of mounting semiconductor elements - Google Patents

Method of mounting semiconductor elements

Info

Publication number
CA2055845A1
CA2055845A1 CA002055845A CA2055845A CA2055845A1 CA 2055845 A1 CA2055845 A1 CA 2055845A1 CA 002055845 A CA002055845 A CA 002055845A CA 2055845 A CA2055845 A CA 2055845A CA 2055845 A1 CA2055845 A1 CA 2055845A1
Authority
CA
Canada
Prior art keywords
semiconductor elements
wiring board
electrodes
bump electrodes
heat sink
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
CA002055845A
Other languages
French (fr)
Inventor
Masanori Nishiguchi
Atsushi Miki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Masanori Nishiguchi
Atsushi Miki
Sumitomo Electric Industries, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2312665A external-priority patent/JPH04184950A/en
Priority claimed from JP2312666A external-priority patent/JPH04184951A/en
Priority claimed from JP2312667A external-priority patent/JPH04184952A/en
Application filed by Masanori Nishiguchi, Atsushi Miki, Sumitomo Electric Industries, Ltd. filed Critical Masanori Nishiguchi
Publication of CA2055845A1 publication Critical patent/CA2055845A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8012—Aligning
    • H01L2224/80136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/80138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8014—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Abstract

ABSTRACT OF THE DISCLOSURE
A method of mounting a plurality of semiconductor elements each having bump electrodes on a wiring board by pressing the semiconductor elements to the wiring board while aligning the electrodes and heating the structure. In the mounting method, one or more heat sinks are previously joined to the backs opposite to the surfaces with the bump electrodes formed thereon of the semiconductor elements.

Description

2~8~

~E~HOD OF MOUNTING SENICONDUCTOR ELEMENTS

BACKGROUND OF THE INVENTION
Field of the Invention The present invention relates to a method of mounting a plurality of semiconductor elements on a wiring board.
Description of the Related Art When a plurality of semiconductor elements are joined to a wiring board by face down bonding, the following method has been carried out conventionally. That is, the plurality of semiconductor elements are mounted on the wiring board by pressing the plurality of semiconductor elements having bump electrodes with soldering bumps formed thereon to the wiring board while aligning the electrodes to fix them temporarily and then heat-melting the soldering bumps.
As the heat produced in the semiconductor element thus mounted is compelled to escape via the bump electrodes toward the wiring board, the thermal resistance has been extremely high.
This has posed a serious problem particularly when - the power consumption of such a semiconductor element is large.
As a result, there has generally been employed a method of providing a heat sink as a radiation path for semiconductor elements ("Handbook of Semiconductor Nounting 2 0 5 e~

Technique~ compiled by Koqhi Nihei, Masao Hayakawa and Fumio Miyashiro, K.K. Science Forum (1986)).
However, the above method is still problematical because the heat sink is joined to a plurality of semiconductor elements after the elements are joined to a wiring board by face down bonding. In other words, slants of the semiconductor elements, variations of their thickness and the like tend to cause bad contact between the heat sink and the semiconductor elements.

SUMMARY OF THE INVENTION
The present invention has been made in view of the foregoing problems in the conventional method and an object of the invention is therefore to provide a method of mounting semiconductor elements which ensures that a plurality of semiconductor elements to be mounted on a wiring board by face down bonding are made to contact respective radiation fins or heat sinks to reduce their thermal resistance.
In order to accomplish the above object, a method of mounting semiconductor elements according to the present invention comprises the steps of providing a plurality of semiconductor elements each having bump electrodes, joining radiation means to backs opposite to surfaces with the bump electrodes formed thereon of the semiconductor elements, pressing the semiconductor elements to a wiring board while ' ' 2V~58~5 aligning the bump electrodes, and heating to mount the semiconductor elements on the wiring board.
Since the bump electrodes are joined to electrodes on the wiring board by face down bonding after the radiation means is joined to the backs opposite to the surfaces with the bump electrodes formed thereon of the semiconductor elements, the radiation means and the semiconductor elements are made to contact certainly even though the semiconductor elements vary in thickness or slant, so that the thermal resistance therebetween is reduced.

BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is an explanatory diagram for explaining a method of mounting semiconductor elements accordinq to a first embodiment of the present invention.
Figs. 2 and 3 are explanatory diagrams f or explaining a method of mounting semiconductor elements according to a second embodiment of the present invention:
Fig. 2 illustrates a process of joining semiconductor elements to a heat sink; and Fig. 3 illustrates a process of joining the semiconductor elements to a wiring board by face down bonding.
Figs. 4 and 5 are explanatory diagrams for explaining a method of mounting semiconductor elements according to a 2S third embodiment of the present invention:

2~5~

Fig. 4 illustrates a process of ~oining semiconductor elements to a wiring board by face down bonding; and Fig. 5 illustrates self-alignment of the semiconductor elements.

s DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Hereinafter, three embodiments of the present invention will be described in detail with reference to the accompanying drawings.
First Embodiment First, as shown in Fig. 1, heat sinks 1 are joined to a plurality of semiconductor elements 2, respectively.
As bump electrodes with soldering bumps 4 formed thereon are arranged on the surface of each semiconductor element 2, the heat sink 1 is joined to the back on the opposite side thereof.
In this case, AuSn or the like is used to join the semiconductor elements 2 to the respective heat sinks 1 respectively.
Then the plurality of semiconductor elements 2 are joined to a wiring board 5 by face down bonding.
More specifically, the semiconductor elements 2 are mounted on the wiring board 5 by pressing the semiconductor elements 2 to the wiring board 5 while aligning the electrodes to fix them temporarily and then heat-melting the soldering bumps 4.

Subsequently, molding resin 6 is formed among the wiring board 5, the semiconductor elements 2 and the heat sinks l so as to reinforce them.
A resin material having good thermal conductivity is suitable for the molding resin 6.
As seen from the foregoing description, the heat sinks 1 and the semiconductor elements 2 are previously joined to each other before the semiconductor elements 2 and the wiring board 5 are joined by face down bonding to ensure lo that the semiconductor elements 2 come in contact with the heat sinks 1, so that thermal resistance therebetween becomes reducible in this way.
Even though the plurality of semiconductor elements 2 differ in thickness or they are mounted on the wiring board 5 while being slanted, the contacts between the semiconductor elements 2 and the heat sinks l are established for certain.
Accordingly, even though the power consumption of the semiconductor elements 2 mounted on the wiring board S is large, the heat generated therefrom is allowed to quickly escape from the heat sinks l. Reliability of the elements is thus improved.
Further, since the semiconductor elements 2 and the wiring board 5 are reinforced with the molding resin 6, no deficiency in their strength arises.

2 ~

Although the molding resin has been used in the above embodiment, the use of such molding resin may be omitted if the soldering bumps 4 provide satisfactory junctions.
Although the soldering bumps 4 have been used in the above embodiment, Au, AuSn, In bumps or the like may be used instead.
Second Embodiment First, as shown in Fig. 2, a resist pattern 3 is formed on the undersurface of a heat sink 1 for use as a lo radiation fin.
The resist pattern 3 is used for aligning a plurality of semiconductor elements 2 and formed by photolithography, for instance.
For this reason, the shape of an opening of the resist pattern 3 is rendered consistent with the exterior of each semiconductor element and the openings are provided corresponding to positions where the semiconductor elements are subjected to face down bonding.
On the other hand, a plurality of bump electrodes with soldering bumps 4 projectively formed thereon are disposed on the surface of each semiconductor element 2.
Subsequently, as shown in Fig. 2, the backs of the semiconductor elements 2 opposite to the surfaces with the bump electrodes formed thereon are positioned on and joined to the heat sink 1.

~` 2~8~

In this case, AuSn or the like i8 used to join the semiconductor elements 2.
Then the plurality of semiconductor elements 2 are joined to a wiring board 5 by face down bonding as shown in 5 Fig. 3.
More specifically, the semiconductor elements 2 are mounted on the wiring board 5 by pressing the semiconductor elements 2 to the wiring board 5 while aligning the electrodes to fix them temporarily and then heat-melting the lo soldering bumps 4.
As seen from the foregoing description, the heat sink l and the plurality of semiconductor elements 2 are previously joined together before the semiconductor elements 2 and the wiring board 5 are joined by face down bonding to ensure that the semiconductor elements 2 come in contact with the heat sink 1 without slants of all the surfaces of the semiconductor elements 2 against the corresponding surface of the heat sink l, so that the thermal resistance therebetween is reducible in this way.
Accordingly, even though the power consumption of the semiconductor elements 2 mounted on the wiring board 5 is large, the heat generated therefrom is allowed to quickly escape from the heat sink 1. Reliability of the elements is thus improved.
The resist pattern has been used to position the plurality of semiconductor elements relative to the heat sink 8 4 ~

in this embodiment. However, provided the relative position between the semiconductor elements and the heat sink is determined certainly, the use of the resist pattern may be omitted.
Third Embodiment In this embodiment, a resist pattern 3 is formed on the undersurface of a heat sink 1 and a plurality of semiconductor elements 2 are joined to the heat sink l, in the same manner as in the second embodiment.
However, solder 8 (see Fig. 5) having a melting point lower than that of soldering bumps 4 is used to join the semiconductor elements 2.
The positioning accuracy of the semiconductor elements 2 may be defined liberally: e.g., +50 ~m in this embodiment instead of _10 ~m conventionally specified for a bump having a diameter of 80 ~m and an electrode of wiring board 5 having a diameter of 100 ~m.
~hen the semiconductor elements 2 are joined to the wiring board 5 by face down bonding as shown in Fig. 4.
More specifically, the semiconductor elements 2 are mounted on the wiring board 5 by pressing the semiconductor elements 2 to the wiring board 5 while aligning the electrodes to fix them temporarily and then heat-melting the soldering bumps 4.
Even if the semiconductor elements 2 are accurately positioned relative to the wiring board 5 at this stage, the , ..

-20~58~

semiconductor elements are self-aligned and automatically moved to respective accurate positions for mounting.
In other words, a plurality of recessed or concave electrodes 7 are bored in the wiring board 5 and as these electrodes 7 correspond in position to the soldering bumps 4 of the respective bump electrodes, the electrodes 7 and the bumps 4 are unable to fit together completely unless they are perfectly held in position.
The soldering bumps 4 will fail to fit into the lo recessed electrodes 7 completely as shown in Fig. 5 if the positioning accuracy of both is at approximately +50 ~m.
However, the semiconductor elements 2 are temporari~y fixed to the wiring board 5 in such a state that the leading ends of the soldering bumps remain fitted in the electrodes 7, and the force of moving the soldering bumps to the center positions of the electrodes in that state.
When heating is applied subsequently, the low melting point solder 8 melts before the soldering bumps 4 melt and the semiconductor elements 2 are caused to slide on the heat sink 1 into accurate positions respectively due to the force of moving the soldering bumps 4 to the center positions of the recessed electrodes 7.
Thereafter, if heating is continuously applied, the solder bumps 4 melt, whereby the recessed electrodes 7 and the bump electrodes become joined.

2 ~ 3 When heating is stopped later, the solder bumps solidify first and then the low melting point solder 8 solidifies.
As seen from the foregoing description, the heat sink 1 and the semiconductor elements 2 are joined before the semiconductor elements 2 and the wiring board S are ~oined by face down bonding to ensure the contact between the semiconductor elements 2 and the heat sink 1, so that thermal resistance therebetween is reduced.
lo Moreover, as the semiconductor elements are moved automatically by self-alignment to respective accurate positions relative to the wiring board, no high-accurate positioning technique is required. With this arrangement, the mounting time is shortened, thus improving reliability.

Claims (9)

1. A method of mounting semiconductor elements comprising the steps of:
providing a plurality of semiconductor elements each having bump electrodes;
joining radiation means to backs opposite to surfaces with the bump electrodes formed thereon of said semiconductor elements;
pressing said semiconductor elements to a wiring board while aligning the bump electrodes; and heating to mount said semiconductor elements on said wiring board.
2. The method according to claim 1, wherein said radiation means includes a plurality of heat sinks corresponding to said semiconductor elements respectively.
3. The method according to claim 1, further comprising a step of forming molding resin among said wiring board, said semiconductor elements and said radiation means after the heating step.
4. The method according to claim 1, wherein said radiation means includes a single heat sink.
5. The method according to claim 1, wherein electrodes of said wiring board is formed in a convex shape.
6. The method according to claim 1, further comprising a step of forming a resist pattern on said radiation means to align said semiconductor elements before the joining step.
7. The method according to claim 4, further comprising a step of forming a resist pattern on an undersurface of said heat sink to align said semiconductor elements before the joining step.
8. The method according to claim 1, electrodes of said wiring board is formed in a concave shape.
9. The method according to claim 8, wherein solder having a melting point lower than that of material of said bump electrodes is used to join said semiconductor elements to said radiation means.
CA002055845A 1990-11-20 1991-11-19 Method of mounting semiconductor elements Abandoned CA2055845A1 (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP2-312665 1990-11-20
JP2-312666 1990-11-20
JP2-312667 1990-11-20
JP2312665A JPH04184950A (en) 1990-11-20 1990-11-20 Semiconductor element mounting method
JP2312666A JPH04184951A (en) 1990-11-20 1990-11-20 Semiconductor element mounting method
JP2312667A JPH04184952A (en) 1990-11-20 1990-11-20 Semiconductor element mounting method

Publications (1)

Publication Number Publication Date
CA2055845A1 true CA2055845A1 (en) 1992-05-21

Family

ID=27339261

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KR960000696B1 (en) 1996-01-11
KR920010761A (en) 1992-06-27
AU8799891A (en) 1992-05-21
EP0490125B1 (en) 1996-03-13
DE69117891D1 (en) 1996-04-18
US5244142A (en) 1993-09-14
DE69117891T2 (en) 1996-07-25
AU640537B2 (en) 1993-08-26
EP0490125A1 (en) 1992-06-17
US5348214A (en) 1994-09-20

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