CA2056781C - Multichip module - Google Patents
Multichip moduleInfo
- Publication number
- CA2056781C CA2056781C CA002056781A CA2056781A CA2056781C CA 2056781 C CA2056781 C CA 2056781C CA 002056781 A CA002056781 A CA 002056781A CA 2056781 A CA2056781 A CA 2056781A CA 2056781 C CA2056781 C CA 2056781C
- Authority
- CA
- Canada
- Prior art keywords
- wiring layer
- conductive track
- standard
- module
- aluminium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5382—Adaptable interconnections, e.g. for engineering changes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01084—Polonium [Po]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Abstract
Multichip module is provided with standard wiring layers comprising standardized wiring patterns, a custom wiring layers comprising customized wiring patterns and chip mounting pads, a plurality of antifuses which are positioned in standardized installation positions and each of which provides the possibility of defining the presence or absence of an electrical connection between a specified conductive track of a standard wiring layer and a specified conductive track of the custom wiring layer, and a plurality of wafer chips which are electrically connected to the chip mounting pads and mounted on the chip mounting pads, whereby disadvantages of hybrid integrated circuits are overcome while offering numerous advantages of hybrid integrated circuits.
Description
` ~ 20S6781 MULTICHIP MODULE
~A~BQ~ QE_~E_l~YE~
1. Field of the Invention The Present invention relates to the integration of an electronic circuit. More particularly, the present invention relates to a multichiP module comprising a pluralitY of wafer ch iPS .
~A~BQ~ QE_~E_l~YE~
1. Field of the Invention The Present invention relates to the integration of an electronic circuit. More particularly, the present invention relates to a multichiP module comprising a pluralitY of wafer ch iPS .
2. DescriPtion of the Prior Art Circuit integration of electronic equipment not onlY
provides the possibility of miniaturizing the size of entire electronic apParatuses, but it also offers numerous advantages including imProvement in the reliabilitY and reduction of the power consumPtion of electronic equiPment. Accordingly, circuit integration of digital circuits which Perform logical operations of binary numbers as well as circuit integration of various types of analog circuits has been attemPted.
An integrated circuit which integrates onlY digital circuits is called a digital integrated circuit. On the other hand. an integrated circuit which integrates onlY analog circuits is called an analog integrated circuit.
Furthermore, in such digital and analog integrated circuits, an integrated circuit which is integrated on a single wafer chiP is called a monolithic integrated circuit.
Monolithic integrated circuits not onlY provide the PossibilitY of drastically miniaturizing electronic circuits.
but also allow improvement of reliabilitY. reduction of power ~056781 consumption, and the like.
Also, an integrated circuit which integrates a mixture of more than one digital or analog integrated circuit (wafer chip) and. as required, other devices or Parts, is called a hybrid integrated circuit.
Compared with monolithic integrated circuits, hYbrid integrated circuits allow efficient development of circuit integration of large-scale electronic circuits in a relatively short Period of time. Furthermore, hYbrid integrated circuits also provide an easY waY to realize integrated circuits which use a combination of different processes, such as the accommodation of biPolar analog integrated circuits and CMOS
(complementary metal-oxide-semiconductor) digital integrated circuits in the same Package.
However, Problems such as the relative difficultY of development of integrated circuits of the des;red electronic circuits, a longer Period of develoPment and higher development costs have been associated with the above-described monolithic integrated circuits.
These Problems become especially significant as the scale of the electronic circuits, which are to be integrated, increase.
Furthermore, the difficulty in realizing a change in the design (change in the circuit) is another problem with the above-described monolithic integrated circuits. The need for a maior design change involves the Problem that the costs and the Period of time required for the design change are equal to the costs and time needed for an entirely new development.
DeveloPment costs for an ordinarY monolithic integrated circuit are said to amount to approximatelY 5 million yen.
In addition, higher Process costs are a problem with monolithic integrated circuits when integrated circuits such as BiCMOS integrated circuits are fabricated bY emPloYing a different Process.
Major circuit elements which are integrated into a single wafer chiP are transistors, diodes and resistors. As these circuit elements are limited to those with relatively small capacities, electronic circuits which allow integration into monolithic integrated circuits are subject to nu~erous restrictions.
On the other hand, a Problem concerning the above-described hybrid integrated circuits is a decline in reliabilitY with regard to the conductive tracks which interconnect a pluralitY of wafer chips, namelY, the digital or analog integrated circuits which comPose the hYbrid integrated circuit.
Another Problem is that, due to the interconnecting conductive tracks between a PluralitY of wafer chiPs and the like, the mounting area increases, which in turn results in a decrease in the overall degree of integration.
Another issue is the difficulty of handling during Production.
ComPared with monolithic integrated circuits, the development of hYbrid integrated circuits is easY. However, as with monolithic integrated circuits, a change in the design of hybrid integrated circuits is difficult. The need for a major change in the design of a hybrid integrated circuit involves the problem that a long period of time for the design change and high development costs are required.
In general, the development costs for a hybrid integrated circuit are said to amount to approximately 1 million yen.
SUMMARY OF THE INVENTION
The present invention was carried out in order to solve the above-described existing problems. It is an object of the present invention to provide a multichip module which allows the relatively easy development of relatively large-scale electronic circuits whose development is difficult with monolithic integrated circuits, which realizes a module that allows integration of a combination of different processes, and which provides the possibility of reducing the period of development and development cost.
According to the present invention, there is provided a multichip module including:
- at least one standard wiring layer comprising standardized wiring patterns, - a custom wiring layer on the at least one standard wiring layer and comprising customized wiring patterns and chip mounting pads, - a plurality of connection defining means positioned in standardized installation positions and defining an electrical connection between a specified conductive track of the standard wiring layer and a specified conductive track of the custom wiring layer, and ~-~A
- a plurality of wafer chips which are electrically connected to the chip mounting pads and mounted on the chip mounting pads.
Preferably, the at least one standard wiring layer is a plurality of the standard wiring layers, and - the plurality of connection defining means positioned in standardized installation positions and defining the electrical connection between a specified conductive track of one of the plurality of standard wiring layers and at least one of the following:
- a specified conductive track of another one of the plurality of standard wiring layers or a specified conductive track of the custom wiring layer; and a specified conductive track of a standard wiring layer.
The object is also achieved by using antifuses as a means for defining connections.
Further, the object is achieved by providing the multichip module with a standardized active element as well.
The multichip module according to the present invention integrates in the same manner as conventional hybrid circuits a mixture of a plurality of wafer chips, that is, digital or analog integrated circuits and a plurality of devices and parts, and it offers numerous advantages of hybrid integrated circuits.
In addition to this, a multilayered wiring layer configuration in the multichip module according to the present invention aims to overcome the disadvantages of hybrid integrated circuits. That is, multilayered wiring layers not only improve the reliability of the wiring, but also allow the ~' ~)t~
; 20S6781 realization of complex connections of conductive tracks in an efficient way.
In addition, in the multichip module according to the present invention, the structure of the conductive tracks interconnecting the PluralitY of wafer chips, devices and Parts, which compose the multichip module, is able to meet with requirements of multi-Product, small-scale Production.
That is, according to the Present invention, it is possible to readily design this kind of wiring and to readilY make a design change.
The multichiP module of the Present invention comprises standard wiring layers with standardized wiring patterns as well as a custom viring layer which comprises customized wiring Patterns and customized chiP mounting Pads. In addition, the multichiP module Provides a PluralitY of connection defining means which are Positioned in standardized installation Positions and each of which provides the PossibilitY of defining the Presence or absence of an electrical connection between a specified conductive track of a standard viring laYer and a sPecified conductive track of the custom wiring laYer. The definition of the presence or absence of an electrical connection can be made in accordance with the specified method of definition of the connection defining means. To be concrete, fuses, antifuses, and the like can be used as a means for defining connections.
A configuration mainly comPrising the above-described standard wiring laYers, the custom wiring laYer and the means _ for defining connections will be hereinafter called a module board.
Among the plurality of wiring laYers of the module board, the custom wiring laYer is formed closest to the surface.
~afer chiPs, and the like can be mounted on the custom wiring layer by means of customized chiP mounting Pads.
Normally, to Prevent malfunction caused by noise, it is necessarY to Provide the wafer chiPs and the like with Power supply lines as thick and short as possible. The custom wiring allows these requirements to be met.
Accordingly, the formation of the customized wiring Patterns and customized chiP mounting Pads (by etching, and the like) of the custom wirin~ laYer is also possible during a later stage of the module board's manufacturing Process.
Also, the conductive tracks on the module board give rise to points where it is necessarY to electricallY insulate a PluralitY of conductive tracks and make the conductive tracks cross each other.
In this case, using standard wiring layers with standardized wiring Patterns facilitates the designing of the wiring so that a sPecified conductive track leaps over another conductive track. That is, it suffices to connect the conductive track, which is to leaP, to the conductive tracks of the standardized wiring Pattern by means of a connection defining means, to cross the conductive track, which is to be - leaped over, using the standardized wiring pattern, and thereafter, to make connection to the customized wiring ;
20~6781 Pattern once again bY using another connection defining means.
Accordingly, the module board of the Present invention's multichip module can be used for various multichiP modules, and for each multichip module customization of the module board is readi 1Y made. Also, the configuration of such a module board provides sufficient reliability so that satisfactory reliabilitY of the entire multichiP module is achieved.
The standard wiring laYer of the module board comPrises standardized wiring Patterns, and one standard wiring laYer or a PluralitY of the standard wiring layers maY be provided.
For examPle, if the angle of the direction of the conductive tracks of each standard wiring pattern of the pluralitY of wiring laYers is different, it is Possible to wire the module board more unrestrictedlY. What is more, the wiring length of each conductive track can be made shorter. Also, even after the design of the custom wiring laYer is comPleted, using a PluralitY of standard wiring laYers and the means for defining connections Provides a relativelY easY way to make change in the wiring. If a PluralitY of wiring layers are used, connection defining means for defining the Presence or absence of electrical connections between the PluralitY of wiring layers should be Provided.
Furthermore, the Present invention does not impose anY
restrictions on the connection defining means. However, it is expected that among the numerous connection defining means on the module board, the number of means which will define the presence of an electrical connection will be smaller than the number of means which will define the absence of an electrical connection. Accordingly, it is desirable that the connection defining means of the module board should be such that the definition of the absence of an electrical connection can be made more easily than the definition of the Presence of an electrical connection. Therefore, if antifuses are used as a means for defining connections, it suffices to make a relativelY small number of electrical connection Present definitions (create a conducting state), which allows the efficient making of definitions of all connection defining means of the entire multichip module.
Also, in the module board of the Present invention, no restrictions are imposed on whether passive elements. such as registors, and/or active elements, such as transistors, are configured or not. However, the module board requires standardized active elements such as buffer gates for the inputs and outputs with the outside of the multichip module.
Accordingly, installing active elements as well on the multichip module's module board Provides the PossibilitY of imProving design efficiencY of the multichiP module.
In the embodiments described hereinunder, the standard wiring laYers and the custom wiring laYer of the Present invention are aluminium wiring laYers. However, the present invention is not restricted to only aluminium wiring layers.
Any electrically conductive material which is suitable for the wiring can be used.
` _ 2056781 According to the present invention, a multichiP module is -~
provided, wherein it is relativelY easY to develop relativelY
large-scale electronic circuits whose development is difficult with monolithic integrated circuits. Furthermore, the Present invention realizes a module which allows the integration of a combination of different Processes, reduces the develoPment period and costs.
~BIEE_nE~Bl~lQ~_QE_~E_nB~lN~
The Preferred embodiments will be described with reference to the drawings, wherein like e`lements have been denoted throughout the figures with like reference numerals, and wherein:
Fig. 1 is a top view of an embodiment of the present invention;
Fig. 2A is a Partial side view of the embodiment;
Fig. 2B is an enlarged view of the portion designated bY
the reference D in the side view of Fig. 2A;
Fig. 3 is a cross-sectional model drawing showing the module board which is used in the first embodiment according to the PreSent invention;
Fig. 4 is a cross-sectional model drawing showing the module board which is used in the second embodiment according to the Present invention;
Fig. 5 shows a circuit diagram for the conductive tracks of the aluminium wiring laYer ALl and aluminium wiring la~er AL2 of the first embodiment;
Fig. 6 is a drawing showing a top view of the sections : - 10 -` ~ 2056781 where, in the first embodiment, a conductive track of the aluminium wiring laYer AL1. a conductive track of the aluminium wiring laYer AL2 and a conductive track of the aluminium wiring laYer AL3 cross each other;
Fig. 7A is a drawing showing a cross section of an inter ALI - AL2 antifuse which is used in the embodiment according to the present invention;
Fig. 7B is a drawing showing a cross section of an inter AL1 - AL3 antifuse which is used in the embodiment according to the present invention;
Fig. 7C, Fig. 7D and Fig. 7E are drawings showing a cross section of an inter AL2 - AL3 antifuse;
Fig. 8 is a circuit diagram for the write circuit of inter AL1 - AL2 antifuses which are used in the embodiment according to the Present invention;
Fig. 9 is a toP view of a module Pad of the module board of the embodiment according to the present invention;
Fig. 10 is a circuit diagram for the wiring of the aluminium wiring laYer ALl and the wiring of the aluminium wiring laYer AL2 of the module Pad;
Fig. llA is a circuit diagram of the standard wiring laYer in the second embodiment according to the Present invention; and Fi~. 11B is a wiring Pattern drawing showing one examPle of a wiring pattern defined in the second embodiment.
~ES~Ie~lQ~_QE_~E_~EEEB~E~_EM~Q~l~E~
Embodiments according to the Present invention will be described in detail hereinunder with reference to the accompanying drawings.
Fig. 1 is a toP view of an embodiment according to the present invention.
In Fig. 1, a multichip module 1 comprises a module board 3 and a total of five chiPs 5 mounted on the module board 3.
The module board 3 is Provided with module Pins (not shown). The module Pins provide the PossibilitY of mounting ~-the entire multichiP module 1 on, for instance, a Printed board and of making electrical connections.
The module board 3 is Provided with module pads 10b so that the module Pads 10b correspond to the module pins. The module pads 10b are electricallY connected to the module Pins.
Accordingly, external connection to the multichip module 1 can be made by making wiring connections to the module pads 10b on the module board 3.
Furthermore, the module board 3 is Provided with module pads 10a which are customized chiP mounting Pads.
In the embodiment, the installation positions of the module pads 10a are determined and customized in accordance with the tYpe and size of the chiPs 5 which are to be mounted on module board 3.
AccordinglY, there are no unnecessarY module Pads 10a on the module board 3. This allows wiring to be Performed while unrestrictedly utilizing the sPace on the module board 3.
However, if sufficient sPace is available for the conductive tracks on the module board 3, the positioning of the module pads 10a can also be standardized.
As will be described in detail and with reference to Fig.
2B hereinafter. the module pads 10a are used to make electrical connections for the chiPs 5 which are mounted on the module board 3.
Furthermore, on the module board 3, the interconnections of the module Pads 10a, which are connected to the chips 5 mounted on the module board 3, and the connections between the module Pads 10a and the module Pads 10b, with the module pads 10b being connected to the module Pins, are made bY means of module board wiring 7, which is illustrated bY solid lines.
As will be described in detail hereinafter, the module board wiring 7 has a multilayer wiring laYer structure. That is, the module board wiring 7 comPrises conductive tracks of standard wiring laYers and conductive tracks of a custom wiring laYer.
Fig. 2A is a Partial side view of the embodiment according to the present invention.
In Fig. 2A, the numerals 3, 5 and 10a indicate the same parts that the same numerals of the above-described Fig. 1 indicate.
Fig. 2B is an enlarged view of a Portion where a chiP and the module board are connected. That is, Fig. 2B is an enlarged view of the part designated by the reference D in the side view of Fig. 2A.
In Fig. 2B, the numerals 3, 5 and 10a indicate the same parts that the same numerals of the above-described Fig. 1 and Fig. 2A indicate. 205678 i In Figs. 2A and 2B, the electrical connections between the module pads lOa on the module board 3 and the chiPs 5 mounted on the module board 3, and the fixation of the chiPs S
are made bY using bumps 12 of the chiPs 5 and an electrically conductive bond 14 which is applied to the module Pads 10a on the module board 3. That is, after formation of the module pads 10a on the module board 3, a ProPer amount of the electrically conductive bond 14 is applied to the surface of the module Pads lOa, then chiPs 5 are mounted, and thereafter, the electricallY conductive bond 14 is allowed to harden.
Figs. 3 and 4 are cross-sectional model drawings showing the module boards used in the embodiments according to the present invention.
lS In Fig. 3, the lowest laYer of module board 3 is a silicon substrate. Above the lowest laYer, the following laYers and films are formed according to the following order:
a thick SiO2 film 22, a first standard aluminium wiring laYer 24, a thin SiO2 film 26, a fist inter-layer film 28, a second standard aluminium wiring laYer 30, a thin SiO2 film 26, a second inter-laYer film 32, a custom aluminium wiring layer 34 and a passivation film 36.
The standard wiring laYers of the module board 3 in Fig.
3 comprises two layers. That is, the module board 3 in the Fig. 3 is Provided with the first standard aluminium wiring laYer 24 and the second standard aluminium wiring layer 30.
An embodiment of the multichip module comPrising two of such standard wiring laYers will be hereinafter called the first embodiment according to the present invention.
On the other hand. the module board 3 in Fig. 4 comprises only one standard wiring layer. That is, the standard wiring layer of the module board 3 in Fig. 4 comPrise only the standard aluminium wiring layer 24 and do not comPrise the second standard aluminium wiring laYer 30.
That is, the lowest layer of module board 3 in Fig. 4 is a silicon substrate. Above the lowest laYer. the following layers and films are formed according to the following order:
a thick SiO2 film 22, the standard aluminium wiring layer 24.
a thin SiO2 film 26, an inter-layer fiIm 28, a custom aluminium wiring laYer 34 and a Passivation film 36.
An embodiment of the multichiP module which uses a module board comprising only one standard wiring laYer. as shown in Fig. 4, will be hereinafter called the second embodiment according to the Present invention.
In Fig. 3 and Fig. 4, numerals 10a and 10b indicate module pads. Here, the custom aluminium wiring layer 34 is exPosed .
Fig. 3 and Fig. 4 are intended to be model drawings onlY.
Cross sections of each Portion of the module board 3 maY have a structure different from that shown in Fig. 3 or Fig. 4.
That is. the cross section of one portion may not comprise the custom aluminium wiring layer 34, the cross section of another Portion maY not comPrise the first standard aluminium wiring layer 24, and so on. NamelY, Fig. 3 and Fig. 4 are model drawings intended to illustrate the structure of the module board 3 in order from the lowest laYer. which is a silicon substrate.
Each aluminium wiring laYer the module board is comPosed of will be hereinafter called in order from-the lowest layer, which is a silicon substrate, the aluminium wiring laYer AL1, the aluminium wiring laYer AL2 and the aluminium wiring laYer AL3, resPectivelY.
That is, in the first embodiment according to the present invention shown in Fig. 3, the first standard aluminium wiring laYer 24 is the aluminium wiring laYer AL1, the second standard aluminium wiring layer 30 is the aluminium wiring laYer AL2. and the custom aluminium wiring laYer 34 is the aluminium wiring laYer AL3.
On the other hand. in the second embodiment according to the Present invention shown in Fig. 4, the standard aluminium wiring laYer 24 is the aluminium wiring laYer AL1 and the custom aluminium wiring laYer 34 is the aluminium wiring laYer AL2.
Fig. 5 shows a circuit diagram for the aluminium wiring laYer AL1 and the aluminium wiring laYer AL2 of the first embodiment according to the present invention.
In Fig. 5, the aluminium wiring laYer AL1 is arranged in straight lines which decline toward the right side and which are sPaced at equal distances. On the other hand. the 20~6781 aluminium wiring layer AL2 is arranged in straight lines which decline toward the left side and which are sPaced at equal distances. In Fig. 5, aluminium wiring laYer AL3 is not shown. It is, however, assumed that the aluminium wiring layer AL3, which is the custom wiring laYer comPrising the customized wiring Patterns and the chiP mounting Pads, exist.
At the points of intersection between each conductive track of the aluminium wiring laYer AL1 and each conductive track of the aluminium wiring laYer AL2, inter AL1 - AL2 antifuses 50a are Positioned, as illustrated bY circular marks. Furthermore, inter AL1 - AL3 antifuses 50b are Positioned, as illustrated by square marks, between the inter AL1 - AL2 antifuses 50a illustrated bY the circular marks on each conductive track of the aluminium wiring laYer AL1.
Inter AL2 - AL3 antifuses 50c are Positioned, as illustrated by triangular marks, between the inter AL1 - AL2 antifuses 50a illustrated bY the circular marks on each conductive track of the aluminium wiring laYer AL2.
The initial state of the antifuses 50a - 50c is the insulated state. However, the antifuses 50a - 50c are elements which allow, through application of a sPecified voltage, to define the Presence of an electrical connection.
If the thickness of the thin SiO2 fiIm 26 is 150 angstrom, the program voltage required for this definition is 12.5 V.
In Fig. 5, a combined use of the AL1 write circuit 40a and the AL2 write circuit 40b allows the writing of the definition of the Presence of electrical connections for the inter AL1 - AL2 antifuses 50a.
On the other hand. there is the AL3 write circuit 40c which is not shown in Fig. 5. A combined use of the AL1 write circuit 40a and the AL3 write circuit 40c allows the writing of the definition of the Presence of electrical connections for the inter AL1 - AL3 antifuses 50b. A combined use of the AL2 write circuit 40b and the AL3 write circuit 40c allows the writing of the definition of the presence of electrical connections for the inter AL2 - AL3 antifuses 50c.
In the aluminium wiring laYer AL3. a custom designed wiring Provides the connection to the AL3 write circuit 40c.
Furthermore, as described hereinafter with reference to Fig.
7B, there is a way of not using the AL3 write circuit 40c.
Fig. 6 is a toP view of a total of three tYPes of aluminium wiring laYers of the Present invention's first embodiment.
In Fig. 6. the aluminium wiring laYer AL1 is the lowest laYer. followed in uPward direction bY the aluminium wiring layer AL2 and the aluminium wiring laYer AL3. Furthermore. in the section where the conductive track of the aluminium wiring laYer AL1 and the conductive track of the aluminium wiring laYer AL2 cross, namely, in the section designated by the numeral A in Fig. 6, a first polYsilicon film 54, which is used as an antifuse along with the thin SiO2 film. which is an electrically insulating material. is Provided between the aluminium wiring laYer AL1 and the aluminium wiring laYer AL2.
Also. in the section where the conductive track of the aluminium wiring laYer AL1 and the conductive track of the aluminium wiring laYer AL3 cross, namely. in the section designated bY the numeral B in Fig. 6, a first polysilicon film 54, which is used as an antifuse along with the thin SiO2 film. which is an electricallY insulating material. is Provided between the aluminium wiring laYer AL1 and the aluminium wiring laYer AL3. Furthermore. in the section where the conductive track of the aluminium wiring laYer AL2 and the conductive track of the aluminium wiring layer AL3 cross, namely in the section designated bY the numeral C in Fig. 6, a second PolYsilicon film 56, which is used as an antifuse along with the thin SiO2 film. which is an electricallY insulating material, is Provided between the aluminium wiring laYer AL2 and the aluminium wiring layer AL3.
The first PolYsilicon film 54 and the second polysilicon film 56, which are Provided between the aluminium wiring layers AL1 - AL3, consist of doped polYsilicon, are electrically conductive and are used as antifuses along with the thin SiO2 film, which is an electricallY insulating material. That is, aPPlication of a fixed voltage to two different aluminium wiring laYers from among the aluminium wiring laYers AL1 - AL3, between which the first polysilicon film 54 or the second PolYsilicon film 56 and the thin SiO2 film are located, destroYs the insulation of the thin 2056781- ~
SiO2 film, and, the Presence of an electrical connection can be defined bY the first PolYsilicon film 54 or the second PolYsilicon fiIm 56.
The oblique lines (AL1, AL2) and the vertical lines (AL3) S in Fig. 6 do not show indePendent conductive tracks of the wiring, but indicate areas. That is, the areas indicate one conductive track AL1, one conductive track AL2 and one module pad (AL3).
Fig. 7A, Fig. 7B, Fig. 7C, Fig. 7D and Fig. 7E are drawings showing cross sections of antifuses used in the embodiment according to the Present invention.
That is, Fig. 7A is a drawing showing a cross section of an inter AL1 - AL2 antifuse 50a. Fig. 7B is a drawing showing a cross section of an inter AL1 - A13 antifuse 50b. Fig. 7C, Fig. 7D and Fig. 7E are drawings showing a cross section of an inter AL2 - AL3 antifuse 50c.
In Fig. 7A, the lowest layer of the module board 3 is a silicon substrate. Above the silicon substrate, a thick SiO2 film 22, conductive tracks formed where required bY means of the aluminium wiring laYer AL1, a thin SiO2 film 26, a first inter-layer film 28, conductive tracks formed where required bY means of the aluminium wiring laYer AL2, a thin SiO2 film 26, a second inter-laYer film 32, and a Passivation film 36 are formed according to the cited order. In addition, in the section between the conductive tracks of the aluminium wiring layer AL1 and the conductive tracks of the aluminium wiring layer AL2, the first PolYsilicon film 54 is provided above the lower thin SiO2 film 26.
In the initial state, the thin SiO2 film 26, which is adjacent to the iirst PolYsilicon film 54, is electrically insulated. However, aPPlYing a fixed voltage between the conductive tracks of the aluminium wiring laYer AL1 and the conductive tracks of the aluminium wiring laYer AL2 destroYs the insulation of the thin SiO2 film 26, which allows to define the Presence of electrical connections between the conductive tracks of the aluminium wiring layer AL1 and the conductive tracks of the aluminium wiring laYer AL2 bY the first PolYsilicon film 54.
In Fig. 7B, the numerals 3, 22, 26, 28, 32, 36, 54, AL1 and AL2 indicate the same Parts that the same numerals of the above-described Fig. 7A indicate.
In Fig. 7B, a conductive track of the aluminium wiring layer AL3 is Provided. This conductive track is connected to a conductive track of the aluminium wiring layer AL2.
Accordingly, if it is defined that an electrical connection between the conductive track of the aluminium wiring layer AL1 and the conductive track of the aluminium wiring layer AL2 is Present, then the conductive track of the aluminium wiring layer AL1 is also connected to the conductive track of the aluminium wiring laYer AL3.
In Fig. 7C, the numerals 3, 22, 26, 28, 32, 36, AL2 and AL3 indicate the same parts that the same numerals of the above-described Fig. 7A and Fig. 7B indicate.
In Fig. 7C, there is no conductive track of the aluminium wiring laYer AL1, but only conductive track of the aluminium wiring layer AL2 and conductive track of the aluminium wiring layer AL3 exist. Furthermore, in the section between the conductive track of the aluminium wiring laYer AL2 and the conductive track of the aluminium wiring layer AL3, the second PolYsilicon film 56 is Provided above the upper thin SiO2 film 26.
In the initial state, the thin SiO2 film 26, which is adjacent to the second PolYsilicon film 56, is electricallY
insulated. However, aPplYing a fixed voltage between the conductive track of the aluminium wiring layer AL2 and the conductive track of the aluminium wiring laYer AL3 destroys the insulation of the thin SiO2 film 26, which allows the definition of the Presence of electrical connections between these conductive tracks by the second polysilicon film 56.
In Fig. 7D, the numerals 3, 22, 26, 28, 32, 36, 54, AL1, AL2 and AL3 indicate the same parts that the same numerals of the above-described Fig. 7A, Fig. 7B and Fig. 7C indicate.
In Fig. 7D, the conductive track of the aluminium wiring layer AL3 is provided. This conductive track is connected to the conductive track of the aluminium wiring laYer AL1 through the conductive track of an aluminium wiring laYer AL2 31.
AccordinglY, if it is defined that an electrical connnection between the conductive track of the aluminium wiring layer AL1 20~6781 and the conductive track of the aluminium wiring laYer AL2 which is above the first polYsilicon film 54 is Present, then the conductive track of the aluminium wiring layer AL2 which is above the first PolYsilicon film 54 is also connected to the conductive track of the aluminium wiring layer AL3.
In this case, the second polYsilicon film 56 is not needed.
In Fig. 7E, the numerals 3, 26, 28, 31, 32, 36, 54, AL1, AL2 and AL3 indicate the same parts that the same numerals of the above-described Fig. 7A, Fig. 7B, Fig. 7C and Fig. 7D
indicate.
In Fig. 7E, there is no thick SiO2 film 22. A diffusion 18 on the silicon substrate is used as a conductive track. In the section between the conductive track of the diffusion 18 and the conductive track of the aluminium wiring layer AL2, the first PolYsilicon film 54 above the thin SiO2 film 26 and the conductive track of an aluminium wiring layer AL1 25 which is connected to the conductive track of the aluminium wiring laYer AL2 are Provided. The conductive track of the aluminium wiring laYer AL3 is connected to the diffusion 18 through the conductive track of the aluminium wiring laYer AL2 31 and the conductive track of the aluminium wiring laYer AL1.
Accordingly, if it is defined that an electrical connection between the conducti ve track of the aluminium wiring laYer AL1 and the conductive track of the aluminium wiring layer AL2 is present, then the conductive track of the aluminium wiring 20~6781 laYer AL2 is also connected to the conductive track of the aluminium wiring laYer AL3.
In this case, the second polysilicon film 56 is not needed.
This method is able to migrate into a cross section of an inter AL1 - AL2 antifuse and/or an inter AL1 - AL3 antifuse (not shown).
Fig. 8 is a circuit diagram for the AL1 write circuit and the AL2 write circuit which are used in the embodiment of the present invention.
In Fig. 8, a total of only three conductive tracks from among the conductive tracks of the aluminium wiring laYer AL1, a total of onlY four conductive tracks from among the conductive tracks of the aluminium wiring layer AL2, and onlY
the circuits for the writing of the antifuses with regard to these conductive tracks (the definition that electrical connection is Present) are shown in order to obtain a clear -explanation of the operation of the circuits.
The AL1 write circuit 40a in Fig. 8 comPrises an AL1 selector register 60a and a total of three switching transistors 62. Furthermore, the AL2 write circuit 40b conprises an AL2 selector register 60b and a total of four switching transistors 62.
Also, at the Points of intersection between the conductive tracks of the aluminium wiring laYer AL1 and the conductive tracks of the aluminium wiring layer AL2, inter AL1 - AL2 antifuses 50a, which use the above-described first polYsilicon film 54, are Provided. That is, in Fig. 8, a total of 12 inter AL1 - AL2 antifuses 50a are Provided.
At the time the definition of the presence of electrical connections (writing) for each of these inter AL1 - AL2 antifuses 50a is made, one of-the switching transistors 62 within the AL1 write circuit 40a, which corresPonds to the corresponding conductive track of the aluminium wiring laYer AL1, is selected bY the AL1 selector register 60a within the AL1 write circuit 40a and is switched to achieve the ON state, so that the corresPonding conductive track is connected to the program voltage 64. Furthermore, at the time the definition (writing) of these inter AL1 - AL2 antifuses 50a is made, one of the switching transistors 62 of the AL2 write circuit 40b, which corresPonds to the corresPonding conductive tracks of the aluminium wiring laYer AL2, is selected by the AL2 selector register 60b of the AL2 write circuit 40b and is switched to achieve the ON state, so that the corresPonding conductive track is connected to the Program voltage 64.
The definition of the presence of an electrical connection is made bY aPPlying, in this manner, the program voltage 64 to the conductive track of the aluminium wiring layer AL1 and the conductive track of the aluminium wiring layer Al2, with these conductive tracks corresPonding to the inter AL1 - AL2 antifuse 50a for which the definition (writing~ of the Presence of an electrical connection is to be made.
It is possible to simultaneouslY define the Presence of electrical connections of the antifuses for a pluralitY of antifuses.
Fig. 8 relates to antifuses between the conductive tracks of the aluminium wiring laYer AL1, which is a standard wiring layer. and the conductive tracks of the aluminium wiring layer AL2, which also is a standard wiring laYer. However. using the same configuration. it is also Possible to make definitions (writing the Presence of an electrical connection) for the conductive tracks of the aluminium wiring laYer AL1, which is a standard wiring laYer. and the conductive tracks of the aluminium wiring layer AL3, which is the custom wiring layer (this also aPplies to the second embodiment of the present invention). The definition (writing) of the inter AL1 - AL3 antifuses 50b is made by switching the corresponding switching transistor 62 of the aluminium wiring laYer AL1 to the ON state, thus making connection to be Program voltage 64, and bY connecting the corresPonding module pads 10b (and module pins) of the aluminium wiring laYer AL3 to the program voltage 64. Furthermore, as for the definition of the antifuses between the conductive tracks of the aluminium wiring laYer AL2, which is a standard wiring layer, and the conductive tracks of the aluminium wiring laYer AL3. which is the custom wiring laYer, it is also possible to define the presence of the electrical connections bY using a similar configuration.
Usually, the Program voltage is Provided outside of the multichip module 1. The AL1 selector register 60a and the AL2 selector register 60b are shift registers. and their data are external shift inPut data. In the pulse state, after specified data are set in the shift register. the Program voltage is actually applied.
Fig. 9 is a top view of a module pad used on the module board 3 of the embodiment according to the present invention.
In Fig. 9, the module pad 10a (or 10b) is a 100 micro meter square.
Fig. 10 is a circuit diagram for the standard wiring of the module Pad on the module board of the embodiment according to the Present invention.
In Fig. 10, the module Pad lOa (or 10b) is Provided with a total of 8 inter AL1 - AL2 antifuses 50a, which are illustrated bY circular marks, a total of 12 inter AL1 - AL3 antifuses 50b, which are illustrated bY square marks, and a - total of 13 inter AL2 - AL3 antifuses 50c, which are illustrated bY triangular marks. The module Pad 10a (or 10b) is formed in the custom wiring laYer which itself is the aluminium wiring laYer AL3. AccordinglY. using the inter AL1 - AL3 antifuses 50b and the inter AL2 - AL3 antifuses 50c, it is Possible to connect the conductive tracks of the aluminium wiring layer AL1 and the conductive tracks of the aluminium wiring laYer AL2 to the module pad 10a (or 10b). Furthermore, using the inter AL1 - AL2 antifuses 50a allows a more comPlex wiring to be defined.
Fig. 11A is a drawing showing the wiring pattern of the standard wiring layer in the second embodiment according to .
the Present invention.
In the second embodiment, the standard wiring laYers comprise onlY one layer, namelY the aluminium wiring laYer AL1.
The wiring pattern of the standard wiring layer of the second embodiment consists of straight lines having the same direction and being arranged at equal distances, as shown in Fig. 11A.
Also, in Fig. 11A, the inter AL1 - AL2 antifuses 50a illustrated bY circular marks are Positioned uniformlY at equal distances.
Fig. 11B is a wirine Pattern showine one examPle of a wiring defined in the second embodiment.
In the left wiring Pattern of Fie. 11B, a total of three electrically insulated, independent conductive tracks cross each other in almost one Point. In a configuration comPrising only a single wiring laYer, it is imPossible to realize, in this manner, crossings of a pluralitY of electrically insulated conductive tracks.
However, as shown in the right figure of Fig. 11B, even if a crossing in almost one Point of a pluralitY of electrically insulated, independent conductive tracks must be made, it can be realized bY using one custom wiring laYer in addition to the standard wiring laYer with a standardized wiring Pattern.
In the right figure of Fig. 11B, the broken lines AL1 are the conductive tracks of the aluminium wiring laYer AL1, and the solid lines AL2 are the conductive tracks of the aluminium wiring layer AL2. Furthermore, the conductive tracks of the aluminium wiring laYer ALI and the conductive tracks of the aluminium wiring layer AL2 are connected by means of the inter AL1 - AL2 antifuses 50a illustrated bY circular marks.
In this way, the second embodiment according to the present invention uses a common module board, which comPrises the standard wiring laYers and the standardized means for defining connections (antifuses) and which meets the requirements of various multichip modules. In addition, adding onlY a customized custom wiring layer Provides the possibilitY of Producing the module board for use in the desired multichiP module and of comPosing the desired multichip module.
Furthermore, in the first embodiment according to the Present invention, adding, in the same manner as in the second embodiment of the Present invention, only a customized custom wiring laYer to the common module board provides the Possibility of comPosing the desired multichiP module. In addition, since, comPared with the second embodiment, the standard wiring laYer of the module board in the first embodiment is a two laYer structure, it is possible to provide a more optimized wiring Pattern, even if the wiring is more complex, comPared with the second embodiment. For example, even if the wiring is comPlex, it is Possible to cut down the length of each of the conductive tracks which comPose the entire comPlex wiring.
provides the possibility of miniaturizing the size of entire electronic apParatuses, but it also offers numerous advantages including imProvement in the reliabilitY and reduction of the power consumPtion of electronic equiPment. Accordingly, circuit integration of digital circuits which Perform logical operations of binary numbers as well as circuit integration of various types of analog circuits has been attemPted.
An integrated circuit which integrates onlY digital circuits is called a digital integrated circuit. On the other hand. an integrated circuit which integrates onlY analog circuits is called an analog integrated circuit.
Furthermore, in such digital and analog integrated circuits, an integrated circuit which is integrated on a single wafer chiP is called a monolithic integrated circuit.
Monolithic integrated circuits not onlY provide the PossibilitY of drastically miniaturizing electronic circuits.
but also allow improvement of reliabilitY. reduction of power ~056781 consumption, and the like.
Also, an integrated circuit which integrates a mixture of more than one digital or analog integrated circuit (wafer chip) and. as required, other devices or Parts, is called a hybrid integrated circuit.
Compared with monolithic integrated circuits, hYbrid integrated circuits allow efficient development of circuit integration of large-scale electronic circuits in a relatively short Period of time. Furthermore, hYbrid integrated circuits also provide an easY waY to realize integrated circuits which use a combination of different processes, such as the accommodation of biPolar analog integrated circuits and CMOS
(complementary metal-oxide-semiconductor) digital integrated circuits in the same Package.
However, Problems such as the relative difficultY of development of integrated circuits of the des;red electronic circuits, a longer Period of develoPment and higher development costs have been associated with the above-described monolithic integrated circuits.
These Problems become especially significant as the scale of the electronic circuits, which are to be integrated, increase.
Furthermore, the difficulty in realizing a change in the design (change in the circuit) is another problem with the above-described monolithic integrated circuits. The need for a maior design change involves the Problem that the costs and the Period of time required for the design change are equal to the costs and time needed for an entirely new development.
DeveloPment costs for an ordinarY monolithic integrated circuit are said to amount to approximatelY 5 million yen.
In addition, higher Process costs are a problem with monolithic integrated circuits when integrated circuits such as BiCMOS integrated circuits are fabricated bY emPloYing a different Process.
Major circuit elements which are integrated into a single wafer chiP are transistors, diodes and resistors. As these circuit elements are limited to those with relatively small capacities, electronic circuits which allow integration into monolithic integrated circuits are subject to nu~erous restrictions.
On the other hand, a Problem concerning the above-described hybrid integrated circuits is a decline in reliabilitY with regard to the conductive tracks which interconnect a pluralitY of wafer chips, namelY, the digital or analog integrated circuits which comPose the hYbrid integrated circuit.
Another Problem is that, due to the interconnecting conductive tracks between a PluralitY of wafer chiPs and the like, the mounting area increases, which in turn results in a decrease in the overall degree of integration.
Another issue is the difficulty of handling during Production.
ComPared with monolithic integrated circuits, the development of hYbrid integrated circuits is easY. However, as with monolithic integrated circuits, a change in the design of hybrid integrated circuits is difficult. The need for a major change in the design of a hybrid integrated circuit involves the problem that a long period of time for the design change and high development costs are required.
In general, the development costs for a hybrid integrated circuit are said to amount to approximately 1 million yen.
SUMMARY OF THE INVENTION
The present invention was carried out in order to solve the above-described existing problems. It is an object of the present invention to provide a multichip module which allows the relatively easy development of relatively large-scale electronic circuits whose development is difficult with monolithic integrated circuits, which realizes a module that allows integration of a combination of different processes, and which provides the possibility of reducing the period of development and development cost.
According to the present invention, there is provided a multichip module including:
- at least one standard wiring layer comprising standardized wiring patterns, - a custom wiring layer on the at least one standard wiring layer and comprising customized wiring patterns and chip mounting pads, - a plurality of connection defining means positioned in standardized installation positions and defining an electrical connection between a specified conductive track of the standard wiring layer and a specified conductive track of the custom wiring layer, and ~-~A
- a plurality of wafer chips which are electrically connected to the chip mounting pads and mounted on the chip mounting pads.
Preferably, the at least one standard wiring layer is a plurality of the standard wiring layers, and - the plurality of connection defining means positioned in standardized installation positions and defining the electrical connection between a specified conductive track of one of the plurality of standard wiring layers and at least one of the following:
- a specified conductive track of another one of the plurality of standard wiring layers or a specified conductive track of the custom wiring layer; and a specified conductive track of a standard wiring layer.
The object is also achieved by using antifuses as a means for defining connections.
Further, the object is achieved by providing the multichip module with a standardized active element as well.
The multichip module according to the present invention integrates in the same manner as conventional hybrid circuits a mixture of a plurality of wafer chips, that is, digital or analog integrated circuits and a plurality of devices and parts, and it offers numerous advantages of hybrid integrated circuits.
In addition to this, a multilayered wiring layer configuration in the multichip module according to the present invention aims to overcome the disadvantages of hybrid integrated circuits. That is, multilayered wiring layers not only improve the reliability of the wiring, but also allow the ~' ~)t~
; 20S6781 realization of complex connections of conductive tracks in an efficient way.
In addition, in the multichip module according to the present invention, the structure of the conductive tracks interconnecting the PluralitY of wafer chips, devices and Parts, which compose the multichip module, is able to meet with requirements of multi-Product, small-scale Production.
That is, according to the Present invention, it is possible to readily design this kind of wiring and to readilY make a design change.
The multichiP module of the Present invention comprises standard wiring layers with standardized wiring patterns as well as a custom viring layer which comprises customized wiring Patterns and customized chiP mounting Pads. In addition, the multichiP module Provides a PluralitY of connection defining means which are Positioned in standardized installation Positions and each of which provides the PossibilitY of defining the Presence or absence of an electrical connection between a specified conductive track of a standard viring laYer and a sPecified conductive track of the custom wiring laYer. The definition of the presence or absence of an electrical connection can be made in accordance with the specified method of definition of the connection defining means. To be concrete, fuses, antifuses, and the like can be used as a means for defining connections.
A configuration mainly comPrising the above-described standard wiring laYers, the custom wiring laYer and the means _ for defining connections will be hereinafter called a module board.
Among the plurality of wiring laYers of the module board, the custom wiring laYer is formed closest to the surface.
~afer chiPs, and the like can be mounted on the custom wiring layer by means of customized chiP mounting Pads.
Normally, to Prevent malfunction caused by noise, it is necessarY to Provide the wafer chiPs and the like with Power supply lines as thick and short as possible. The custom wiring allows these requirements to be met.
Accordingly, the formation of the customized wiring Patterns and customized chiP mounting Pads (by etching, and the like) of the custom wirin~ laYer is also possible during a later stage of the module board's manufacturing Process.
Also, the conductive tracks on the module board give rise to points where it is necessarY to electricallY insulate a PluralitY of conductive tracks and make the conductive tracks cross each other.
In this case, using standard wiring layers with standardized wiring Patterns facilitates the designing of the wiring so that a sPecified conductive track leaps over another conductive track. That is, it suffices to connect the conductive track, which is to leaP, to the conductive tracks of the standardized wiring Pattern by means of a connection defining means, to cross the conductive track, which is to be - leaped over, using the standardized wiring pattern, and thereafter, to make connection to the customized wiring ;
20~6781 Pattern once again bY using another connection defining means.
Accordingly, the module board of the Present invention's multichip module can be used for various multichiP modules, and for each multichip module customization of the module board is readi 1Y made. Also, the configuration of such a module board provides sufficient reliability so that satisfactory reliabilitY of the entire multichiP module is achieved.
The standard wiring laYer of the module board comPrises standardized wiring Patterns, and one standard wiring laYer or a PluralitY of the standard wiring layers maY be provided.
For examPle, if the angle of the direction of the conductive tracks of each standard wiring pattern of the pluralitY of wiring laYers is different, it is Possible to wire the module board more unrestrictedlY. What is more, the wiring length of each conductive track can be made shorter. Also, even after the design of the custom wiring laYer is comPleted, using a PluralitY of standard wiring laYers and the means for defining connections Provides a relativelY easY way to make change in the wiring. If a PluralitY of wiring layers are used, connection defining means for defining the Presence or absence of electrical connections between the PluralitY of wiring layers should be Provided.
Furthermore, the Present invention does not impose anY
restrictions on the connection defining means. However, it is expected that among the numerous connection defining means on the module board, the number of means which will define the presence of an electrical connection will be smaller than the number of means which will define the absence of an electrical connection. Accordingly, it is desirable that the connection defining means of the module board should be such that the definition of the absence of an electrical connection can be made more easily than the definition of the Presence of an electrical connection. Therefore, if antifuses are used as a means for defining connections, it suffices to make a relativelY small number of electrical connection Present definitions (create a conducting state), which allows the efficient making of definitions of all connection defining means of the entire multichip module.
Also, in the module board of the Present invention, no restrictions are imposed on whether passive elements. such as registors, and/or active elements, such as transistors, are configured or not. However, the module board requires standardized active elements such as buffer gates for the inputs and outputs with the outside of the multichip module.
Accordingly, installing active elements as well on the multichip module's module board Provides the PossibilitY of imProving design efficiencY of the multichiP module.
In the embodiments described hereinunder, the standard wiring laYers and the custom wiring laYer of the Present invention are aluminium wiring laYers. However, the present invention is not restricted to only aluminium wiring layers.
Any electrically conductive material which is suitable for the wiring can be used.
` _ 2056781 According to the present invention, a multichiP module is -~
provided, wherein it is relativelY easY to develop relativelY
large-scale electronic circuits whose development is difficult with monolithic integrated circuits. Furthermore, the Present invention realizes a module which allows the integration of a combination of different Processes, reduces the develoPment period and costs.
~BIEE_nE~Bl~lQ~_QE_~E_nB~lN~
The Preferred embodiments will be described with reference to the drawings, wherein like e`lements have been denoted throughout the figures with like reference numerals, and wherein:
Fig. 1 is a top view of an embodiment of the present invention;
Fig. 2A is a Partial side view of the embodiment;
Fig. 2B is an enlarged view of the portion designated bY
the reference D in the side view of Fig. 2A;
Fig. 3 is a cross-sectional model drawing showing the module board which is used in the first embodiment according to the PreSent invention;
Fig. 4 is a cross-sectional model drawing showing the module board which is used in the second embodiment according to the Present invention;
Fig. 5 shows a circuit diagram for the conductive tracks of the aluminium wiring laYer ALl and aluminium wiring la~er AL2 of the first embodiment;
Fig. 6 is a drawing showing a top view of the sections : - 10 -` ~ 2056781 where, in the first embodiment, a conductive track of the aluminium wiring laYer AL1. a conductive track of the aluminium wiring laYer AL2 and a conductive track of the aluminium wiring laYer AL3 cross each other;
Fig. 7A is a drawing showing a cross section of an inter ALI - AL2 antifuse which is used in the embodiment according to the present invention;
Fig. 7B is a drawing showing a cross section of an inter AL1 - AL3 antifuse which is used in the embodiment according to the present invention;
Fig. 7C, Fig. 7D and Fig. 7E are drawings showing a cross section of an inter AL2 - AL3 antifuse;
Fig. 8 is a circuit diagram for the write circuit of inter AL1 - AL2 antifuses which are used in the embodiment according to the Present invention;
Fig. 9 is a toP view of a module Pad of the module board of the embodiment according to the present invention;
Fig. 10 is a circuit diagram for the wiring of the aluminium wiring laYer ALl and the wiring of the aluminium wiring laYer AL2 of the module Pad;
Fig. llA is a circuit diagram of the standard wiring laYer in the second embodiment according to the Present invention; and Fi~. 11B is a wiring Pattern drawing showing one examPle of a wiring pattern defined in the second embodiment.
~ES~Ie~lQ~_QE_~E_~EEEB~E~_EM~Q~l~E~
Embodiments according to the Present invention will be described in detail hereinunder with reference to the accompanying drawings.
Fig. 1 is a toP view of an embodiment according to the present invention.
In Fig. 1, a multichip module 1 comprises a module board 3 and a total of five chiPs 5 mounted on the module board 3.
The module board 3 is Provided with module Pins (not shown). The module Pins provide the PossibilitY of mounting ~-the entire multichiP module 1 on, for instance, a Printed board and of making electrical connections.
The module board 3 is Provided with module pads 10b so that the module Pads 10b correspond to the module pins. The module pads 10b are electricallY connected to the module Pins.
Accordingly, external connection to the multichip module 1 can be made by making wiring connections to the module pads 10b on the module board 3.
Furthermore, the module board 3 is Provided with module pads 10a which are customized chiP mounting Pads.
In the embodiment, the installation positions of the module pads 10a are determined and customized in accordance with the tYpe and size of the chiPs 5 which are to be mounted on module board 3.
AccordinglY, there are no unnecessarY module Pads 10a on the module board 3. This allows wiring to be Performed while unrestrictedly utilizing the sPace on the module board 3.
However, if sufficient sPace is available for the conductive tracks on the module board 3, the positioning of the module pads 10a can also be standardized.
As will be described in detail and with reference to Fig.
2B hereinafter. the module pads 10a are used to make electrical connections for the chiPs 5 which are mounted on the module board 3.
Furthermore, on the module board 3, the interconnections of the module Pads 10a, which are connected to the chips 5 mounted on the module board 3, and the connections between the module Pads 10a and the module Pads 10b, with the module pads 10b being connected to the module Pins, are made bY means of module board wiring 7, which is illustrated bY solid lines.
As will be described in detail hereinafter, the module board wiring 7 has a multilayer wiring laYer structure. That is, the module board wiring 7 comPrises conductive tracks of standard wiring laYers and conductive tracks of a custom wiring laYer.
Fig. 2A is a Partial side view of the embodiment according to the present invention.
In Fig. 2A, the numerals 3, 5 and 10a indicate the same parts that the same numerals of the above-described Fig. 1 indicate.
Fig. 2B is an enlarged view of a Portion where a chiP and the module board are connected. That is, Fig. 2B is an enlarged view of the part designated by the reference D in the side view of Fig. 2A.
In Fig. 2B, the numerals 3, 5 and 10a indicate the same parts that the same numerals of the above-described Fig. 1 and Fig. 2A indicate. 205678 i In Figs. 2A and 2B, the electrical connections between the module pads lOa on the module board 3 and the chiPs 5 mounted on the module board 3, and the fixation of the chiPs S
are made bY using bumps 12 of the chiPs 5 and an electrically conductive bond 14 which is applied to the module Pads 10a on the module board 3. That is, after formation of the module pads 10a on the module board 3, a ProPer amount of the electrically conductive bond 14 is applied to the surface of the module Pads lOa, then chiPs 5 are mounted, and thereafter, the electricallY conductive bond 14 is allowed to harden.
Figs. 3 and 4 are cross-sectional model drawings showing the module boards used in the embodiments according to the present invention.
lS In Fig. 3, the lowest laYer of module board 3 is a silicon substrate. Above the lowest laYer, the following laYers and films are formed according to the following order:
a thick SiO2 film 22, a first standard aluminium wiring laYer 24, a thin SiO2 film 26, a fist inter-layer film 28, a second standard aluminium wiring laYer 30, a thin SiO2 film 26, a second inter-laYer film 32, a custom aluminium wiring layer 34 and a passivation film 36.
The standard wiring laYers of the module board 3 in Fig.
3 comprises two layers. That is, the module board 3 in the Fig. 3 is Provided with the first standard aluminium wiring laYer 24 and the second standard aluminium wiring layer 30.
An embodiment of the multichip module comPrising two of such standard wiring laYers will be hereinafter called the first embodiment according to the present invention.
On the other hand. the module board 3 in Fig. 4 comprises only one standard wiring layer. That is, the standard wiring layer of the module board 3 in Fig. 4 comPrise only the standard aluminium wiring layer 24 and do not comPrise the second standard aluminium wiring laYer 30.
That is, the lowest layer of module board 3 in Fig. 4 is a silicon substrate. Above the lowest laYer. the following layers and films are formed according to the following order:
a thick SiO2 film 22, the standard aluminium wiring layer 24.
a thin SiO2 film 26, an inter-layer fiIm 28, a custom aluminium wiring laYer 34 and a Passivation film 36.
An embodiment of the multichiP module which uses a module board comprising only one standard wiring laYer. as shown in Fig. 4, will be hereinafter called the second embodiment according to the Present invention.
In Fig. 3 and Fig. 4, numerals 10a and 10b indicate module pads. Here, the custom aluminium wiring layer 34 is exPosed .
Fig. 3 and Fig. 4 are intended to be model drawings onlY.
Cross sections of each Portion of the module board 3 maY have a structure different from that shown in Fig. 3 or Fig. 4.
That is. the cross section of one portion may not comprise the custom aluminium wiring layer 34, the cross section of another Portion maY not comPrise the first standard aluminium wiring layer 24, and so on. NamelY, Fig. 3 and Fig. 4 are model drawings intended to illustrate the structure of the module board 3 in order from the lowest laYer. which is a silicon substrate.
Each aluminium wiring laYer the module board is comPosed of will be hereinafter called in order from-the lowest layer, which is a silicon substrate, the aluminium wiring laYer AL1, the aluminium wiring laYer AL2 and the aluminium wiring laYer AL3, resPectivelY.
That is, in the first embodiment according to the present invention shown in Fig. 3, the first standard aluminium wiring laYer 24 is the aluminium wiring laYer AL1, the second standard aluminium wiring layer 30 is the aluminium wiring laYer AL2. and the custom aluminium wiring laYer 34 is the aluminium wiring laYer AL3.
On the other hand. in the second embodiment according to the Present invention shown in Fig. 4, the standard aluminium wiring laYer 24 is the aluminium wiring laYer AL1 and the custom aluminium wiring laYer 34 is the aluminium wiring laYer AL2.
Fig. 5 shows a circuit diagram for the aluminium wiring laYer AL1 and the aluminium wiring laYer AL2 of the first embodiment according to the present invention.
In Fig. 5, the aluminium wiring laYer AL1 is arranged in straight lines which decline toward the right side and which are sPaced at equal distances. On the other hand. the 20~6781 aluminium wiring layer AL2 is arranged in straight lines which decline toward the left side and which are sPaced at equal distances. In Fig. 5, aluminium wiring laYer AL3 is not shown. It is, however, assumed that the aluminium wiring layer AL3, which is the custom wiring laYer comPrising the customized wiring Patterns and the chiP mounting Pads, exist.
At the points of intersection between each conductive track of the aluminium wiring laYer AL1 and each conductive track of the aluminium wiring laYer AL2, inter AL1 - AL2 antifuses 50a are Positioned, as illustrated bY circular marks. Furthermore, inter AL1 - AL3 antifuses 50b are Positioned, as illustrated by square marks, between the inter AL1 - AL2 antifuses 50a illustrated bY the circular marks on each conductive track of the aluminium wiring laYer AL1.
Inter AL2 - AL3 antifuses 50c are Positioned, as illustrated by triangular marks, between the inter AL1 - AL2 antifuses 50a illustrated bY the circular marks on each conductive track of the aluminium wiring laYer AL2.
The initial state of the antifuses 50a - 50c is the insulated state. However, the antifuses 50a - 50c are elements which allow, through application of a sPecified voltage, to define the Presence of an electrical connection.
If the thickness of the thin SiO2 fiIm 26 is 150 angstrom, the program voltage required for this definition is 12.5 V.
In Fig. 5, a combined use of the AL1 write circuit 40a and the AL2 write circuit 40b allows the writing of the definition of the Presence of electrical connections for the inter AL1 - AL2 antifuses 50a.
On the other hand. there is the AL3 write circuit 40c which is not shown in Fig. 5. A combined use of the AL1 write circuit 40a and the AL3 write circuit 40c allows the writing of the definition of the Presence of electrical connections for the inter AL1 - AL3 antifuses 50b. A combined use of the AL2 write circuit 40b and the AL3 write circuit 40c allows the writing of the definition of the presence of electrical connections for the inter AL2 - AL3 antifuses 50c.
In the aluminium wiring laYer AL3. a custom designed wiring Provides the connection to the AL3 write circuit 40c.
Furthermore, as described hereinafter with reference to Fig.
7B, there is a way of not using the AL3 write circuit 40c.
Fig. 6 is a toP view of a total of three tYPes of aluminium wiring laYers of the Present invention's first embodiment.
In Fig. 6. the aluminium wiring laYer AL1 is the lowest laYer. followed in uPward direction bY the aluminium wiring layer AL2 and the aluminium wiring laYer AL3. Furthermore. in the section where the conductive track of the aluminium wiring laYer AL1 and the conductive track of the aluminium wiring laYer AL2 cross, namely, in the section designated by the numeral A in Fig. 6, a first polYsilicon film 54, which is used as an antifuse along with the thin SiO2 film. which is an electrically insulating material. is Provided between the aluminium wiring laYer AL1 and the aluminium wiring laYer AL2.
Also. in the section where the conductive track of the aluminium wiring laYer AL1 and the conductive track of the aluminium wiring laYer AL3 cross, namely. in the section designated bY the numeral B in Fig. 6, a first polysilicon film 54, which is used as an antifuse along with the thin SiO2 film. which is an electricallY insulating material. is Provided between the aluminium wiring laYer AL1 and the aluminium wiring laYer AL3. Furthermore. in the section where the conductive track of the aluminium wiring laYer AL2 and the conductive track of the aluminium wiring layer AL3 cross, namely in the section designated bY the numeral C in Fig. 6, a second PolYsilicon film 56, which is used as an antifuse along with the thin SiO2 film. which is an electricallY insulating material, is Provided between the aluminium wiring laYer AL2 and the aluminium wiring layer AL3.
The first PolYsilicon film 54 and the second polysilicon film 56, which are Provided between the aluminium wiring layers AL1 - AL3, consist of doped polYsilicon, are electrically conductive and are used as antifuses along with the thin SiO2 film, which is an electricallY insulating material. That is, aPPlication of a fixed voltage to two different aluminium wiring laYers from among the aluminium wiring laYers AL1 - AL3, between which the first polysilicon film 54 or the second PolYsilicon film 56 and the thin SiO2 film are located, destroYs the insulation of the thin 2056781- ~
SiO2 film, and, the Presence of an electrical connection can be defined bY the first PolYsilicon film 54 or the second PolYsilicon fiIm 56.
The oblique lines (AL1, AL2) and the vertical lines (AL3) S in Fig. 6 do not show indePendent conductive tracks of the wiring, but indicate areas. That is, the areas indicate one conductive track AL1, one conductive track AL2 and one module pad (AL3).
Fig. 7A, Fig. 7B, Fig. 7C, Fig. 7D and Fig. 7E are drawings showing cross sections of antifuses used in the embodiment according to the Present invention.
That is, Fig. 7A is a drawing showing a cross section of an inter AL1 - AL2 antifuse 50a. Fig. 7B is a drawing showing a cross section of an inter AL1 - A13 antifuse 50b. Fig. 7C, Fig. 7D and Fig. 7E are drawings showing a cross section of an inter AL2 - AL3 antifuse 50c.
In Fig. 7A, the lowest layer of the module board 3 is a silicon substrate. Above the silicon substrate, a thick SiO2 film 22, conductive tracks formed where required bY means of the aluminium wiring laYer AL1, a thin SiO2 film 26, a first inter-layer film 28, conductive tracks formed where required bY means of the aluminium wiring laYer AL2, a thin SiO2 film 26, a second inter-laYer film 32, and a Passivation film 36 are formed according to the cited order. In addition, in the section between the conductive tracks of the aluminium wiring layer AL1 and the conductive tracks of the aluminium wiring layer AL2, the first PolYsilicon film 54 is provided above the lower thin SiO2 film 26.
In the initial state, the thin SiO2 film 26, which is adjacent to the iirst PolYsilicon film 54, is electrically insulated. However, aPPlYing a fixed voltage between the conductive tracks of the aluminium wiring laYer AL1 and the conductive tracks of the aluminium wiring laYer AL2 destroYs the insulation of the thin SiO2 film 26, which allows to define the Presence of electrical connections between the conductive tracks of the aluminium wiring layer AL1 and the conductive tracks of the aluminium wiring laYer AL2 bY the first PolYsilicon film 54.
In Fig. 7B, the numerals 3, 22, 26, 28, 32, 36, 54, AL1 and AL2 indicate the same Parts that the same numerals of the above-described Fig. 7A indicate.
In Fig. 7B, a conductive track of the aluminium wiring layer AL3 is Provided. This conductive track is connected to a conductive track of the aluminium wiring layer AL2.
Accordingly, if it is defined that an electrical connection between the conductive track of the aluminium wiring layer AL1 and the conductive track of the aluminium wiring layer AL2 is Present, then the conductive track of the aluminium wiring layer AL1 is also connected to the conductive track of the aluminium wiring laYer AL3.
In Fig. 7C, the numerals 3, 22, 26, 28, 32, 36, AL2 and AL3 indicate the same parts that the same numerals of the above-described Fig. 7A and Fig. 7B indicate.
In Fig. 7C, there is no conductive track of the aluminium wiring laYer AL1, but only conductive track of the aluminium wiring layer AL2 and conductive track of the aluminium wiring layer AL3 exist. Furthermore, in the section between the conductive track of the aluminium wiring laYer AL2 and the conductive track of the aluminium wiring layer AL3, the second PolYsilicon film 56 is Provided above the upper thin SiO2 film 26.
In the initial state, the thin SiO2 film 26, which is adjacent to the second PolYsilicon film 56, is electricallY
insulated. However, aPplYing a fixed voltage between the conductive track of the aluminium wiring layer AL2 and the conductive track of the aluminium wiring laYer AL3 destroys the insulation of the thin SiO2 film 26, which allows the definition of the Presence of electrical connections between these conductive tracks by the second polysilicon film 56.
In Fig. 7D, the numerals 3, 22, 26, 28, 32, 36, 54, AL1, AL2 and AL3 indicate the same parts that the same numerals of the above-described Fig. 7A, Fig. 7B and Fig. 7C indicate.
In Fig. 7D, the conductive track of the aluminium wiring layer AL3 is provided. This conductive track is connected to the conductive track of the aluminium wiring laYer AL1 through the conductive track of an aluminium wiring laYer AL2 31.
AccordinglY, if it is defined that an electrical connnection between the conductive track of the aluminium wiring layer AL1 20~6781 and the conductive track of the aluminium wiring laYer AL2 which is above the first polYsilicon film 54 is Present, then the conductive track of the aluminium wiring layer AL2 which is above the first PolYsilicon film 54 is also connected to the conductive track of the aluminium wiring layer AL3.
In this case, the second polYsilicon film 56 is not needed.
In Fig. 7E, the numerals 3, 26, 28, 31, 32, 36, 54, AL1, AL2 and AL3 indicate the same parts that the same numerals of the above-described Fig. 7A, Fig. 7B, Fig. 7C and Fig. 7D
indicate.
In Fig. 7E, there is no thick SiO2 film 22. A diffusion 18 on the silicon substrate is used as a conductive track. In the section between the conductive track of the diffusion 18 and the conductive track of the aluminium wiring layer AL2, the first PolYsilicon film 54 above the thin SiO2 film 26 and the conductive track of an aluminium wiring layer AL1 25 which is connected to the conductive track of the aluminium wiring laYer AL2 are Provided. The conductive track of the aluminium wiring laYer AL3 is connected to the diffusion 18 through the conductive track of the aluminium wiring laYer AL2 31 and the conductive track of the aluminium wiring laYer AL1.
Accordingly, if it is defined that an electrical connection between the conducti ve track of the aluminium wiring laYer AL1 and the conductive track of the aluminium wiring layer AL2 is present, then the conductive track of the aluminium wiring 20~6781 laYer AL2 is also connected to the conductive track of the aluminium wiring laYer AL3.
In this case, the second polysilicon film 56 is not needed.
This method is able to migrate into a cross section of an inter AL1 - AL2 antifuse and/or an inter AL1 - AL3 antifuse (not shown).
Fig. 8 is a circuit diagram for the AL1 write circuit and the AL2 write circuit which are used in the embodiment of the present invention.
In Fig. 8, a total of only three conductive tracks from among the conductive tracks of the aluminium wiring laYer AL1, a total of onlY four conductive tracks from among the conductive tracks of the aluminium wiring layer AL2, and onlY
the circuits for the writing of the antifuses with regard to these conductive tracks (the definition that electrical connection is Present) are shown in order to obtain a clear -explanation of the operation of the circuits.
The AL1 write circuit 40a in Fig. 8 comPrises an AL1 selector register 60a and a total of three switching transistors 62. Furthermore, the AL2 write circuit 40b conprises an AL2 selector register 60b and a total of four switching transistors 62.
Also, at the Points of intersection between the conductive tracks of the aluminium wiring laYer AL1 and the conductive tracks of the aluminium wiring layer AL2, inter AL1 - AL2 antifuses 50a, which use the above-described first polYsilicon film 54, are Provided. That is, in Fig. 8, a total of 12 inter AL1 - AL2 antifuses 50a are Provided.
At the time the definition of the presence of electrical connections (writing) for each of these inter AL1 - AL2 antifuses 50a is made, one of-the switching transistors 62 within the AL1 write circuit 40a, which corresPonds to the corresponding conductive track of the aluminium wiring laYer AL1, is selected bY the AL1 selector register 60a within the AL1 write circuit 40a and is switched to achieve the ON state, so that the corresPonding conductive track is connected to the program voltage 64. Furthermore, at the time the definition (writing) of these inter AL1 - AL2 antifuses 50a is made, one of the switching transistors 62 of the AL2 write circuit 40b, which corresPonds to the corresPonding conductive tracks of the aluminium wiring laYer AL2, is selected by the AL2 selector register 60b of the AL2 write circuit 40b and is switched to achieve the ON state, so that the corresPonding conductive track is connected to the Program voltage 64.
The definition of the presence of an electrical connection is made bY aPPlying, in this manner, the program voltage 64 to the conductive track of the aluminium wiring layer AL1 and the conductive track of the aluminium wiring layer Al2, with these conductive tracks corresPonding to the inter AL1 - AL2 antifuse 50a for which the definition (writing~ of the Presence of an electrical connection is to be made.
It is possible to simultaneouslY define the Presence of electrical connections of the antifuses for a pluralitY of antifuses.
Fig. 8 relates to antifuses between the conductive tracks of the aluminium wiring laYer AL1, which is a standard wiring layer. and the conductive tracks of the aluminium wiring layer AL2, which also is a standard wiring laYer. However. using the same configuration. it is also Possible to make definitions (writing the Presence of an electrical connection) for the conductive tracks of the aluminium wiring laYer AL1, which is a standard wiring laYer. and the conductive tracks of the aluminium wiring layer AL3, which is the custom wiring layer (this also aPplies to the second embodiment of the present invention). The definition (writing) of the inter AL1 - AL3 antifuses 50b is made by switching the corresponding switching transistor 62 of the aluminium wiring laYer AL1 to the ON state, thus making connection to be Program voltage 64, and bY connecting the corresPonding module pads 10b (and module pins) of the aluminium wiring laYer AL3 to the program voltage 64. Furthermore, as for the definition of the antifuses between the conductive tracks of the aluminium wiring laYer AL2, which is a standard wiring layer, and the conductive tracks of the aluminium wiring laYer AL3. which is the custom wiring laYer, it is also possible to define the presence of the electrical connections bY using a similar configuration.
Usually, the Program voltage is Provided outside of the multichip module 1. The AL1 selector register 60a and the AL2 selector register 60b are shift registers. and their data are external shift inPut data. In the pulse state, after specified data are set in the shift register. the Program voltage is actually applied.
Fig. 9 is a top view of a module pad used on the module board 3 of the embodiment according to the present invention.
In Fig. 9, the module pad 10a (or 10b) is a 100 micro meter square.
Fig. 10 is a circuit diagram for the standard wiring of the module Pad on the module board of the embodiment according to the Present invention.
In Fig. 10, the module Pad lOa (or 10b) is Provided with a total of 8 inter AL1 - AL2 antifuses 50a, which are illustrated bY circular marks, a total of 12 inter AL1 - AL3 antifuses 50b, which are illustrated bY square marks, and a - total of 13 inter AL2 - AL3 antifuses 50c, which are illustrated bY triangular marks. The module Pad 10a (or 10b) is formed in the custom wiring laYer which itself is the aluminium wiring laYer AL3. AccordinglY. using the inter AL1 - AL3 antifuses 50b and the inter AL2 - AL3 antifuses 50c, it is Possible to connect the conductive tracks of the aluminium wiring layer AL1 and the conductive tracks of the aluminium wiring laYer AL2 to the module pad 10a (or 10b). Furthermore, using the inter AL1 - AL2 antifuses 50a allows a more comPlex wiring to be defined.
Fig. 11A is a drawing showing the wiring pattern of the standard wiring layer in the second embodiment according to .
the Present invention.
In the second embodiment, the standard wiring laYers comprise onlY one layer, namelY the aluminium wiring laYer AL1.
The wiring pattern of the standard wiring layer of the second embodiment consists of straight lines having the same direction and being arranged at equal distances, as shown in Fig. 11A.
Also, in Fig. 11A, the inter AL1 - AL2 antifuses 50a illustrated bY circular marks are Positioned uniformlY at equal distances.
Fig. 11B is a wirine Pattern showine one examPle of a wiring defined in the second embodiment.
In the left wiring Pattern of Fie. 11B, a total of three electrically insulated, independent conductive tracks cross each other in almost one Point. In a configuration comPrising only a single wiring laYer, it is imPossible to realize, in this manner, crossings of a pluralitY of electrically insulated conductive tracks.
However, as shown in the right figure of Fig. 11B, even if a crossing in almost one Point of a pluralitY of electrically insulated, independent conductive tracks must be made, it can be realized bY using one custom wiring laYer in addition to the standard wiring laYer with a standardized wiring Pattern.
In the right figure of Fig. 11B, the broken lines AL1 are the conductive tracks of the aluminium wiring laYer AL1, and the solid lines AL2 are the conductive tracks of the aluminium wiring layer AL2. Furthermore, the conductive tracks of the aluminium wiring laYer ALI and the conductive tracks of the aluminium wiring layer AL2 are connected by means of the inter AL1 - AL2 antifuses 50a illustrated bY circular marks.
In this way, the second embodiment according to the present invention uses a common module board, which comPrises the standard wiring laYers and the standardized means for defining connections (antifuses) and which meets the requirements of various multichip modules. In addition, adding onlY a customized custom wiring layer Provides the possibilitY of Producing the module board for use in the desired multichiP module and of comPosing the desired multichip module.
Furthermore, in the first embodiment according to the Present invention, adding, in the same manner as in the second embodiment of the Present invention, only a customized custom wiring laYer to the common module board provides the Possibility of comPosing the desired multichiP module. In addition, since, comPared with the second embodiment, the standard wiring laYer of the module board in the first embodiment is a two laYer structure, it is possible to provide a more optimized wiring Pattern, even if the wiring is more complex, comPared with the second embodiment. For example, even if the wiring is comPlex, it is Possible to cut down the length of each of the conductive tracks which comPose the entire comPlex wiring.
Claims (10)
1. A multichip module including:
- at least one standard wiring layer comprising standardized wiring patterns, - a custom wiring layer on the at least one standard wiring layer and comprising customized wiring patterns and chip mounting pads, - a plurality of connection defining means positioned in standardized installation positions and defining an electrical connection between a specified conductive track of said standard wiring layer and a specified conductive track of said custom wiring layer, and - a plurality of wafer chips which are electrically connected to said chip mounting pads and mounted on said chip mounting pads.
- at least one standard wiring layer comprising standardized wiring patterns, - a custom wiring layer on the at least one standard wiring layer and comprising customized wiring patterns and chip mounting pads, - a plurality of connection defining means positioned in standardized installation positions and defining an electrical connection between a specified conductive track of said standard wiring layer and a specified conductive track of said custom wiring layer, and - a plurality of wafer chips which are electrically connected to said chip mounting pads and mounted on said chip mounting pads.
2. The multichip module according to claim 1, wherein a module board is composed of said at least one standard wiring layer, said custom wiring layer and said connection defining means.
3. The multichip module according to claim 2, wherein said at least one standard wiring layer is a plurality of wiring layers of said module board, and said custom wiring layer is formed closest to a surface of said module board.
4. The multichip module according to claim 1, wherein power supply lines of said wafer chips are formed in said custom wiring layer.
5. The multichip module according to claim 1, wherein:
- the at least one standard wiring layer is a plurality of said standard wiring layers, and - the plurality of connection defining means positioned in standardized installation positions and defining the electrical connection between a specified conductive track of one of the plurality of standard wiring layers and at least one of the following:
- a specified conductive track of another one of the plurality of standard wiring layers or a specified conductive track of the custom wiring layer; and a specified conductive track of a standard wiring layer.
- the at least one standard wiring layer is a plurality of said standard wiring layers, and - the plurality of connection defining means positioned in standardized installation positions and defining the electrical connection between a specified conductive track of one of the plurality of standard wiring layers and at least one of the following:
- a specified conductive track of another one of the plurality of standard wiring layers or a specified conductive track of the custom wiring layer; and a specified conductive track of a standard wiring layer.
6. The multichip module according to claim 5, wherein each standardized wiring pattern of said plurality of wiring layers has at least different wiring direction angles.
7. The multichip module according to claim 1, wherein antifuses are used as said connection defining means.
8. The multichip module according to claim 7, wherein said antifuses consist of a polysilicon film and a thin SiO2 film which are positioned between different wiring layers.
9. The multichip module according to claim 1, wherein said multichip module is provided with a standardized active element.
10. The multichip module according to claim 1, wherein installation positions of said chip mounting pads are standardized.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2-332130 | 1990-11-29 | ||
| JP2332130A JPH0714024B2 (en) | 1990-11-29 | 1990-11-29 | Multi-chip module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2056781A1 CA2056781A1 (en) | 1992-05-30 |
| CA2056781C true CA2056781C (en) | 1996-02-27 |
Family
ID=18251491
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002056781A Expired - Fee Related CA2056781C (en) | 1990-11-29 | 1991-11-28 | Multichip module |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5258891A (en) |
| EP (1) | EP0488319A1 (en) |
| JP (1) | JPH0714024B2 (en) |
| KR (1) | KR920010872A (en) |
| CA (1) | CA2056781C (en) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5367208A (en) | 1986-09-19 | 1994-11-22 | Actel Corporation | Reconfigurable programmable interconnect architecture |
| US5427979A (en) * | 1993-10-18 | 1995-06-27 | Vlsi Technology, Inc. | Method for making multi-level antifuse structure |
| US5485031A (en) * | 1993-11-22 | 1996-01-16 | Actel Corporation | Antifuse structure suitable for VLSI application |
| US5844297A (en) * | 1995-09-26 | 1998-12-01 | Symbios, Inc. | Antifuse device for use on a field programmable interconnect chip |
| US5793094A (en) * | 1995-12-28 | 1998-08-11 | Vlsi Technology, Inc. | Methods for fabricating anti-fuse structures |
| US5723358A (en) * | 1996-04-29 | 1998-03-03 | Vlsi Technology, Inc. | Method of manufacturing amorphous silicon antifuse structures |
| US5753540A (en) * | 1996-08-20 | 1998-05-19 | Vlsi Technology, Inc. | Apparatus and method for programming antifuse structures |
| US5899707A (en) * | 1996-08-20 | 1999-05-04 | Vlsi Technology, Inc. | Method for making doped antifuse structures |
| US5946552A (en) * | 1996-08-20 | 1999-08-31 | International Business Machines Corporation | Universal cost reduced substrate structure method and apparatus |
| US5764563A (en) * | 1996-09-30 | 1998-06-09 | Vlsi Technology, Inc. | Thin film load structure |
| US6576848B1 (en) * | 1996-11-22 | 2003-06-10 | International Business Machines Corporation | Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same |
| US5959466A (en) * | 1997-01-31 | 1999-09-28 | Actel Corporation | Field programmable gate array with mask programmed input and output buffers |
| US6150837A (en) * | 1997-02-28 | 2000-11-21 | Actel Corporation | Enhanced field programmable gate array |
| US5959845A (en) * | 1997-09-18 | 1999-09-28 | International Business Machines Corporation | Universal chip carrier connector |
| US6683384B1 (en) * | 1997-10-08 | 2004-01-27 | Agere Systems Inc | Air isolated crossovers |
| US5903051A (en) * | 1998-04-03 | 1999-05-11 | Motorola, Inc. | Electronic component and method of manufacture |
| JP3737333B2 (en) | 2000-03-17 | 2006-01-18 | 沖電気工業株式会社 | Semiconductor device |
| KR100480174B1 (en) * | 2002-08-23 | 2005-04-06 | 엘지전자 주식회사 | Drive device of plasma dispaly panel and method of fabricating the same |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2673424B2 (en) * | 1984-02-21 | 1997-11-05 | エンバィアロンメンタル・リサーチ・インスティテュート・オブ・ミシガン | Substrate for integrated circuit |
| US4739448A (en) * | 1984-06-25 | 1988-04-19 | Magnavox Government And Industrial Electronics Company | Microwave multiport multilayered integrated circuit chip carrier |
| US4598166A (en) * | 1984-08-06 | 1986-07-01 | Gte Communication Systems Corporation | High density multi-layer circuit arrangement |
| JPS6156493A (en) * | 1984-08-28 | 1986-03-22 | 日本電気株式会社 | Power source wiring structure of multilayer circuit board |
| JPS61296800A (en) * | 1985-06-25 | 1986-12-27 | 日本電気株式会社 | Electrode for altering design |
| JPS62265796A (en) * | 1986-05-14 | 1987-11-18 | 株式会社住友金属セラミックス | Ceramic multilayer interconnection board and manufacture of the same |
| US4782193A (en) * | 1987-09-25 | 1988-11-01 | Ibm Corp. | Polygonal wiring for improved package performance |
| JPH02153552A (en) * | 1988-08-23 | 1990-06-13 | Seiko Epson Corp | Semiconductor element and its manufacture |
-
1990
- 1990-11-29 JP JP2332130A patent/JPH0714024B2/en not_active Expired - Fee Related
-
1991
- 1991-11-26 US US07/797,920 patent/US5258891A/en not_active Expired - Fee Related
- 1991-11-28 EP EP91120440A patent/EP0488319A1/en not_active Withdrawn
- 1991-11-28 CA CA002056781A patent/CA2056781C/en not_active Expired - Fee Related
- 1991-11-28 KR KR1019910021567A patent/KR920010872A/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| EP0488319A1 (en) | 1992-06-03 |
| US5258891A (en) | 1993-11-02 |
| KR920010872A (en) | 1992-06-27 |
| CA2056781A1 (en) | 1992-05-30 |
| JPH0714024B2 (en) | 1995-02-15 |
| JPH04199742A (en) | 1992-07-20 |
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