CA2068042C - Multi-source image real time mixing and anti-aliasing - Google Patents
Multi-source image real time mixing and anti-aliasingInfo
- Publication number
- CA2068042C CA2068042C CA002068042A CA2068042A CA2068042C CA 2068042 C CA2068042 C CA 2068042C CA 002068042 A CA002068042 A CA 002068042A CA 2068042 A CA2068042 A CA 2068042A CA 2068042 C CA2068042 C CA 2068042C
- Authority
- CA
- Canada
- Prior art keywords
- frame buffer
- output
- pixel value
- image pixel
- buffer means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000002156 mixing Methods 0.000 title claims abstract description 47
- 239000000872 buffer Substances 0.000 claims abstract description 73
- 238000000034 method Methods 0.000 claims abstract description 25
- 230000003111 delayed effect Effects 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 3
- 230000008878 coupling Effects 0.000 claims 3
- 238000010168 coupling process Methods 0.000 claims 3
- 238000005859 coupling reaction Methods 0.000 claims 3
- 239000002131 composite material Substances 0.000 claims 1
- 230000006870 function Effects 0.000 abstract description 26
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- 238000013459 approach Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000000203 mixture Substances 0.000 description 6
- 101001096074 Homo sapiens Regenerating islet-derived protein 4 Proteins 0.000 description 2
- 102100037889 Regenerating islet-derived protein 4 Human genes 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005070 sampling Methods 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000011144 upstream manufacturing Methods 0.000 description 2
- 101100301524 Drosophila melanogaster Reg-5 gene Proteins 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 108091058543 REG3 Proteins 0.000 description 1
- 102100027336 Regenerating islet-derived protein 3-alpha Human genes 0.000 description 1
- 238000011094 buffer selection Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000002674 ointment Substances 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
- H04N5/272—Means for inserting a foreground image in a background image, i.e. inlay, outlay
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/14—Display of multiple viewports
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/12—Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
- G09G2340/125—Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels wherein one of the images is motion video
Abstract
Method and apparatus for implementing a raster graphic display video data path that provides arbitrary mixing of a plurality of images. The video data path is highly parallelized, and employs parallel devices operating under the control of a set of look-up tables. The look-up tables are loadable from a controller, such as a host workstation. The raster graphic display video data path functions with unlimited screen resolutions, and also enables a variety of different pixel data formats from a potentially large number of different sources. Outputs from several image sources are mixed under the control of the host workstation, with a resultant pixel value being based on (a) a combined translucency coefficient (alpha) of the images, for each image source, and (b) a window identification number assigned by the host workstation. Pixel value conversion to a common predetermined format provides coherency between pixel values generated by a number of different image sources, such as HDTV and graphics servers. A separate frame buffer is allocated for each of the sources.
Description
~09-91-08~ 1 MULTI-SOURCE IMAGE REAL TIME MIXING
AND ANTI-ALIASING
FIE~D OF THE INVENTIOM:
This invention relates generally to image display apparatus and method and, in particular, to the simultaneous display of images from a plurality of image sources.
BACKGROUND OF THE INVENTION:
In a modern display system data from multiple image sources are displayed. These images are shown on the display using a "window" ! a technique in which an area of a display is assigned to an image source. However, problems arise when the outputs from multiple sources must be coordinated on the display. ~hen there is more than one source for the display, a machanism is required to coordinate the output to a single display monitor.
A straightforward solution is to design the system such that only one source can be displayed at a time. For example, if a High Definition Televisions (HDTV) sampler input is selected, then only the HDTV output is output to the display. However, with an increased demand for "windowing" in graphics systems, and with an increased emphasis on a multimedia environment, where there exists more than one video source, this relatively simple solution is not adequate.
In order to accomplish windowing there must be provided a mechanism such that, within the total area defined by a monitor screen, different sub-areas are sourced by different video sources. Fig. 1 shows an example of a windowed graphics monitor screen. Area A may be sourced by a local host or workstation. Area B may be sourced by a remote graphics server connected ~ia a high speed network. Area C may be sourced by a HDTV sampler. One technique to provide such a display is known in the art ~09-91-0~4 2 2a~ 3~
as pixel switching. That is, for a given display area, or window, the source of pixels ~or that area i~ selected from a specified image plane.
A more compl.ex problem is presented when an arbitrari~y shaped image from a source is overlayed on top of another image, rather than over a simple rectangular window. For example, an image of an automobile may be rendered using a graphics server, and the automobile image may ba required to be overlayed upon a HDTV-generated background image. This requires -that all pixel selection be accomplished on a pixel-by-pixel basis, since the shape of the foreground object, or automobile, is not rectangular.
One solution that is applicable to a two-image source system utilizes color keyed pi~el switching, and allows pixel-by-pixel selection between two sources. This technique is described in commonly assigned U.S. Patent No. 4,994,912, enti-tled "Audio ~isual Interactive Display", by L. ~umelsky et. al..
~owever, for the case where there are more than two video sources, such as is illustrated in Fig. 1, a different ~olution is re~uired for displaying N, where (N>2), image sources on a pixel-by-pixel basis.
Another problem that arises in overlaying arbitrarily shaped multiple source images is due to an aliasing effect resulting from imag~ pixel switching. In that a pixel of one image source may not blend with a pixel from a second image source, aliasing results. Aliasing causes the resultant image to exhibit undesirable artifacts along the boundary between the foreground and the background images, such as stair-casing and color distortion. In order to e].iminate the artifacts, an anti-aliasing techni~ue is necessary. However, in that the foreground image does not contain information about the background image, the anti-aliasing should be accomplished in real-time at the video output. Thus, a ~0~-91-084 3 2~
technique for anti-aliasing N image sources in real-time is required. Furthermore, in order to anti-alias an arbitrarily shaped foreground object, the anti-aliasing must be accomplished on a pixel-by-pixel basis.
However, in modern high resolution displays the video data bandwidth and data rates are very high, thus placing severe timing constraints on any pixel processing -that is to be accomplished in a r.~eal-time manner.
In U.S. Patent No. 5,001,469, issued March 19, 1991, entitled "Window-Dependent Buffer Selection" to Pappas et al. there is described window control hardware in a graphics sub-system in which multiple image sources are shown on to a single monitor. This is accomplished by defining each window as a separate frame buffer and defining for each window, i.e. frame buffer, a window identification, and a window size and location based on four values of top location, bottom location, left location, and right location. This system also employs a prioritizing scheme where N frame buffers ("windows") are prioritized from 0 to N-1, where 0 has the highest priority and N-1 has the lowest priority. The graphics sub-system includes N window detection logics, one for each frame buffar, which use comparators for window size and location values to determine if the associated window is active for a region of the screen. If the window is active an image source pointer and other information are sent to prioritizing logic which prioritizes N inpu-t signals to determine which "active" imaye source has a highest priority. An active image with the highest priority is chosen by the prior~ty logic and shown on a monitor.
Pappas et. al. employ window size and location values to control multiple image sources, and an image frame bu~fer does not contain multiple windows. Furthermore, this system appears to be limited for use with only rectangularly shaped windows. Also, the problem of ~09-91-084 4 3~ x~
displaying multiple sources with differincJ image forma-ts is not addressed.
It is thus one objec-t of the invention to provide for the simultaneous display of video data from N independent image sources, where N may be greater tharl two, through the use of pixel switching and control on a pixel-by-pixel basis for the N image sources.
It is another object of the invention to provide a method and apparatus for displaying video data from a plurality of image sources on a monitor using a combination of alpha mixing and pixel switching, on a pixel-by-pixel basis, based on pixel color keying and window identification.
SUMM~R~ OF l'HE INVENTION
The foregoing and other problems are overcome and the objects of the invention are realized by method and apparatus for implementing a raster graphic display video data path that provides arbitrary mixing of a plurality of images. The video data path ls highly parallelized, and employs parallel devices operating under the control of a set of look-up tables. The look-up tables are loadable from a controller, such as a host workstation.
The raster graphic display video data path functions with unlimited screen resolutions, and also enables a variety of different pixel data formats from a potentially large number of different sources. Outputs from many image sources are mixed under the control of the host workstation, with pixel accuracy being based on (a~ a comblned transparency coefficient (alpha) of the images, for each image source, and (b) a window identification number assigned by the host workstation.
Pixel data format conversion to a common prede-termined forma-t provides coherency between pixel values generated by a number of dif~erent image sources, such as ~DTV and ~09-91-084 5 high resolution graphics servers, such as a supercomputer.
An anti-aliasing function is disclosed for use in eliminating artifacts between a foreground image s boundary with a background image. The anti-aliasing function may also be used for generating special effects, such as showing a translucent image foreground from one source on top oE a background image from another source.
The preferred anti-aliasing approach employ~ pixel mixing.
In order to allow any number of independent video sources, a separate frame buffer is allocated for each of the sources. ~hus, for a system with M separate video data sources, there are N frame buffers. Depending on display monitor bandwidth requirements, each of the N
frame buffers may also be interleaved M ways.
The invention also pertains to a~ integrated circuit device that provides, in a high speed pipelined manner, a pixel mixing function and a pixel multiplexing function.
BRIEF DESCRIPTION OF THE DRAWING
The above set ~orth and other features of the invention are made more apparent in the ensuing Detailed Description of the Invention, when read in conjunction with the attached Drawing, wherein:
Fig. 1 illustrates an exemplary display screen having multiple video data sources each displayed within an associa-ted windowi Fig. 2 is a block diagram showiny, in accordance with the invention, a plurality of hierarchically arranged frame buffers having look-up tables, pixel mixing, and pixel multiplexing circuitry interposed between frame buffers;
~09-91-084 6 Fig. 3 is a block diagram showing an N by M configuration of hierarchically arranged frame buffers having look-up tables, pixel mixing, and pixel multiplexing circuitry interposed between frame buffers;
Fig. 4 illustrates a local host video path;
Fig. 5 is a block diagram illustrating pixel mixing and multiplexing logic embodied within an integrated circuit device; and Fig. 6 is a schematic diagram illustrating an alpha control logic function from the pixel mixing logic of Fig. 5.
DETAILED DESCRIPTION OF THE INVENTION
Referring to Fig. 2 there is illu~trated a block diagram of a multi-source video display pixel mixing system 10 that is constructed and operated in accordance with the invention. System 10 receives video data input from N
sources, with each source having an associated frame buffer (FB) memory ~FB_l to FB_N). Also shown is a video output data path for a pixel (x,y) of each FB. In that there are N overlay FBs, there are N overlay pixels for a pi~el displayed at display 12 location ~x,y), one from each FB. The FBs are hierarchically ordered from 1 to N, where 1 is considered to have a highest priority and where N is considered to have a lowest priority. By preference, but not as a limitation upon the practice of the invention~ FB_l is associated with a host 14 and FB_N
is associated with, by example, an HDTV video source that does not provide an indication of pixel translucency, or alpha. The FBs are addressed in parallel so that each operates in lock-step with the others.
In a multi-media system such as the one depicted in Fig.
2 a coherency of pixel format cannot be assumed. For example, an image generated by a supercomputer and/or a graphic server and received from a communication network ~09-91-084 7 ~ ~~
may have a 24-bit Red, Green, Blue (~,G,B) forma-t.
However, the local workstation host 1~ may have an 8-bit pixel format, and an HDTV sampled input may have a chrominance/luminance (Y/C) ~ormat. In order to mix pixels from these diverse sources a first step converts the pixel values to a common format. In the sys-tem 10 the R, G, B format is chosen as the common format due to its relative simplici-ty, although other formats are within the scope of the teaching o~ the invention. Thus, all pixel data is converted to R, G, B. This data conversion is accomplished at each FB through the use of a Look-Up-Table (LUT) 15. That is, knowing the particular format stored within a given FB, the associated LUT 15 is programmed such that when a pixel of the format to be converted is applied to the address inputs of the LUT 15, a corresponding R,G,B value is output. Each LUT 15 is preferably coupled to the local host 14 and is programmable thereby, although fixed-content LUTs may also be employed, depending upon the application. It should be appreciated that the host 14 may also be a source of video data to one of the FBs, such as is illustrated in Fig. 1 for the data displayed within window A. As an example, if the host 14 is a workstation then alphanumeri.c text information may be generated by the host 14 for display.
It is further noted tha-t for some video sources, such as a HDTV source, the video signal may be expressed in an analog format. As such, an analog-to-dlgital converter is employed to first convert the analog video input to a digital format suitable for storage within the FB_N.
The use of the LUT 15 pixel data format converters thus overcomas the problem of coherency of the pixel data format provided by each independent image source, in -that a common pixel format is provided prior to pixel mixing.
In order to perform mixing and anti-aliasing per pixel boundary, each of the FBs includes an alpha buffer memory plane, except for the FB_N, which has no down-stream FB
~ Y09-91-084 8 %~ 3~'~
and, thus, no background image to mix with. The alpha bu~fer memory plane is accessed by the device which is also the source of the video data for the associated FB.
For example, FB_~ may have a 32-bit memory plane organized as a 24-bit R, G, B plane and an 8-bit alpha plane, both of which are sourced by a graphics server over a communication network. When the graphics server renders an image it also generates an alpha value associated with each pixel rendered for the image.
As employed herein alpha is considered to be an indication o~ pixel translucency or transparency, and may assume values between ~ero and one. With alpha equal to zero the associated pixel is considered to be totally transparent. That is, any background pixel or pixels are visible. With alpha equal to one the associated pixel is considered to be totally opaque. Values between zero and one provide for gradiations in pixel transparency and are employed to advantage at the boundaries of foreground and background images to anti-alias the boundary pixels to eliminate undesirable display artifacts.
The pixel data and alpha values are both transferred over the comm~lnication network into the associated FB_2. The 8-bit alpha value is used for pixel mixing, via MIX logic 16 and multiplexer (MUX) logic 17, so as to mix R,G,B
image pixel ~ata passed up from the down-stream FB with the pixel from FB_2. The alpha FB plane thus enables real-time, pixel-by-pixel mixing of the foreground pixels with the backgrou~d pixels. Anti-aliasing may also be accomplished in real-time, as will be described ~elow.
In operation, the FB having the lowest priority (N~
converts a pixel (x,y) to R, G, B pixel format, ~ia the associated LUT 15, and passes the converted pixel value on for mixing with a corresponding pixel ~rom the next highest priority frame buffer (FB N-l), via the MI~ 16.
All FBj, excepk for the N-th FB (lowest priority), may perform one of three operations. These operatio~s are shown in TABLF 1.
YO9-91-084 9 ~ A
1. Discard the pixel passed from the j+l FB and pass the associated pi.xel to the upstream j-1 FB, or to the display 12 if j=1. This is accomplished by selecting the A input of the associa-ted MUX 17.
2. Discard its own pixel and pass the pixel received from the j-~1 FB to the j-1 E'B, or to the display 12 if j=1. This is accomplished by selecting the C
: input of the associated MUX 17.
3. Use the value of alpha, from the associated FB, to - mix its own pixel value with the pixel received from the j~1 FB3 and then pass the mixed pixel value to the j-1 FB, or to the display 12 if j=1. This is accomplished by selecting the B input of the ~ associated MUX 17.
;j The method set forth above provides a technique where, for a given display pixel (x,y~, either a single pixel (x,y) from any FB is selected (pixel switching), or any mixed result of two or more pixels (x,y), from different FBs, is selected (pixel mixing).
As seen in Fig. 4, the invention employs a color keying method based on the pixel value of the local host 14.
The local host 14 FB is comprised of three planes. One plane stores a local host 14 pixel value, or color index (CI). A second plane stores a local host 14 window identification number (WID). A third plane storas a local host 14 alpha value (WS_alpha). The system 10 employs control logic 19 for generating a plurality of signals based on inputs from the host 14 FB. These inputs include a CI input for "color keying" to determine display 10 operation. WID provides a mechanism where different windows of the display 12 may have one or more key colors associated therewith. This is accomplished through the use of a palette LUT 15 and a video con-trol (VC) LUT 22. VC_LUT 22 has 2(M-1) outputs which are Y09-9l-084 lO
provided :in palrs to each of the MUXes 17 for controlling the operation thereof, in accordance with TABLE 1.
For example, for a first window a red CI may be defined as "key" to select, via the VC_LUT 22, the HDTV input.
For another window a red CI may be the "key" to cause, via VC_LUT 22, the mixing o~ a host 14 pixel with a HDTV
background pixel, using WS_alpha for modifying the values of boundary pixels so as to perform anti-aliasing. For another window, a red CI may be a pixel that is displayed on the monitor 12, via the palette LUT 20 where the CI is converted to 24-bit R,G,B format. This method advantageously enables any number of independent image sources to be coordinated, rather -than being limited to only two image sources. Furthermore, this method also provides pixel mixing for functions such as real-time anti-aliasing or image blending. All of -these functions may be accomplished on pixels contained within and/or bounding an object of interest, based on the value of WID. Furthermore, these functions are applied on pixel-by-pixel basis.
Preferably, video output controls are implemented using the local host 12 FB. For illustration, FB_1 is chosen as the local host FB, but any one of the FBs may be been chosen instead. As seen in Fig. 4, for the local host 12 graphics work space there are a total of P bit planes for the FB. Of the P-bits output by these planes, C-bits are used as the color index (CI), W-bits are used as the window identificater (WID), and M-bits are used for ~WS_alpha) for blending the local host 12 image with another image. Both CI and WID are employed as indexes (addresses) to the LUT 15 to provide 24 bit R, G, B data.
Furthermore, these same bits are used as indexes (addresses~ to VC_LUT 22 to provide the video path control bits (VID_CNTRL), which are used to coordinate the display output. The width of VID_CNTRL is a function of the total number of the image sources ~N).
For each FBj, where 1 < j < N, two bits are re~uired to choose one of the three operations described in TABLE 1.
The definition of these two bits may be expressed as:
00 - Mixing Disabled. Select Input A for MUX;
01 - Mixing Disabled. Select Input C ~Eor MUX;
and lx - Mixing Enabled. Select input B for MUX.
~or FBj, if bit 1 ~MSB) is set, mixing is enabled and the result of the mixed pixel of FBj and FBj~l is passed to the j-l FB. In this case bit 0 (LSB) is ignored. If bit 1 is reset, then alpha mixing is disabled, and either the pixel value from FBj (if bit 0 is reset) or the pixel value received from FBj+1 (if bit 0 is set) is passed to FBj 1 In that the FB_N can only pass its output pixel value upstream, it does not require any control bits. Thus, the total number of bits required for VID_CNTRL, for N
image sources, is B = 2(N-1), where B is number of bits in VID_CNTRL and N is the number of independent image I
/ sources.
:~ :
The VID_CNTRL assignment for FBj are bits 2j-2 for the least significant bit and 2j-1 for the most significant bit. This provides a flexible mechanism for window control for a multi-source system. It should be noted that from the local host 12, by using the color keying, a user may cause any display pixel to be formed from a result of all corresponding pixels from all FBs. That is, the user defines a color key to represent a specific output format, and then employs that color key where a specific output is desired. Furthermore, through the use of WID the user is enabled to select the color keying as a function of window identification. For example, if the width of WID is 4-bits, then there may be up to 24, or 16, windows that are simultaneously displayed and controlled. For this case the VC_LUT 22 include~ up to 1~ different storage regions, each region containing Y09-91-0~4 12 2~
different VID_CNTRL values. A specific one of the regions within VC_LUT 22 is selected by the value of WID, while a specific VID_CNTRL bi-t combination within the region is selected by the value of CI.
In summary, this mechanism provides a flexible output control for any number of FBs utilizing both color keying and mixing ~anti-aliasing) techniques on a pixel~by-pixel basis. If FB mixing is enabled for each level, the equation for the resulting displayed pixel (R) is given by:
R = ~lPl ~ 2P2~(l a2)(~3P3 ( 3) ~~~(aN_lPN~ N-l)PN)) where Pj represents a pixel from the FBj, and where represents an alpha value from the FBj.
A high resolution monitor, e.g. 2048 X 2048 pixels, requires a video bandwidth in excess of 360 Mhz. In order to provide the bandwidth necessary for a high resolution monitor, th~ serial video output from the FB
VRAMs is re~uired to be interleaved. For example, for a conventional VRAM, having a serial output bandwidth of 33 Mhz, the FB video output path needs to be, for a 60 Hz 2048 X 2048 resolution monitor, interleaved at least 11 ways and, thus, requires 11 independent data paths. As a further example of interleaving, for a monitor resolution of 1~80 x lQ24, the video bandwidth is 110 MHz. Thus, four way interleaving is sufficient for this resolution.
However, for a monitor resolution of 2048 x 1536, the video bandwidth is 260 Mhz. This requires eight way interleaving, in that four way interleaving provides only 4 x 33 Mhz, or 132 Mhz, while eight way interleaving provides 26~ MHz.
The MIX logic 16 and the MUX logic ~7 for each FB is replicated to match the interleave f~ctor. In general, there is a MIX logic 16 and a MUX logic 17 for each of the interleaved, independent data paths. Thus, if the display output of the FB is interleaved M ways for N
image sources, there are ((M X N)-N) pairs of MIX and MUX
logic blocks, in that the lowest priority FB level does not require mixing. This modular approach enables pixel mixing in real-time for any monitor resolution.
Fiy. 3 shows a M X N embodiment for an interleaved video system. A Sarializer 24 accepts the outputs from j=1 MIXERS 30 and shifts these outputs out to the display 12 at the video clock rate.
An integrated circuit implementation of the foregoing may be accomplished by several methods. One method is to provide a fast integrated circuit device after serializing the interleaved video data output from the FB
VRAM's. However, this requires, for 260 Mhz display, a 3.85 nanosecond cycle time to perform any operation, such as blendiny two images. Another method is to provide multiple, slower devices at the output of each interleaved memory data path, as in Fig. 3. The second method is preferred over the firs-t in that -the first requires either ECL or GaAs gate arrays to accommodate the high video bandwidth. However, the same circuit architecture described below lends itself to either approach.
A most time critical section of the video data path flow is the blending functiorl~ in that this function requires multipliers and adders. The blending function for the FBj uses the equation:
Rj = (ajPj) + ((1-~j3Rj+1)' where R; is the resulting pixel value output to the next FB, Pj is the pixel from the FBj, Rj~1 is the pixel value input from the previous FBj+l, and j is the Pj/(Pj+Rj~1) pixel weight, wherein (0 <a< 1. O~ . This approach requires two multipliers and an adder. However, using an algebraic manipulation there is obtained, 2~~ A~
Rj = (ajPj) ~ ((1-aj)Rj+1), Rj = (ajP~ Rj~l - (ajRj~1), and Rj - (~j(Pj - Rj+l)) ~ Rj~l This latter expression ~or Rj re~uires but one multiplier and two adders.
Fig. 5 illustrates a mixer integrated circuit device 30 block diagram. Because of the required cycle time, the adders 32 and the multiplier 34 are pipelined, and al.l data values are delayed to mainkain them in synchronous order, as will be described.
The following describes the ~unction of the MIXER 30 of Fig. 5. Reference is also made to Fig. 3. The image data associated with each pixel arrives at the inputs simultaneously. In order to provide a maximum clock speed all inputs and outputs are registered (REG1-REG8) and clocked by the system clock.
The system clock is derived by dividing the video bandwidth by M for an M-way interleaved memory. For example, in the case of a medium resolution monitor, the video bandwidth is 110 MHz. The FB memory is interleaved, by example, four ways. Therefore, the system clock is 110 Mhz/4, or 27.5 Mhz. In case o~ the high resolution monitor, the video bandwidth is 260 Mhz and the memory is interleaved eight ways. Thus, the system clock is 260 Mhz/8, or 32.5 Mhz.
In -that it is difficult to economically achieve a full multiplier that operates at approximately 33 Mh~, the multiplier 34 is preferably pipelined. The depth of the pipelining depends on the selected chip technology. Using readily available integrated circuit technology the multiplier pipeline depth may be achieved with two stages, and the adder 34 achieved with one stage. To maximize the throughput, the outpu-t of each functional block i~ reclocked. Thus, the MIXER 30 is totally synchronous with a single free running system clock.
lO9-91-084 15 2~
The function of the MIXER 30 is described as follows.
All inputs are simultaneously clocked i.nto the chip registers REGl through REG4. These inputs are VID_CNTRL~ , Pj and Rj~l. I'he output of REG3 and REG4 are fed into function block EUNCl where -the (R3-R4) operation is performed. Meanwhile, to synchronize all other inputs, Rl, R2, and R4 are delayed via registers REG5 and REG6. The function of (FUNC4) is discussed later. For the next two clock cycles, R5 and Fl are multiplied by FUNC2, and R6 is correspondingly delayed two clock cycles with REG7 and REG8. Finally, F2 and R8 are fed through the function block FUNC3 where the (F2 R8) operation is performed.
In order to obtain perfect mixing across N frame buffers, the full precision of Rj, which increases by the wid-th of Pj at each EBj, should ~e propagated. However, this is not a practical solution in that it is not cost effective to carry the full resolution of Rj to the next stage.
~owe~er, a simple truncation may be used and results in, on the average, a 1/2 bit error per mixing stage.
If rounding off is parformed at the function block FUNC5 then, on average, the error is l/4 bit, or one half of the 1/2 bit error if FUNC5 were not employed. Thus, FUNC5 provides that the resulting pixel Rj has the same number of bits as Pj. Therefore, the total cycle time re~uired ~or MIXER 30 is six system clock periods.
MIXER 30 serves two functions. The first function is alpha mixing (or anti-aliasing~. The second function is data path control. As shown in Fig. 2, for each FB, except the FB_N, there is provided a three-to-one MUX 17.
To further reduce cost and complexity the function of MUX
17 is incorporated within MIXER 30, as described below.
When alpha is set to 1.0, Rj (the result of alpha mixing) is Pj. When alpha is set to 0.0, then Rj is Rj 1 In other words, the mixing function may also perform a multiplexer function, provided that the values of alpha lO9-91-0~4 16 ~3~
are properly selected. This is accomplished in the block ~FUNC4), as shown in Fig. 5. The logic for FUNC~, for an ~-bit wide alpha value, is shown in Fig. 6. The two bit VIDEO_CNTRL is employed to control the alpha value. When the alpha enable bit (VID_CNTROL_l) is asserted, then alpha-OUT is identical to the alpha input. When the alpha enable bit (VID_CNTRL_l) is deasserted, alpha_OUT_O
to alpha_OUT_6 are forced to a zero by AND6 through ANDO.
Furthermore, alpha _OUT_7 is set to a one, making alpha_OUT = 1.0, which causes the MIXER 30 to select Pj ~l .
The total number of inputs and outputs to MIXER 30, assuming an 8-bit alpha value, are for each R,G,B color: 8 outputs ~or Rj;
8 inputs for Pj;
8 inputs for Rj+l;
common signals 8 inputs for alpha;
2 inputs for VID_CNTRL; and 1 input ~or SYSTEM CLOCK, for a total of 83 pins, not including power, etc.
As was stated, one of the problems encountered with pixel mixing is that -two images, generated from two different sources, may be di~ferent in format. For example, pixel sizes may be dif~erent between two images sources, where one image source pixel may be a square pixel while the other image source pixel is not a square pixel. Another example is that two image sources may not have the same resolution. Thus, in order to have a pixel-by-pixel correspondence for the entire FB structure, one image may need to be either scaled up, i~ that image source is smaller than the other, or scaled down, if that image source is larger than the other. One solution to these problems, which is accommodated by the teaching o~ the invention, is to over-sample on all of the FBs where the resolution of the image source ~or the FB is a common least mul-tiple o~ the resolution of each o~ the image lO9-91-084 17 sources, in both the hori~ontal and vertical directions.
The common least multiple FB approach ls preferable, in that over-sampling is not always readily accomplished, as in the case of an HVTV image sampler in which the resolution is fixed at 1920 X 1035 pi~els~ However, i~
the FB size is the size of a least common multiple, then pixels may be either simply replicated or interpolated as a means for over-sampling. Another approach is to employ digital signal processing in order to over-sample.
It should be noted however that the leas-t common multiple approach may result in a very large F~. For e~ample, the least common multiple of 480 scanlines and 1035 scanlines is 33,120 scanlines. Furthermore, the resulting pixel may not be a square pixel. ~lso, a -time-base correction may be necessary to match the monitor bandwidth.
Fortunately, for many graphics or video systems the pixels are normally square (or almost square).
Eurthermore~ due to windowing, image sources need not fill the entire FB, so that each pixel can be treated equally. Thus, pixel P(x,y)j may be considered as being both square and eq~al in size for all j (1 ~ j > N~, where j represents the j-th FB and N is the number of frame buffers in the system.
In summary, the invention addresses and solves the problems of combining multiple image sources at a display monitor. Overlay and blending techniques are disclosed for a system with N independent image sources.
The technique of the invention allows for any number of independent image sources (N), where each source has an associated FB. The architecture also enables the serial output of each FB to be interleaved so as to match the video output. Thus, if the interleaving requires M
arrays, then the total number of MIXERS 30 is N x M, which enables mixing of any number of images with a pixel accuracy that is a function of the combined transparency coefficient of the images.
'~09-91-084 18 Z~?~
The teaching of the invention also employs video look-up tables to enable a variety of mixing operations to occur in a multi-tasking environment, based on an application specific window identification number.
The invention also provides real-time pixel swi-tching and control on a pixel-by-pixel basis, for any number of independent image sources per window, using the WID
value.
While the invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that changes in form and details may be made therein wlthout departing from the scope and splrit of the invention.
AND ANTI-ALIASING
FIE~D OF THE INVENTIOM:
This invention relates generally to image display apparatus and method and, in particular, to the simultaneous display of images from a plurality of image sources.
BACKGROUND OF THE INVENTION:
In a modern display system data from multiple image sources are displayed. These images are shown on the display using a "window" ! a technique in which an area of a display is assigned to an image source. However, problems arise when the outputs from multiple sources must be coordinated on the display. ~hen there is more than one source for the display, a machanism is required to coordinate the output to a single display monitor.
A straightforward solution is to design the system such that only one source can be displayed at a time. For example, if a High Definition Televisions (HDTV) sampler input is selected, then only the HDTV output is output to the display. However, with an increased demand for "windowing" in graphics systems, and with an increased emphasis on a multimedia environment, where there exists more than one video source, this relatively simple solution is not adequate.
In order to accomplish windowing there must be provided a mechanism such that, within the total area defined by a monitor screen, different sub-areas are sourced by different video sources. Fig. 1 shows an example of a windowed graphics monitor screen. Area A may be sourced by a local host or workstation. Area B may be sourced by a remote graphics server connected ~ia a high speed network. Area C may be sourced by a HDTV sampler. One technique to provide such a display is known in the art ~09-91-0~4 2 2a~ 3~
as pixel switching. That is, for a given display area, or window, the source of pixels ~or that area i~ selected from a specified image plane.
A more compl.ex problem is presented when an arbitrari~y shaped image from a source is overlayed on top of another image, rather than over a simple rectangular window. For example, an image of an automobile may be rendered using a graphics server, and the automobile image may ba required to be overlayed upon a HDTV-generated background image. This requires -that all pixel selection be accomplished on a pixel-by-pixel basis, since the shape of the foreground object, or automobile, is not rectangular.
One solution that is applicable to a two-image source system utilizes color keyed pi~el switching, and allows pixel-by-pixel selection between two sources. This technique is described in commonly assigned U.S. Patent No. 4,994,912, enti-tled "Audio ~isual Interactive Display", by L. ~umelsky et. al..
~owever, for the case where there are more than two video sources, such as is illustrated in Fig. 1, a different ~olution is re~uired for displaying N, where (N>2), image sources on a pixel-by-pixel basis.
Another problem that arises in overlaying arbitrarily shaped multiple source images is due to an aliasing effect resulting from imag~ pixel switching. In that a pixel of one image source may not blend with a pixel from a second image source, aliasing results. Aliasing causes the resultant image to exhibit undesirable artifacts along the boundary between the foreground and the background images, such as stair-casing and color distortion. In order to e].iminate the artifacts, an anti-aliasing techni~ue is necessary. However, in that the foreground image does not contain information about the background image, the anti-aliasing should be accomplished in real-time at the video output. Thus, a ~0~-91-084 3 2~
technique for anti-aliasing N image sources in real-time is required. Furthermore, in order to anti-alias an arbitrarily shaped foreground object, the anti-aliasing must be accomplished on a pixel-by-pixel basis.
However, in modern high resolution displays the video data bandwidth and data rates are very high, thus placing severe timing constraints on any pixel processing -that is to be accomplished in a r.~eal-time manner.
In U.S. Patent No. 5,001,469, issued March 19, 1991, entitled "Window-Dependent Buffer Selection" to Pappas et al. there is described window control hardware in a graphics sub-system in which multiple image sources are shown on to a single monitor. This is accomplished by defining each window as a separate frame buffer and defining for each window, i.e. frame buffer, a window identification, and a window size and location based on four values of top location, bottom location, left location, and right location. This system also employs a prioritizing scheme where N frame buffers ("windows") are prioritized from 0 to N-1, where 0 has the highest priority and N-1 has the lowest priority. The graphics sub-system includes N window detection logics, one for each frame buffar, which use comparators for window size and location values to determine if the associated window is active for a region of the screen. If the window is active an image source pointer and other information are sent to prioritizing logic which prioritizes N inpu-t signals to determine which "active" imaye source has a highest priority. An active image with the highest priority is chosen by the prior~ty logic and shown on a monitor.
Pappas et. al. employ window size and location values to control multiple image sources, and an image frame bu~fer does not contain multiple windows. Furthermore, this system appears to be limited for use with only rectangularly shaped windows. Also, the problem of ~09-91-084 4 3~ x~
displaying multiple sources with differincJ image forma-ts is not addressed.
It is thus one objec-t of the invention to provide for the simultaneous display of video data from N independent image sources, where N may be greater tharl two, through the use of pixel switching and control on a pixel-by-pixel basis for the N image sources.
It is another object of the invention to provide a method and apparatus for displaying video data from a plurality of image sources on a monitor using a combination of alpha mixing and pixel switching, on a pixel-by-pixel basis, based on pixel color keying and window identification.
SUMM~R~ OF l'HE INVENTION
The foregoing and other problems are overcome and the objects of the invention are realized by method and apparatus for implementing a raster graphic display video data path that provides arbitrary mixing of a plurality of images. The video data path ls highly parallelized, and employs parallel devices operating under the control of a set of look-up tables. The look-up tables are loadable from a controller, such as a host workstation.
The raster graphic display video data path functions with unlimited screen resolutions, and also enables a variety of different pixel data formats from a potentially large number of different sources. Outputs from many image sources are mixed under the control of the host workstation, with pixel accuracy being based on (a~ a comblned transparency coefficient (alpha) of the images, for each image source, and (b) a window identification number assigned by the host workstation.
Pixel data format conversion to a common prede-termined forma-t provides coherency between pixel values generated by a number of dif~erent image sources, such as ~DTV and ~09-91-084 5 high resolution graphics servers, such as a supercomputer.
An anti-aliasing function is disclosed for use in eliminating artifacts between a foreground image s boundary with a background image. The anti-aliasing function may also be used for generating special effects, such as showing a translucent image foreground from one source on top oE a background image from another source.
The preferred anti-aliasing approach employ~ pixel mixing.
In order to allow any number of independent video sources, a separate frame buffer is allocated for each of the sources. ~hus, for a system with M separate video data sources, there are N frame buffers. Depending on display monitor bandwidth requirements, each of the N
frame buffers may also be interleaved M ways.
The invention also pertains to a~ integrated circuit device that provides, in a high speed pipelined manner, a pixel mixing function and a pixel multiplexing function.
BRIEF DESCRIPTION OF THE DRAWING
The above set ~orth and other features of the invention are made more apparent in the ensuing Detailed Description of the Invention, when read in conjunction with the attached Drawing, wherein:
Fig. 1 illustrates an exemplary display screen having multiple video data sources each displayed within an associa-ted windowi Fig. 2 is a block diagram showiny, in accordance with the invention, a plurality of hierarchically arranged frame buffers having look-up tables, pixel mixing, and pixel multiplexing circuitry interposed between frame buffers;
~09-91-084 6 Fig. 3 is a block diagram showing an N by M configuration of hierarchically arranged frame buffers having look-up tables, pixel mixing, and pixel multiplexing circuitry interposed between frame buffers;
Fig. 4 illustrates a local host video path;
Fig. 5 is a block diagram illustrating pixel mixing and multiplexing logic embodied within an integrated circuit device; and Fig. 6 is a schematic diagram illustrating an alpha control logic function from the pixel mixing logic of Fig. 5.
DETAILED DESCRIPTION OF THE INVENTION
Referring to Fig. 2 there is illu~trated a block diagram of a multi-source video display pixel mixing system 10 that is constructed and operated in accordance with the invention. System 10 receives video data input from N
sources, with each source having an associated frame buffer (FB) memory ~FB_l to FB_N). Also shown is a video output data path for a pixel (x,y) of each FB. In that there are N overlay FBs, there are N overlay pixels for a pi~el displayed at display 12 location ~x,y), one from each FB. The FBs are hierarchically ordered from 1 to N, where 1 is considered to have a highest priority and where N is considered to have a lowest priority. By preference, but not as a limitation upon the practice of the invention~ FB_l is associated with a host 14 and FB_N
is associated with, by example, an HDTV video source that does not provide an indication of pixel translucency, or alpha. The FBs are addressed in parallel so that each operates in lock-step with the others.
In a multi-media system such as the one depicted in Fig.
2 a coherency of pixel format cannot be assumed. For example, an image generated by a supercomputer and/or a graphic server and received from a communication network ~09-91-084 7 ~ ~~
may have a 24-bit Red, Green, Blue (~,G,B) forma-t.
However, the local workstation host 1~ may have an 8-bit pixel format, and an HDTV sampled input may have a chrominance/luminance (Y/C) ~ormat. In order to mix pixels from these diverse sources a first step converts the pixel values to a common format. In the sys-tem 10 the R, G, B format is chosen as the common format due to its relative simplici-ty, although other formats are within the scope of the teaching o~ the invention. Thus, all pixel data is converted to R, G, B. This data conversion is accomplished at each FB through the use of a Look-Up-Table (LUT) 15. That is, knowing the particular format stored within a given FB, the associated LUT 15 is programmed such that when a pixel of the format to be converted is applied to the address inputs of the LUT 15, a corresponding R,G,B value is output. Each LUT 15 is preferably coupled to the local host 14 and is programmable thereby, although fixed-content LUTs may also be employed, depending upon the application. It should be appreciated that the host 14 may also be a source of video data to one of the FBs, such as is illustrated in Fig. 1 for the data displayed within window A. As an example, if the host 14 is a workstation then alphanumeri.c text information may be generated by the host 14 for display.
It is further noted tha-t for some video sources, such as a HDTV source, the video signal may be expressed in an analog format. As such, an analog-to-dlgital converter is employed to first convert the analog video input to a digital format suitable for storage within the FB_N.
The use of the LUT 15 pixel data format converters thus overcomas the problem of coherency of the pixel data format provided by each independent image source, in -that a common pixel format is provided prior to pixel mixing.
In order to perform mixing and anti-aliasing per pixel boundary, each of the FBs includes an alpha buffer memory plane, except for the FB_N, which has no down-stream FB
~ Y09-91-084 8 %~ 3~'~
and, thus, no background image to mix with. The alpha bu~fer memory plane is accessed by the device which is also the source of the video data for the associated FB.
For example, FB_~ may have a 32-bit memory plane organized as a 24-bit R, G, B plane and an 8-bit alpha plane, both of which are sourced by a graphics server over a communication network. When the graphics server renders an image it also generates an alpha value associated with each pixel rendered for the image.
As employed herein alpha is considered to be an indication o~ pixel translucency or transparency, and may assume values between ~ero and one. With alpha equal to zero the associated pixel is considered to be totally transparent. That is, any background pixel or pixels are visible. With alpha equal to one the associated pixel is considered to be totally opaque. Values between zero and one provide for gradiations in pixel transparency and are employed to advantage at the boundaries of foreground and background images to anti-alias the boundary pixels to eliminate undesirable display artifacts.
The pixel data and alpha values are both transferred over the comm~lnication network into the associated FB_2. The 8-bit alpha value is used for pixel mixing, via MIX logic 16 and multiplexer (MUX) logic 17, so as to mix R,G,B
image pixel ~ata passed up from the down-stream FB with the pixel from FB_2. The alpha FB plane thus enables real-time, pixel-by-pixel mixing of the foreground pixels with the backgrou~d pixels. Anti-aliasing may also be accomplished in real-time, as will be described ~elow.
In operation, the FB having the lowest priority (N~
converts a pixel (x,y) to R, G, B pixel format, ~ia the associated LUT 15, and passes the converted pixel value on for mixing with a corresponding pixel ~rom the next highest priority frame buffer (FB N-l), via the MI~ 16.
All FBj, excepk for the N-th FB (lowest priority), may perform one of three operations. These operatio~s are shown in TABLF 1.
YO9-91-084 9 ~ A
1. Discard the pixel passed from the j+l FB and pass the associated pi.xel to the upstream j-1 FB, or to the display 12 if j=1. This is accomplished by selecting the A input of the associa-ted MUX 17.
2. Discard its own pixel and pass the pixel received from the j-~1 FB to the j-1 E'B, or to the display 12 if j=1. This is accomplished by selecting the C
: input of the associated MUX 17.
3. Use the value of alpha, from the associated FB, to - mix its own pixel value with the pixel received from the j~1 FB3 and then pass the mixed pixel value to the j-1 FB, or to the display 12 if j=1. This is accomplished by selecting the B input of the ~ associated MUX 17.
;j The method set forth above provides a technique where, for a given display pixel (x,y~, either a single pixel (x,y) from any FB is selected (pixel switching), or any mixed result of two or more pixels (x,y), from different FBs, is selected (pixel mixing).
As seen in Fig. 4, the invention employs a color keying method based on the pixel value of the local host 14.
The local host 14 FB is comprised of three planes. One plane stores a local host 14 pixel value, or color index (CI). A second plane stores a local host 14 window identification number (WID). A third plane storas a local host 14 alpha value (WS_alpha). The system 10 employs control logic 19 for generating a plurality of signals based on inputs from the host 14 FB. These inputs include a CI input for "color keying" to determine display 10 operation. WID provides a mechanism where different windows of the display 12 may have one or more key colors associated therewith. This is accomplished through the use of a palette LUT 15 and a video con-trol (VC) LUT 22. VC_LUT 22 has 2(M-1) outputs which are Y09-9l-084 lO
provided :in palrs to each of the MUXes 17 for controlling the operation thereof, in accordance with TABLE 1.
For example, for a first window a red CI may be defined as "key" to select, via the VC_LUT 22, the HDTV input.
For another window a red CI may be the "key" to cause, via VC_LUT 22, the mixing o~ a host 14 pixel with a HDTV
background pixel, using WS_alpha for modifying the values of boundary pixels so as to perform anti-aliasing. For another window, a red CI may be a pixel that is displayed on the monitor 12, via the palette LUT 20 where the CI is converted to 24-bit R,G,B format. This method advantageously enables any number of independent image sources to be coordinated, rather -than being limited to only two image sources. Furthermore, this method also provides pixel mixing for functions such as real-time anti-aliasing or image blending. All of -these functions may be accomplished on pixels contained within and/or bounding an object of interest, based on the value of WID. Furthermore, these functions are applied on pixel-by-pixel basis.
Preferably, video output controls are implemented using the local host 12 FB. For illustration, FB_1 is chosen as the local host FB, but any one of the FBs may be been chosen instead. As seen in Fig. 4, for the local host 12 graphics work space there are a total of P bit planes for the FB. Of the P-bits output by these planes, C-bits are used as the color index (CI), W-bits are used as the window identificater (WID), and M-bits are used for ~WS_alpha) for blending the local host 12 image with another image. Both CI and WID are employed as indexes (addresses) to the LUT 15 to provide 24 bit R, G, B data.
Furthermore, these same bits are used as indexes (addresses~ to VC_LUT 22 to provide the video path control bits (VID_CNTRL), which are used to coordinate the display output. The width of VID_CNTRL is a function of the total number of the image sources ~N).
For each FBj, where 1 < j < N, two bits are re~uired to choose one of the three operations described in TABLE 1.
The definition of these two bits may be expressed as:
00 - Mixing Disabled. Select Input A for MUX;
01 - Mixing Disabled. Select Input C ~Eor MUX;
and lx - Mixing Enabled. Select input B for MUX.
~or FBj, if bit 1 ~MSB) is set, mixing is enabled and the result of the mixed pixel of FBj and FBj~l is passed to the j-l FB. In this case bit 0 (LSB) is ignored. If bit 1 is reset, then alpha mixing is disabled, and either the pixel value from FBj (if bit 0 is reset) or the pixel value received from FBj+1 (if bit 0 is set) is passed to FBj 1 In that the FB_N can only pass its output pixel value upstream, it does not require any control bits. Thus, the total number of bits required for VID_CNTRL, for N
image sources, is B = 2(N-1), where B is number of bits in VID_CNTRL and N is the number of independent image I
/ sources.
:~ :
The VID_CNTRL assignment for FBj are bits 2j-2 for the least significant bit and 2j-1 for the most significant bit. This provides a flexible mechanism for window control for a multi-source system. It should be noted that from the local host 12, by using the color keying, a user may cause any display pixel to be formed from a result of all corresponding pixels from all FBs. That is, the user defines a color key to represent a specific output format, and then employs that color key where a specific output is desired. Furthermore, through the use of WID the user is enabled to select the color keying as a function of window identification. For example, if the width of WID is 4-bits, then there may be up to 24, or 16, windows that are simultaneously displayed and controlled. For this case the VC_LUT 22 include~ up to 1~ different storage regions, each region containing Y09-91-0~4 12 2~
different VID_CNTRL values. A specific one of the regions within VC_LUT 22 is selected by the value of WID, while a specific VID_CNTRL bi-t combination within the region is selected by the value of CI.
In summary, this mechanism provides a flexible output control for any number of FBs utilizing both color keying and mixing ~anti-aliasing) techniques on a pixel~by-pixel basis. If FB mixing is enabled for each level, the equation for the resulting displayed pixel (R) is given by:
R = ~lPl ~ 2P2~(l a2)(~3P3 ( 3) ~~~(aN_lPN~ N-l)PN)) where Pj represents a pixel from the FBj, and where represents an alpha value from the FBj.
A high resolution monitor, e.g. 2048 X 2048 pixels, requires a video bandwidth in excess of 360 Mhz. In order to provide the bandwidth necessary for a high resolution monitor, th~ serial video output from the FB
VRAMs is re~uired to be interleaved. For example, for a conventional VRAM, having a serial output bandwidth of 33 Mhz, the FB video output path needs to be, for a 60 Hz 2048 X 2048 resolution monitor, interleaved at least 11 ways and, thus, requires 11 independent data paths. As a further example of interleaving, for a monitor resolution of 1~80 x lQ24, the video bandwidth is 110 MHz. Thus, four way interleaving is sufficient for this resolution.
However, for a monitor resolution of 2048 x 1536, the video bandwidth is 260 Mhz. This requires eight way interleaving, in that four way interleaving provides only 4 x 33 Mhz, or 132 Mhz, while eight way interleaving provides 26~ MHz.
The MIX logic 16 and the MUX logic ~7 for each FB is replicated to match the interleave f~ctor. In general, there is a MIX logic 16 and a MUX logic 17 for each of the interleaved, independent data paths. Thus, if the display output of the FB is interleaved M ways for N
image sources, there are ((M X N)-N) pairs of MIX and MUX
logic blocks, in that the lowest priority FB level does not require mixing. This modular approach enables pixel mixing in real-time for any monitor resolution.
Fiy. 3 shows a M X N embodiment for an interleaved video system. A Sarializer 24 accepts the outputs from j=1 MIXERS 30 and shifts these outputs out to the display 12 at the video clock rate.
An integrated circuit implementation of the foregoing may be accomplished by several methods. One method is to provide a fast integrated circuit device after serializing the interleaved video data output from the FB
VRAM's. However, this requires, for 260 Mhz display, a 3.85 nanosecond cycle time to perform any operation, such as blendiny two images. Another method is to provide multiple, slower devices at the output of each interleaved memory data path, as in Fig. 3. The second method is preferred over the firs-t in that -the first requires either ECL or GaAs gate arrays to accommodate the high video bandwidth. However, the same circuit architecture described below lends itself to either approach.
A most time critical section of the video data path flow is the blending functiorl~ in that this function requires multipliers and adders. The blending function for the FBj uses the equation:
Rj = (ajPj) + ((1-~j3Rj+1)' where R; is the resulting pixel value output to the next FB, Pj is the pixel from the FBj, Rj~1 is the pixel value input from the previous FBj+l, and j is the Pj/(Pj+Rj~1) pixel weight, wherein (0 <a< 1. O~ . This approach requires two multipliers and an adder. However, using an algebraic manipulation there is obtained, 2~~ A~
Rj = (ajPj) ~ ((1-aj)Rj+1), Rj = (ajP~ Rj~l - (ajRj~1), and Rj - (~j(Pj - Rj+l)) ~ Rj~l This latter expression ~or Rj re~uires but one multiplier and two adders.
Fig. 5 illustrates a mixer integrated circuit device 30 block diagram. Because of the required cycle time, the adders 32 and the multiplier 34 are pipelined, and al.l data values are delayed to mainkain them in synchronous order, as will be described.
The following describes the ~unction of the MIXER 30 of Fig. 5. Reference is also made to Fig. 3. The image data associated with each pixel arrives at the inputs simultaneously. In order to provide a maximum clock speed all inputs and outputs are registered (REG1-REG8) and clocked by the system clock.
The system clock is derived by dividing the video bandwidth by M for an M-way interleaved memory. For example, in the case of a medium resolution monitor, the video bandwidth is 110 MHz. The FB memory is interleaved, by example, four ways. Therefore, the system clock is 110 Mhz/4, or 27.5 Mhz. In case o~ the high resolution monitor, the video bandwidth is 260 Mhz and the memory is interleaved eight ways. Thus, the system clock is 260 Mhz/8, or 32.5 Mhz.
In -that it is difficult to economically achieve a full multiplier that operates at approximately 33 Mh~, the multiplier 34 is preferably pipelined. The depth of the pipelining depends on the selected chip technology. Using readily available integrated circuit technology the multiplier pipeline depth may be achieved with two stages, and the adder 34 achieved with one stage. To maximize the throughput, the outpu-t of each functional block i~ reclocked. Thus, the MIXER 30 is totally synchronous with a single free running system clock.
lO9-91-084 15 2~
The function of the MIXER 30 is described as follows.
All inputs are simultaneously clocked i.nto the chip registers REGl through REG4. These inputs are VID_CNTRL~ , Pj and Rj~l. I'he output of REG3 and REG4 are fed into function block EUNCl where -the (R3-R4) operation is performed. Meanwhile, to synchronize all other inputs, Rl, R2, and R4 are delayed via registers REG5 and REG6. The function of (FUNC4) is discussed later. For the next two clock cycles, R5 and Fl are multiplied by FUNC2, and R6 is correspondingly delayed two clock cycles with REG7 and REG8. Finally, F2 and R8 are fed through the function block FUNC3 where the (F2 R8) operation is performed.
In order to obtain perfect mixing across N frame buffers, the full precision of Rj, which increases by the wid-th of Pj at each EBj, should ~e propagated. However, this is not a practical solution in that it is not cost effective to carry the full resolution of Rj to the next stage.
~owe~er, a simple truncation may be used and results in, on the average, a 1/2 bit error per mixing stage.
If rounding off is parformed at the function block FUNC5 then, on average, the error is l/4 bit, or one half of the 1/2 bit error if FUNC5 were not employed. Thus, FUNC5 provides that the resulting pixel Rj has the same number of bits as Pj. Therefore, the total cycle time re~uired ~or MIXER 30 is six system clock periods.
MIXER 30 serves two functions. The first function is alpha mixing (or anti-aliasing~. The second function is data path control. As shown in Fig. 2, for each FB, except the FB_N, there is provided a three-to-one MUX 17.
To further reduce cost and complexity the function of MUX
17 is incorporated within MIXER 30, as described below.
When alpha is set to 1.0, Rj (the result of alpha mixing) is Pj. When alpha is set to 0.0, then Rj is Rj 1 In other words, the mixing function may also perform a multiplexer function, provided that the values of alpha lO9-91-0~4 16 ~3~
are properly selected. This is accomplished in the block ~FUNC4), as shown in Fig. 5. The logic for FUNC~, for an ~-bit wide alpha value, is shown in Fig. 6. The two bit VIDEO_CNTRL is employed to control the alpha value. When the alpha enable bit (VID_CNTROL_l) is asserted, then alpha-OUT is identical to the alpha input. When the alpha enable bit (VID_CNTRL_l) is deasserted, alpha_OUT_O
to alpha_OUT_6 are forced to a zero by AND6 through ANDO.
Furthermore, alpha _OUT_7 is set to a one, making alpha_OUT = 1.0, which causes the MIXER 30 to select Pj ~l .
The total number of inputs and outputs to MIXER 30, assuming an 8-bit alpha value, are for each R,G,B color: 8 outputs ~or Rj;
8 inputs for Pj;
8 inputs for Rj+l;
common signals 8 inputs for alpha;
2 inputs for VID_CNTRL; and 1 input ~or SYSTEM CLOCK, for a total of 83 pins, not including power, etc.
As was stated, one of the problems encountered with pixel mixing is that -two images, generated from two different sources, may be di~ferent in format. For example, pixel sizes may be dif~erent between two images sources, where one image source pixel may be a square pixel while the other image source pixel is not a square pixel. Another example is that two image sources may not have the same resolution. Thus, in order to have a pixel-by-pixel correspondence for the entire FB structure, one image may need to be either scaled up, i~ that image source is smaller than the other, or scaled down, if that image source is larger than the other. One solution to these problems, which is accommodated by the teaching o~ the invention, is to over-sample on all of the FBs where the resolution of the image source ~or the FB is a common least mul-tiple o~ the resolution of each o~ the image lO9-91-084 17 sources, in both the hori~ontal and vertical directions.
The common least multiple FB approach ls preferable, in that over-sampling is not always readily accomplished, as in the case of an HVTV image sampler in which the resolution is fixed at 1920 X 1035 pi~els~ However, i~
the FB size is the size of a least common multiple, then pixels may be either simply replicated or interpolated as a means for over-sampling. Another approach is to employ digital signal processing in order to over-sample.
It should be noted however that the leas-t common multiple approach may result in a very large F~. For e~ample, the least common multiple of 480 scanlines and 1035 scanlines is 33,120 scanlines. Furthermore, the resulting pixel may not be a square pixel. ~lso, a -time-base correction may be necessary to match the monitor bandwidth.
Fortunately, for many graphics or video systems the pixels are normally square (or almost square).
Eurthermore~ due to windowing, image sources need not fill the entire FB, so that each pixel can be treated equally. Thus, pixel P(x,y)j may be considered as being both square and eq~al in size for all j (1 ~ j > N~, where j represents the j-th FB and N is the number of frame buffers in the system.
In summary, the invention addresses and solves the problems of combining multiple image sources at a display monitor. Overlay and blending techniques are disclosed for a system with N independent image sources.
The technique of the invention allows for any number of independent image sources (N), where each source has an associated FB. The architecture also enables the serial output of each FB to be interleaved so as to match the video output. Thus, if the interleaving requires M
arrays, then the total number of MIXERS 30 is N x M, which enables mixing of any number of images with a pixel accuracy that is a function of the combined transparency coefficient of the images.
'~09-91-084 18 Z~?~
The teaching of the invention also employs video look-up tables to enable a variety of mixing operations to occur in a multi-tasking environment, based on an application specific window identification number.
The invention also provides real-time pixel swi-tching and control on a pixel-by-pixel basis, for any number of independent image sources per window, using the WID
value.
While the invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that changes in form and details may be made therein wlthout departing from the scope and splrit of the invention.
Claims (18)
1. Image display apparatus, comprising:
a plurality of frame buffer means organized in a hierarchical manner so as to provide a highest priority frame buffer means and a plurality of lower priority frame buffer means, each of said frame buffer means storing image pixel data received from an associated image source;
means, coupled to an output of each of said frame buffer means, for converting a display format of the stored image pixel data to a predetermined display format; and means, having inputs coupled to individual ones of said converting means outputs, for selectively combining an image pixel from each of said plurality of frame buffer means so as to form a composite image pixel, wherein said combining means includes a plurality of means, individual ones of which are interposed between two hierarchically adjacent ones of said frame buffer means, for selectively generating an image pixel value and for providing the generated image pixel value to an input of a generating means at a next highest level, said generating means being responsive to a control means for selectively providing one of (a) an image pixel value that is equal to an image pixel value output by a first one of the hierarchically adjacent ones of the frame buffer means, (b) an image pixel value that is equal to an image pixel value output by a second one of the hierarchically adjacent ones of the frame buffer means, and (c) an image pixel value that is equal to a combination of the image pixel values output by each of the first and the second hierarchically adjacent ones of the frame buffer means, the combined image pixel value being a function of a pixel transparency value associated with a pixel from one of the hierarchically adjacent ones of the frame buffer means, wherein each of said generating means includes mixer means for mixing together, in accordance with a pixel transparency value provided by the associated frame buffer means, a pixel value from the associated frame buffer means and a pixel value received from a next lower priority level, and wherein said mixer means includes first means for subtracting the converted pixel value output by the associated frame buffer means from the pixel value received from the mixer means associated with the frame buffer means at the next lower priority level, second means for multiplying a difference value output by said first means times a transparency value associated with the pixel value output by the associated frame buffer means, and third means for adding a product value output by said second means to the pixel value received from the mixer means associated with the frame buffer means at the next lower priority level.
a plurality of frame buffer means organized in a hierarchical manner so as to provide a highest priority frame buffer means and a plurality of lower priority frame buffer means, each of said frame buffer means storing image pixel data received from an associated image source;
means, coupled to an output of each of said frame buffer means, for converting a display format of the stored image pixel data to a predetermined display format; and means, having inputs coupled to individual ones of said converting means outputs, for selectively combining an image pixel from each of said plurality of frame buffer means so as to form a composite image pixel, wherein said combining means includes a plurality of means, individual ones of which are interposed between two hierarchically adjacent ones of said frame buffer means, for selectively generating an image pixel value and for providing the generated image pixel value to an input of a generating means at a next highest level, said generating means being responsive to a control means for selectively providing one of (a) an image pixel value that is equal to an image pixel value output by a first one of the hierarchically adjacent ones of the frame buffer means, (b) an image pixel value that is equal to an image pixel value output by a second one of the hierarchically adjacent ones of the frame buffer means, and (c) an image pixel value that is equal to a combination of the image pixel values output by each of the first and the second hierarchically adjacent ones of the frame buffer means, the combined image pixel value being a function of a pixel transparency value associated with a pixel from one of the hierarchically adjacent ones of the frame buffer means, wherein each of said generating means includes mixer means for mixing together, in accordance with a pixel transparency value provided by the associated frame buffer means, a pixel value from the associated frame buffer means and a pixel value received from a next lower priority level, and wherein said mixer means includes first means for subtracting the converted pixel value output by the associated frame buffer means from the pixel value received from the mixer means associated with the frame buffer means at the next lower priority level, second means for multiplying a difference value output by said first means times a transparency value associated with the pixel value output by the associated frame buffer means, and third means for adding a product value output by said second means to the pixel value received from the mixer means associated with the frame buffer means at the next lower priority level.
2. Image display apparatus as set forth in claim 1 wherein each of said generating means further includes multiplexer means having a plurality of inputs, wherein one of said inputs is coupled to an output of said mixer means, one of said inputs is coupled to the output of the associated converting means, and one of said inputs is coupled to an output of the mixer means associated with the frame buffer means at the next priority level, said multiplexer means being responsive to a signal generated by said control means for selectively providing at an output a value corresponding to one of said three inputs.
3. Image display apparatus as set forth in claim 2 wherein said control means includes look-up table means for generating said control signal on a pixel-by-pixel basis in accordance with a pixel color code and a display means window identifier.
4. Image display apparatus as set forth in claim 3 wherein said pixel color code and said display screen window identifier are stored within one of said frame buffer means that is associated with said control means.
5. Image display apparatus as set forth in claim 4 wherein said frame buffer means that is associated with said control means is a highest priority frame buffer means.
6. Image display apparatus as set forth in claim 5 wherein the output of said multiplexer means, that is associated with said highest priority frame buffer means, is coupled to said display means.
7. Image display apparatus as set forth in claim 1 wherein at least one of said converting means is programmable and has an input coupled to control means for having data, representing the predetermined format, stored within under the control of the control means.
8. A method for generating video pixel data, comprising the steps of:
providing a plurality of frame buffer means organized in a hierarchical manner so as to provide a highest priority frame buffer means and a plurality of lower priority frame buffer means, each of said frame buffer means storing image pixel data from an associated image pixel source; and at each level of the hierarchy of frame buffer means other than a lowest level, selecting as an output of that level one of, a) a first image pixel value that is equal to an image pixel value that is output from the frame buffer means associated with that level, b) a second image pixel value that is output from the adjacent, lower level of the hierarchy of frame buffer means, and c) a third image pixel value that is a combination of the image pixel value that is output from the frame buffer means associated with that level and the image pixel value that is output from the adjacent, lower level of the hierarchy of frame buffer means, wherein the combination is made in accordance with a transparency value that is associated with the image pixel value that is output from the frame buffer means associated with that level, wherein the step of selecting the third image pixel value includes a step of mixing together, in accordance with the transparency value provided by the associated frame buffer means, a pixel value from the associated frame buffer means and a pixel value received from the adjacent, lower priority frame buffer means, and wherein the step of mixing together includes the steps of, subtracting the pixel value output by the associated frame buffer means from the pixel value received from the frame buffer means at the next lower priority level;
multiplying a difference value that results from the step of subtracting times the pixel transparency value associated with the pixel value output by the associated frame buffer means; and adding a product value that results from the step of multiplying to the pixel value received from the frame buffer means at the next lower priority level.
providing a plurality of frame buffer means organized in a hierarchical manner so as to provide a highest priority frame buffer means and a plurality of lower priority frame buffer means, each of said frame buffer means storing image pixel data from an associated image pixel source; and at each level of the hierarchy of frame buffer means other than a lowest level, selecting as an output of that level one of, a) a first image pixel value that is equal to an image pixel value that is output from the frame buffer means associated with that level, b) a second image pixel value that is output from the adjacent, lower level of the hierarchy of frame buffer means, and c) a third image pixel value that is a combination of the image pixel value that is output from the frame buffer means associated with that level and the image pixel value that is output from the adjacent, lower level of the hierarchy of frame buffer means, wherein the combination is made in accordance with a transparency value that is associated with the image pixel value that is output from the frame buffer means associated with that level, wherein the step of selecting the third image pixel value includes a step of mixing together, in accordance with the transparency value provided by the associated frame buffer means, a pixel value from the associated frame buffer means and a pixel value received from the adjacent, lower priority frame buffer means, and wherein the step of mixing together includes the steps of, subtracting the pixel value output by the associated frame buffer means from the pixel value received from the frame buffer means at the next lower priority level;
multiplying a difference value that results from the step of subtracting times the pixel transparency value associated with the pixel value output by the associated frame buffer means; and adding a product value that results from the step of multiplying to the pixel value received from the frame buffer means at the next lower priority level.
9. A method as set forth in claim 8 wherein the step of selecting is executed on a pixel-by-pixel basis for each image pixel stored within each of the frame buffer means.
10. A method as set forth in claim 8 wherein the step of selecting includes the steps of decoding a predetermined pixel color value in conjunction with a display window identifier so as to generate a plurality of control signals for controlling the selection of image pixel values.
11. A method as set forth in claim 10 wherein the predetermined pixel color value and the display window identifier are stored within a highest priority frame buffer means.
12. A method as set forth in claim 8 wherein the step of selecting includes a step of converting a display format of a stored image pixel data to a predetermined display format.
13. An integrated circuit device for processing image pixel data, said integrated circuit device comprising a first input port for coupling to an output of a first source of image pixel values, a second input port for coupling to an output of a second source of image pixel values, and a third input port for coupling to an output of a source of image pixel transparency values that are associated with the image pixel values output from the first source, said integrated circuit device further comprising means, responsive to a predetermined state of a control signal applied to a control input port, for selectively mixing together image pixel values received from said first input port and from said second input port, said means for selectively mixing comprising first means for subtracting an image pixel value received from the first input port from an image pixel value received from the second input port, second means for multiplying a difference value output from said first means times an image pixel transparency value received from the third input port, and third means for adding a product value output from said second means to the image pixel value received from the second input port, said integrated circuit device further comprising an output port, coupled to an output of said third means, for outputting a resultant image pixel value.
14. An integrated circuit device as set forth in claim 13 and further comprising means for delaying an image pixel value received from the second input port by an amount of time required for the operation of the first and second means, said delaying means having an output coupled to said third means for providing the delayed image pixel value thereto for adding to the product value that is output from said second means.
15. Image display apparatus, comprising:
a plurality of frame buffer means organized in a hierarchical manner so as to provide a highest priority frame buffer means and a plurality of lower priority frame buffer means, each of said frame buffer means storing image pixel data from an associated source; and means, interposed between hierarchically adjacent frame buffer means, for selecting an image pixel value and for providing the selected image pixel value to an input of another selecting means at a next highest level, said selecting means being responsive to control signals for selecting as an output at each level one of, a) an image pixel value that is equal to an image pixel that is output from the frame buffer means associated with that level, b) an image pixel value that is output from the adjacent, lower level of the hierarchy of frame buffer means, and c) an image pixel value that is a combination of the image pixel value that is output from the frame buffer means associated with that level and the image pixel value that is output from the adjacent, lower level of the hierarchy of frame buffer means, wherein the combination is made in accordance with a transparency value that is associated with the image pixel value that is output from the frame buffer means associated with that level, wherein said selecting means includes first means for subtracting the pixel value output by the associated frame buffer means from the pixel value received from the selecting means associated with the frame buffer means at the next lower priority level, second means for multiplying a difference value output by said first means times the transparency value associated with the pixel value output by the associated frame buffer means, and third means for adding a product value output by said second means to the pixel value received from the selecting means associated with the frame buffer means at the next lower priority level.
a plurality of frame buffer means organized in a hierarchical manner so as to provide a highest priority frame buffer means and a plurality of lower priority frame buffer means, each of said frame buffer means storing image pixel data from an associated source; and means, interposed between hierarchically adjacent frame buffer means, for selecting an image pixel value and for providing the selected image pixel value to an input of another selecting means at a next highest level, said selecting means being responsive to control signals for selecting as an output at each level one of, a) an image pixel value that is equal to an image pixel that is output from the frame buffer means associated with that level, b) an image pixel value that is output from the adjacent, lower level of the hierarchy of frame buffer means, and c) an image pixel value that is a combination of the image pixel value that is output from the frame buffer means associated with that level and the image pixel value that is output from the adjacent, lower level of the hierarchy of frame buffer means, wherein the combination is made in accordance with a transparency value that is associated with the image pixel value that is output from the frame buffer means associated with that level, wherein said selecting means includes first means for subtracting the pixel value output by the associated frame buffer means from the pixel value received from the selecting means associated with the frame buffer means at the next lower priority level, second means for multiplying a difference value output by said first means times the transparency value associated with the pixel value output by the associated frame buffer means, and third means for adding a product value output by said second means to the pixel value received from the selecting means associated with the frame buffer means at the next lower priority level.
16. Image display apparatus as set forth in claim 15 and further including means, coupled to an output of each of said plurality of frame buffer means, for converting a format of the stored image pixel data to a predetermined format.
17. Image display apparatus as set forth in claim 16 wherein the predetermined format is R,G,B.
18. Image display apparatus as set forth in claim 15 wherein said control signals are generated by control means that includes look-up table means for generating the control signals on a pixel-by-pixel basis in accordance with a pixel color code and a display means window identifier, wherein said pixel color code and said display screen window identifier are stored within one of said frame buffer means that is associated with said control means.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/733,766 | 1991-07-22 | ||
| US07/733,766 US5351067A (en) | 1991-07-22 | 1991-07-22 | Multi-source image real time mixing and anti-aliasing |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2068042A1 CA2068042A1 (en) | 1993-01-23 |
| CA2068042C true CA2068042C (en) | 1999-03-02 |
Family
ID=24949033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002068042A Expired - Fee Related CA2068042C (en) | 1991-07-22 | 1992-05-05 | Multi-source image real time mixing and anti-aliasing |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US5351067A (en) |
| EP (1) | EP0524461A3 (en) |
| JP (1) | JP2970216B2 (en) |
| KR (1) | KR960013369B1 (en) |
| CN (1) | CN1030813C (en) |
| CA (1) | CA2068042C (en) |
| SG (1) | SG43717A1 (en) |
Families Citing this family (116)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6336180B1 (en) | 1997-04-30 | 2002-01-01 | Canon Kabushiki Kaisha | Method, apparatus and system for managing virtual memory with virtual-physical mapping |
| US5585824A (en) * | 1991-07-22 | 1996-12-17 | Silicon Graphics, Inc. | Graphics memory apparatus and method |
| US20020091850A1 (en) | 1992-10-23 | 2002-07-11 | Cybex Corporation | System and method for remote monitoring and operation of personal computers |
| US5852444A (en) | 1992-12-07 | 1998-12-22 | Intel Corporation | Application of video to graphics weighting factor to video image YUV to RGB color code conversion |
| DE69315969T2 (en) | 1992-12-15 | 1998-07-30 | Sun Microsystems Inc | Presentation of information in a display system with transparent windows |
| US5621429A (en) * | 1993-03-16 | 1997-04-15 | Hitachi, Ltd. | Video data display controlling method and video data display processing system |
| US5638501A (en) * | 1993-05-10 | 1997-06-10 | Apple Computer, Inc. | Method and apparatus for displaying an overlay image |
| US5889499A (en) * | 1993-07-29 | 1999-03-30 | S3 Incorporated | System and method for the mixing of graphics and video signals |
| FR2721470B1 (en) * | 1994-06-16 | 1996-07-26 | Alcatel Business Systems | Apparatus with screen display device and arrangement allowing the display of images composed from one or more video streams. |
| US5731799A (en) * | 1994-06-17 | 1998-03-24 | Motorola Inc. | Pixel-wise video registration system |
| US5912656A (en) * | 1994-07-01 | 1999-06-15 | Ohmeda Inc. | Device for producing a display from monitored data |
| US5737455A (en) * | 1994-12-12 | 1998-04-07 | Xerox Corporation | Antialiasing with grey masking techniques |
| US6356275B1 (en) * | 1995-02-13 | 2002-03-12 | International Business Machines Corporation | Pixel color matching across X servers in network conferencing systems by master-participant pair mapping |
| US6160547A (en) * | 1995-10-12 | 2000-12-12 | Asc Audio Video Corporation | Shared video data storage system with separate video data and information buses |
| JP3995114B2 (en) * | 1995-10-30 | 2007-10-24 | アルパイン株式会社 | Switch image display method |
| US6023302A (en) * | 1996-03-07 | 2000-02-08 | Powertv, Inc. | Blending of video images in a home communications terminal |
| JPH09288477A (en) * | 1996-04-19 | 1997-11-04 | Mitsubishi Electric Corp | Picture display controller |
| AUPO648397A0 (en) | 1997-04-30 | 1997-05-22 | Canon Information Systems Research Australia Pty Ltd | Improvements in multiprocessor architecture operation |
| JP2845857B2 (en) * | 1997-04-01 | 1999-01-13 | コナミ株式会社 | Translucent display device for image, translucent display method, and machine-readable recording medium recording computer program |
| US6311258B1 (en) | 1997-04-03 | 2001-10-30 | Canon Kabushiki Kaisha | Data buffer apparatus and method for storing graphical data using data encoders and decoders |
| US6195674B1 (en) | 1997-04-30 | 2001-02-27 | Canon Kabushiki Kaisha | Fast DCT apparatus |
| US6707463B1 (en) | 1997-04-30 | 2004-03-16 | Canon Kabushiki Kaisha | Data normalization technique |
| US6289138B1 (en) | 1997-04-30 | 2001-09-11 | Canon Kabushiki Kaisha | General image processor |
| AUPO647997A0 (en) * | 1997-04-30 | 1997-05-22 | Canon Information Systems Research Australia Pty Ltd | Memory controller architecture |
| US6259456B1 (en) | 1997-04-30 | 2001-07-10 | Canon Kabushiki Kaisha | Data normalization techniques |
| US6038031A (en) * | 1997-07-28 | 2000-03-14 | 3Dlabs, Ltd | 3D graphics object copying with reduced edge artifacts |
| JPH1166271A (en) * | 1997-08-11 | 1999-03-09 | Sony Computer Entertainment:Kk | Method and device for image composition |
| US6002397A (en) * | 1997-09-30 | 1999-12-14 | International Business Machines Corporation | Window hatches in graphical user interface |
| WO2000017766A2 (en) | 1998-09-22 | 2000-03-30 | Cybex Computer Products Corporation | System for accessing personal computers remotely |
| US6977649B1 (en) | 1998-11-23 | 2005-12-20 | 3Dlabs, Inc. Ltd | 3D graphics rendering with selective read suspend |
| US20020122045A1 (en) * | 1998-12-19 | 2002-09-05 | Morgan Woodson | Font anti-aliasing system |
| JP3068590B1 (en) | 1999-02-18 | 2000-07-24 | 日本電気アイシーマイコンシステム株式会社 | Two-dimensional image processing device |
| JP3394473B2 (en) * | 1999-08-20 | 2003-04-07 | エヌイーシーマイクロシステム株式会社 | Graphics processing apparatus, method and recording medium |
| US6628291B1 (en) * | 1999-09-02 | 2003-09-30 | International Business Machines Corporation | Method and apparatus for display refresh using multiple frame buffers in a data processing system |
| US6727959B2 (en) * | 1999-11-22 | 2004-04-27 | Conexant Systems, Inc. | System of and method for gamma correction of real-time video |
| US6670970B1 (en) | 1999-12-20 | 2003-12-30 | Apple Computer, Inc. | Graduated visual and manipulative translucency for windows |
| AU2710201A (en) * | 2000-01-24 | 2001-07-31 | Matsushita Electric Industrial Co., Ltd. | Image composting apparatus, recording medium and program |
| KR100512138B1 (en) * | 2000-03-08 | 2005-09-02 | 엘지전자 주식회사 | Video Browsing System With Synthetic Key Frame |
| WO2001078005A2 (en) * | 2000-04-11 | 2001-10-18 | Cornell Research Foundation, Inc. | System and method for three-dimensional image rendering and analysis |
| JP4859154B2 (en) * | 2000-06-09 | 2012-01-25 | キヤノン株式会社 | Display control device, display control system, display control method, and storage medium |
| JP2002175068A (en) * | 2000-09-22 | 2002-06-21 | Canon Inc | System and method for image display, storage medium and image display device |
| US6829015B2 (en) * | 2001-01-19 | 2004-12-07 | Samsung Electronics Co., Ltd. | Device and method for realizing transparency in an on screen display |
| GB0109720D0 (en) | 2001-04-20 | 2001-06-13 | Koninkl Philips Electronics Nv | Display apparatus and image encoded for display by such an apparatus |
| US6705404B2 (en) * | 2001-09-10 | 2004-03-16 | Gordon F. Bosley | Open well plunger-actuated gas lift valve and method of use |
| WO2003024184A2 (en) * | 2001-09-14 | 2003-03-27 | Cornell Research Foundation, Inc. | System, method and apparatus for small pulmonary nodule computer aided diagnosis from computed tomography scans |
| US6728334B1 (en) | 2001-10-24 | 2004-04-27 | Cornell Research Foundation, Inc. | Automatic detection of pulmonary nodules on volumetric computed tomography images using a local density maximum algorithm |
| US9189467B1 (en) | 2001-11-07 | 2015-11-17 | Apple Inc. | Method and apparatus for annotating an electronic document |
| US20040015551A1 (en) * | 2002-07-18 | 2004-01-22 | Thornton Barry W. | System of co-located computers with content and/or communications distribution |
| US7265764B2 (en) * | 2002-08-27 | 2007-09-04 | Nvidia Corporation | System and method for providing a hardware icon with magnification and security |
| US7499578B2 (en) | 2002-10-18 | 2009-03-03 | Cornell Research Foundation, Inc. | System, method and apparatus for small pulmonary nodule computer aided diagnosis from computed tomography scans |
| US8737810B2 (en) | 2002-11-15 | 2014-05-27 | Thomson Licensing | Method and apparatus for cropping of subtitle elements |
| WO2004047430A1 (en) | 2002-11-15 | 2004-06-03 | Thomson Licensing S.A. | Method and apparatus for composition of subtitles |
| US20040131276A1 (en) * | 2002-12-23 | 2004-07-08 | John Hudson | Region-based image processor |
| US20040174379A1 (en) * | 2003-03-03 | 2004-09-09 | Collodi David J. | Method and system for real-time anti-aliasing |
| US8045770B2 (en) * | 2003-03-24 | 2011-10-25 | Cornell Research Foundation, Inc. | System and method for three-dimensional image rendering and analysis |
| US7242778B2 (en) | 2003-04-08 | 2007-07-10 | Gennum Corporation | Hearing instrument with self-diagnostics |
| WO2004093043A1 (en) * | 2003-04-15 | 2004-10-28 | Fujitsu Limited | Drawing device and display controller |
| US7596284B2 (en) * | 2003-07-16 | 2009-09-29 | Hewlett-Packard Development Company, L.P. | High resolution image reconstruction |
| US20050091279A1 (en) * | 2003-09-29 | 2005-04-28 | Rising Hawley K.Iii | Use of transform technology in construction of semantic descriptions |
| US7486337B2 (en) * | 2003-12-22 | 2009-02-03 | Intel Corporation | Controlling the overlay of multiple video signals |
| WO2005103877A1 (en) | 2004-04-22 | 2005-11-03 | Fujitsu Limited | Image processing device and graphics memory device |
| US7545389B2 (en) * | 2004-05-11 | 2009-06-09 | Microsoft Corporation | Encoding ClearType text for use on alpha blended textures |
| KR100469820B1 (en) | 2004-06-29 | 2005-02-03 | 엔에이치엔(주) | Method and system for renewing screen |
| WO2006030401A2 (en) * | 2004-09-16 | 2006-03-23 | Koninklijke Philips Electronics N.V. | Multi-layer video/graphics blending including identifying composited non-transparent regions in the alpha multiplied overlay |
| US8631342B2 (en) * | 2004-12-22 | 2014-01-14 | Hewlett-Packard Development Company, L.P. | Computer display control system and method |
| US20060168537A1 (en) * | 2004-12-22 | 2006-07-27 | Hochmuth Roland M | Computer display control system and method |
| US20060171602A1 (en) * | 2005-01-31 | 2006-08-03 | International Business Machines Corporation | Method and system for using a look-up table for a linear operation in image processing |
| US20060184893A1 (en) * | 2005-02-17 | 2006-08-17 | Raymond Chow | Graphics controller providing for enhanced control of window animation |
| US7400328B1 (en) | 2005-02-18 | 2008-07-15 | Neomagic Corp. | Complex-shaped video overlay using multi-bit row and column index registers |
| US8731069B2 (en) * | 2005-08-25 | 2014-05-20 | Canon Kabushiki Kaisha | Remote display system and method |
| JP4593406B2 (en) * | 2005-09-05 | 2010-12-08 | Ｎｅｃパーソナルプロダクツ株式会社 | Computer |
| CN101496387B (en) | 2006-03-06 | 2012-09-05 | 思科技术公司 | System and method for access authentication in a mobile wireless network |
| CN100379264C (en) * | 2006-04-30 | 2008-04-02 | 北京中星微电子有限公司 | Displaying screen controller and and method for refreshing display screen |
| KR100744937B1 (en) | 2006-06-29 | 2007-08-01 | 삼성전기주식회사 | Lens distortion correction method |
| JP5033475B2 (en) * | 2006-10-09 | 2012-09-26 | 三星電子株式会社 | Liquid crystal display device and driving method thereof |
| KR100884400B1 (en) * | 2007-01-23 | 2009-02-17 | 삼성전자주식회사 | Image process apparatus and method thereof |
| EP1968311A1 (en) * | 2007-03-07 | 2008-09-10 | Telefonaktiebolaget LM Ericsson (publ) | Display controller,electronic apparatus and method for creating a translucency effect using color model transform |
| US8749575B2 (en) * | 2007-03-07 | 2014-06-10 | Telefonaktiebolaget L M Ericssson (Publ) | Display controller, electronic apparatus and method for creating a translucency effect using color model transform |
| WO2008124397A1 (en) | 2007-04-03 | 2008-10-16 | David Fishbaine | Inspection system and method |
| JP4780101B2 (en) * | 2007-12-26 | 2011-09-28 | 日本電気株式会社 | Image display system, image display method, and program |
| JP5045428B2 (en) * | 2007-12-26 | 2012-10-10 | 日本電気株式会社 | Image display system, image display method, and program |
| US8797377B2 (en) | 2008-02-14 | 2014-08-05 | Cisco Technology, Inc. | Method and system for videoconference configuration |
| WO2009114647A1 (en) * | 2008-03-11 | 2009-09-17 | Robe Lighting Inc | A universal color control matrix |
| US8694658B2 (en) | 2008-09-19 | 2014-04-08 | Cisco Technology, Inc. | System and method for enabling communication sessions in a network environment |
| US8659637B2 (en) | 2009-03-09 | 2014-02-25 | Cisco Technology, Inc. | System and method for providing three dimensional video conferencing in a network environment |
| US8659639B2 (en) | 2009-05-29 | 2014-02-25 | Cisco Technology, Inc. | System and method for extending communications between participants in a conferencing environment |
| US9082297B2 (en) | 2009-08-11 | 2015-07-14 | Cisco Technology, Inc. | System and method for verifying parameters in an audiovisual environment |
| US9225916B2 (en) | 2010-03-18 | 2015-12-29 | Cisco Technology, Inc. | System and method for enhancing video images in a conferencing environment |
| US9313452B2 (en) | 2010-05-17 | 2016-04-12 | Cisco Technology, Inc. | System and method for providing retracting optics in a video conferencing environment |
| US9092128B2 (en) | 2010-05-21 | 2015-07-28 | Apple Inc. | Method and apparatus for managing visual information |
| US8896655B2 (en) | 2010-08-31 | 2014-11-25 | Cisco Technology, Inc. | System and method for providing depth adaptive video conferencing |
| US8599934B2 (en) | 2010-09-08 | 2013-12-03 | Cisco Technology, Inc. | System and method for skip coding during video conferencing in a network environment |
| US8599865B2 (en) | 2010-10-26 | 2013-12-03 | Cisco Technology, Inc. | System and method for provisioning flows in a mobile network environment |
| US8699457B2 (en) | 2010-11-03 | 2014-04-15 | Cisco Technology, Inc. | System and method for managing flows in a mobile network environment |
| US8902244B2 (en) | 2010-11-15 | 2014-12-02 | Cisco Technology, Inc. | System and method for providing enhanced graphics in a video environment |
| US9338394B2 (en) | 2010-11-15 | 2016-05-10 | Cisco Technology, Inc. | System and method for providing enhanced audio in a video environment |
| US9143725B2 (en) | 2010-11-15 | 2015-09-22 | Cisco Technology, Inc. | System and method for providing enhanced graphics in a video environment |
| US8730297B2 (en) | 2010-11-15 | 2014-05-20 | Cisco Technology, Inc. | System and method for providing camera functions in a video environment |
| US8542264B2 (en) | 2010-11-18 | 2013-09-24 | Cisco Technology, Inc. | System and method for managing optics in a video environment |
| US8723914B2 (en) | 2010-11-19 | 2014-05-13 | Cisco Technology, Inc. | System and method for providing enhanced video processing in a network environment |
| US9111138B2 (en) | 2010-11-30 | 2015-08-18 | Cisco Technology, Inc. | System and method for gesture interface control |
| US8692862B2 (en) | 2011-02-28 | 2014-04-08 | Cisco Technology, Inc. | System and method for selection of video data in a video conference environment |
| US8670019B2 (en) | 2011-04-28 | 2014-03-11 | Cisco Technology, Inc. | System and method for providing enhanced eye gaze in a video conferencing environment |
| US8786631B1 (en) * | 2011-04-30 | 2014-07-22 | Cisco Technology, Inc. | System and method for transferring transparency information in a video environment |
| US8934026B2 (en) | 2011-05-12 | 2015-01-13 | Cisco Technology, Inc. | System and method for video coding in a dynamic environment |
| CN102752519B (en) * | 2011-05-17 | 2017-04-12 | 新奥特（北京）视频技术有限公司 | Graph picture mixed processing method in two-dimensional and three-dimensional environments |
| DE112011105323T5 (en) * | 2011-06-10 | 2014-02-27 | Mitsubishi Electric Corporation | Window combining device |
| US8947493B2 (en) | 2011-11-16 | 2015-02-03 | Cisco Technology, Inc. | System and method for alerting a participant in a video conference |
| US8682087B2 (en) | 2011-12-19 | 2014-03-25 | Cisco Technology, Inc. | System and method for depth-guided image filtering in a video conference environment |
| US9148699B2 (en) * | 2012-06-01 | 2015-09-29 | Texas Instruments Incorporated | Optimized algorithm for construction of composite video from a set of discrete video sources |
| US9681154B2 (en) | 2012-12-06 | 2017-06-13 | Patent Capital Group | System and method for depth-guided filtering in a video conference environment |
| TWI524733B (en) * | 2013-02-07 | 2016-03-01 | 晨星半導體股份有限公司 | Image access method and image access device |
| US9843621B2 (en) | 2013-05-17 | 2017-12-12 | Cisco Technology, Inc. | Calendaring activities based on communication processing |
| US9967476B2 (en) * | 2014-10-17 | 2018-05-08 | Ross Video Limited | Parallel video effects, mix trees, and related methods |
| US20160112723A1 (en) * | 2014-10-17 | 2016-04-21 | Ross Video Limited | Transfer of video and related data over serial data interface (sdi) links |
| CN111402380B (en) * | 2020-03-12 | 2023-06-30 | 杭州小影创新科技股份有限公司 | GPU compressed texture processing method |
Family Cites Families (41)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4357624A (en) * | 1979-05-15 | 1982-11-02 | Combined Logic Company | Interactive video production system |
| US4599611A (en) * | 1982-06-02 | 1986-07-08 | Digital Equipment Corporation | Interactive computer-based information display system |
| US4691295A (en) * | 1983-02-28 | 1987-09-01 | Data General Corporation | System for storing and retreiving display information in a plurality of memory planes |
| IL72685A (en) * | 1983-08-30 | 1988-08-31 | Gen Electric | Advanced video object generator |
| US4653020A (en) * | 1983-10-17 | 1987-03-24 | International Business Machines Corporation | Display of multiple data windows in a multi-tasking system |
| JPS60220387A (en) * | 1984-04-13 | 1985-11-05 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Raster scan display unit |
| US4758892A (en) * | 1984-04-27 | 1988-07-19 | Ampex Corporation | System for producing a video combine from multiple video images |
| JPS61109174A (en) * | 1984-10-31 | 1986-05-27 | Toshiba Corp | Picture processor |
| JPS61188582A (en) * | 1985-02-18 | 1986-08-22 | 三菱電機株式会社 | Multi-window writing controller |
| JPS61210395A (en) * | 1985-03-14 | 1986-09-18 | ソニー株式会社 | Image processor |
| US4742474A (en) * | 1985-04-05 | 1988-05-03 | Tektronix, Inc. | Variable access frame buffer memory |
| US4684990A (en) * | 1985-04-12 | 1987-08-04 | Ampex Corporation | Method and apparatus for combining multiple video images in three dimensions |
| US4717951A (en) * | 1985-10-31 | 1988-01-05 | Rca Corporation | Adaptive digital filter |
| US4692880A (en) * | 1985-11-15 | 1987-09-08 | General Electric Company | Memory efficient cell texturing for advanced video object generator |
| CA1309768C (en) * | 1986-03-06 | 1992-11-03 | Richard A. Jackson | Apparatus for combining video signals |
| US4772881A (en) * | 1986-10-27 | 1988-09-20 | Silicon Graphics, Inc. | Pixel mapping apparatus for color graphics display |
| JPS63114472A (en) * | 1986-10-31 | 1988-05-19 | Victor Co Of Japan Ltd | Picture processor |
| JPS6378478U (en) * | 1986-11-10 | 1988-05-24 | ||
| JPS63188191A (en) * | 1987-01-31 | 1988-08-03 | 株式会社東芝 | Multiple color pallet control circuit |
| JPH0636183B2 (en) * | 1987-04-27 | 1994-05-11 | 横河メディカルシステム株式会社 | Multiple image display device |
| US4954819A (en) * | 1987-06-29 | 1990-09-04 | Evans & Sutherland Computer Corp. | Computer graphics windowing system for the display of multiple dynamic images |
| US4857901A (en) * | 1987-07-24 | 1989-08-15 | Apollo Computer, Inc. | Display controller utilizing attribute bits |
| GB2210540A (en) * | 1987-09-30 | 1989-06-07 | Philips Electronic Associated | Method of and arrangement for modifying stored data,and method of and arrangement for generating two-dimensional images |
| JPH01205688A (en) * | 1988-02-10 | 1989-08-18 | Nec Corp | Television receiver |
| US5128658A (en) * | 1988-06-27 | 1992-07-07 | Digital Equipment Corporation | Pixel data formatting |
| US5001469A (en) * | 1988-06-29 | 1991-03-19 | Digital Equipment Corporation | Window-dependent buffer selection |
| US4951229A (en) * | 1988-07-22 | 1990-08-21 | International Business Machines Corporation | Apparatus and method for managing multiple images in a graphic display system |
| US5065231A (en) * | 1988-09-26 | 1991-11-12 | Apple Computer, Inc. | Apparatus and method for merging input RGB and composite video signals to provide both RGB and composite merged video outputs |
| US4956640A (en) * | 1988-11-28 | 1990-09-11 | Hewlett-Packard Company | Method and apparatus for controlling video display priority |
| JPH02163793A (en) * | 1988-12-16 | 1990-06-25 | Matsushita Electric Ind Co Ltd | Graphics display device |
| DE3842978C2 (en) * | 1988-12-21 | 1996-04-11 | Broadcast Television Syst | Mixing device for video signals |
| JP2502728B2 (en) * | 1989-02-13 | 1996-05-29 | 松下電器産業株式会社 | Video data processor |
| US4994912A (en) * | 1989-02-23 | 1991-02-19 | International Business Machines Corporation | Audio video interactive display |
| JPH02285393A (en) * | 1989-04-26 | 1990-11-22 | Matsushita Electric Ind Co Ltd | Parallel type multiple motion image display device |
| JPH03105388A (en) * | 1989-09-19 | 1991-05-02 | Matsushita Electric Ind Co Ltd | Frame buffer for work station |
| US5220312A (en) * | 1989-09-29 | 1993-06-15 | International Business Machines Corporation | Pixel protection mechanism for mixed graphics/video display adaptors |
| GB2238214A (en) * | 1989-10-13 | 1991-05-22 | Quantel Ltd | Electronic graphic system combines images using variable density stencil |
| JPH03154577A (en) * | 1989-11-13 | 1991-07-02 | Fujitsu Ltd | Weighted mean processing circuit |
| US5185858A (en) * | 1989-12-01 | 1993-02-09 | Megatek Corporation | Image priority video switch |
| US5140315A (en) * | 1990-04-16 | 1992-08-18 | Analog Devices, Inc. | Antialiased pixel based display system for lines and solids |
| US5124688A (en) * | 1990-05-07 | 1992-06-23 | Mass Microsystems | Method and apparatus for converting digital YUV video signals to RGB video signals |
-
1991
- 1991-07-22 US US07/733,766 patent/US5351067A/en not_active Expired - Lifetime
-
1992
- 1992-05-05 CA CA002068042A patent/CA2068042C/en not_active Expired - Fee Related
- 1992-05-29 JP JP4138572A patent/JP2970216B2/en not_active Expired - Lifetime
- 1992-06-22 KR KR1019920010808A patent/KR960013369B1/en not_active IP Right Cessation
- 1992-06-22 CN CN92104921A patent/CN1030813C/en not_active Expired - Fee Related
- 1992-07-02 SG SG1996000134A patent/SG43717A1/en unknown
- 1992-07-02 EP EP19920111173 patent/EP0524461A3/en not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| KR960013369B1 (en) | 1996-10-04 |
| SG43717A1 (en) | 1997-11-14 |
| KR930002933A (en) | 1993-02-23 |
| EP0524461A3 (en) | 1993-09-01 |
| CN1030813C (en) | 1996-01-24 |
| US5351067A (en) | 1994-09-27 |
| JPH05225328A (en) | 1993-09-03 |
| JP2970216B2 (en) | 1999-11-02 |
| EP0524461A2 (en) | 1993-01-27 |
| CN1068926A (en) | 1993-02-10 |
| CA2068042A1 (en) | 1993-01-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA2068042C (en) | Multi-source image real time mixing and anti-aliasing | |
| US6466224B1 (en) | Image data composition and display apparatus | |
| US5260695A (en) | Color map image fader for graphics window subsystem | |
| US5577203A (en) | Video processing methods | |
| US4827253A (en) | Video compositing using a software linear keyer | |
| CA1250379A (en) | Method and apparatus for providing anti-aliased edges in pixel-mapped computer graphics | |
| US5572235A (en) | Method and apparatus for processing image data | |
| US5243447A (en) | Enhanced single frame buffer display system | |
| US5227863A (en) | Programmable digital video processing system | |
| US5473342A (en) | Method and apparatus for on-the-fly multiple display mode switching in high-resolution bitmapped graphics system | |
| CA1229441A (en) | Color-signal converting circuit | |
| AU640496B2 (en) | A graphics engine for true colour 2d graphics | |
| US5404447A (en) | Apparatus for manipulating image pixel streams to generate an output image pixel stream in response to a selected mode | |
| US5966116A (en) | Method and logic system for the rotation of raster-scan display images | |
| US5923316A (en) | Optimized color space conversion | |
| KR19990087566A (en) | Mixing Video Images at Home Communication Terminals | |
| US5140315A (en) | Antialiased pixel based display system for lines and solids | |
| JPH05204373A (en) | High precision multimedia-display | |
| JP2001169181A (en) | Video magnifying device | |
| JPH01310432A (en) | Display system | |
| US5450098A (en) | Tri-dimensional visual model | |
| CA1326536C (en) | Method and apparatus for generating video signals | |
| GB2153638A (en) | Method and apparatus for assigning color values to bit map memory display locations | |
| US5606652A (en) | Real-time processing system for animation images to be displayed on high definition television systems | |
| JPH03500692A (en) | video display system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed | ||
| MKLA | Lapsed |
Effective date: 20050505 |