CA2068867A1 - Clock dejitter circuits for regenerating jittered clock signals - Google Patents

Clock dejitter circuits for regenerating jittered clock signals

Info

Publication number
CA2068867A1
CA2068867A1 CA2068867A CA2068867A CA2068867A1 CA 2068867 A1 CA2068867 A1 CA 2068867A1 CA 2068867 A CA2068867 A CA 2068867A CA 2068867 A CA2068867 A CA 2068867A CA 2068867 A1 CA2068867 A1 CA 2068867A1
Authority
CA
Canada
Prior art keywords
divide
circuits
value
clock
jittered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2068867A
Other languages
French (fr)
Other versions
CA2068867C (en
Inventor
Daniel C. Upp
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Transwitch Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2068867A1 publication Critical patent/CA2068867A1/en
Application granted granted Critical
Publication of CA2068867C publication Critical patent/CA2068867C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06—Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/061—Adapt frequency, i.e. clock frequency at one side is adapted to clock frequency, or average clock frequency, at the other side; Not pulse stuffing only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/12—Indexing scheme relating to groups G06F5/12 - G06F5/14
    • G06F2205/123—Contention resolution, i.e. resolving conflicts between simultaneous read and write operations

Abstract

Clock dejitter circuits are provided and comprise control circuits (30) for generating a plurality of pulses over a clock cycle, and clock circuits (60) for tracking the speeds of jittered incoming data signal arid based on those speeds, and utilizing the plurality of pulses, generating substantially unjittered data signals at the nominal rates of the jittered. incoming signals. A control circuit (30) broadly includes a divide by value x-divide by value x + I circuit (42) which receives a fast input clock signal, a modules y counter (46), and a count decode (52) for providing z control pulses over the count of y, and a logic gate (56) for taking the outputs from the count decode (52) and controlling the divide block (42) to guarantee that the divide block (42) divides the fast input clock signal by value x q.times for every r times the divide. block (42) divides the fast input clock signal by value x + i ; wherein q plus r equals y, and z equals either q+ I or r+ I.
CA002068867A 1989-11-17 1990-11-16 Clock dejitter circuits for regenerating jittered clock signals Expired - Fee Related CA2068867C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US439,097 1989-11-17
US07/439,097 US5033064A (en) 1988-12-09 1989-11-17 Clock dejitter circuit for regenerating DS1 signal
PCT/US1990/006742 WO1991007830A1 (en) 1989-11-17 1990-11-16 Clock dejitter circuits for regenerating jittered clock signals

Publications (2)

Publication Number Publication Date
CA2068867A1 true CA2068867A1 (en) 1991-05-18
CA2068867C CA2068867C (en) 2000-04-11

Family

ID=23743279

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002068867A Expired - Fee Related CA2068867C (en) 1989-11-17 1990-11-16 Clock dejitter circuits for regenerating jittered clock signals

Country Status (6)

Country Link
US (2) US5033064A (en)
EP (1) EP0579595B1 (en)
JP (1) JPH05503195A (en)
CA (1) CA2068867C (en)
DE (1) DE69034026T2 (en)
WO (1) WO1991007830A1 (en)

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US5297180A (en) * 1989-11-17 1994-03-22 Transwitch Corporation Digital clock dejitter circuits for regenerating clock signals with minimal jitter
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GB9024084D0 (en) * 1990-11-06 1990-12-19 Int Computers Ltd First-in-first-out buffer
JP2723699B2 (en) 1991-07-31 1998-03-09 日本電気株式会社 TU-3 pointer replacement processing method
US5691976A (en) * 1992-04-02 1997-11-25 Applied Digital Access Performance monitoring and test system for a telephone network
JP2888022B2 (en) * 1992-04-02 1999-05-10 三菱電機株式会社 Communication control device
DE4238090C1 (en) * 1992-11-11 1994-03-03 Siemens Ag Method and arrangement for recovering plesiochronous signals transmitted in function data blocks
US5784377A (en) 1993-03-09 1998-07-21 Hubbell Incorporated Integrated digital loop carrier system with virtual tributary mapper circuit
US5367534A (en) * 1993-06-16 1994-11-22 Universal Data Systems, Inc. Synchronous flow control method
ES2102938B1 (en) * 1994-03-28 1998-04-16 Alcatel Standard Electrica PHASE FLUCTUATION REDUCTION SYSTEM IN DIGITAL DEMULTIPLEXERS.
DE4412060C1 (en) * 1994-04-07 1995-02-23 Siemens Ag Arrangement for recovering a plesiochronous digital signal
US5548534A (en) * 1994-07-08 1996-08-20 Transwitch Corporation Two stage clock dejitter circuit for regenerating an E4 telecommunications signal from the data component of an STS-3C signal
ATE281032T1 (en) * 1996-01-12 2004-11-15 Koninkl Philips Electronics Nv TRANSMITTER AND METHOD FOR TRANSMITTING A BROADBAND DIGITAL INFORMATION SIGNAL
US6064706A (en) * 1996-05-01 2000-05-16 Alcatel Usa, Inc. Apparatus and method of desynchronizing synchronously mapped asynchronous data
CN1061193C (en) * 1996-09-13 2001-01-24 清华大学 Method and device for double self-following frequency prediction to restore end branch clock
US6205182B1 (en) * 1998-02-25 2001-03-20 Cisco Technology, Inc. Encoding a clock signal and a data signal into a single signal for distribution in a signal forwarding device
US6647502B1 (en) * 1999-07-13 2003-11-11 Sony Corporation Method and apparatus for providing power based on the amount of data stored in buffers
US6356550B1 (en) 1999-07-30 2002-03-12 Mayan Networks Corporation Flexible time division multiplexed bus using sonet formatting
CN1307406A (en) 2000-01-27 2001-08-08 华为技术有限公司 Filtering method of digital phase lock loop
US6577651B2 (en) * 2001-01-24 2003-06-10 Transwitch Corp. Methods and apparatus for retiming and realigning sonet signals
US6463111B1 (en) 2001-05-25 2002-10-08 Transwitch Corporaton Method and apparatus for desynchronizing a DS-3 signal and/or an E3 signal from the data portion of an STS-STM payload
CN1330095C (en) * 2003-04-14 2007-08-01 中兴通讯股份有限公司 Single crystal vibrator digital phase-locked loop device realizing E1T1 debouncing
US7349444B2 (en) * 2004-08-23 2008-03-25 Transwitch Corporation SONET/SDH SPE/virtual container retiming with adaptive dual pointer leak rate computation
CN104219015B (en) 2013-06-03 2018-05-25 中兴通讯股份有限公司 The clock and data recovery method and device of tributary signal in a kind of SDH

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Also Published As

Publication number Publication date
EP0579595A1 (en) 1994-01-26
EP0579595A4 (en) 1993-01-22
DE69034026D1 (en) 2003-01-23
US5289507A (en) 1994-02-22
CA2068867C (en) 2000-04-11
WO1991007830A1 (en) 1991-05-30
US5033064A (en) 1991-07-16
JPH05503195A (en) 1993-05-27
EP0579595B1 (en) 2002-12-11
DE69034026T2 (en) 2003-09-25

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