CA2069658C - Active intelligent termination - Google Patents
Active intelligent terminationInfo
- Publication number
- CA2069658C CA2069658C CA002069658A CA2069658A CA2069658C CA 2069658 C CA2069658 C CA 2069658C CA 002069658 A CA002069658 A CA 002069658A CA 2069658 A CA2069658 A CA 2069658A CA 2069658 C CA2069658 C CA 2069658C
- Authority
- CA
- Canada
- Prior art keywords
- signals
- gate
- transmission line
- terminal
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
Abstract
An active intelligent termination circuit is designed to function as a self-switching clamp adapted to attenuate unwanted signals on a data bus. A field effect transistor is switched on or off in a conducting mode or non-conducting mode respectively in accordance with the data transmitted on the data bus. Any low level unwanted signals which may appear on the bus when data having a voltage level corresponding to a logic zero is present will be attenuated by the field effect transistor which is coupled to both the data bus and to a ground plane. The field effect transistor switches to the non-conducting mode when data corresponding to a logic level one is transmitted on the bus.
Description
'.~.
Active Intelligent Termination Field of the Invention The invention relates generally to a circuit and method for attenuating unwanted signals on a transmission line.
Background of the Invention During the transmission of a signal on a transmission line, signal energy is transferred most efficiently when no reflected wave is present. Thus to obtain a transmission of energy with a maximum efficiency, it ;s necessary to provide means for matching any actual load impedance to the characteristic impedance of the transmission line.
However, only under exceptional cases will the load impedance be a 15 resistance that is exactly equal to the characteristic impedance of the line. In many instances a load can be matched to the characteristic impedance of a line by coupling to the load a network of reactances that tunes out the network and load reactance and simultaneously transforms to a value equal to the characteristic impedance of the line; in other 20 instances where the actual load or number of loads on a line may be variable or not precisely known, active termination circuits may be used.
United States Patent number 4,748,426 issued May 31, 1988 in the name of Alexander Stewart discloses an active termination circuit having 25 a resistor combination permanently connected to a bus that couples a plurality of peripheral devices to one another. Other ends of the resistors are coupled to a positive voltage supply line and to a logic ground plane, respectively. Stewart teaches active impedance matching by on/off control of switches which open or close paths to the 30 resistors.
Computer systems and telecommunication ystems often have a plurality of source and destination nodes connected to and sharing a common data transmission facility such as a bus. These nodes may simply be receivers and transceivers located on circuit packs electrically 5 coupled to the bus. Such systems are often designed to be flexible, permitting variable configurations; the capability is therefore provided for an operator to add or remove circuit packs according to the particular requirements. In a system having loads which vary from time to time according to the configuration of circuit packs connected to the 10 bus, it may be difficult to provide adequate terminations to eliminate unwanted signal reflections. In addition, in systems where any particular node may transmit data to one of many possible receiver nodes and the distance between the respective nodes is variable, it is difficult to predict and provide the form of termination that will be 15 required.
In an attempt to overcome some of the aforementioned limitations it is an object of the invention to provide a circuit for attenuating unwanted signals.
The invention provides an active self~switching clamp which is 20 adapted to attenuate unwanted signals having a voltage level which varies from a logic zero level by a small increment.
Summary of the Invention In accordance with the invention there is provided a circuit for 25 attenuating unwanted signals on a transmission line adapted to carry data signals comprising: a controllable transmission gate operable in a first mode for conducting unwanted current from the transmission gate to a voltage reference terminal in response to unwanted signals on the transmission line and operable in a second mcde for preventing the conduction of current from the transmission line to the terminal, the gate having a first terminal connected to the transmission line a second terminal connected to the voltage reference terminal and a control terminal, and a control circuit means for releasing the transmission gate from conducting in the first mode in response to a clock signal and to the data signals on the transmission line, said control circuit means being coupled to the transmission line via an inverter gate and having its output connected to the control terminal of the controllable transmission gate.
Description of the Drawings The invention will be described in conjunction with the drawings 0 in which:
Figure 1 is a schematic diagram of a bus including a plurality of receivers and transmitters coupled to termination circuits;
Figure 2 is circuit diagram of an embodiment of the termination circuit of figure 1, having self-switching capability; and Figure 3 is a circuit diagram of an alternative embodiment of the invention for use with a tri-stateable bus.
In figure 1 a bus 10 is connected to a plurality of transceivers 13. Each transceiver 13 is coupled to a termination circuit 11. It will be understood that an arbitration scheme may be implemented to 20 prevent bus contention and that a transceiver 13 is capable of broadcasting over the bus 10 to more than 1 transceiver 13.
Figure 2 shows the bus 10 connected to the termination circuit 11 which includes a resistor 12, an inverter 14, and an n-channel field effect transistor (NFET) 16. The resistor 12 is an off-the-shelf 25 termination resistor having predetermined resistance. Both the NFET 16 and the resistor 12 are coupled to a ground plane having a voltage corresponding to a logic zero value or zero volts. As a form of ~..
illustration, a portion of a digital signal having a hi to lo transition is shown having superimposed thereon an unwanted alternating signal. It is desirable to eliminate unwanted signals, caused by reflection, noise, or the like which may not totally be absorbed by conventional s termination means such as the termination resistor 12. If the magnitude of any reflected signals becomes too great, transmitted data may become corrupted. For example, if a zero bit is being transmitted, and the unwanted signal reaches a voltage level near the threshold level associated with switching from one logic state to another, the transmitted zero bit may be perceived as a one-bit.
In the preferred embodiment shown in figure 3, a flip-flop 20 is coupled to an inverter 14 and to an AND gate 22 having inverted input terminals. An NFET 16 is similarly configured as in figure 2 having the source and drain connected to the bus 10 and to a ground plane 15 respectively. The circuit shown in figure 3 is suitable for use on a tristatable bus. The flip-flop 20 allows the NFET 16 to switch on and conduct thereby eliminating most of any unwanted signals, and releases the clamp after the data on the bus has been latched. A detailed description of the operation of the circuit will follow.
With reference to figure 2, the termination circuit 11 provides a means of self-switching and clamping unwanted spurious reflected signals which otherwise may be perceived as one-bits instead of transmitted zero-bits. The NFET 16 performs the function of clamping when switched on, in a conducting mode. In the instance that a one-bit followed by a 25 zero-bit is transmitted as is illustrated by the waveform in figure 2, the zero-bit received at the input terminal of the inverter 14 results in a one-bit at its output terminal. This one-bit corresponding to a digital hi voltage level switches on the gate of the NFET 16 thereby providing a path to ground. In the instance that a one-bit is presented 30 to the input terminal of the inverter 14, a resulting zero-bit corresponding to approximately zero volts switches off the NFET 16 preventing it from conducting and isolating the bus 10 from the ground plane. It should be obvious to a person skilled in the art that the transceivers 13 must be adequately powered to provide enough current to allow the NFET 16 to switch off. More specifically, the transceivers must supply enough current to overpower a switched on conducting NFET to allow the NFET to switch off.
In the preferred embodiment shown in figure 3, as data on the bus 5 10 changes from a one to a zero the NFET 16 switches on and conducts thereby reducing unwanted signals by providing a path to ground. One clock cycle later the zero-bit of data is inverted and is clocked through the flip-flop and the clamp is released, the NFET switching off and not conducting. If the data on the bus 10 changes from a zero to a 1, the clamp remains released and the NFET does not conduct. In the event that the bus becomes tristated, a pull-up resistor 24 provides a voltage corresponding to a logic hi, and the NFET remains switched off and in the non-conducting mode of operation. The flip-flop 20 and the AND gate 22 essentially provide a means of releasing the clamp one clock 15 cycle after the data has been available on the bus 10.
Numerous modifications and variations may be considered without departing from the scope of the invention.
Active Intelligent Termination Field of the Invention The invention relates generally to a circuit and method for attenuating unwanted signals on a transmission line.
Background of the Invention During the transmission of a signal on a transmission line, signal energy is transferred most efficiently when no reflected wave is present. Thus to obtain a transmission of energy with a maximum efficiency, it ;s necessary to provide means for matching any actual load impedance to the characteristic impedance of the transmission line.
However, only under exceptional cases will the load impedance be a 15 resistance that is exactly equal to the characteristic impedance of the line. In many instances a load can be matched to the characteristic impedance of a line by coupling to the load a network of reactances that tunes out the network and load reactance and simultaneously transforms to a value equal to the characteristic impedance of the line; in other 20 instances where the actual load or number of loads on a line may be variable or not precisely known, active termination circuits may be used.
United States Patent number 4,748,426 issued May 31, 1988 in the name of Alexander Stewart discloses an active termination circuit having 25 a resistor combination permanently connected to a bus that couples a plurality of peripheral devices to one another. Other ends of the resistors are coupled to a positive voltage supply line and to a logic ground plane, respectively. Stewart teaches active impedance matching by on/off control of switches which open or close paths to the 30 resistors.
Computer systems and telecommunication ystems often have a plurality of source and destination nodes connected to and sharing a common data transmission facility such as a bus. These nodes may simply be receivers and transceivers located on circuit packs electrically 5 coupled to the bus. Such systems are often designed to be flexible, permitting variable configurations; the capability is therefore provided for an operator to add or remove circuit packs according to the particular requirements. In a system having loads which vary from time to time according to the configuration of circuit packs connected to the 10 bus, it may be difficult to provide adequate terminations to eliminate unwanted signal reflections. In addition, in systems where any particular node may transmit data to one of many possible receiver nodes and the distance between the respective nodes is variable, it is difficult to predict and provide the form of termination that will be 15 required.
In an attempt to overcome some of the aforementioned limitations it is an object of the invention to provide a circuit for attenuating unwanted signals.
The invention provides an active self~switching clamp which is 20 adapted to attenuate unwanted signals having a voltage level which varies from a logic zero level by a small increment.
Summary of the Invention In accordance with the invention there is provided a circuit for 25 attenuating unwanted signals on a transmission line adapted to carry data signals comprising: a controllable transmission gate operable in a first mode for conducting unwanted current from the transmission gate to a voltage reference terminal in response to unwanted signals on the transmission line and operable in a second mcde for preventing the conduction of current from the transmission line to the terminal, the gate having a first terminal connected to the transmission line a second terminal connected to the voltage reference terminal and a control terminal, and a control circuit means for releasing the transmission gate from conducting in the first mode in response to a clock signal and to the data signals on the transmission line, said control circuit means being coupled to the transmission line via an inverter gate and having its output connected to the control terminal of the controllable transmission gate.
Description of the Drawings The invention will be described in conjunction with the drawings 0 in which:
Figure 1 is a schematic diagram of a bus including a plurality of receivers and transmitters coupled to termination circuits;
Figure 2 is circuit diagram of an embodiment of the termination circuit of figure 1, having self-switching capability; and Figure 3 is a circuit diagram of an alternative embodiment of the invention for use with a tri-stateable bus.
In figure 1 a bus 10 is connected to a plurality of transceivers 13. Each transceiver 13 is coupled to a termination circuit 11. It will be understood that an arbitration scheme may be implemented to 20 prevent bus contention and that a transceiver 13 is capable of broadcasting over the bus 10 to more than 1 transceiver 13.
Figure 2 shows the bus 10 connected to the termination circuit 11 which includes a resistor 12, an inverter 14, and an n-channel field effect transistor (NFET) 16. The resistor 12 is an off-the-shelf 25 termination resistor having predetermined resistance. Both the NFET 16 and the resistor 12 are coupled to a ground plane having a voltage corresponding to a logic zero value or zero volts. As a form of ~..
illustration, a portion of a digital signal having a hi to lo transition is shown having superimposed thereon an unwanted alternating signal. It is desirable to eliminate unwanted signals, caused by reflection, noise, or the like which may not totally be absorbed by conventional s termination means such as the termination resistor 12. If the magnitude of any reflected signals becomes too great, transmitted data may become corrupted. For example, if a zero bit is being transmitted, and the unwanted signal reaches a voltage level near the threshold level associated with switching from one logic state to another, the transmitted zero bit may be perceived as a one-bit.
In the preferred embodiment shown in figure 3, a flip-flop 20 is coupled to an inverter 14 and to an AND gate 22 having inverted input terminals. An NFET 16 is similarly configured as in figure 2 having the source and drain connected to the bus 10 and to a ground plane 15 respectively. The circuit shown in figure 3 is suitable for use on a tristatable bus. The flip-flop 20 allows the NFET 16 to switch on and conduct thereby eliminating most of any unwanted signals, and releases the clamp after the data on the bus has been latched. A detailed description of the operation of the circuit will follow.
With reference to figure 2, the termination circuit 11 provides a means of self-switching and clamping unwanted spurious reflected signals which otherwise may be perceived as one-bits instead of transmitted zero-bits. The NFET 16 performs the function of clamping when switched on, in a conducting mode. In the instance that a one-bit followed by a 25 zero-bit is transmitted as is illustrated by the waveform in figure 2, the zero-bit received at the input terminal of the inverter 14 results in a one-bit at its output terminal. This one-bit corresponding to a digital hi voltage level switches on the gate of the NFET 16 thereby providing a path to ground. In the instance that a one-bit is presented 30 to the input terminal of the inverter 14, a resulting zero-bit corresponding to approximately zero volts switches off the NFET 16 preventing it from conducting and isolating the bus 10 from the ground plane. It should be obvious to a person skilled in the art that the transceivers 13 must be adequately powered to provide enough current to allow the NFET 16 to switch off. More specifically, the transceivers must supply enough current to overpower a switched on conducting NFET to allow the NFET to switch off.
In the preferred embodiment shown in figure 3, as data on the bus 5 10 changes from a one to a zero the NFET 16 switches on and conducts thereby reducing unwanted signals by providing a path to ground. One clock cycle later the zero-bit of data is inverted and is clocked through the flip-flop and the clamp is released, the NFET switching off and not conducting. If the data on the bus 10 changes from a zero to a 1, the clamp remains released and the NFET does not conduct. In the event that the bus becomes tristated, a pull-up resistor 24 provides a voltage corresponding to a logic hi, and the NFET remains switched off and in the non-conducting mode of operation. The flip-flop 20 and the AND gate 22 essentially provide a means of releasing the clamp one clock 15 cycle after the data has been available on the bus 10.
Numerous modifications and variations may be considered without departing from the scope of the invention.
Claims (4)
1. A circuit for attenuating unwanted signals on a transmission line adapted to carry data signals comprising:
an inverter gate coupled to the transmission line for providing inverted data signals corresponding to the signals appearing on the transmission line;
a flip-flop responsive to the inverted data signals and to a local clock signal for providing output signals;
circuit means connected to the flip-flop for providing inverted output signals thereof;
an AND gate responsive to the inverted data signals and to the inverted output signals from the flip-flop to provide ANDED signals;
and a controllable transmission gate connected between the transmission line and terminal connected to a reference voltage, the controllable gate being responsive to the ANDED signals for providing a conducting path to the terminal from the transmission line in a first mode and for preventing conduction between the transmission line and the terminal in a second mode.
an inverter gate coupled to the transmission line for providing inverted data signals corresponding to the signals appearing on the transmission line;
a flip-flop responsive to the inverted data signals and to a local clock signal for providing output signals;
circuit means connected to the flip-flop for providing inverted output signals thereof;
an AND gate responsive to the inverted data signals and to the inverted output signals from the flip-flop to provide ANDED signals;
and a controllable transmission gate connected between the transmission line and terminal connected to a reference voltage, the controllable gate being responsive to the ANDED signals for providing a conducting path to the terminal from the transmission line in a first mode and for preventing conduction between the transmission line and the terminal in a second mode.
2. The circuit as defined in claim 1 wherein the controllable gate is a field effect transistor.
3. A circuit for attenuating unwanted signals on a transmission line adapted to carry data signals, comprising:
a controllable transmission gate operable in a first mode for conducting unwanted current from the transmission gate to a voltage reference terminal in response to unwanted signals on the transmission line and operable in a second mode for preventing the conduction of current from the transmission line to the terminal, the gate having a first terminal connected to the transmission line, a second terminal connected to the voltage reference terminal and a control terminal, and a control circuit means for releasing the transmission gate from conducting in the first mode in response to a clock signal and to the data signals on the transmission line, said control circuit means being coupled to the transmission line via an inverter gate and having a control circuit output connected to the control terminal of the controllable transmission gate.
a controllable transmission gate operable in a first mode for conducting unwanted current from the transmission gate to a voltage reference terminal in response to unwanted signals on the transmission line and operable in a second mode for preventing the conduction of current from the transmission line to the terminal, the gate having a first terminal connected to the transmission line, a second terminal connected to the voltage reference terminal and a control terminal, and a control circuit means for releasing the transmission gate from conducting in the first mode in response to a clock signal and to the data signals on the transmission line, said control circuit means being coupled to the transmission line via an inverter gate and having a control circuit output connected to the control terminal of the controllable transmission gate.
4. A circuit as defined in claim 3 wherein the control circuit means comprises:
a flip-flop responsive to the inverted data signals and to a local clock signal for providing output signals;
inverting circuit means connected to the flip-flop for providing inverted output signals thereof; and an AND gate responsive to the inverted data signals and to the inverted output signals from the flip-flop to provide control signals to the controllable transmission gate.
a flip-flop responsive to the inverted data signals and to a local clock signal for providing output signals;
inverting circuit means connected to the flip-flop for providing inverted output signals thereof; and an AND gate responsive to the inverted data signals and to the inverted output signals from the flip-flop to provide control signals to the controllable transmission gate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/735,730 US5166561A (en) | 1991-07-25 | 1991-07-25 | Active intelligent termination |
| US735,730 | 1991-07-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2069658A1 CA2069658A1 (en) | 1993-01-26 |
| CA2069658C true CA2069658C (en) | 1998-09-15 |
Family
ID=24956953
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002069658A Expired - Fee Related CA2069658C (en) | 1991-07-25 | 1992-05-27 | Active intelligent termination |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US5166561A (en) |
| CA (1) | CA2069658C (en) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4234402A1 (en) * | 1992-10-07 | 1994-04-14 | Siemens Ag | Arrangement for transmitting binary signals over a signal line |
| US5329174A (en) * | 1992-10-23 | 1994-07-12 | Xilinx, Inc. | Circuit for forcing known voltage on unconnected pads of an integrated circuit |
| US5534811A (en) * | 1993-06-18 | 1996-07-09 | Digital Equipment Corporation | Integrated I/O bus circuit protection for multiple-driven system bus signals |
| US5466975A (en) * | 1993-08-13 | 1995-11-14 | The Whitaker Corporation | Switched termination for bus tap-off line |
| US5585741B1 (en) * | 1994-04-22 | 2000-05-02 | Unitrode Corp | Impedance emulator |
| US5811984A (en) * | 1995-10-05 | 1998-09-22 | The Regents Of The University Of California | Current mode I/O for digital circuits |
| US5933021A (en) * | 1996-06-18 | 1999-08-03 | Sun Microsystems, Inc | Noise suppression method and circuits for sensitive circuits |
| US5994918A (en) * | 1997-08-29 | 1999-11-30 | Hewlett-Packard Co. | Zero delay regenerative circuit for noise suppression on a computer data bus |
| KR100304691B1 (en) * | 1998-05-29 | 2001-09-29 | 윤종용 | Tristate detection circuit & digital signal generator having the same |
| US6294942B2 (en) | 1999-03-09 | 2001-09-25 | International Business Machines Corporation | Method and apparatus for providing self-terminating signal lines |
| US6424169B1 (en) | 2000-01-24 | 2002-07-23 | Broadcom Corporation | Active termination network |
| US6351138B1 (en) | 2001-03-22 | 2002-02-26 | Pericom Semiconductor Corp. | Zero-DC-power active termination with CMOS overshoot and undershoot clamps |
| US6429678B1 (en) | 2001-03-22 | 2002-08-06 | Pericom Semiconductor Corp. | Capacitively-coupled extended swing zero-DC-power active termination with CMOS overshoot/undershoot clamps |
| US6686763B1 (en) | 2002-05-16 | 2004-02-03 | Pericam Semiconductor Corp. | Near-zero propagation-delay active-terminator using transmission gate |
| JP4018941B2 (en) * | 2002-06-26 | 2007-12-05 | オリオン電機株式会社 | Signal interference prevention unit and signal processing apparatus |
| US7026839B1 (en) * | 2003-06-26 | 2006-04-11 | Marvell International Ltd. | Circuits, architectures, systems and methods for overvoltage protection |
| US10425361B2 (en) | 2017-03-16 | 2019-09-24 | Trane International Inc. | Dynamic allocation of termination resistors in a communication network |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5321266B2 (en) * | 1972-10-04 | 1978-07-01 | ||
| US3832575A (en) * | 1972-12-27 | 1974-08-27 | Ibm | Data bus transmission line termination circuit |
| US3937988A (en) * | 1974-04-05 | 1976-02-10 | Fairchild Camera And Instrument Corporation | Active termination network for clamping a line signal |
| US4015147A (en) * | 1974-06-26 | 1977-03-29 | International Business Machines Corporation | Low power transmission line terminator |
| US4228369A (en) * | 1977-12-30 | 1980-10-14 | International Business Machines Corporation | Integrated circuit interconnection structure having precision terminating resistors |
| US4450370A (en) * | 1979-01-31 | 1984-05-22 | Phillips Petroleum Company | Active termination for a transmission line |
| US4345171A (en) * | 1980-06-30 | 1982-08-17 | Texas Instruments Incorporated | Adaptable nonlinear transmission line terminator |
| US4498021A (en) * | 1982-07-13 | 1985-02-05 | Matsushita Electric Industrial Co., Ltd. | Booster for transmitting digital signal |
| US4596940A (en) * | 1984-04-19 | 1986-06-24 | Hewlett-Packard Company | Three state differential ECL bus driver |
| US4766334A (en) * | 1986-03-07 | 1988-08-23 | The Singer Company | Level clamp for Tri-state CMOS bus structure |
| JPS62214714A (en) * | 1986-03-15 | 1987-09-21 | Fujitsu Ltd | Lsi device equipped with noise countermeasure circuit |
| US4748426A (en) * | 1986-11-07 | 1988-05-31 | Rodime Plc | Active termination circuit for computer interface use |
| US4859877A (en) * | 1988-01-04 | 1989-08-22 | Gte Laboratories Incorporated | Bidirectional digital signal transmission system |
-
1991
- 1991-07-25 US US07/735,730 patent/US5166561A/en not_active Expired - Fee Related
-
1992
- 1992-05-27 CA CA002069658A patent/CA2069658C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US5166561A (en) | 1992-11-24 |
| CA2069658A1 (en) | 1993-01-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| MKLA | Lapsed |