CA2072264A1 - Thin-film transistor manufacture - Google Patents
Thin-film transistor manufactureInfo
- Publication number
- CA2072264A1 CA2072264A1 CA002072264A CA2072264A CA2072264A1 CA 2072264 A1 CA2072264 A1 CA 2072264A1 CA 002072264 A CA002072264 A CA 002072264A CA 2072264 A CA2072264 A CA 2072264A CA 2072264 A1 CA2072264 A1 CA 2072264A1
- Authority
- CA
- Canada
- Prior art keywords
- gate
- conductive layer
- film
- substrate
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000010409 thin film Substances 0.000 title abstract description 4
- 239000010408 film Substances 0.000 claims abstract description 76
- 239000000758 substrate Substances 0.000 claims abstract description 56
- 239000004065 semiconductor Substances 0.000 claims abstract description 47
- 239000000463 material Substances 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 13
- 230000005855 radiation Effects 0.000 claims abstract description 10
- 238000000137 annealing Methods 0.000 claims abstract description 8
- 238000010521 absorption reaction Methods 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 41
- 238000005286 illumination Methods 0.000 claims description 14
- 230000008569 process Effects 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 230000000295 complement effect Effects 0.000 claims description 3
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 68
- 229910021417 amorphous silicon Inorganic materials 0.000 description 12
- 230000037230 mobility Effects 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005334 plasma enhanced chemical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- HFGHRUCCKVYFKL-UHFFFAOYSA-N 4-ethoxy-2-piperazin-1-yl-7-pyridin-4-yl-5h-pyrimido[5,4-b]indole Chemical compound C1=C2NC=3C(OCC)=NC(N4CCNCC4)=NC=3C2=CC=C1C1=CC=NC=C1 HFGHRUCCKVYFKL-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000905957 Channa melasoma Species 0.000 description 1
- UOACKFBJUYNSLK-XRKIENNPSA-N Estradiol Cypionate Chemical compound O([C@H]1CC[C@H]2[C@H]3[C@@H](C4=CC=C(O)C=C4CC3)CC[C@@]21C)C(=O)CCC1CCCC1 UOACKFBJUYNSLK-XRKIENNPSA-N 0.000 description 1
- 101100536883 Legionella pneumophila subsp. pneumophila (strain Philadelphia 1 / ATCC 33152 / DSM 7513) thi5 gene Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 101100240664 Schizosaccharomyces pombe (strain 972 / ATCC 24843) nmt1 gene Proteins 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 240000004543 Vicia ervilia Species 0.000 description 1
- 239000005407 aluminoborosilicate glass Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
- H01L21/02686—Pulsed laser beam
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
- H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/15—Silicon on sapphire SOS
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/948—Radiation resist
- Y10S438/949—Energy beam treating radiation resist on semiconductor
Abstract
ABSTRACT
THIN-FILM TRANSISTOR MANUFACTURE
Source (51) and drain (52) of a thin-film transistor (TFT) are formed from a conductive layer (5) using a photolithographic step (Figure 3) in which the gate (4) serves as a photomask. In accordance with the invention the insulated gate structure (3,4) is formed at the upper face of the channel-forming semiconductor film (2), i.e. remote from the transparent substrate (1). The semiconductor film (2) may be annealed to high-mobility polycrystalline material before depositing the gate structure (3,4) and the overlying conductive layer (5). In this way, high speed TFTs can be formed due to a combination of low gate-to-drain and gate-to-source capacitances and the provision of the transistor channel in the high quality semiconductor material adjacent to the upper face of the film (2). Preferably ultra-violet radiation (20:
Figure 1) is used for the annealing with an absorption depth less than the thickness of the film (2) so that the film-substrate interface is not heated which otherwise may weaken the adhesion of the film (2) to the substrate (1). By using an angled exposure in a photolithographic and etching step with the gate (4) as a shadow photomask, a low-doped drain part can be defined from a conductive layer (5) comprising highly-doped material on low-doped material.
This low-doped drain part reduces the effect of high drain bias in operation of the TFT.
(Figures 1,3 & 4).
THIN-FILM TRANSISTOR MANUFACTURE
Source (51) and drain (52) of a thin-film transistor (TFT) are formed from a conductive layer (5) using a photolithographic step (Figure 3) in which the gate (4) serves as a photomask. In accordance with the invention the insulated gate structure (3,4) is formed at the upper face of the channel-forming semiconductor film (2), i.e. remote from the transparent substrate (1). The semiconductor film (2) may be annealed to high-mobility polycrystalline material before depositing the gate structure (3,4) and the overlying conductive layer (5). In this way, high speed TFTs can be formed due to a combination of low gate-to-drain and gate-to-source capacitances and the provision of the transistor channel in the high quality semiconductor material adjacent to the upper face of the film (2). Preferably ultra-violet radiation (20:
Figure 1) is used for the annealing with an absorption depth less than the thickness of the film (2) so that the film-substrate interface is not heated which otherwise may weaken the adhesion of the film (2) to the substrate (1). By using an angled exposure in a photolithographic and etching step with the gate (4) as a shadow photomask, a low-doped drain part can be defined from a conductive layer (5) comprising highly-doped material on low-doped material.
This low-doped drain part reduces the effect of high drain bias in operation of the TFT.
(Figures 1,3 & 4).
Description
2~722~
PY.B33727 DESCRIPTION
THIN-FILM TRANSISTOR MANUFI~CTURE
This invention relates to methods of manufac~uring an insulated-gate thin-film transistor (TP'r) using a photolithographic step in which the gate serves as a photomask, and further relates to TFTs manufactured by such a method. Such a method i9 particularly but not exclusively applicable for the ~anufacture of high speed TFTs comprising, for example, a polycrystalline silicon film which provides the transistor channel. Such transistors are of interest at present for large-area electronic circuitry on glass, for example in the driving circuitry of a large-area liquid-crystal display (LCD) or a sensor array or a memory array or a printer.
Published Japanese patent application Kokai JP-A-62-152174 discloses a method of manufacturing an insulated-gate thin-film tranqistor comprising a semiconductor film which provides a transistor channel adjacent to an insulated gate between source and drain of the transistor. In this ~nown method the semiconductor film is of amorphous silicon. The source and drain are formed from a conductive layer (of ITO, i.e. indium-tin-oxide, in this known method) which is removed from over the gate using a photolithographic step in which the gate serves as a photomask.
This step involves exposing a negative photoresist on the conductive lay&r by illumination through a transparent substrate which is of glass in the known method.
In thi~ known method of JP-A-62-152174, the insulated gate is formed on the substrate, after which the following sequence of layers are deposited: the semiconductor film, the conductive layer and the negative photores;st. The combination of the substrate, semiconductor film and conductive layer together is transparent to the illumination used to expose the photoresist, while the gate which serves as the photomask is opaque. The photomasked part of the ITO layer is etched away from the semiconductor film over the 207~2~
2 P~B337Z7 gate, after developing the photoresist.
~ y using this photolithographic and etching process as compared with a photolithographic lift-of process, the occurrence of short-circuits between the source and drain call be reduce~.
; Ihis improves the yield of the manu~actur~ng process and enhancesthe reliability of the product. Furthermore, because the edges of the source and drain are defined using the gate as the photomask, an overlap between the gate and the source and drain is small or even avoided so reducing gate-to-drain and gate-to-source capacitance and hence increasing the speed of the TFT.
Published European patent application EP-A-0 071 244 discloses a variant of such a method in which, after the insulated gate is provided on the substrate, the conductive layer and photoresist are deposited before the semiconductor film. The photolithographic step and the definition of the source and drain are then carried out before depositing the semiconductor film. Subsequently this film is deposited either as polycrystalline or amorphous semiconductor material and provides the TFT channel adjacent to its bottom face. An advantage of polycrystalline material is that it has a higher mobility than amorphous material so increasing the speed of the TFTs, but this fact is not commented on in EP-A-0 071 244.
The present invention is based on a recognition that by adopting a different sequence of processing steps still using the gate as a photomask, even better device characteristics can be obtained in a manufacturing process with good yield and reliability. Thus, the applicants have found that it is advantageous to provide the semiconductor film on the substrate and to form the insulated gate (which is to serve as the photomask) at the upper face of the semiconductor film remote from the substrate. The source and drain conductive layer is removed from over the gate, but in this case the transistor channel is adjacent to the upper face of the semiconductor film. This configuration is beneficial especially (but not solely) when providing ~.,, - : :, :: . , : :" , : ~ :~ ,, :. , , . : -, .:
207226~
PY.B33727 DESCRIPTION
THIN-FILM TRANSISTOR MANUFI~CTURE
This invention relates to methods of manufac~uring an insulated-gate thin-film transistor (TP'r) using a photolithographic step in which the gate serves as a photomask, and further relates to TFTs manufactured by such a method. Such a method i9 particularly but not exclusively applicable for the ~anufacture of high speed TFTs comprising, for example, a polycrystalline silicon film which provides the transistor channel. Such transistors are of interest at present for large-area electronic circuitry on glass, for example in the driving circuitry of a large-area liquid-crystal display (LCD) or a sensor array or a memory array or a printer.
Published Japanese patent application Kokai JP-A-62-152174 discloses a method of manufacturing an insulated-gate thin-film tranqistor comprising a semiconductor film which provides a transistor channel adjacent to an insulated gate between source and drain of the transistor. In this ~nown method the semiconductor film is of amorphous silicon. The source and drain are formed from a conductive layer (of ITO, i.e. indium-tin-oxide, in this known method) which is removed from over the gate using a photolithographic step in which the gate serves as a photomask.
This step involves exposing a negative photoresist on the conductive lay&r by illumination through a transparent substrate which is of glass in the known method.
In thi~ known method of JP-A-62-152174, the insulated gate is formed on the substrate, after which the following sequence of layers are deposited: the semiconductor film, the conductive layer and the negative photores;st. The combination of the substrate, semiconductor film and conductive layer together is transparent to the illumination used to expose the photoresist, while the gate which serves as the photomask is opaque. The photomasked part of the ITO layer is etched away from the semiconductor film over the 207~2~
2 P~B337Z7 gate, after developing the photoresist.
~ y using this photolithographic and etching process as compared with a photolithographic lift-of process, the occurrence of short-circuits between the source and drain call be reduce~.
; Ihis improves the yield of the manu~actur~ng process and enhancesthe reliability of the product. Furthermore, because the edges of the source and drain are defined using the gate as the photomask, an overlap between the gate and the source and drain is small or even avoided so reducing gate-to-drain and gate-to-source capacitance and hence increasing the speed of the TFT.
Published European patent application EP-A-0 071 244 discloses a variant of such a method in which, after the insulated gate is provided on the substrate, the conductive layer and photoresist are deposited before the semiconductor film. The photolithographic step and the definition of the source and drain are then carried out before depositing the semiconductor film. Subsequently this film is deposited either as polycrystalline or amorphous semiconductor material and provides the TFT channel adjacent to its bottom face. An advantage of polycrystalline material is that it has a higher mobility than amorphous material so increasing the speed of the TFTs, but this fact is not commented on in EP-A-0 071 244.
The present invention is based on a recognition that by adopting a different sequence of processing steps still using the gate as a photomask, even better device characteristics can be obtained in a manufacturing process with good yield and reliability. Thus, the applicants have found that it is advantageous to provide the semiconductor film on the substrate and to form the insulated gate (which is to serve as the photomask) at the upper face of the semiconductor film remote from the substrate. The source and drain conductive layer is removed from over the gate, but in this case the transistor channel is adjacent to the upper face of the semiconductor film. This configuration is beneficial especially (but not solely) when providing ~.,, - : :, :: . , : :" , : ~ :~ ,, :. , , . : -, .:
207226~
3 P~33727 polycrystalline semiconductor material for high-speed transistors, for example by a crystallizing anneal of the deposited film.
In accordance with the present invention1 there ls provide~ a method of manufacturing an insulated-gate thin-film transis~or comprising a semiconductor film which provides a tran3iator cham1el adjacent to an insulated gate between source and drain of the transistor. The source and drain are formed from a conductive layer which is removed from over the gate using a photolithographic step, in which step the gate serves as a photomask while exposing a negative photoresist on the conductive layer by illumination through a transparent substrate. According to the present invention, such a method is characterised by the steps of:
(a) depositing material for the semiconductor film, on the substrate, (b) forming the insulated gate at the upper face of the semiconductor film, which face is remote from the substrate, (c) depositing the conductive layer on the insulated gate and on the semiconductor film beside the insulated gate, (d) coating the conductive layer with the negative photoresist, and effecting the photolithographic step by exposing the photoresist through the combination of the substrate, semiconductor fil~ and conductive layer which together are transparent to the illumination, and (e) removing the conductive layer from over the gate so as to leave separate parts of the conductive layer on the semiconductor film at opposite sides of the insulated gate, for forming the source and draln of the transistor.
Thus, by providing the gate as a photomask at the upper face of the semiconductor film, the present invention permits the achievement of low gate-to-drain and gate-to-source capacitances while also obtaining benefits of providing the transistor channel in the semiconductor material remote from the substrate. The applicants find that a better quality channel can be formed adjacent to the upper face of the semiconductor film, as compared with a transistor channel formed at the lower face of a semiconductor film deposited on an insulated gate on the -- , . . .
In accordance with the present invention1 there ls provide~ a method of manufacturing an insulated-gate thin-film transis~or comprising a semiconductor film which provides a tran3iator cham1el adjacent to an insulated gate between source and drain of the transistor. The source and drain are formed from a conductive layer which is removed from over the gate using a photolithographic step, in which step the gate serves as a photomask while exposing a negative photoresist on the conductive layer by illumination through a transparent substrate. According to the present invention, such a method is characterised by the steps of:
(a) depositing material for the semiconductor film, on the substrate, (b) forming the insulated gate at the upper face of the semiconductor film, which face is remote from the substrate, (c) depositing the conductive layer on the insulated gate and on the semiconductor film beside the insulated gate, (d) coating the conductive layer with the negative photoresist, and effecting the photolithographic step by exposing the photoresist through the combination of the substrate, semiconductor fil~ and conductive layer which together are transparent to the illumination, and (e) removing the conductive layer from over the gate so as to leave separate parts of the conductive layer on the semiconductor film at opposite sides of the insulated gate, for forming the source and draln of the transistor.
Thus, by providing the gate as a photomask at the upper face of the semiconductor film, the present invention permits the achievement of low gate-to-drain and gate-to-source capacitances while also obtaining benefits of providing the transistor channel in the semiconductor material remote from the substrate. The applicants find that a better quality channel can be formed adjacent to the upper face of the semiconductor film, as compared with a transistor channel formed at the lower face of a semiconductor film deposited on an insulated gate on the -- , . . .
4 P~B33727 substrate. The properties of the semiconductor material at the upper face are less affected by the substrate. The transistor may comprise an amorphou9 ~emiconductor ilm, but the invention is particularly advantageous for transistors with rrystalline film material at least in the region of the transi~tor cha~lel. Thus, the invention permits the manufacture of high-speed TFT~ due both to the low gate-to-drain and gate-to-source capacitances and to the high mobility of the crystalline semiconductor material adjacent to the insulated gate at the upper face of the film.
There is at presen~ con3iderable interest in developing high-speed polycrystalline TFTs for large-area flat-panel LCDs.
These displays are addressed by a matrix of active devices (TFTs or diodes) with at least one device per pixel. The dominant and most widely used technology at present i9 based on amorphous silicon TFTs. However amorphous silicon TFTs are too slow to provide the driving circuitry 90 that at present the display is normally connected externally to peripherally-mounted integrated-circuits formed in monocrystalline silicon. The present invention permits the manufacture of sufficiently fast TFTs to implement the scanning and addressing circuitry functions for such large-area displays, and the display can be Eabricated on the same substrate as these TFTs. For thi~ purpose, the TFTs should have a sufficiently high mobility and low parasitic capacitance as to allow the construction of row and column shift registers operating at, for example, about 30kHz and llMHz respectively, and for output driver TFTs to be able to charge the appropriate row or column capacitances. Such TFTs can be manufactured in accordance with the invention.
The semiconductor film may be deposited as crystalline material on the substrate in step (a)~ Thus, for example, by chemical vapour depo~ition at sub~trate temperatures of 600 to 620C, columnar polycrystalline silicon can be deposited in a fine grain form with grain widths of up to about O.l~m. TFTs made from this material with the insulated gate at the upper face remote from the substrate may have mobilities in the range of, for example, 5 to lOcm2.V l.s~l. It is found that the '~:
20722~
P~33727 :
crystalline grain structure of the upper deposited material is usually better than that deposited immediately adjacent to the substrate.
However, the material for the semiconductor Eilm may be deposited in a fine-grain or even amorphous form in step (a), and this deposited material may thsn be annealed on the substrate before step (b) so as to crystallize the film at least adjacent to its upper face which i9 remote from the substrate. Thus, for example, substantially amorphous silicon can be deposited with a substrate temperature of about 540C and using low-pressure chemical vapour deposition. Alternatively using plasma-enhanced chemical vapour deposition, amorphous silicon material may be deposited at a temperature as low as about 250C to 300C. The film may be annealed by heating in a furnace. Thus, for example, with a furnace temperature of about 600C, such amorphous silicon material can be converted into large-grain (about l~m in width) polycrysta~line silicon as a result of random nucleation.
Mobilities in the range of, for example 20 to 80cm2.V~l.s-can be obtained.
However, instead of furnace annealing, it can be even more advantageous to anneal the deposited film material by irradiating its upper face with an energy beam, for example a laser beam.
Depending on the detailed conditions polycrystalline silicon mobilities in the range of, for example, 10 to 175 cm2. V l.s~l can be obtained in this manner. Furthermore, laser annealing permits selective local crystallization of the film so that, for example, polycrystalline silicon driver ~FTs can be formed in peripheral areas of a LCD substrate, and a central area of the same substrate may comprise amorphous silicon devices of the Visible light from an argon laser or infrared radiation from a C2 laser may be used for the annealing step. However~ it is preferable to employ ultra-violet radiation from, for example, an excimer laser. An advantage of ultra-violet radiation is its smaller absorption depth so that, for example, the thickness of the film may be larger than ~he absorption depth of the ultra-violet radiation in the amorphous material. This smaller absorption depth -~ .
2~722~4 6 P~B3,72 reduces heating of the substrate and of the interface between the substrate and the semiconductor film. The applicants have found that such heating of the substrate can reduce the yield of the manufacturing process by weakening the a~hesion o the semiconductor film to the 9ub~trate. Hence, it is advantageous in accordance with the invsntion to provide the in3ulated gate at the opposite (i.e. upper) face of the film and to do so after annealing the ftlm to form a good quality cry~tal grain structure adjacent to its upper face. An insulating layer of the insulated-gate structure may be present on the semiconductor film during the annealing. However, it seems at present that a better crystal grain structure may be obtained for the TFT channel when the upper face of the film is not covered with such a layer during the annealing.
In addition to the advantages already described in providing the gate as a photomask at the upper face of the semiconductor film, a particular method in accordance with the present invention also permits the formation of a lower-doped part of the drain to reduce the field at the drain. Thus 9 for example, one particular method in accordance with the invention may be further characterised in that the conductive layer is of doped semiconductor material having a lower doping level in a lower part of the layar below an upper part of higher conductance, and in that, after removing the conductive layer from ovar the gate, the upper part i8 etched away from the lower part at an area at least at the drain side of the gate so as to space the hlgher-conductance upper part of the drain laterally from the channel by a lower-doped part of the conductive layer. The provi~ion of thi~ lower-doped part can ~erve to reduce a localised high electric field which occurs at the drain edge of the gate with high drain bias and which may otherwise lead to degradation of the TFT performance by trapping hot carriers injected into the insulated-gate structure.
If desired, a similar low-doped source part may be formed at the source side of the gate. However, using a particular method in accordance with the invention, it is possible to expose the ~`
20~22~
7 P1~3~727 low-doped part only at the drain side and even to deine the lateral extent of the low-doped drain part using a shadow-masXing affect of the insulated gate.
Thus, for example, in one form in accordance with the invention a second photolithographic step using negative photoresist is used to define the area at which the upper part of the conductive layer i8 etched away from the lower part, the negative photoresist in the second photolithographic step being exposed by illumination through the substrate at such an angle that the insulated gate shadow-mask~ the photoresist over an area of the 1 conductive layer at the drain side of the insulated gate. In another form in accordance with the invention a photolithographic step using a positive photoresist is used to define the araa at which the upper part of the conductive layer is etched away from the lower part, tha positive photoresi~t beingexposed by illuminating its upper face which is remote from the substrate at such an angle that the insulated gate shadow-masks the photoresist over the area of the conductive layer at the drain side of the insulated gate; and in this case the shadow-masked area of the photoresist which re~ains after developing the exposed photoresist may be used in a lift-off process to form a complementary mask on the surrounding area for protecting the surrounding area while etching away said upper part of the conductive layer at the drain side of the insulated gate.
These and other featureQ in accordance with the invention are illustrated specifically in embodiments o the invention now to be described, by way of example, with reference to the accompanying diagrammatic drawing~. In these drawings:
Figure l is a cross-section of a semiconductor film deposited on a substrate at an early stage in the manufacture oE a TFT by a method in accordance with the invention;
Fi~ures 2 to 5 are similar cross-sections to that of Figure 1 but at later stages in the manufacture of the TPT whose final structure is illustrated in Figure 5;
:; , . ,, :
, . : :
-:
8 ~HB~37~7 Figure 6 i9 a cross-section similar to that of Figure 5 but illustrating a modified TFT structure havlng a low-doped drain part extending laterally between the insulated gate and the main dra~n electrode part;
Figure 7 is a simllar cros~-section of the TFT ~tructure oE
Figure 6 but at a 3tage in one method for its manufacture in accordance with the invention and involving a second photolithographic step using the insulated gate to shadow-mask a negative photoresist, and Figures 8 and 9 are similar cross-~ections of the T~T
structure oE Figure 6 but at two succe~sive stages in another method for its manufacture in accordance with the inve~tion and involving a photolithographic step using the insulated gate to shadow-mask a positive photoresist.
It should be noted that all the drawings are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of the Figules have been shown exaggerated or reduced in size for the sake of clarity and convenience in the drawings. The same reference sign~ are generally used to refer to corresponding or similar features in the different embodimentq.
Figures 1 to 5 illustrate one example of a method in accordance with the invention for manuacturing an in~ulated-gate TFT. The TFT of Figure 5 is pre~ent on a tranRparen~ substrate 1 and comprise~ a ~emiconductor film 2, for example of polycrystalline silicon. The film 2 provides a tranRistor channel adjacent to an insulated gate structure 3 and 4. The channel and the insulated gate are present between source and drain 51 and 52 of the TFT. These source and drain 51 and S~ are ~ormed from a conductive layer 5 ~Figure 3) which in the form illustrated iS9 for example, highly doped n-type ~ilicon (n~. These n~ source and drain 51 and 52 are contacted in the TFT structure of Figure 5 by metal electrodes 41 and 42 respectively of, for example, aluminium or chromium.
In brief summary the manufactuIing method illustrated in . . , : .
`` 2~72~
Figures l to 5 comprises the steps of:
(a) depositing material Eor the semiconductor film 2, on the substrate l, see Figure 1, (b) forming the insulated gate structure 3 and 4 at the upper face of the film 2, i.e. the face remote from the substrate l, (c) depositing the conductive layer 5 on the insulat~d gate 3 and 4 and on the semiconductor film 2 beside the insulated gate, (d) coating the conductive layer 5 with a negative photoresist 6, and then e~posing the photoresist by illumination 25 through the substrate 1 while using the gate 4 as a photomask, see Figure 3, and (e~ removing the conductive layer 5 from over the gate 4 so as to leave separate parts Sl and 52 on the semiconductor film 2 at opposite sides of the insulated gate 394, for forming the source and drain of the transistor.
A specific example of the method of Figures 1 to 5 will now be described. In this specific example, the substrate 1 may be an alkali-free alumino-borosilicate glass, and a LCD may, for example, be constructed on another area of the substrate 1 not shown in the cross-section of Figures 1 to 5. Using either a low-pressure chemical vapour deposition process at about 540C or a plasma-enhanced chemical vapour deposition process at about 250C, hydrogenated amorphous silicon may be deposited on the glass substrate 1 from silane to form the film 2 with a thickness of, less than O.l~m, for example about 40nm or 60nm. A
photolithographic step is then carried out to mask areas of the film 2 where the TFT and other devices are to be formed, and the unmasked areas are etched away to leave amorphous silicon islands 2 on the substrate 1.
Figure l shows one such island 2 where a single polycrystalline silicon TFT is to be formed. It should be understood that the substrate 1 of Figure 1 carries many other such silicon islands 2, some of which are to be processed in the same manner as that shown in Figures l to 5 and some of which may be processed differently to form a different type of TFT ~e.g. an , ., :
.
722~
amorphous silicon TFT~ or other device.
As illustrated by the arrows 20 in Figure 1 those amorphous silicon islands 2 which are to be annealed to polycrystalline silicon are irradiated at their upper face remote from the substrate l with a laser beam 20. Preferably ultra-violet radiation 20 is used with an absorption depth in the silicon oE
less than the thickness of the si:licon film 2. Thus, for example7 an ultra-violet wavelength of 248nm from an excimer laser may be used and has an absorption depth of about 6nm in the amorphous silicon film 2. The film Z may be exposed to multiple pulses (for example, several tens of pulses) from this laser with a pulse energy of between lOOmJ.cm~2 and 300mJ.cm~2 per pulse. In this case it is found for a 40nm or 60nm thick film 2, crystallization into large grains of about 80nm width occurs adjacent to its upper surface whereas the underlying material adjacent to tha substrate 1 comprises only fine grains of up to about 25nm in width and may even remain substantially amorphous at the interface with the substrate 1. The grain size at the upper surface may increase with increase in the numb~r of pulses to which it is exposed at a given scan rate. More pulses are needed to effect the same anneal if a faster scan rate is used.
The large-grain layer adjacent the upper face of the film 2 provides a high mobility te.g. in excess of 30cm2.V l.s~l for a 200mJ.cm~2 energy pulse) for the TFT channel. This is adequate for both row and column driver circuits of a LCD. Thus, for example, for row and column shift registers operating at about 30kHz and llMHz respectively, the field-eEfect mobility for row driver TFTs should be in excess of about 1 cm2.V l.s~l1 whereas that for column driver TFTs should be in excess of about 25 cm2.V l.s~l. The conductivity of the large-grain layer is effectively intrinsic with its Fermi level near the middle of the energy bandgap. However the film 2 may be lightly doped with a suitable donor such as phosphorus or a suitable acceptor such as boron so as to adjust the gate threshold voltage of the TFT and/or to give the crystallized film 2 a light n or p type conductivity.
20722~4 The large grains in the upper portion are believed to result from surface melting of the silicon by the strongly absorbed ultra-violet, whereas the underlying fine grains appear to result from 301id-phase recrystallization. The depth of ~he large-graln surface layer is found to be a strong function of ~ncident laser energy, varying from about lOnm for a 150mJ.cm~2 pulse to about 50nm for a 250mJ.cm~2 pulse. Annealing the film 2 in this manner with an ultra-violet laser is advantageous in preserving good adhesion of the film 2 to the substrate 1. The applicants have also annealed such films 2 using visible radiation (514.5nm) from an argon laser; in this case the film 2 is annealed to large crys~al grains through most of its thickness, but there was a tendency for the film 2 to peel away from the substrate 1 due to the strong heating of the sub~trate.
After the film 2 is annealed in this manner, an insulating layer (for example of silicon dioxide) is deposited in known manner, followed by a conductive gate layer (for example of aluminium or chromium). A photolithographic and etching process is then carried out in known manner to remove these layers except in the areas where required to form the insulated gate structure 3 and 4 for the TFTs. The resulting structure is illustrated in Figure 2. The remaining layer parts 3 and 4 extend as stripes (perpendicular to the plane of the drawing) across the film islands 2 which protrude laterally from benea~h opposite ends of the insulated gate structure 3 and 4 as shown in Pigure 2.
The conductive layar 5 of for example phosphorus-doped siliron is then deposited in known manner by chemical vapor deposition and is coated with the negative photoresis~ 6. The n type layer 5 may be, for example~ about 20nm thick, and the photoresist 6 may be about l~m thick. The photolithographic and etching process for forming the source and drain 51 and 52 from the layer 5 is now carried out.
As illustrated in Yigure 3, the negative photoresist 6 is exposed by illumination with radiation 25 through the comhination of the substrate 1, film 2, and layer 5 which together are transparent to the wavelength (for example in the near ultraviolet or visible region of the spectrum) chosen for the illumination 25.
Although the insulating layer 3 may also be transparent, the metal gate 4 is opaque at this wavelength and so acts a~ a photomask, The photoresist is then developed in known manner, and so a window 14 is opened in the unexposed photoresi~t above the insulated gate 3 and 4 and uncovers the conductive layer 5 in this area. The window 14 i~ illustrated in bro~en outline in Figure 3. The layer 5 is then etched away at the window 14 so as to expose the insulated-gate s~ructure 3 and 4 and form the separate source and drain 51 and 52 from the remaining parts of the layer 5 covered by the remaining photoresist 6. The gate 4 is not etched to any significant extent in thi3 etching trea~ment. Figure 4 illustrates the resulting structure after removal of the remaining photoresist 6.
As illustrated by the broken lines at the edges of the source and drain 51 and 52 adjacent to the insulated~gate structure 3 and 4, the etch removal of the layer 5 at the window 14 may be continued until a small gap 53 appears between the edge~ of the gate structure and the facing edges of the source and drain 51 and 52. Alternatively the etching may be stopped when the source and drain layers 51 and 52 still abut the insulating layer 3, although care is then required to ensure that these layer~ 51 and 52 are etched back sufficiently as to avoid short-circuiting to the conductive gate 4. It is also possible for a silicon dioxide or other insulating layer to be deposited on the surface of the conductive gate 4 before the layer 5 so as to avoid any such short-circuit abutment of the source and drain 51 and 52 with the gate 4. Furthermore, such an inqulating layer may as3ist in the etch removal of the layer 5 from over the gate 4 when the gate 4 or layer 5 are of materials which are differen~ to those described above and for which selective etchant treatments are not so readily available.
The remaining source and drain parts interface with the large-grain high-mobility material at the upper face of the film 2 -, : ,, ,; - . ,: :
., ~ . ; ,- . .
20722~4 extending laterally beyond the insulated-gate structure 3 and 4.
This arrangement provides a goo~ and reliable electrical connection between the TFT channel and the source and drain 51 and 52. The sheet resistance of the source and drain layers 51 and 5Z may be reduced if ~esired by a laser anneal. Because the source and drain 51 and 52 are formed using the gate 4 as a photomask, the gate-to-source and gate-to-drain capacitances are very low, ~or example less than about 2 x 10-16F per ~m of channel width, 90 permitting fast operation of this high-mobility polycrystalline silicon TFT in, for example, column driver circuits of LCDs.
The further extent of the source and drain layers 51 and 52 are then defined in a further photolithographic and etching step, An insulating overlay 8 i8 subsequently deposited, and metal connections 41,42,44 respectively to the source, drain and gate 51,52 and 4 are provided. Gate connection 44 is outside the plane of the drawings and so is not illustrated in any of the Figures.
With high drain bias (for example with drain voltages of above 15 voltq) a localised high electric field region can be formed in the channel edge adjacent the drain 52. Charge carriers in this high field can attain kinetic energies in excess of a few eV and so may be injected over the interfacial potential barrier between the film 2 and the gate oxide 3. This carrier injection can cause degradation of the TFT characteristics, such as a reduction in transconductance or a ~hift in threshold voltage. As already described with reference to Figures 3 and ~, the conductive layer 5 at the window 14 can be etched back to such an extent that a small gap 53 i9 present between the facing edges of the drain 52 and the insulated-gate structure 3 and 4. This gap can assist in reducing the high field in this area and 90 reducing hot-carrier injection.
However, an even more advantageous structure can be obtained using a modified process which is also in accordance with the present invention. In this modified process the doping of the conductive layer 5 changes through the thic~ness of the layer 5 so as to be less in a lower part 55 than it is in a highly conductive upper part 56. The doping level may be varied progressively during .,., ,; . :
. . :
~722~
14 PH$33727 the deposition of the layer S, or the layer 5 may be deposited as two superimpo~ed layers 55 and 56 of different doping levels.
After removing the layers or layer parts 55 and 56 from over the gate 4, the upper part 56 is in this case etched away Erorn ~he lower part 55 at an area A at least at the drain side of the gate 4 so as to space the higher-conductance upper part 56 of the drain 52 laterally from the channel by a lower-doped part 55 of the layer 5. The resulting structure i~ illustrated in Figure 6.
The area A over which the upper part 56 is etched away may be defined using a separate photoma9k and requiring an extra alignment step. However, it is also possible to use the insulated-gate structure 3,4 as the photomas~, by illuminating the photoresist at such an angle that the insulated-gate structure 3,4 shadow-masks an area of the photoresist at the drain side of the gate 4. This is illustrated by the arrows 26 in Figure 6. The angled illumination 26 may be used instead of the perpendicular illumination 25 of Figure 3 so that the window 14 formed in the negative photoresist 6 is shifted laterally towards the drain. The etching away of the upper part 56 from the lower part 55 may then be effected through this window 14 by continuation of the etching step(s) to remove the layert 9 ) 55 and 56 from over the gate 4. However this variation in the photolithographic and etching process steps of Figures 3 and 4 can be difficult to reproduce reliably in a manufacturing process, and so preferably the angled illumination 26 is carried out in a separate photolithographic Rtep after the steps of Figures 3 and 4.
Figure 7 illustrates such a separate step in which a new negative photomask 16 i9 coated on the Figure 4 structure, the conductive layer 5 of which has the di~ferent doping levels of 55 and 56. The exposed photoresist 16 is then slightly overdeveloped 39 so as ts form a widened window 15 at the unexposed area which was shadow-masked by the gate 4. Figure 7 illustrates the resulting structure before carrying out the etching step to remove the exposed higher-doped upper part 56 rom the lower part 55 at the drain side of the insulated-gate structure 3 and 4. If desired a selective etchant may be used which at~acks the higher doped :
--` 20722~
material more rapidly than the lower doped material.
Instead of using a second photolithographic step wi~h a negative photoresist 16, a step wi~h a positive photoresist 11 ma~
be used as illustrated in Figure 8. In this case, the positlve photoresist i9 exposed by illuminating its upper face at a ~uitable angle (arrows 27) for the insulated gate 4 to shadow-mask the resist 17 over an area at the drain slde. The original coating of positive resist 17 i9 shown in broken outline in ~igure 8, which also shows in solid outline the shadow-mas~ed area of the resist 17 which remains after developing the exposed photoresist. This remaining resist area 17 is then used in a lift-off process to form a complementary mask 28 on the surrounding area. The mask 28 i~
formed by depositing a layer of gold for example and then dissolving the remaining resist area 17 to float off the overlying part of gold layer. The mask 28 i~ then used to protect the underlying surrounding area while etching away the upper part 56 from the lower part 55 at the drain side of the insulated gate 3 and 4. Figure 9 shows the resulting structure before removal of the mask 28.
The manufacture of n channel TFTs has been illustrated with reference to ~he drawings. However, the invention may also be used in the manufacture of p channel devices, having p type source and drain 51 and 52. The source and drain layers 51 and 52 may even be metallic, for example of indium-tin~oxide, in which case the deposition of an insulating layer on the gate 4 before depositing the metallic layer S can be desirable to facilitate the etch-removal of the layer 5 from over the gate 4.
From reading the pre~ent disclosure, other variations and modifications will be apparent to persons skilled in the art. Such variations and modifications may involve equivalents and other features which are already known in the design, manufacture and use of TFTs and other semiconductor devices and component parts thereof, and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of :, - -,: :
2~722~4 features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relate~
to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.
; ~5
There is at presen~ con3iderable interest in developing high-speed polycrystalline TFTs for large-area flat-panel LCDs.
These displays are addressed by a matrix of active devices (TFTs or diodes) with at least one device per pixel. The dominant and most widely used technology at present i9 based on amorphous silicon TFTs. However amorphous silicon TFTs are too slow to provide the driving circuitry 90 that at present the display is normally connected externally to peripherally-mounted integrated-circuits formed in monocrystalline silicon. The present invention permits the manufacture of sufficiently fast TFTs to implement the scanning and addressing circuitry functions for such large-area displays, and the display can be Eabricated on the same substrate as these TFTs. For thi~ purpose, the TFTs should have a sufficiently high mobility and low parasitic capacitance as to allow the construction of row and column shift registers operating at, for example, about 30kHz and llMHz respectively, and for output driver TFTs to be able to charge the appropriate row or column capacitances. Such TFTs can be manufactured in accordance with the invention.
The semiconductor film may be deposited as crystalline material on the substrate in step (a)~ Thus, for example, by chemical vapour depo~ition at sub~trate temperatures of 600 to 620C, columnar polycrystalline silicon can be deposited in a fine grain form with grain widths of up to about O.l~m. TFTs made from this material with the insulated gate at the upper face remote from the substrate may have mobilities in the range of, for example, 5 to lOcm2.V l.s~l. It is found that the '~:
20722~
P~33727 :
crystalline grain structure of the upper deposited material is usually better than that deposited immediately adjacent to the substrate.
However, the material for the semiconductor Eilm may be deposited in a fine-grain or even amorphous form in step (a), and this deposited material may thsn be annealed on the substrate before step (b) so as to crystallize the film at least adjacent to its upper face which i9 remote from the substrate. Thus, for example, substantially amorphous silicon can be deposited with a substrate temperature of about 540C and using low-pressure chemical vapour deposition. Alternatively using plasma-enhanced chemical vapour deposition, amorphous silicon material may be deposited at a temperature as low as about 250C to 300C. The film may be annealed by heating in a furnace. Thus, for example, with a furnace temperature of about 600C, such amorphous silicon material can be converted into large-grain (about l~m in width) polycrysta~line silicon as a result of random nucleation.
Mobilities in the range of, for example 20 to 80cm2.V~l.s-can be obtained.
However, instead of furnace annealing, it can be even more advantageous to anneal the deposited film material by irradiating its upper face with an energy beam, for example a laser beam.
Depending on the detailed conditions polycrystalline silicon mobilities in the range of, for example, 10 to 175 cm2. V l.s~l can be obtained in this manner. Furthermore, laser annealing permits selective local crystallization of the film so that, for example, polycrystalline silicon driver ~FTs can be formed in peripheral areas of a LCD substrate, and a central area of the same substrate may comprise amorphous silicon devices of the Visible light from an argon laser or infrared radiation from a C2 laser may be used for the annealing step. However~ it is preferable to employ ultra-violet radiation from, for example, an excimer laser. An advantage of ultra-violet radiation is its smaller absorption depth so that, for example, the thickness of the film may be larger than ~he absorption depth of the ultra-violet radiation in the amorphous material. This smaller absorption depth -~ .
2~722~4 6 P~B3,72 reduces heating of the substrate and of the interface between the substrate and the semiconductor film. The applicants have found that such heating of the substrate can reduce the yield of the manufacturing process by weakening the a~hesion o the semiconductor film to the 9ub~trate. Hence, it is advantageous in accordance with the invsntion to provide the in3ulated gate at the opposite (i.e. upper) face of the film and to do so after annealing the ftlm to form a good quality cry~tal grain structure adjacent to its upper face. An insulating layer of the insulated-gate structure may be present on the semiconductor film during the annealing. However, it seems at present that a better crystal grain structure may be obtained for the TFT channel when the upper face of the film is not covered with such a layer during the annealing.
In addition to the advantages already described in providing the gate as a photomask at the upper face of the semiconductor film, a particular method in accordance with the present invention also permits the formation of a lower-doped part of the drain to reduce the field at the drain. Thus 9 for example, one particular method in accordance with the invention may be further characterised in that the conductive layer is of doped semiconductor material having a lower doping level in a lower part of the layar below an upper part of higher conductance, and in that, after removing the conductive layer from ovar the gate, the upper part i8 etched away from the lower part at an area at least at the drain side of the gate so as to space the hlgher-conductance upper part of the drain laterally from the channel by a lower-doped part of the conductive layer. The provi~ion of thi~ lower-doped part can ~erve to reduce a localised high electric field which occurs at the drain edge of the gate with high drain bias and which may otherwise lead to degradation of the TFT performance by trapping hot carriers injected into the insulated-gate structure.
If desired, a similar low-doped source part may be formed at the source side of the gate. However, using a particular method in accordance with the invention, it is possible to expose the ~`
20~22~
7 P1~3~727 low-doped part only at the drain side and even to deine the lateral extent of the low-doped drain part using a shadow-masXing affect of the insulated gate.
Thus, for example, in one form in accordance with the invention a second photolithographic step using negative photoresist is used to define the area at which the upper part of the conductive layer i8 etched away from the lower part, the negative photoresist in the second photolithographic step being exposed by illumination through the substrate at such an angle that the insulated gate shadow-mask~ the photoresist over an area of the 1 conductive layer at the drain side of the insulated gate. In another form in accordance with the invention a photolithographic step using a positive photoresist is used to define the araa at which the upper part of the conductive layer is etched away from the lower part, tha positive photoresi~t beingexposed by illuminating its upper face which is remote from the substrate at such an angle that the insulated gate shadow-masks the photoresist over the area of the conductive layer at the drain side of the insulated gate; and in this case the shadow-masked area of the photoresist which re~ains after developing the exposed photoresist may be used in a lift-off process to form a complementary mask on the surrounding area for protecting the surrounding area while etching away said upper part of the conductive layer at the drain side of the insulated gate.
These and other featureQ in accordance with the invention are illustrated specifically in embodiments o the invention now to be described, by way of example, with reference to the accompanying diagrammatic drawing~. In these drawings:
Figure l is a cross-section of a semiconductor film deposited on a substrate at an early stage in the manufacture oE a TFT by a method in accordance with the invention;
Fi~ures 2 to 5 are similar cross-sections to that of Figure 1 but at later stages in the manufacture of the TPT whose final structure is illustrated in Figure 5;
:; , . ,, :
, . : :
-:
8 ~HB~37~7 Figure 6 i9 a cross-section similar to that of Figure 5 but illustrating a modified TFT structure havlng a low-doped drain part extending laterally between the insulated gate and the main dra~n electrode part;
Figure 7 is a simllar cros~-section of the TFT ~tructure oE
Figure 6 but at a 3tage in one method for its manufacture in accordance with the invention and involving a second photolithographic step using the insulated gate to shadow-mask a negative photoresist, and Figures 8 and 9 are similar cross-~ections of the T~T
structure oE Figure 6 but at two succe~sive stages in another method for its manufacture in accordance with the inve~tion and involving a photolithographic step using the insulated gate to shadow-mask a positive photoresist.
It should be noted that all the drawings are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of the Figules have been shown exaggerated or reduced in size for the sake of clarity and convenience in the drawings. The same reference sign~ are generally used to refer to corresponding or similar features in the different embodimentq.
Figures 1 to 5 illustrate one example of a method in accordance with the invention for manuacturing an in~ulated-gate TFT. The TFT of Figure 5 is pre~ent on a tranRparen~ substrate 1 and comprise~ a ~emiconductor film 2, for example of polycrystalline silicon. The film 2 provides a tranRistor channel adjacent to an insulated gate structure 3 and 4. The channel and the insulated gate are present between source and drain 51 and 52 of the TFT. These source and drain 51 and S~ are ~ormed from a conductive layer 5 ~Figure 3) which in the form illustrated iS9 for example, highly doped n-type ~ilicon (n~. These n~ source and drain 51 and 52 are contacted in the TFT structure of Figure 5 by metal electrodes 41 and 42 respectively of, for example, aluminium or chromium.
In brief summary the manufactuIing method illustrated in . . , : .
`` 2~72~
Figures l to 5 comprises the steps of:
(a) depositing material Eor the semiconductor film 2, on the substrate l, see Figure 1, (b) forming the insulated gate structure 3 and 4 at the upper face of the film 2, i.e. the face remote from the substrate l, (c) depositing the conductive layer 5 on the insulat~d gate 3 and 4 and on the semiconductor film 2 beside the insulated gate, (d) coating the conductive layer 5 with a negative photoresist 6, and then e~posing the photoresist by illumination 25 through the substrate 1 while using the gate 4 as a photomask, see Figure 3, and (e~ removing the conductive layer 5 from over the gate 4 so as to leave separate parts Sl and 52 on the semiconductor film 2 at opposite sides of the insulated gate 394, for forming the source and drain of the transistor.
A specific example of the method of Figures 1 to 5 will now be described. In this specific example, the substrate 1 may be an alkali-free alumino-borosilicate glass, and a LCD may, for example, be constructed on another area of the substrate 1 not shown in the cross-section of Figures 1 to 5. Using either a low-pressure chemical vapour deposition process at about 540C or a plasma-enhanced chemical vapour deposition process at about 250C, hydrogenated amorphous silicon may be deposited on the glass substrate 1 from silane to form the film 2 with a thickness of, less than O.l~m, for example about 40nm or 60nm. A
photolithographic step is then carried out to mask areas of the film 2 where the TFT and other devices are to be formed, and the unmasked areas are etched away to leave amorphous silicon islands 2 on the substrate 1.
Figure l shows one such island 2 where a single polycrystalline silicon TFT is to be formed. It should be understood that the substrate 1 of Figure 1 carries many other such silicon islands 2, some of which are to be processed in the same manner as that shown in Figures l to 5 and some of which may be processed differently to form a different type of TFT ~e.g. an , ., :
.
722~
amorphous silicon TFT~ or other device.
As illustrated by the arrows 20 in Figure 1 those amorphous silicon islands 2 which are to be annealed to polycrystalline silicon are irradiated at their upper face remote from the substrate l with a laser beam 20. Preferably ultra-violet radiation 20 is used with an absorption depth in the silicon oE
less than the thickness of the si:licon film 2. Thus, for example7 an ultra-violet wavelength of 248nm from an excimer laser may be used and has an absorption depth of about 6nm in the amorphous silicon film 2. The film Z may be exposed to multiple pulses (for example, several tens of pulses) from this laser with a pulse energy of between lOOmJ.cm~2 and 300mJ.cm~2 per pulse. In this case it is found for a 40nm or 60nm thick film 2, crystallization into large grains of about 80nm width occurs adjacent to its upper surface whereas the underlying material adjacent to tha substrate 1 comprises only fine grains of up to about 25nm in width and may even remain substantially amorphous at the interface with the substrate 1. The grain size at the upper surface may increase with increase in the numb~r of pulses to which it is exposed at a given scan rate. More pulses are needed to effect the same anneal if a faster scan rate is used.
The large-grain layer adjacent the upper face of the film 2 provides a high mobility te.g. in excess of 30cm2.V l.s~l for a 200mJ.cm~2 energy pulse) for the TFT channel. This is adequate for both row and column driver circuits of a LCD. Thus, for example, for row and column shift registers operating at about 30kHz and llMHz respectively, the field-eEfect mobility for row driver TFTs should be in excess of about 1 cm2.V l.s~l1 whereas that for column driver TFTs should be in excess of about 25 cm2.V l.s~l. The conductivity of the large-grain layer is effectively intrinsic with its Fermi level near the middle of the energy bandgap. However the film 2 may be lightly doped with a suitable donor such as phosphorus or a suitable acceptor such as boron so as to adjust the gate threshold voltage of the TFT and/or to give the crystallized film 2 a light n or p type conductivity.
20722~4 The large grains in the upper portion are believed to result from surface melting of the silicon by the strongly absorbed ultra-violet, whereas the underlying fine grains appear to result from 301id-phase recrystallization. The depth of ~he large-graln surface layer is found to be a strong function of ~ncident laser energy, varying from about lOnm for a 150mJ.cm~2 pulse to about 50nm for a 250mJ.cm~2 pulse. Annealing the film 2 in this manner with an ultra-violet laser is advantageous in preserving good adhesion of the film 2 to the substrate 1. The applicants have also annealed such films 2 using visible radiation (514.5nm) from an argon laser; in this case the film 2 is annealed to large crys~al grains through most of its thickness, but there was a tendency for the film 2 to peel away from the substrate 1 due to the strong heating of the sub~trate.
After the film 2 is annealed in this manner, an insulating layer (for example of silicon dioxide) is deposited in known manner, followed by a conductive gate layer (for example of aluminium or chromium). A photolithographic and etching process is then carried out in known manner to remove these layers except in the areas where required to form the insulated gate structure 3 and 4 for the TFTs. The resulting structure is illustrated in Figure 2. The remaining layer parts 3 and 4 extend as stripes (perpendicular to the plane of the drawing) across the film islands 2 which protrude laterally from benea~h opposite ends of the insulated gate structure 3 and 4 as shown in Pigure 2.
The conductive layar 5 of for example phosphorus-doped siliron is then deposited in known manner by chemical vapor deposition and is coated with the negative photoresis~ 6. The n type layer 5 may be, for example~ about 20nm thick, and the photoresist 6 may be about l~m thick. The photolithographic and etching process for forming the source and drain 51 and 52 from the layer 5 is now carried out.
As illustrated in Yigure 3, the negative photoresist 6 is exposed by illumination with radiation 25 through the comhination of the substrate 1, film 2, and layer 5 which together are transparent to the wavelength (for example in the near ultraviolet or visible region of the spectrum) chosen for the illumination 25.
Although the insulating layer 3 may also be transparent, the metal gate 4 is opaque at this wavelength and so acts a~ a photomask, The photoresist is then developed in known manner, and so a window 14 is opened in the unexposed photoresi~t above the insulated gate 3 and 4 and uncovers the conductive layer 5 in this area. The window 14 i~ illustrated in bro~en outline in Figure 3. The layer 5 is then etched away at the window 14 so as to expose the insulated-gate s~ructure 3 and 4 and form the separate source and drain 51 and 52 from the remaining parts of the layer 5 covered by the remaining photoresist 6. The gate 4 is not etched to any significant extent in thi3 etching trea~ment. Figure 4 illustrates the resulting structure after removal of the remaining photoresist 6.
As illustrated by the broken lines at the edges of the source and drain 51 and 52 adjacent to the insulated~gate structure 3 and 4, the etch removal of the layer 5 at the window 14 may be continued until a small gap 53 appears between the edge~ of the gate structure and the facing edges of the source and drain 51 and 52. Alternatively the etching may be stopped when the source and drain layers 51 and 52 still abut the insulating layer 3, although care is then required to ensure that these layer~ 51 and 52 are etched back sufficiently as to avoid short-circuiting to the conductive gate 4. It is also possible for a silicon dioxide or other insulating layer to be deposited on the surface of the conductive gate 4 before the layer 5 so as to avoid any such short-circuit abutment of the source and drain 51 and 52 with the gate 4. Furthermore, such an inqulating layer may as3ist in the etch removal of the layer 5 from over the gate 4 when the gate 4 or layer 5 are of materials which are differen~ to those described above and for which selective etchant treatments are not so readily available.
The remaining source and drain parts interface with the large-grain high-mobility material at the upper face of the film 2 -, : ,, ,; - . ,: :
., ~ . ; ,- . .
20722~4 extending laterally beyond the insulated-gate structure 3 and 4.
This arrangement provides a goo~ and reliable electrical connection between the TFT channel and the source and drain 51 and 52. The sheet resistance of the source and drain layers 51 and 5Z may be reduced if ~esired by a laser anneal. Because the source and drain 51 and 52 are formed using the gate 4 as a photomask, the gate-to-source and gate-to-drain capacitances are very low, ~or example less than about 2 x 10-16F per ~m of channel width, 90 permitting fast operation of this high-mobility polycrystalline silicon TFT in, for example, column driver circuits of LCDs.
The further extent of the source and drain layers 51 and 52 are then defined in a further photolithographic and etching step, An insulating overlay 8 i8 subsequently deposited, and metal connections 41,42,44 respectively to the source, drain and gate 51,52 and 4 are provided. Gate connection 44 is outside the plane of the drawings and so is not illustrated in any of the Figures.
With high drain bias (for example with drain voltages of above 15 voltq) a localised high electric field region can be formed in the channel edge adjacent the drain 52. Charge carriers in this high field can attain kinetic energies in excess of a few eV and so may be injected over the interfacial potential barrier between the film 2 and the gate oxide 3. This carrier injection can cause degradation of the TFT characteristics, such as a reduction in transconductance or a ~hift in threshold voltage. As already described with reference to Figures 3 and ~, the conductive layer 5 at the window 14 can be etched back to such an extent that a small gap 53 i9 present between the facing edges of the drain 52 and the insulated-gate structure 3 and 4. This gap can assist in reducing the high field in this area and 90 reducing hot-carrier injection.
However, an even more advantageous structure can be obtained using a modified process which is also in accordance with the present invention. In this modified process the doping of the conductive layer 5 changes through the thic~ness of the layer 5 so as to be less in a lower part 55 than it is in a highly conductive upper part 56. The doping level may be varied progressively during .,., ,; . :
. . :
~722~
14 PH$33727 the deposition of the layer S, or the layer 5 may be deposited as two superimpo~ed layers 55 and 56 of different doping levels.
After removing the layers or layer parts 55 and 56 from over the gate 4, the upper part 56 is in this case etched away Erorn ~he lower part 55 at an area A at least at the drain side of the gate 4 so as to space the higher-conductance upper part 56 of the drain 52 laterally from the channel by a lower-doped part 55 of the layer 5. The resulting structure i~ illustrated in Figure 6.
The area A over which the upper part 56 is etched away may be defined using a separate photoma9k and requiring an extra alignment step. However, it is also possible to use the insulated-gate structure 3,4 as the photomas~, by illuminating the photoresist at such an angle that the insulated-gate structure 3,4 shadow-masks an area of the photoresist at the drain side of the gate 4. This is illustrated by the arrows 26 in Figure 6. The angled illumination 26 may be used instead of the perpendicular illumination 25 of Figure 3 so that the window 14 formed in the negative photoresist 6 is shifted laterally towards the drain. The etching away of the upper part 56 from the lower part 55 may then be effected through this window 14 by continuation of the etching step(s) to remove the layert 9 ) 55 and 56 from over the gate 4. However this variation in the photolithographic and etching process steps of Figures 3 and 4 can be difficult to reproduce reliably in a manufacturing process, and so preferably the angled illumination 26 is carried out in a separate photolithographic Rtep after the steps of Figures 3 and 4.
Figure 7 illustrates such a separate step in which a new negative photomask 16 i9 coated on the Figure 4 structure, the conductive layer 5 of which has the di~ferent doping levels of 55 and 56. The exposed photoresist 16 is then slightly overdeveloped 39 so as ts form a widened window 15 at the unexposed area which was shadow-masked by the gate 4. Figure 7 illustrates the resulting structure before carrying out the etching step to remove the exposed higher-doped upper part 56 rom the lower part 55 at the drain side of the insulated-gate structure 3 and 4. If desired a selective etchant may be used which at~acks the higher doped :
--` 20722~
material more rapidly than the lower doped material.
Instead of using a second photolithographic step wi~h a negative photoresist 16, a step wi~h a positive photoresist 11 ma~
be used as illustrated in Figure 8. In this case, the positlve photoresist i9 exposed by illuminating its upper face at a ~uitable angle (arrows 27) for the insulated gate 4 to shadow-mask the resist 17 over an area at the drain slde. The original coating of positive resist 17 i9 shown in broken outline in ~igure 8, which also shows in solid outline the shadow-mas~ed area of the resist 17 which remains after developing the exposed photoresist. This remaining resist area 17 is then used in a lift-off process to form a complementary mask 28 on the surrounding area. The mask 28 i~
formed by depositing a layer of gold for example and then dissolving the remaining resist area 17 to float off the overlying part of gold layer. The mask 28 i~ then used to protect the underlying surrounding area while etching away the upper part 56 from the lower part 55 at the drain side of the insulated gate 3 and 4. Figure 9 shows the resulting structure before removal of the mask 28.
The manufacture of n channel TFTs has been illustrated with reference to ~he drawings. However, the invention may also be used in the manufacture of p channel devices, having p type source and drain 51 and 52. The source and drain layers 51 and 52 may even be metallic, for example of indium-tin~oxide, in which case the deposition of an insulating layer on the gate 4 before depositing the metallic layer S can be desirable to facilitate the etch-removal of the layer 5 from over the gate 4.
From reading the pre~ent disclosure, other variations and modifications will be apparent to persons skilled in the art. Such variations and modifications may involve equivalents and other features which are already known in the design, manufacture and use of TFTs and other semiconductor devices and component parts thereof, and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of :, - -,: :
2~722~4 features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relate~
to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.
; ~5
Claims (10)
1. A method of manufacturing an insulated-gate thin-film transistor comprising a semiconductor film which provides a transistor channel adjacent to an insulated gate between source and drain of the transistor, the source and drain being formed from a conductive layer which is removed from over the gate using a photolithographic step, in which step the gate serves as a photomask while exposing a negative photoresist on the conductive layer by illumination through a transparent substrate, which method is characterised by the steps of:
(a) depositing material for the semiconductor film, on the substrate, (b) forming the insulated gate at the upper face of the semiconductor film, which face is remote from the substrate, (c) depositing the conductive layer on the insulated gate and on the semiconductor film beside the insulated gate, (d) coating the conductive layer with the negative photoresist, and effecting the photolithographic step by exposing the photoresist through the combination of the substrate, semiconductor film and conductive layer which together are transparent to the illumination, and (e) removing the conductive layer from over the gate so as to leave separate parts of the conductive layer on the semiconductor film at opposite sides of the insulated gate, for forming the source and drain of the transistor.
(a) depositing material for the semiconductor film, on the substrate, (b) forming the insulated gate at the upper face of the semiconductor film, which face is remote from the substrate, (c) depositing the conductive layer on the insulated gate and on the semiconductor film beside the insulated gate, (d) coating the conductive layer with the negative photoresist, and effecting the photolithographic step by exposing the photoresist through the combination of the substrate, semiconductor film and conductive layer which together are transparent to the illumination, and (e) removing the conductive layer from over the gate so as to leave separate parts of the conductive layer on the semiconductor film at opposite sides of the insulated gate, for forming the source and drain of the transistor.
2. A method as claimed in claim 1, further characterised in that the film material is deposited in a fine-grain or amorphous form in step (a), and in that this deposited material is annealed on the substrate before step (b) so as to crystallize the film at least adjacent to its upper face which is remote from the substrate.
3. A method as claimed in claim 2, further characterised in that the deposited material is annealed in a furnace by heating on the substrate.
4. A method as claimed in claim 2, further characterised in that the deposited material is annealed by irradiating its upper face with an energy beam, for example a laser beam.
5. A method as claimed in claim 4, further characterised in that the annealing is carried out with ultra-violet radiation from a laser.
6. A method as claimed in claim 5, further characterised in that the thickness of the film deposited on the substrate is larger than the absorption depth of the ultra-violet radiation in the semiconductor material.
7. A method as claimed in any one of claims 2 to 5, further characterised in that the step (b) includes providing an insulating layer at the crystallized upper face of the film and depositing a gate layer on the insulating layer.
8. A method as claimed in any one of the preceding claims, further characterised in that the conductive layer is of doped semiconductor material having a lower doping level in a lower part of the layer below an upper part of higher conductance, and in that, after removing the conductive layer from over the gate, the upper part is etched away from the lower part at an area at least at the drain side of the gate so as to space the higher conductance upper part of the drain laterally from the channel by a lower-doped part of the conductive layer.
9. A method as claimed in claim 8, further characterised in that a second photolithographic step using negative photoresist is used to define the area at which the upper part of the conductive layer is etched away from the lower part, the negative photoresist in the second photolithographic step being exposed by illumination through the substrate at such an angle that the insulated gate shadow-masks the photoresist over an area of the conductive layer at the drain side of the insulated gate.
10. A method as claimed in claim 8, further characterised in that a photolithographic step using a positive photoresist is used to define the area at which the upper part of the conductive layer is etched away from the lower part, the positive photoresist being exposed by illuminating its upper face which is remote from the substrate at such an angle that the insulated gate shadow-masks the photoresist over the area of the conductive layer at the drain side of the insulated gate, and in that the shadow-masked area of the photoresist remains after developing the exposed photoresist and is used in a lift-off process to form a complementary mask on the surrounding area for protecting the surrounding area while etching away said upper part of the conductive layer at the drain side of the insulated gate.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB919114018A GB9114018D0 (en) | 1991-06-28 | 1991-06-28 | Thin-film transistor manufacture |
| GB9114018.6 | 1991-06-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2072264A1 true CA2072264A1 (en) | 1992-12-29 |
Family
ID=10697510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002072264A Abandoned CA2072264A1 (en) | 1991-06-28 | 1992-06-25 | Thin-film transistor manufacture |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US5264383A (en) |
| EP (1) | EP0523768B1 (en) |
| JP (1) | JPH05190568A (en) |
| KR (1) | KR100260063B1 (en) |
| CA (1) | CA2072264A1 (en) |
| DE (1) | DE69216311T2 (en) |
| GB (1) | GB9114018D0 (en) |
| TW (1) | TW232088B (en) |
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| US5372836A (en) * | 1992-03-27 | 1994-12-13 | Tokyo Electron Limited | Method of forming polycrystalling silicon film in process of manufacturing LCD |
| JPH06124913A (en) * | 1992-06-26 | 1994-05-06 | Semiconductor Energy Lab Co Ltd | Laser treatment |
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| JP3497198B2 (en) | 1993-02-03 | 2004-02-16 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device and thin film transistor |
| US5985741A (en) * | 1993-02-15 | 1999-11-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of fabricating the same |
| EP1119053B1 (en) * | 1993-02-15 | 2011-11-02 | Semiconductor Energy Laboratory Co., Ltd. | Method for fabricating TFT semiconductor device |
| US6997985B1 (en) | 1993-02-15 | 2006-02-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor, semiconductor device, and method for fabricating the same |
| US6875628B1 (en) * | 1993-05-26 | 2005-04-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and fabrication method of the same |
| JP3450376B2 (en) | 1993-06-12 | 2003-09-22 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
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-
1991
- 1991-06-28 GB GB919114018A patent/GB9114018D0/en active Pending
-
1992
- 1992-05-12 TW TW081103693A patent/TW232088B/zh active
- 1992-06-19 DE DE69216311T patent/DE69216311T2/en not_active Expired - Fee Related
- 1992-06-19 EP EP92201808A patent/EP0523768B1/en not_active Expired - Lifetime
- 1992-06-23 US US07/902,642 patent/US5264383A/en not_active Expired - Fee Related
- 1992-06-25 KR KR1019920011070A patent/KR100260063B1/en not_active IP Right Cessation
- 1992-06-25 CA CA002072264A patent/CA2072264A1/en not_active Abandoned
- 1992-06-25 JP JP4167813A patent/JPH05190568A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| EP0523768A2 (en) | 1993-01-20 |
| DE69216311T2 (en) | 1997-06-12 |
| KR100260063B1 (en) | 2000-07-01 |
| TW232088B (en) | 1994-10-11 |
| JPH05190568A (en) | 1993-07-30 |
| DE69216311D1 (en) | 1997-02-13 |
| EP0523768A3 (en) | 1993-06-16 |
| GB9114018D0 (en) | 1991-08-14 |
| US5264383A (en) | 1993-11-23 |
| KR930001504A (en) | 1993-01-16 |
| EP0523768B1 (en) | 1997-01-02 |
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