CA2074529A1 - Chip interconnect with high density of vias - Google Patents
Chip interconnect with high density of viasInfo
- Publication number
- CA2074529A1 CA2074529A1 CA002074529A CA2074529A CA2074529A1 CA 2074529 A1 CA2074529 A1 CA 2074529A1 CA 002074529 A CA002074529 A CA 002074529A CA 2074529 A CA2074529 A CA 2074529A CA 2074529 A1 CA2074529 A1 CA 2074529A1
- Authority
- CA
- Canada
- Prior art keywords
- substrate
- posts
- solder
- set forth
- wells
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0364—Conductor shape
- H05K2201/0367—Metallic bump or raised conductor not used as solder bump
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S428/00—Stock material or miscellaneous articles
- Y10S428/901—Printed circuit
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49149—Assembling terminal to base by metal fusion bonding
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/53—Means to assemble or disassemble
- Y10T29/5313—Means to assemble electrical device
- Y10T29/53174—Means to fasten electrical component to wiring board, base, or substrate
Abstract
A solder interconnection for forming vias between first and second substrates (12, 14) comprises a plurality of solder containing wells (16) extending into a flat surface (18) of the first substrate (12), the solder (20) in each well (16) being soldered to one of a corresponding plurality of conductor posts (22) extending outwardly from a flat surface (23) of the second substrate (14).
The plurality of the wells (16) are created in a pattern, an aliquot of solder (20) is deposited in each well (16), with the aliquot being of substantially no greater volume than that of the well (16) it occupies, the posts (22) are provided in aligned array with the pattern, the solder (20) is melted, the posts (22) are inserted and the solder (20) solidifies. Very closely placed vias can be formed.
The plurality of the wells (16) are created in a pattern, an aliquot of solder (20) is deposited in each well (16), with the aliquot being of substantially no greater volume than that of the well (16) it occupies, the posts (22) are provided in aligned array with the pattern, the solder (20) is melted, the posts (22) are inserted and the solder (20) solidifies. Very closely placed vias can be formed.
Description
. . .
~ r ~ L ~ ~ ~
~e~cri~tion CHI~I NTERCQNN~ W~ JlLg~-2E~slTy OF VI~
The present invention relates to interconnection structures for joinlng a microminiaturized CompQnent on one substrate ~o circuitry on another sub~tratë, and, more particularly, to a structurë for forming solder - ~ i~terconnection joints having improved fatigue life and being ~ery close together as well as to a method of making such interconnection structures.
; ", j . , . , -, , . . . . . ..
~ackq~ound^O~ ThQ_Inv.ention : - ~ ` Usë of solder interconnectlon structures for -joining'semiconductor devices to substrates is : ----relatively we'll known in the art. U.S. Patent - 4,'604,644, i6sued August 5, 1986 to R.F. ~eckham, A.E.~Rolman, ~.M; McGuire, K.J. Puttlit~ and H.
., ,,, , . .. j . . ..... ... .. . . . .
.. ~ -- Quinones, show~ one such solder interconnect :~ 25 structur~. Th~ solder lnterconnection ~tructure of ... . , - . ~ .
.
:: - : ~ : ' ' .. :~
. . . . . . . . . ..
~ r ~ L ~ ~ ~
~e~cri~tion CHI~I NTERCQNN~ W~ JlLg~-2E~slTy OF VI~
The present invention relates to interconnection structures for joinlng a microminiaturized CompQnent on one substrate ~o circuitry on another sub~tratë, and, more particularly, to a structurë for forming solder - ~ i~terconnection joints having improved fatigue life and being ~ery close together as well as to a method of making such interconnection structures.
; ", j . , . , -, , . . . . . ..
~ackq~ound^O~ ThQ_Inv.ention : - ~ ` Usë of solder interconnectlon structures for -joining'semiconductor devices to substrates is : ----relatively we'll known in the art. U.S. Patent - 4,'604,644, i6sued August 5, 1986 to R.F. ~eckham, A.E.~Rolman, ~.M; McGuire, K.J. Puttlit~ and H.
., ,,, , . .. j . . ..... ... .. . . . .
.. ~ -- Quinones, show~ one such solder interconnect :~ 25 structur~. Th~ solder lnterconnection ~tructure of ... . , - . ~ .
.
:: - : ~ : ' ' .. :~
. . . . . . . . . ..
2~r,l~hs~,s W09l/11833 PCr/US91/0035 the aforementioned patent, as well as other solder interconnection structures of the art, u~ilize beads o~ ~older whlch fit upon the ~urface of a 6ub~rate and which are solderably attached to solder-wettable land pad~ via melting of the solder when the solder is in contact with the land pads.
The solder int~rconnection structures of the prior art can flow laterally along the surfaces of the two sub6trates which are being joined together when the interconnects or vias are formed. This limits how close together the vias are, or, as the term is used in the art, the density of vias attainable, With integrated circuit semiconductor devices being produced in smaller and smaller sizes the need for a very high density of vias, beyond that of the prior art, becomes increasingly important.
It is also desirable to very carefully control where vi~s are to be positioned. When drops c,f solder are deposited on a surface a small misplacement of one or more such drops can oc~ur. As a result, any final device which results from soldering, and thereby forming vias between two substrates, can fail simpiy due to the mi~placement of a drop of soldér on a surface.
The present invention is directed to overcomi~g one or morë of the problems as set forth ' ~ a~ove.
.. ' ''. ' ~ 7 ,'; j ' , ,; r., ~isclosùre Qf Inven~iQn ~ 30 I~ accordance with an embodiment of the -~ present lnvention a solder interconnection is set forth ~or forming I/0 (input/output) electrical connectlons between a first 6ubstrate and ; ,écond substrate. The intérconnection includes a plurality of soider contalning wella extending into a flat sur~'ace Of thé first substrate. ~he soldér in each . .. ~
., : , , ,, :
' .. . .
'. , ' ' :
~091/11833 '',,~'' ,'~ ,PCT/US91/00359 of the wells iq ln soldered contact with one of a corresponding plurality of conductive po~ts whlch extend ou~wardly from a flat surface of the second ~ub6trate.
In accordanee with another embodiment of the present inv,ention a method is set forth for forming a plurality of solder I/0 connections between a first substrate and a second substrate. A plurality of wells is created arrayed in a pattern and with each ,' well extending into the first substrate from a flat surface thersof. A plurality of aliquots of solder are deposited, one in each of the wells, each of the aliquots being of substantially no greater volume than that of the respective well it occupies. A
plurality of conductive posts are provided which extend outwardly from a flat surface of the 6econd sub~trate. The posts are arrayed in alignment with the pattern of the wells. The first substrate is hea~ed adjacent its flat surface sufficiently to melt ,the solder in the wells. Each post is inserted into ~, the molten solder,in the corresponding well and the ~,~ solder is allowed to solidify.
'~ A solder interconnection as set forth above ~., , . .., . , _ , ... ... .. . . .
ca~,havs a very high de~sity,of vias between the ,-~ 25 first substrate and the second substrate.- Sinee the ,, , _ , '',- , solder is posltloned-,in.wells,there,:is an assurance ,of proper alignment of the,solder,in each one of the ~"~ wells,,with the, re~pective,post to-which it,is in " ~oldered contact., ,Since;each dropj,of solder:is ~ 30 retained by,a~respective.-~ell solder,flow:along the ;~' facing~,~urfaces,.of3the;substrates:cannot occur.
,,whereby~ horting,between~vias is prevented.i-A-''',~ polymer~ for;exa~plq/ an epoxy resinican;, , ,~, , ~ advantageously ba,~applied,between.the two,~wafers to ~urther reduc~the pos~ibi,lity,o~-metal-flowing laterally between the,surfaces, to prevent-fluid from :, . , ,, . .. ., , ,, ~, . , .. ~ ..... . .. .
W091/11833 2~ PCT/US91/003 flowlng between the ~ub6trates if the solder interconnection is immer6ed in a fluid and to reduce the crl,icality of alignment of the su~strates.
,Brie~ Descri~tion Of_The_Drawinus The invention will be better understood b~
. reference to the figures of the drawings wherein like numbers denote like parts throughout and wherein:
-: Figure 1 illu~tra~es, in cro~s-sectional view, a first substrate in accordance with an -, embodiment of ths present invention, Figure 2 illustrate, in cross-sectional view, a second substrate in accordance with an e~bodiment of-the present invention, the Figure 1 and ' 15 Figure 2 substrates being adapted to fit together to '~ form a solder interconnection in accordance with an . e~bodiment of the:pre ent inventio~; and' ; ~ .
Figure 3 illustrates, in cross-~ectional .` view, an alternative solder interconnection joining .-- 20 ... ..together first and second substrates in accordance '`, . with:another embodi~ent of the present inven~ion.
,,~ .. :. e~t-Mode For C~ying Out Inven~iQn ~ ' In'accordance;with the prèsent-invention a '~' 25 ~ 7solder interconnectioa lO is set-forth for forming ~` - . I/O.interconnections betwsen a first substrate 12 :r..J "~and~a second substrate 14.- There?are a pluraiity of .~solder'-containing'weIls'rl6"which extend lnto a flat ~` surface.~l8^of':thé first~substraté~-12.- A`~drop'20 of ~: 3O?f~:J solder~ located in each'of'thè wells 16.' ;-As-' illustrated''in'Figure 3~thé'drops'i20 oflsoldër~'in each of~the'~wells 16 i's'in'solderéd'contact''with one ..... . . .. . .
: of a corresponding'-'pluralityiof-electrically'-''~~
o~ conductiv'e'posts-'22 whicX~extend outwardly'from a fIat'isurfac'e'i23 of the secio'nd-substrate 14.'' The term ~ second~substrate 14 is used to'lncïude a~dieléctric - , ., .. . , ~. , :
. . . . . .. .
, . . ~: ;
.
Z~
~`'091/llX33 PCT/USgl/00359 ~ayer 24, e.g., silicon dioxide, nitride or oxynitride. The flat surfaces 18 and 23 are, in the embodlment of Figure 3, ln abuttins relatlon to one another following formation of the solder interconnection 10. In such an instance, each of the posts 22 must extend no further from the flat surface 23 of the second substrate 14 than the corresponding well 16 extends into the flat surface 18 of the first substrate 12. If desired, the flat surfaces 18 and 23 may be in adjacent but non-touching relationship.
Figures l and 2 illustrate an embodiment ', where an intermediate polymeric layer 25 is deposited over one of the flat surfaces 18 and 23 (as shown in ~' , Figure 1 the layer 25 i's on the flat surace 23).
lS The layer 25 can serve to increase the effective size of the wells l6-whether it is initially present on the surface 23, as illustrated, or on the surface 18.
~'~ When the substrates l2 and l4 are brought together ~', with the formation of the solder interconnection lO
~, 20 the layer 25,is then present and aids in preventing ,; , flow of molten solder along the abutting surfaces.
~' ,,, It.also prevents fluid from,flowing.laterally-,between th~ substrates 12-~and 14 if the solder' nterconnection 10 is immersed. Since the layer 25 is polymeric it has some give,thus-,alleviating''-' stresses whereby,alignment~of:the,surfaces 18 and 23 '~ becomes less critical.,,,-;, f~
-' ,~ ,,, . ~rhe po,lymeric layer 25,' when'present;' must be a~good~insulator so~as to~no,-conductively~
interconnect,~,oneOpost,22-;orisolder drop 20^with':~
another.,iGeneral,,ly,the polymeric:layer -25 is:' - ~ adhesi,ve-sor,as,Jto,,better hold~together th~ substrates -i,, i2~and 14,.J-,-.~P,,ref,erably~the.-jlayer~:25 is-suffi'ci~eT~tly ' flexible,,o,r,deformable!~o~as to~allow ~correction'~for ; any,lack,o~,planarity,or,~misalignment o~ the surfaces 18 and 23. ~The,particular polymer~u~ed is''a matter . . .. ... .
W091/11833 2 ~ ,9 PCT/US91/0035 of choice al~hough epoxy compounds have been found to work very well.
The polymer layer 25 can be formed by any o_ a number of ~echniques. For example, lf the posts 22 have reasonably sharp points 27 as illustrated, spin . casting, palnting or dipping the surface 23 will provide the desired layer 25 with the points 27 ..
extending through the layer 25. If'the posts 22 do . not have points 27, it is best to use silk'screening techniques to assure that ~he pOfits 22 extend beyond the layer 25.
Utilizing anisotropic etching technology or - laser drilling technology .the wells 16 can be placed very close to one another. For example, the spacing , 15 on a center-to-center.basis of the wells 16 can be :` . less than 100 microns and can generally be as small . .
i . ,as 50 microns.
: Each of the drops 20 of solder in each of 3the wells 16 is of substantially, no greater volume ~'.,20 ~ than.th~ effective volume of the respective well 16 ~'.which it;occupies. :As a result, solder:cannot flow ~,'laterally,along-thé' surfaces'18 and''2~:when-they are :~abutting whereby the resulting~interconnects or vias ~;~ r formed in the structure--shown in Figure'3 can be ~' 25 quite close together;'., -~
;' ; ,; ,, ,j In~the?particular embodiment shown in' ~:
Figures 1 and 2 the solder 20'connects~`to an : .... elec,tro,de.~,26lat the bottom-of-a'.'mic'roelectrochemical well~28..or-~n~,opposite ~urface-30 of~`'the-first-^
substrateel2; --An,~appropriate';insu'l'ati`ng'"laye'r~32, for,example;~:silicon-dioxide',':silicon'-nitride-or -silicon.i,oxynitride,~.can be-cbnventi`onally''iformëd to electrically. isolate,~the'3first subs~tratè 12 frôm the ~ co,nductor;26,~where desired-and~n`eb'ess''ary'.'~ The 35 ~ ,resulting.product~.i3.a~icroelectroche'mlcal~ceil 33.~' ,;The presence o~:the polymeric'1ayer'l25 i8 -. : ,,, , : , ,. `
2~7 ~9 ~O9lJ~1833 PCT/US91/0035g ..
particularly advantageous wi~h the microelectrochemical cell 33 since the cell 33 may then be immersed in a fluid to measure d_ssolved analytes without fear of leakage of the luid betwsen the substrates 12 and 14.
It should be noted that insteac of tne microelectrochemical cell 33 as i~ showr. in Figure 1 the conductor 26 can lead to any desired device, for example, an integrated circuit. Similarly, the posts - 10 22 can be interconnected with any de~ired device on the second substrate 14, for example, an integrated circuit.
In accordance with the present invention the posts 22 can be created by a modified bu~p bonder of the type commonly used in semiconductor fabrication.
Basically, molten metal is connected to desired spots ~ on the substrate 14 and the bump bonder and the `~ substrate 14 are moved apart thus drawing out and forming the posts 22 as the molten metal solidifies ~ 20 and thereby also providing the points 2?. Any - desired metal which can be drawn in this manner and which~is sufficiently conductive can be used.~ Gold `~ works particularly well. - .
I~ The first and second substrates 12 and 14 .. 25 can be made of.any of a number of materials. For -- example, the substrate may be made of an-.insulatiYe material., that is, a dielectric material;~.-such as a ~` non-conducting plastic or glass,jif,-~for example, the microelectronic co~ponent on the particular substrate 12 or 14 i6 a microelectrochemical cell or half~cell which must be electrically isolated.
`~ Alternatively,~the substrate can-be made of a semiconducting-material such as sil-icon or-even of a : WO9l/11~33 PCT/US91/003S,9~
2~ h~. ~9 8 conducting material so long as an apprcrriate dlelectric mater;al isola~es the microe_ec~ron:c co~ponent, where neces~ary.
In accordance with the method of the invention a plurality of 601der I~O connections are provided betw~en the f1rst ~ubstrate 12 a~d th~
second substrate 14. The method of formation .~ :. comprises creating a plurality of the wells 16 ` -- arrayed in a pattern and with each well 16 extending ~: 10 into the first substrate 12 from its flat surface 18.
A plurality of aliquots or drops 20 of solder are deposited, one in each of the wells 16. Each of the . aliquots or drops 20 are of substantially no greater . volume than the volume of the respective well 16 .` 15 which it occupies. A plurality of conductive posts :~ 22 are provided which extend outwardly from the flat surface 23 of the second substrate 14. The posts 22 ; are arrayed in alig~ment with the pattern of the wells 16. The first substrate 12 is heated . 20 sufficiently to melt the solder in the wells 16.
;. Each post 22 is inserted into the molten solder in the corresponding one of the wells 16. The solder is . then allowed to eolidify whereby the solder ~ _ interconnection.10-is completed.
... ~ 25 ~ .In accordancç with an embodiment of-the :' . invention a polymeric layer 25 can:be positio~ed .. , . between the.flat.. surfaces 18 and 23 prior to the insertion of.the posts -22-in the molten solder in the In~ustriaL_a~licability -The present!invention provides a solder interconnection 10-for connecting together`-:;';
subRtrates, ~or exam~le silicon substrates, whereby a plurality of I/O connectlon~ can be made between two substrates 12 and 14. Such ls useful far .. . . .
, ~.. ;
.
~091/11833 PCT/US91/00359 " . , .
interconnectlng integrated circuits and in ~he formation of microelectrochemical sensors and thelr interconnection with integrated clrcuits on a seconc ` substrate 1~. The vias between the first substrate -~ 5 12 and the second substrate 14 can be made very close together in accordance with the invention.
While the invention has been described in connection with specific embodiments thereof, it will be understood that it is capable of further ; 10 modificatio~, and this application is intended to cover any variations, use5, or adaptations of the invention following, in general, the principles of the invention and including ~uch departures from the ~: present disclosure as come within known or customary practice in the art to which the invention pertains and as may be applied to the essential features r ~ hersinbefore set forth, and a~ fall within the scope -' of the invention and the limits of the appended ~ claims.
, ~ .
~`' ' . ~
.. ~` .
.. :;
. .' :' ' ,. : . , ", ,' ':~
The solder int~rconnection structures of the prior art can flow laterally along the surfaces of the two sub6trates which are being joined together when the interconnects or vias are formed. This limits how close together the vias are, or, as the term is used in the art, the density of vias attainable, With integrated circuit semiconductor devices being produced in smaller and smaller sizes the need for a very high density of vias, beyond that of the prior art, becomes increasingly important.
It is also desirable to very carefully control where vi~s are to be positioned. When drops c,f solder are deposited on a surface a small misplacement of one or more such drops can oc~ur. As a result, any final device which results from soldering, and thereby forming vias between two substrates, can fail simpiy due to the mi~placement of a drop of soldér on a surface.
The present invention is directed to overcomi~g one or morë of the problems as set forth ' ~ a~ove.
.. ' ''. ' ~ 7 ,'; j ' , ,; r., ~isclosùre Qf Inven~iQn ~ 30 I~ accordance with an embodiment of the -~ present lnvention a solder interconnection is set forth ~or forming I/0 (input/output) electrical connectlons between a first 6ubstrate and ; ,écond substrate. The intérconnection includes a plurality of soider contalning wella extending into a flat sur~'ace Of thé first substrate. ~he soldér in each . .. ~
., : , , ,, :
' .. . .
'. , ' ' :
~091/11833 '',,~'' ,'~ ,PCT/US91/00359 of the wells iq ln soldered contact with one of a corresponding plurality of conductive po~ts whlch extend ou~wardly from a flat surface of the second ~ub6trate.
In accordanee with another embodiment of the present inv,ention a method is set forth for forming a plurality of solder I/0 connections between a first substrate and a second substrate. A plurality of wells is created arrayed in a pattern and with each ,' well extending into the first substrate from a flat surface thersof. A plurality of aliquots of solder are deposited, one in each of the wells, each of the aliquots being of substantially no greater volume than that of the respective well it occupies. A
plurality of conductive posts are provided which extend outwardly from a flat surface of the 6econd sub~trate. The posts are arrayed in alignment with the pattern of the wells. The first substrate is hea~ed adjacent its flat surface sufficiently to melt ,the solder in the wells. Each post is inserted into ~, the molten solder,in the corresponding well and the ~,~ solder is allowed to solidify.
'~ A solder interconnection as set forth above ~., , . .., . , _ , ... ... .. . . .
ca~,havs a very high de~sity,of vias between the ,-~ 25 first substrate and the second substrate.- Sinee the ,, , _ , '',- , solder is posltloned-,in.wells,there,:is an assurance ,of proper alignment of the,solder,in each one of the ~"~ wells,,with the, re~pective,post to-which it,is in " ~oldered contact., ,Since;each dropj,of solder:is ~ 30 retained by,a~respective.-~ell solder,flow:along the ;~' facing~,~urfaces,.of3the;substrates:cannot occur.
,,whereby~ horting,between~vias is prevented.i-A-''',~ polymer~ for;exa~plq/ an epoxy resinican;, , ,~, , ~ advantageously ba,~applied,between.the two,~wafers to ~urther reduc~the pos~ibi,lity,o~-metal-flowing laterally between the,surfaces, to prevent-fluid from :, . , ,, . .. ., , ,, ~, . , .. ~ ..... . .. .
W091/11833 2~ PCT/US91/003 flowlng between the ~ub6trates if the solder interconnection is immer6ed in a fluid and to reduce the crl,icality of alignment of the su~strates.
,Brie~ Descri~tion Of_The_Drawinus The invention will be better understood b~
. reference to the figures of the drawings wherein like numbers denote like parts throughout and wherein:
-: Figure 1 illu~tra~es, in cro~s-sectional view, a first substrate in accordance with an -, embodiment of ths present invention, Figure 2 illustrate, in cross-sectional view, a second substrate in accordance with an e~bodiment of-the present invention, the Figure 1 and ' 15 Figure 2 substrates being adapted to fit together to '~ form a solder interconnection in accordance with an . e~bodiment of the:pre ent inventio~; and' ; ~ .
Figure 3 illustrates, in cross-~ectional .` view, an alternative solder interconnection joining .-- 20 ... ..together first and second substrates in accordance '`, . with:another embodi~ent of the present inven~ion.
,,~ .. :. e~t-Mode For C~ying Out Inven~iQn ~ ' In'accordance;with the prèsent-invention a '~' 25 ~ 7solder interconnectioa lO is set-forth for forming ~` - . I/O.interconnections betwsen a first substrate 12 :r..J "~and~a second substrate 14.- There?are a pluraiity of .~solder'-containing'weIls'rl6"which extend lnto a flat ~` surface.~l8^of':thé first~substraté~-12.- A`~drop'20 of ~: 3O?f~:J solder~ located in each'of'thè wells 16.' ;-As-' illustrated''in'Figure 3~thé'drops'i20 oflsoldër~'in each of~the'~wells 16 i's'in'solderéd'contact''with one ..... . . .. . .
: of a corresponding'-'pluralityiof-electrically'-''~~
o~ conductiv'e'posts-'22 whicX~extend outwardly'from a fIat'isurfac'e'i23 of the secio'nd-substrate 14.'' The term ~ second~substrate 14 is used to'lncïude a~dieléctric - , ., .. . , ~. , :
. . . . . .. .
, . . ~: ;
.
Z~
~`'091/llX33 PCT/USgl/00359 ~ayer 24, e.g., silicon dioxide, nitride or oxynitride. The flat surfaces 18 and 23 are, in the embodlment of Figure 3, ln abuttins relatlon to one another following formation of the solder interconnection 10. In such an instance, each of the posts 22 must extend no further from the flat surface 23 of the second substrate 14 than the corresponding well 16 extends into the flat surface 18 of the first substrate 12. If desired, the flat surfaces 18 and 23 may be in adjacent but non-touching relationship.
Figures l and 2 illustrate an embodiment ', where an intermediate polymeric layer 25 is deposited over one of the flat surfaces 18 and 23 (as shown in ~' , Figure 1 the layer 25 i's on the flat surace 23).
lS The layer 25 can serve to increase the effective size of the wells l6-whether it is initially present on the surface 23, as illustrated, or on the surface 18.
~'~ When the substrates l2 and l4 are brought together ~', with the formation of the solder interconnection lO
~, 20 the layer 25,is then present and aids in preventing ,; , flow of molten solder along the abutting surfaces.
~' ,,, It.also prevents fluid from,flowing.laterally-,between th~ substrates 12-~and 14 if the solder' nterconnection 10 is immersed. Since the layer 25 is polymeric it has some give,thus-,alleviating''-' stresses whereby,alignment~of:the,surfaces 18 and 23 '~ becomes less critical.,,,-;, f~
-' ,~ ,,, . ~rhe po,lymeric layer 25,' when'present;' must be a~good~insulator so~as to~no,-conductively~
interconnect,~,oneOpost,22-;orisolder drop 20^with':~
another.,iGeneral,,ly,the polymeric:layer -25 is:' - ~ adhesi,ve-sor,as,Jto,,better hold~together th~ substrates -i,, i2~and 14,.J-,-.~P,,ref,erably~the.-jlayer~:25 is-suffi'ci~eT~tly ' flexible,,o,r,deformable!~o~as to~allow ~correction'~for ; any,lack,o~,planarity,or,~misalignment o~ the surfaces 18 and 23. ~The,particular polymer~u~ed is''a matter . . .. ... .
W091/11833 2 ~ ,9 PCT/US91/0035 of choice al~hough epoxy compounds have been found to work very well.
The polymer layer 25 can be formed by any o_ a number of ~echniques. For example, lf the posts 22 have reasonably sharp points 27 as illustrated, spin . casting, palnting or dipping the surface 23 will provide the desired layer 25 with the points 27 ..
extending through the layer 25. If'the posts 22 do . not have points 27, it is best to use silk'screening techniques to assure that ~he pOfits 22 extend beyond the layer 25.
Utilizing anisotropic etching technology or - laser drilling technology .the wells 16 can be placed very close to one another. For example, the spacing , 15 on a center-to-center.basis of the wells 16 can be :` . less than 100 microns and can generally be as small . .
i . ,as 50 microns.
: Each of the drops 20 of solder in each of 3the wells 16 is of substantially, no greater volume ~'.,20 ~ than.th~ effective volume of the respective well 16 ~'.which it;occupies. :As a result, solder:cannot flow ~,'laterally,along-thé' surfaces'18 and''2~:when-they are :~abutting whereby the resulting~interconnects or vias ~;~ r formed in the structure--shown in Figure'3 can be ~' 25 quite close together;'., -~
;' ; ,; ,, ,j In~the?particular embodiment shown in' ~:
Figures 1 and 2 the solder 20'connects~`to an : .... elec,tro,de.~,26lat the bottom-of-a'.'mic'roelectrochemical well~28..or-~n~,opposite ~urface-30 of~`'the-first-^
substrateel2; --An,~appropriate';insu'l'ati`ng'"laye'r~32, for,example;~:silicon-dioxide',':silicon'-nitride-or -silicon.i,oxynitride,~.can be-cbnventi`onally''iformëd to electrically. isolate,~the'3first subs~tratè 12 frôm the ~ co,nductor;26,~where desired-and~n`eb'ess''ary'.'~ The 35 ~ ,resulting.product~.i3.a~icroelectroche'mlcal~ceil 33.~' ,;The presence o~:the polymeric'1ayer'l25 i8 -. : ,,, , : , ,. `
2~7 ~9 ~O9lJ~1833 PCT/US91/0035g ..
particularly advantageous wi~h the microelectrochemical cell 33 since the cell 33 may then be immersed in a fluid to measure d_ssolved analytes without fear of leakage of the luid betwsen the substrates 12 and 14.
It should be noted that insteac of tne microelectrochemical cell 33 as i~ showr. in Figure 1 the conductor 26 can lead to any desired device, for example, an integrated circuit. Similarly, the posts - 10 22 can be interconnected with any de~ired device on the second substrate 14, for example, an integrated circuit.
In accordance with the present invention the posts 22 can be created by a modified bu~p bonder of the type commonly used in semiconductor fabrication.
Basically, molten metal is connected to desired spots ~ on the substrate 14 and the bump bonder and the `~ substrate 14 are moved apart thus drawing out and forming the posts 22 as the molten metal solidifies ~ 20 and thereby also providing the points 2?. Any - desired metal which can be drawn in this manner and which~is sufficiently conductive can be used.~ Gold `~ works particularly well. - .
I~ The first and second substrates 12 and 14 .. 25 can be made of.any of a number of materials. For -- example, the substrate may be made of an-.insulatiYe material., that is, a dielectric material;~.-such as a ~` non-conducting plastic or glass,jif,-~for example, the microelectronic co~ponent on the particular substrate 12 or 14 i6 a microelectrochemical cell or half~cell which must be electrically isolated.
`~ Alternatively,~the substrate can-be made of a semiconducting-material such as sil-icon or-even of a : WO9l/11~33 PCT/US91/003S,9~
2~ h~. ~9 8 conducting material so long as an apprcrriate dlelectric mater;al isola~es the microe_ec~ron:c co~ponent, where neces~ary.
In accordance with the method of the invention a plurality of 601der I~O connections are provided betw~en the f1rst ~ubstrate 12 a~d th~
second substrate 14. The method of formation .~ :. comprises creating a plurality of the wells 16 ` -- arrayed in a pattern and with each well 16 extending ~: 10 into the first substrate 12 from its flat surface 18.
A plurality of aliquots or drops 20 of solder are deposited, one in each of the wells 16. Each of the . aliquots or drops 20 are of substantially no greater . volume than the volume of the respective well 16 .` 15 which it occupies. A plurality of conductive posts :~ 22 are provided which extend outwardly from the flat surface 23 of the second substrate 14. The posts 22 ; are arrayed in alig~ment with the pattern of the wells 16. The first substrate 12 is heated . 20 sufficiently to melt the solder in the wells 16.
;. Each post 22 is inserted into the molten solder in the corresponding one of the wells 16. The solder is . then allowed to eolidify whereby the solder ~ _ interconnection.10-is completed.
... ~ 25 ~ .In accordancç with an embodiment of-the :' . invention a polymeric layer 25 can:be positio~ed .. , . between the.flat.. surfaces 18 and 23 prior to the insertion of.the posts -22-in the molten solder in the In~ustriaL_a~licability -The present!invention provides a solder interconnection 10-for connecting together`-:;';
subRtrates, ~or exam~le silicon substrates, whereby a plurality of I/O connectlon~ can be made between two substrates 12 and 14. Such ls useful far .. . . .
, ~.. ;
.
~091/11833 PCT/US91/00359 " . , .
interconnectlng integrated circuits and in ~he formation of microelectrochemical sensors and thelr interconnection with integrated clrcuits on a seconc ` substrate 1~. The vias between the first substrate -~ 5 12 and the second substrate 14 can be made very close together in accordance with the invention.
While the invention has been described in connection with specific embodiments thereof, it will be understood that it is capable of further ; 10 modificatio~, and this application is intended to cover any variations, use5, or adaptations of the invention following, in general, the principles of the invention and including ~uch departures from the ~: present disclosure as come within known or customary practice in the art to which the invention pertains and as may be applied to the essential features r ~ hersinbefore set forth, and a~ fall within the scope -' of the invention and the limits of the appended ~ claims.
, ~ .
~`' ' . ~
.. ~` .
.. :;
. .' :' ' ,. : . , ", ,' ':~
Claims (20)
1. A solder interconnection for forming I/O connections between a first substrate and a second substrate, comprising:
a plurality of solder containing wells extending into a flat surface of said first substrate, the volume of solder in each respective well being of substantially no greater volume than the volume of the respective well it occupies, the solder in each of said wells being in soldered contact with one of a corresponding plurality of conductive posts extending outwardly from a flat surface of said second substrate.
a plurality of solder containing wells extending into a flat surface of said first substrate, the volume of solder in each respective well being of substantially no greater volume than the volume of the respective well it occupies, the solder in each of said wells being in soldered contact with one of a corresponding plurality of conductive posts extending outwardly from a flat surface of said second substrate.
2. A solder interconnect as set forth in claim 1, wherein the spacing on a center-to-center basis of said wells is less than about 100 microns.
3. A solder interconnect as set forth in claim 1, wherein said first and second substrates each comprises silicon.
4. A solder interconnect as set forth in claim 1, wherein the flat surfaces are in abutting relation to one another.
5. A solder interconnect as set forth in claim 1, further including:
a polymeric layer intermediate and in abutting relation to said flat surfaces.
a polymeric layer intermediate and in abutting relation to said flat surfaces.
6. A solder interconnect as set forth in claim 5, wherein said posts have pointed tips.
7. A solder interconnect as set forth in claim 1, wherein said posts have pointed tips.
8. A method of forming a plurality of solder I/O connections between a first substrate and a second substrate, comprising:
creating a plurality of wells arrayed in a pattern, each well extending into said first substrate from a flat surface thereof;
depositing a plurality of aliquots of solder, one in each of said wells, each of said aliquots being of substantially no greater volume than that of the respective well it occupies;
providing a plurality of conductive posts extending outwardly from a flat surface of said second substrate, said posts being arrayed in alignment with the pattern of said wells;
heating said first substrate sufficiently to melt the solder in said wells;
inserting each post into the molten solder in the corresponding one of said wells; and allowing said solder to solidify.
creating a plurality of wells arrayed in a pattern, each well extending into said first substrate from a flat surface thereof;
depositing a plurality of aliquots of solder, one in each of said wells, each of said aliquots being of substantially no greater volume than that of the respective well it occupies;
providing a plurality of conductive posts extending outwardly from a flat surface of said second substrate, said posts being arrayed in alignment with the pattern of said wells;
heating said first substrate sufficiently to melt the solder in said wells;
inserting each post into the molten solder in the corresponding one of said wells; and allowing said solder to solidify.
9. A method as set forth in claim 8, wherein said wells are created by anisotropic etching.
10. A method as set forth in claim 9, wherein said posts are created by:
bump bonding metal to positions on said flat surface of said second substrate corresponding with the desired array of posts with a bump bonder; and moving said bump bonder and said second substrate apart to draw out said metal and form said posts.
bump bonding metal to positions on said flat surface of said second substrate corresponding with the desired array of posts with a bump bonder; and moving said bump bonder and said second substrate apart to draw out said metal and form said posts.
11. A method as set forth in claim 8, wherein said posts are created by:
bump bonding metal to positions on said flat surface of said second substrate corresponding with the desired array of posts with a bump bonder; and moving said bump bonder and said second substrate apart to draw out said metal and form said posts.
bump bonding metal to positions on said flat surface of said second substrate corresponding with the desired array of posts with a bump bonder; and moving said bump bonder and said second substrate apart to draw out said metal and form said posts.
12. A method as set forth in claim 8, wherein said first substrate includes an electrochemical sensor having an electrode in electrical conductive communication with said solder in said wells.
13. A method as set forth in claim 8, wherein said second substrate includes an integrated circuit having an electrode in electrical conductive communication with said posts.
14. A method as set forth in claim 8, wherein each of said posts extends no further from said flat surface of said second substrate than the aligned well extends into said flat surface of said first substrate and wherein said inserting is to a sufficient depth whereby said flat surfaces abut one another.
15. A method as set forth in claim 8, further including, before inserting said posts into the molten solder:
positioning a polymeric layer between said flat surfaces.
positioning a polymeric layer between said flat surfaces.
16. A method as set forth in claim 15, wherein said wells are created by anisotropic etching.
17. A method as set forth in claim 16, wherein said posts are created by:
bump bonding metal to positions on said flat surface of said second substrate corresponding with the desired array of posts with a bump bonder; and moving said bump bonder and said second substrate apart to draw out said metal and form said posts.
bump bonding metal to positions on said flat surface of said second substrate corresponding with the desired array of posts with a bump bonder; and moving said bump bonder and said second substrate apart to draw out said metal and form said posts.
18. A method as set forth in claim 15, wherein said posts are created by:
bump bonding metal to positions on said flat surface of said second substrate corresponding with the desired array of posts with a bump bonder; and moving said bump bonder and said second substrate apart to draw out said metal and form said posts.
bump bonding metal to positions on said flat surface of said second substrate corresponding with the desired array of posts with a bump bonder; and moving said bump bonder and said second substrate apart to draw out said metal and form said posts.
19. A method as set forth in claim 15, wherein said first substrate includes an electrochemical sensor having an electrode in electrical conductive communication with said solder in said wells.
20. A method as set forth in claim 15, wherein said second substrate includes an integrated circuit having an electrode in electrical conductive communication with said posts.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/470,622 US5056216A (en) | 1990-01-26 | 1990-01-26 | Method of forming a plurality of solder connections |
| US470,622 | 1990-01-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2074529A1 true CA2074529A1 (en) | 1991-07-27 |
Family
ID=23868340
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002074529A Abandoned CA2074529A1 (en) | 1990-01-26 | 1991-01-17 | Chip interconnect with high density of vias |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US5056216A (en) |
| CA (1) | CA2074529A1 (en) |
| WO (1) | WO1991011833A1 (en) |
Families Citing this family (49)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2678432B1 (en) * | 1991-06-27 | 1993-09-03 | Alsthom Gec | METHOD OF BONDING BETWEEN A HIGH CRITICAL TEMPERATURE SUPERCONDUCTIVE CERAMIC AND A NIOBIUM-TITANIUM SUPERCONDUCTIVE CONDUCTOR. |
| US5279711A (en) * | 1991-07-01 | 1994-01-18 | International Business Machines Corporation | Chip attach and sealing method |
| US5261155A (en) * | 1991-08-12 | 1993-11-16 | International Business Machines Corporation | Method for bonding flexible circuit to circuitized substrate to provide electrical connection therebetween using different solders |
| US5973910A (en) * | 1991-12-31 | 1999-10-26 | Intel Corporation | Decoupling capacitor in an integrated circuit |
| US5282312A (en) * | 1991-12-31 | 1994-02-01 | Tessera, Inc. | Multi-layer circuit construction methods with customization features |
| US5414221A (en) | 1991-12-31 | 1995-05-09 | Intel Corporation | Embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias |
| US5472900A (en) * | 1991-12-31 | 1995-12-05 | Intel Corporation | Capacitor fabricated on a substrate containing electronic circuitry |
| US5285017A (en) * | 1991-12-31 | 1994-02-08 | Intel Corporation | Embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias |
| DE59406156D1 (en) * | 1993-02-11 | 1998-07-16 | Siemens Ag | Method for producing a three-dimensional circuit arrangement |
| JPH08510358A (en) * | 1993-04-14 | 1996-10-29 | アムコール・エレクトロニクス・インク | Interconnection of integrated circuit chips and substrates |
| US5435060A (en) * | 1993-05-20 | 1995-07-25 | Compaq Computer Corporation | Method of manufacturing a single side drive system interconnectable ink jet printhead |
| US5401913A (en) * | 1993-06-08 | 1995-03-28 | Minnesota Mining And Manufacturing Company | Electrical interconnections between adjacent circuit board layers of a multi-layer circuit board |
| JP3350152B2 (en) * | 1993-06-24 | 2002-11-25 | 三菱電機株式会社 | Semiconductor device and method of manufacturing the same |
| US5632631A (en) | 1994-06-07 | 1997-05-27 | Tessera, Inc. | Microelectronic contacts with asperities and methods of making same |
| US5615824A (en) * | 1994-06-07 | 1997-04-01 | Tessera, Inc. | Soldering with resilient contacts |
| KR960009074A (en) * | 1994-08-29 | 1996-03-22 | 모리시다 요이치 | Semiconductor device and manufacturing method thereof |
| US5742100A (en) * | 1995-03-27 | 1998-04-21 | Motorola, Inc. | Structure having flip-chip connected substrates |
| JP3145331B2 (en) * | 1996-04-26 | 2001-03-12 | 日本特殊陶業株式会社 | Relay board, method of manufacturing the same, structure including substrate, relay board, and mounting board, connection body of substrate and relay board, and method of manufacturing connection body of relay board and mounting board |
| US5764486A (en) * | 1996-10-10 | 1998-06-09 | Hewlett Packard Company | Cost effective structure and method for interconnecting a flip chip with a substrate |
| US5796590A (en) * | 1996-11-05 | 1998-08-18 | Micron Electronics, Inc. | Assembly aid for mounting packaged integrated circuit devices to printed circuit boards |
| JP3065549B2 (en) * | 1997-01-09 | 2000-07-17 | 富士通株式会社 | Semiconductor chip component mounting method |
| FR2766618B1 (en) | 1997-07-22 | 2000-12-01 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING ANISOTROPIC CONDUCTIVE FILM WITH CONDUCTIVE INSERTS |
| US6048744A (en) | 1997-09-15 | 2000-04-11 | Micron Technology, Inc. | Integrated circuit package alignment feature |
| FR2770339B1 (en) * | 1997-10-27 | 2003-06-13 | Commissariat Energie Atomique | STRUCTURE HAVING FORMED ELECTRIC CONTACTS THROUGH THE SUBSTRATE OF THIS STRUCTURE AND METHOD OF OBTAINING SUCH A STRUCTURE |
| US6198168B1 (en) | 1998-01-20 | 2001-03-06 | Micron Technologies, Inc. | Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same |
| US6150188A (en) | 1998-02-26 | 2000-11-21 | Micron Technology Inc. | Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same |
| US6090636A (en) * | 1998-02-26 | 2000-07-18 | Micron Technology, Inc. | Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same |
| DE69934981T2 (en) | 1998-05-19 | 2007-11-15 | Ibiden Co., Ltd., Ogaki | PRINTED PCB AND METHOD OF MANUFACTURE |
| JP2000101245A (en) * | 1998-09-24 | 2000-04-07 | Ngk Spark Plug Co Ltd | Multilayer resin wiring board and its manufacture |
| US6207903B1 (en) * | 1998-12-10 | 2001-03-27 | Raytheon Company | Via transitions for use as micromachined circuit interconnects |
| US6242935B1 (en) * | 1999-01-21 | 2001-06-05 | Micron Technology, Inc. | Interconnect for testing semiconductor components and method of fabrication |
| CN1278645A (en) * | 1999-06-22 | 2001-01-03 | 张世熹 | Memory for high-density integrated circuit |
| FR2797140B1 (en) * | 1999-07-30 | 2001-11-02 | Thomson Csf Sextant | METHOD FOR MANUFACTURING THROUGH CONNECTIONS IN A SUBSTRATE AND SUBSTRATE PROVIDED WITH SUCH CONNECTIONS |
| US20040029413A1 (en) * | 2000-10-30 | 2004-02-12 | Norbert Angert | Film material comprising spikes and method for the production thereof |
| US6849168B2 (en) * | 2000-11-13 | 2005-02-01 | Kval, Inc. | Electrochemical microsensor package |
| US6991960B2 (en) | 2001-08-30 | 2006-01-31 | Micron Technology, Inc. | Method of semiconductor device package alignment and method of testing |
| JP4850392B2 (en) * | 2004-02-17 | 2012-01-11 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| TWI303864B (en) * | 2004-10-26 | 2008-12-01 | Sanyo Electric Co | Semiconductor device and method for making the same |
| JP4443379B2 (en) * | 2004-10-26 | 2010-03-31 | 三洋電機株式会社 | Manufacturing method of semiconductor device |
| JP4873517B2 (en) * | 2004-10-28 | 2012-02-08 | オンセミコンダクター・トレーディング・リミテッド | Semiconductor device and manufacturing method thereof |
| US7485967B2 (en) * | 2005-03-10 | 2009-02-03 | Sanyo Electric Co., Ltd. | Semiconductor device with via hole for electric connection |
| US20070126445A1 (en) * | 2005-11-30 | 2007-06-07 | Micron Technology, Inc. | Integrated circuit package testing devices and methods of making and using same |
| TWI346826B (en) * | 2006-10-26 | 2011-08-11 | Taiwan Tft Lcd Ass | Bonding structure and method of fabricating the same |
| JP4303282B2 (en) * | 2006-12-22 | 2009-07-29 | Ｔｄｋ株式会社 | Wiring structure of printed wiring board and method for forming the same |
| JP4331769B2 (en) * | 2007-02-28 | 2009-09-16 | Ｔｄｋ株式会社 | Wiring structure, method for forming the same, and printed wiring board |
| FR2936359B1 (en) * | 2008-09-25 | 2010-10-22 | Commissariat Energie Atomique | CONNECTION BY EMBOITEMENT OF TWO INSERTS WELDED. |
| DE102009060217B3 (en) * | 2009-12-23 | 2011-06-22 | Pyreos Ltd. | Method for producing an infrared light detector |
| EP3185290A1 (en) * | 2015-12-24 | 2017-06-28 | IMEC vzw | Method for self-aligned solder reflow bonding and devices obtained therefrom |
| US11875988B2 (en) | 2021-04-29 | 2024-01-16 | Nxp Usa, Inc. | Substrate pad and die pillar design modifications to enable extreme fine pitch flip chip (FC) joints |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3495133A (en) * | 1965-06-18 | 1970-02-10 | Ibm | Circuit structure including semiconductive chip devices joined to a substrate by solder contacts |
| US3373481A (en) * | 1965-06-22 | 1968-03-19 | Sperry Rand Corp | Method of electrically interconnecting conductors |
| US4074342A (en) * | 1974-12-20 | 1978-02-14 | International Business Machines Corporation | Electrical package for lsi devices and assembly process therefor |
| US4349862A (en) * | 1980-08-11 | 1982-09-14 | International Business Machines Corporation | Capacitive chip carrier and multilayer ceramic capacitors |
| US4545610A (en) * | 1983-11-25 | 1985-10-08 | International Business Machines Corporation | Method for forming elongated solder connections between a semiconductor device and a supporting substrate |
| JPS6187396A (en) * | 1984-10-05 | 1986-05-02 | 株式会社日立製作所 | Manufacture of electronic circuit device |
| US4604644A (en) * | 1985-01-28 | 1986-08-05 | International Business Machines Corporation | Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making |
| US4661192A (en) * | 1985-08-22 | 1987-04-28 | Motorola, Inc. | Low cost integrated circuit bonding process |
| US4703599A (en) * | 1985-09-03 | 1987-11-03 | National Concrete Masonry Association | Concrete masonry footer block foundation system and blocks therefor |
| JPH07112041B2 (en) * | 1986-12-03 | 1995-11-29 | シャープ株式会社 | Method for manufacturing semiconductor device |
| US4914814A (en) * | 1989-05-04 | 1990-04-10 | International Business Machines Corporation | Process of fabricating a circuit package |
-
1990
- 1990-01-26 US US07/470,622 patent/US5056216A/en not_active Expired - Fee Related
-
1991
- 1991-01-17 CA CA002074529A patent/CA2074529A1/en not_active Abandoned
- 1991-01-17 WO PCT/US1991/000359 patent/WO1991011833A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| US5056216A (en) | 1991-10-15 |
| WO1991011833A1 (en) | 1991-08-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA2074529A1 (en) | Chip interconnect with high density of vias | |
| KR100196242B1 (en) | Method of making a hybrid semiconductor structure and the semiconductor structure thereof | |
| US6612027B2 (en) | Method for forming metal contacts on a substrate | |
| US6638638B2 (en) | Hollow solder structure having improved reliability and method of manufacturing same | |
| US5925930A (en) | IC contacts with palladium layer and flexible conductive epoxy bumps | |
| US6245594B1 (en) | Methods for forming conductive micro-bumps and recessed contacts for flip-chip technology and method of flip-chip assembly | |
| KR100265616B1 (en) | Flip chip bonding method using electrically conductive polymer bumps | |
| US7335988B2 (en) | Use of palladium in IC manufacturing with conductive polymer bump | |
| US7550317B2 (en) | Method for manufacture of wafer level package with air pads | |
| US6774315B1 (en) | Floating interposer | |
| KR100403062B1 (en) | Method for forming three-dimensional circuitization and circuits formed | |
| KR101117887B1 (en) | Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces | |
| US7368323B2 (en) | Semiconductor device and manufacturing method thereof | |
| US7156362B2 (en) | Method and apparatus for forming metal contacts on a substrate | |
| KR20010023027A (en) | Method for forming bump electrode and method for manufacturing semiconductor device | |
| US6184586B1 (en) | Semiconductor device including a ball grid array | |
| US5936845A (en) | IC package and IC probe card with organic substrate | |
| US6191488B1 (en) | Flip chip type semiconductor package and method of injecting resin into device thereof | |
| US6571468B1 (en) | Traceless flip chip assembly and method | |
| US6204164B1 (en) | Method of making electrical connections to integrated circuit | |
| JPH09283566A (en) | Connection of substrate | |
| KR0166827B1 (en) | Mounting structure of semiconductor chip | |
| JPH01286430A (en) | Mounting method for semiconductor chip | |
| JPS62131554A (en) | Semiconductor device | |
| JPS6388835A (en) | Package for flip chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Discontinued |