CA2087839C - Prioritized data transfer method and apparatus for a radiotelephone peripheral - Google Patents

Prioritized data transfer method and apparatus for a radiotelephone peripheral

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Publication number
CA2087839C
CA2087839C CA002087839A CA2087839A CA2087839C CA 2087839 C CA2087839 C CA 2087839C CA 002087839 A CA002087839 A CA 002087839A CA 2087839 A CA2087839 A CA 2087839A CA 2087839 C CA2087839 C CA 2087839C
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Canada
Prior art keywords
message
data
messages
radiotelephone
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA002087839A
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French (fr)
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CA2087839A1 (en
Inventor
Jeffrey C. Smolinske
Bruce M. Paggeot
Jeffrey W. Tripp
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Motorola Solutions Inc
Original Assignee
Motorola Inc
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Publication date
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Publication of CA2087839A1 publication Critical patent/CA2087839A1/en
Application granted granted Critical
Publication of CA2087839C publication Critical patent/CA2087839C/en
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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04WWIRELESS COMMUNICATION NETWORKS
    • H04W88/00Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
    • H04W88/02Terminal devices

Abstract

A radiotelephone data transfer apparatus (211,219) connects peripheral devices external to the radiotelephone (201) and other user information inputting devices, such as a handset (203) for a cellular mobile radiotelephone, to the radiotelephone's central processor and speech processor (207).
The data bus apparatus generates frame formats in which the information is sent over the data bus. The frame formats are further subdivided into time slots, the time intervals in which individual messages are sent. The data transfer apparatus (211,219) is configured so that messages sent to the cellular radiotelephone's speech processor are not flow controlled, while messages sent to the radiotelephone's central processor are flow controlled. Further, the radiotelephone's central processor controls operation of peripheral devices attached to the radiotelephone.

Description

~7 ~

PRIOR~ ) DATA TRANSFER METHOD AND
APPARATUS FOR A RADIOTELEPHONE PERIPHER~AL

R~ V~ 1 of t11P TnvPnt;~n The present invention relates generally to digital data and analog voice trAnRmiRcions in a radiotelephone unit.
1 0 More particularly, the y-~senl invention relates to the cvllvcy~nce of analog voice mes6ages by a high speed data bus between subsystems of a cellular radiotelephone with prioritized data flow of digital data messages and rlieit;7e~1 analog messages. The present invention is related to U.S.
1 5 Patent Applic~t;~n No.07/732,511, "Data Transfer Method and Apparatus for Co~ r~t;~n 13etween a Peripheral and a Master" filed in behalf of Paggeot et al. on July 18, 1991 and ienP~l to the same assignee.
A cv~Lu~l..;rAt;~ln system which transmits information 20 belwcc~l two lrc~t;QnR inr~ lPs a tr~nRmittpr and a ~~cc;ve~
intelco....~cle(l by a tr~nRmiRRion rh~nnPl An information signal (which cont~inR il~ on, for PY~mrle, an analog voice message) is tr~nRmitte~l by the transmitter upon the tr~nRmiRsion rh~nnPl to the leceiver which receives the 25 tran~ lilled information signal.
Transl lillels and receivers may be cont~inpfl in a single apparatus so that the ap~,al alus may both transmit and receive cc~.. -)ic~t;~n~ over radio-frequency channels.
Cellular radiotelephones contain such transmitters and 3 0 receivers together called transceivers.
The signal to be mo(l~ te-l may be an analog information signal (for PY~mrle, a voice message) or a digital information signal (for PY~mpl~P~ an already digitized me~sage). When the signal to be modulated is an analog 3 5 signal, separate ha~dwale signal lines are used to carry the analog signals and digital ~;ignalB to the point in the ~87839 transmitter where the signal6 are modulated. Signals are input to a cellular radiotelephone at the user interface portion of a cellular radiotelephone. Generally, devices such as microphones, keypads, or other means for inputting 5 infoImation signals into the radiotelephone may be contained in the user interface portion of a cellular radiotelephone, or other external device6, such as f~cRimile m~hin.sR or e~ternal h~n~lRets, can be connected to input information to the cellular r~-liot~lephnne through a user interface to the cellular radiotelephone.
The lece;vel of a radio c.~-~.. nic~t;on system which .eceive6 the mod~ te-l inform~tjon signal from electrom~gnPt;~ energy contsinR C;~.,~LI.~ to detect, or to otherwise recreate, the information signal modulated upon 1 5 the carrier signal. The process of dPtect;ng or recreating the information signal from the mn~nl~ted signal is referred to as demodulation, and such chcui~ r for pe~ru-~lling the demodulation is referred to as demodulation circuitry. The ~,;lC ~ / of the rece;ver i~ constructed to detect, and to 2 0 demodol~te mndlllQted signals which have been previously morllllPted by a tr~nRmittçr mnd~l~tor.
Subsequent to ~lernndlllP.t;on, the original signal input by the user may be reconstructed, generally, after further proce~R~Ring of the d~mo~lnl~t~d signal is done to Plimin~te 2 5 noise added in the tr~n~miRRion of the signal over the radio-frequency rh~nnPl The reconstructed signal is then output at the user interface on the lec~ivel side of the radio system where devices such as spe~kprs~ displays, or f~Rimile m~rhinçg may be interfaced to the radio system.
3 0 Convçnt;on~l cellular radiotelephone systems require the transmitter and receiver to operate simultaneously on lifI~en~ radio freqnenries. The signals modulated by the conventional cellular radiotelephone transmitter and demodulated by the receiver are kept separate from each other 3 5 in the cellular radiotelephone unit. Newer cellular radiotelephone 6ystems do not require the transmitter and eceiver to operate simultaneously on di~ellt frequencies.
In prior cellular radiotelephone llnits, analog information signals were modnlRte-l and transmitted along with digital information RignRlR, therefore, separate parallel haldwale paths were generally necessRry to carry the analog signals and digital signals to the modulation C;lC ~ y in order to transmit the ~ignRlR. Moreover, in general, cellular radiotelephones processed analog signals as well as digital data information. The procçRRing and trRnRmiR~ion of the analog signals within a conventional cellular radiotelephone required additional hardware in the form of hal.lw~re signal lines and RignRlling haldwaie devices that were sepa~ate from the digital data signal lines to convey the analog signals through the cellular r~ ot~lephone from user interface portions of radiotelephones to the transc~;ver. Thus, cellular radiotelephones have parallel hal.lw~le paths for analog signals and digital data signals from the user interface portion of the cellular radiotelephones to the central signal 2 0 processing portion of the radiotelephones where the analog signals may be processed and digital signals properly formatted for m~ ;on and tr~nRmis~RiQn Because a decrease in the size of radiotelephones is a desirable goal in cellular radiotelephone te~hnology, minimi7~t;on of excess 2 ~ hardware ~e~lu,~es that parallel paths, such as the one between the user interface portion of a radiotelephone and the central signal proseRRine portion, be avoided wherever poRRihle in order to decrease the size of cellular radiotelephones 3 o F.~mpleR of serial digital data buses which are presently used in parallel hardwale paths with analog signals may be found in a syllchlonouR self-clocking digital data tnqnRmiRRion system described in U.S. Patent No.
4,369,516 to Byrns, a synchronous/asynchronous data bus 3 ~ system described in U.S. Patent No. 4,972,432 to Wilson, a radiotelephone peripheral bus system described in U.S. Patent 8 3 ~

No. 4,680,787 to Marry; and in U.S. ]?atent No. 5,060,264, "Radiotelephone Controller Configured for Coresident Secure and Nonsecure Modes" to Muellner et al.
The synchronou6/asynchronous data bus, U.S. Patent No. 4,972,432, described a asynchronous data triqnimi~.cirn syst~m layered on a slower self-rlocking synchronous tr~n~mis~ion 6ystem. The asynchronous data tr~n~mi~ion system had much faster data tl~lsrer capability than the synchronous data tr~n~mi~sinn system described in U.S.
1 0 Patent No. 4,369,516 to Byrns. This was a particularly il~lpOl lant characteristic when trying to integrate the filnct;on~ of a portable radiotelephone with a mobile type radiotelephone peripheral to take advantage of superior mobile type chalac~;stics, such as power output, using a 1 5 minim~l amount of time for the required transfer of data. An eY~mple of a mobile type r~Aiotelephone peripheral is described in U.S. Patent No. 4,680,787 "Portable Radiotelephone V~hiclll~r Converter and Remote Handset", a CVC, to Marry. This h,te~ ion was ~ccomrli~h~l by 2 0 splitting radiotelephone filn~t;on~ bel,ween the CVC
peripheral and the portable radiotelephon~ User variable functions were ~llorp~te~l to the CVC and radio functions, like call proces~ing, were left in the portable. This re.luil ed a much faster transfer of information over the cellular 2 5 radiot~lephone data bus in order to integrate radiotelephone functions and information between the portable radiotelephone and the CVC peripheral than possible with the synchronous data tr~n~mi~sion invention described in U.S.
Patent No. 4,369,516 to Byrns, and the synchronous/asynchronous data tr~nsmi~sion system, U.S.
Patent No. 4,972,432 to Wilson, met the requirement of providing greater speed for the transfer of data between the radiotelephone unit and peripheral.
Currently, there is an even greater ~l~m~n~ for faster 3 5 data transfer in cellular radiotelephones because the increased number of users on present cellular systems have 6trained cellular system capacity. Clellular systems require more effirient use of the resources slvailable for cellular systems.
One m~nner in which cellular system capacity could be used more ~!ffiriently i5 to send more messages within a given period of time. This could be ~ccQn pli~hPd by digiti_ing all mes6ages sent on the cellular system by cellular radiotelephones, and then ~en~ling the modul~ted digitSal messages seqllent;~lly to the individual cellular radiotelephones operating on the system. Moreover, digitizing all messages would also enable cellular systems to use the cellular system radio-frequency spectrum more efficiently because ~ligiti 7e-1 analog messages use less of the radio-frequency spectrum than analog voice messages. Therefore, 1 5 more liigiti7~P~ voice messages could be sent over a portion of the radio-frequency ~ye l,r~ than the equivalent analog voice messages. One m~nn~r of doing this is to digitize the message~ at the user interface to the cellular radiotelephnne, and then send the messages to the central yloce~;A;-~g portion 2 0 in the radiota]ephone ~ sceive~ on a high speed data bus, and then to the mn~ t;on point in the transmitter. Analog messages, particularly analog voice messages, could not be digitized and sent on data buses previously used in cellular radiotelephnnes bec~ e the data buses were not fast enough 2 5 to adequately send digitized analog voice messages, that were digitized in a real time m~nnPr, from the user interface to the transceiver portion of the cellular radiotelephone. For this reason a higher speed data bus for cellular radiotelephones is necessary.
3 0 Moreover, much higher capacity systems, such as the time division multiple access (TDMA) systems, are forcing current generation cellular radiotelephone units to process digital data and analog signals at much higher rates and to be more flexible in h~n(llinE data than the aforPmPnti~ned data tr~n~mi~sion systems. In TDMA cellular radiotelephone systems, it is generally desirable that analog voice messages, C~ ~

which come from the user input into the radiotelephone in a continuous m~nnar, take pIiority over digital data or digital control me~sage6 because the cont;nuous nature of voice message6 rlict~tes c~nFt~nt. s~mr1ing of the input while a 5 voice message i6 being input, e.g., at a radiotelephone microphone, otherwise there will be gaps in the voice message; on the other hand, digital data coming into the radiotelephone unit is already in a form such that continuous qslmr1ing is not required ber~ e errors in routine digital data 10 messages can be readily detected and mes6ages can be stored and retrieved from storage and resent if an error is ~etecte-l Thus it would be desirable if a high speed cellular radiot~.1eE!h~ne data bus ~ccommo~ted analog voice mes6age6 input at the radiot~lephone user interfAre in a real 15 time mslnner~ without interruption, as well as already digitized mess~ges.
Not only are ~ i7.~ n of hal.lware and increased data transfer speed impo.~ t con~ prationg for elimin~ting analog signals from cellular radiotelephones, but conve~ion, 20 tr~nsmi~sion, and storage of analog voice message signals in digital form gives the cellular radiotelephone (and cellular system as well) greater flexibility and quality becPll~e once the message is in a di~itally-lep~esçnte~l form it can be stored, proceqse-i, and retrieved in a m~nner whereby the signal is 2 5 not lost or subject to the type of signal degr~t;~ln that occurs in proces~ing, tr~nRmitt;ng, and ~eceiving analog ~
Therefore, it would be desirable to provide a high speed data bus for a cellular radiotelephone that tran6mits data fast enough to allow the cellular radiote1eFhone to function in a 3 0 cellular system that has greater message throughput than current cellular 6ystems (such as a TDMA cellular system)~ It would also be desirable if the high speed data bus were fast enough to allow a rellllc~;on of the number of analog and digital data signals paths in the cellular radiote1ephone by 3 5 digitizing the analog voice message signals at the user interface portion of the cellular radiotelephone such that the L~

same signal paths could be used to c arry digital data messages as well as the ~i~it;7.e~1 analog signals to other sub~ly~l,e~s of the cellular radiotelephone as well as to peripheral device6 which might be used with the cellular 5 radiotelephone. It would also be desirable if the tr~n~mi~sion of digital data transmit~d over the high speed data bus did not cause a degradation of the digitized voice messages in a cellular radiotelephone.

1 0 Snmm~rv of the Tnv~nt;on The present invention enromp~ses a data transfer a~,pa~cltus for a radiotelerhone unit which collvey~ digitized analog and digital data inform~tion messages from a user 1 5 interface portion of the radiotelephone unit to a procçssing unit of the radiotelephone unit. The messages are sent in message timeslots of a message frame. Each frame further cont~in~ a general data timeslot. Analog information is processed into a digitized analog message, is disting~ushed 20 from digital data inro,mation messages, and is prioritized to a higher priority than the digital data information. A first timeslot sllocated for conveyil.g at least a part of the ~ligit;7P~
analog message is detected at the user interface portion of the radiotelephone lmit and at least a part of the digitized analog 2 5 message is sent to the proces~ing portion of the radiotelephone unit. A second timeslot is tlPtecte-l and a determinS~t;on of whether the second timeslot is marked busy is made. When the second timeslot is not marked busy, at least a part of the digitia} d~ta message is sent in the second time slot.
Brief Descri~t;or~ of t~ e Drawin~s FIG. 1 is a block diagram of a cellular system utilizing cellular radiotelephones which may employ the present 3 5 invention.

FIG. 2 is a diagram depicting two principal portions of a cellular radiotelephone which may utilize a high speed data bus to c-~mmnnir~te with each other.
FIG. 3 is a bit diagram of the format for a message sent 5 from a bus master to a device on the data bus of a cellular radiotelephone .
FIG. 4 is a bit diagram of the format for a message sent from a device on the data bus to the bus master.
FIG. 5 is a diagram of a cellular radiotelephr~nP
1 0 inte~con..r~ l by the data bus to an external peripheral apparatu6.
FIG. 6 is a diagram depictinE the rel~tionRhip between the individual data timeslots of the data bus protocol of the present invention.
1 5 FIG. 7 is a block diagram depicting the a~pal at-ls within a device connected to the data bus used to delel~.ne bus contçnt;r~n with other devices connected to the data bus and the device address.
FIG. 8 is a diagram ~lepict;nf~ the sequential nature 2 0 several devices may use to send data to, and from, the - transc~.vdl on the data bus.
FIG. 9 is a diagram ~lepict;nE the main data flow paths, form~tt;ne, and protocol h~n~llinE mP~h~niRmR for digital data and digitized voice messages sent to the data bus for 2 5 tr~nRmiRRion to the transc~,;vdr portion of the radiotelephone or other peripheral devices.
FIG. 10 is a block diagram depict;nE a perirheral device (and collc~l.on~in~ data flow) which may receive the digital data or digitized analog voice messages sent over the data bus 3 0 from a transceiver portion of a cellular radiotelephone, or other peripheral device eonnPcted to the cellular radiotelephone user interface by the data bus.
FIG. 11 depicts a diagram of the clock used for Manchester enco~ling data bits transmitted by the data 3 5 transfer apparatus, as well as samples of 8 bit streams having the values 254 and 255.

FIG. 12 depicts a diagram for the outputs of the Collision Detect circuits for two data transfer apparati which are c~ntentling for access to the data bus, and the resulting determin~ n at ~he eighth bit of the stream.
FIGS. 13A-13D are flowcharts for the process of flow control for the peripheral transmitt,ing to the master (FIG.
13A); for the peripheral rec~ivi,lg from the master (FIG. 13B);
for the master ICC~i;ving from a peripheral (FIG 13C); and for the master trAn~ n~ to a peripherAl (FIG. 13D).
1 0 FIGS 14A and 14B are flowcharts for the process of register sPlçct;on in the master (FIG. 14A) and the peripheral (FIG. 14B).
FIG. 15 is a flowchart for the process of power up employed by the peripheral.
1 5 FIGS. 16A and 16B are flu~. cha~ ~s for the process of peripheral priority flow control for a priority audio message (FIG. 16A) and a special priority message (FIG. 16B).
FIG. 17 is a timing diagram illustrating flow control between a bus master and a peripheral device.
Detailed Description of a P~ efe. . ad Embodiment In reAli7ing the present invention and ~ve~co~ng the aforementioned problems, analog signal messages, in 2 5 particular analog voice signal messages (which require real time s~mrlinE and proces~ g not re~ hle on data buses previously incol~,o.ated in radiotelephones), are digitized at the user interface of a radiot~lephrne and then tr~n~mittR~I to the central processor portion fast enough to meet the s~mpling and proces~in{~ ~e~lui~ ents of such real time messages. Messages trans_itted to the central radio processor for proces~inF are flow controlled, and messages transmitted to the speech processor of the radiotelephoneare not flow controlled, thereby enh~nrin~ the real time 3 5 proce.ssing r~r~hility for digitized analog voice messages. The data transfer device of the p~efe--ad embo-limçnt is fast - l Jt.i~
enough to time multiple~ several digitized voice message peripheral devices (such as rPtliotelPphone handsets or other devices which can be used to input voice information to radiotelephones) to access the high speed data bus and thereby 5 transmit all digitized analog voice messages to the central processing portion of a r~rliot~leph-)ne for procç.s~ing.
A time slotted data bus is created with all the time slots being contPine-l within a frame. Mess~ees are sent within the individual time slots of a frame. Time slots may be allocated to 10 individual peripheral devices for each frame, or several peripheral devices may time multiplex over the same time slot. Each frame c~lnt~in~ at least one general use time slot which can be used by for messages other than digitized analog voice messages. The data transfer app&.al,us can be used 1 5 either to rece*e messages sent to it over the data bus or to transmit messages over the data bus.
The data l-dl~rer al~pa~hlus creates two dirre~ent message formats, one for messages to peripheral devices from the bus master (downlink messages), and another for 2 0 messages from the peripheral devices to the bus master (uplink messages). During the data bus start-up procedure, data bus contention is resolved by information which reaches the data bus as the fourth of four fields (data bit field) cont~inPd in the uplink messages; this information is 2 5 retrieved from a memory device. In the case of uplink messages after the start-up procedure has been e~rP~te~l, bus r~t4~ nn is resolved by the information cQnt~ ell in the first three of the four fields comprising the message format.
The data transfer a~l~al~t.ls can receive uplink 3 0 messages at more than one input port. One of the input ports is for hlpulling digitized analog voice messages and also for illl,ulling information (retrieved from a memory device) used during the data bus start-up to determine the address with which data transfer a~)arali cnnnPcte(l to the high speed data 3 5 bus will be able to access the high speed data bus. The other port is used to input digital data messages and messages of S'J ~-3 the highest priority. Me6sages are routed, and priority and bus content;nn are del~ .ined, by the input port the messages use to enter the data transfer apparatus. In order to operate at the high speed required to sample ~md process digitized 5 analog voice messages, and also accept digital data messages at the other input port, the data transfer a~pala~us has internal devices which are able to receive information in bit form from other devices and to create a 48 bit data field from the ,eceived infor n~t;on All messages sent over the data bus 1 0 contain 48 bit data fields. In addition, 16 bits (the header) are used for message h~n~lling information, included among these 16 bits are a priority field, a register select field, and a field ~lP~ign~t;ng the address of the device ori~in~qting the message. These 16 bits are created within the data transfer 1 5 appa-a~us in Lffelet loc~tinn~ and are routed difrt lc--tly over the data bus, flepPnrling on the type of message, i.e., voice, non-voice, hiEhest priority message, or start-up plvced~le message. The messages are coded before being sent over the data bus, and the coded message is also used to tlPtermin~ bus 2 0 contçnti~ n when several devices are cnnnpcte~l to the data bus.
The data transfer a~&laL.Is is also sble to rece*e messages sent to it over the data bus. The data transfer apl,ala~us determines the ~pprol,l;ate output loc~t;nn for the message sent to the data transfer apparatus ZlCCI:)f .ling to the 2 5 16 bit header inform~ti.m The received messages can be routed to the same devices which comprise the two input ports mentioned above, ~ep~p-ntling on what the message type is, i.e., voice, non-voice, high~Et priority message, or a start-up procedure mçss~ge 3 0 One applic~t;~n which may advantageously employ the present invention is that of a cellular radiotelephone in which a minimum number of signal lines, and ~o~te~
radiotçlephnnP hal.lw~lc, aids in the mini~tl-rization of the radiotelephone eqllipm~nt. Although the invention is 3 5 described with radiotelephones as the plefel .ed emho~1iment the invention may just as well be employed in other applications having similar requirements or ~e4ui~:ments necesh;lsting interconn~ctinn with lequipment employing the present invention.
In the l~le~ll~d embo~limçnt, all information input to a 5 radiotelephone i8 digitized at the uE,er interface portion of the radiotelephone, BO that analog signals are no longer transmitted among the subsystems of a radiotelephone, nor are analog signals diret Uy modulated for trAnRmiRRion over the radio-frequency çh~nnPlR used by a cellular 1 0 radiotelephone system. RadiG-frequency s~c( ~l ~ is conserved bec~ e ~ligit;7e~1 information signals are able to carry equivalent information as non-digitized signals in a smaller portion of the radio-frequency ulJe~,Ll ~u. Accordingly, the present invention could be used in coDJ~nct;on with a 15 system such as TDMA cellular system 60 that radio-frequency spectrum i6 used more effiriPntly. Moreover, ~ligit;7ing all messages at the user intçrf~ce portion (or -within peripheral devices connPctç~l to the radiotelephone over the data bus) reduces the nnmher of signal lines used to inteico~...ect 2 0 dirre~ent sub~y~e Is of the radiotelephone. Thig corregpon-1R
to a reduction of ha,.lwa,e requir~ pnts~ an ilU~JOl Lant factor in rednring the size of radiotelephonPs Additionally, the present invention iB fast enough to provide for simultaneous conn~Pct;on, and operation, of several peripheral 25 co~nic~t;on devices, voice and non-voice, to the radiotelephone.
Cellular radiot~lephnnçs provide the same type of fully ~ntom:~tic service to a mobile or portable radiot~lephnnP user that is provided to a convPntion~l land line telephone 3 0 subscriber. In a cellular radiotelephone system, service is provided over a wide geographic area by dividing the area into a number of cells. In a conventional cellular system, each cell typically has a base station, which provides a Rign~lling radio rh~nnPl and a number of radiot~lephnne voice rh~nnPl~ A
3 5 base station cont~in~ one or more l eceive, s 135 and transmitters 133, as well as control and other ~ ;r. . i~-y 131 to ~8~
operate the base station 117. Telephone calls are placed to, and oriein~ted by, radiotelephones over the ~i~n~lline ~h~nnPl in each of the cells. A general representation of a cell in the ~ystem is depicted in FIG. 1. Depicted in FIG. 1 are a remote rArliotelephonR urlit 113 controlled by cell base station 117 through which the radiotelephone unit 113 may comml1ni~te with second remote radiotelephone unit 119 within the cell controlled by the base station 11 ï . Each radiotelephone within the cell typically has both a transmitter 101 and a leceiver 103 1 0 portions as well as a user interf~re portion 105 where the radiotelephone user may input information into the tr~qnRmitter 101 after n~cess~ ~ signal l~loces~ in a central signal processin~ portion 111. This central signal procesRing portion 111 contsinR the central COlllpu~ g processor for the 1 5 radiotelephone and is generally located in the portion 121 of the radiotelephone which cont~in~ the transmitter 101 and r~,c~;vel- 103. In a convRnt;onQl system, upon completion of the Ri~ns~llin~, the radiotelephone is ~RRi~ne~l a radio voice rh~nnRI to which it gwitcheg from the radio s;gn~lline 2 0 rh~nnel for the duration of the call. In the event that a radiotelephone leaves the cell and enters another cell, the radiotelephone is ~l)tom~t;c~lly switched over, or handed off, to an available voice rh~nnel in the new cell.
The system of the ~refel~ed embo~limRnt has been 2 5 de~i~nRcl to operate in a cellular remote radiotelephone unit that will operate in a time division multiple access systRm (TDMA), although it could be used in any ~ntom~t;c radiotelephone system. A convRntion~l radiotelephone sends information signals among the different fimrtior~l blocks that 3 0 make up the radiot~leF!h-~ne as well as to peripheral devices ronnpcte(3 to the radiotelephone. In a conventional telephone, analog signals and digital signals are routed from the portion of the radiotelephone where the signals are input into the radiotelephone to other filnrtion~l blocks in the 3 5 radiotelephone.

~7 ~3-'~
For e~mple, in a conventional radiotelephone, a user will speak into the microphone input of a cellular radiotelephonP, and then the analog signal (voice message input~ will be routed on analog signal lines to the transmitter 5 modulator, where the analog voice message signal will be m-~A~ t,ed and subsequently transmitted out. This analog signal is trans_itted through the cellular radiotelephone system to a radiotelephone ~eceivel which receives the analog voice message input. Thus in order to get the analog voice 1 0 information into the cellular radioteleph~-na system, two analog signal lines are required.
On the other hand, a digital signal input, for ~Y~mple a keypad press used to dial a user telephone number, will be routed on di~.~n~ signal lines, and be processed by the 1 5 central radio processor before it is sent to the transmitter to be mo~ te~l and transmitted out to the cellular radiote-lephor~e system. Thus, this digital signal tr~nRmi~ion to and through the cellu]ar radiotelephone system requires additional hanlwale signsl lines to send the information from the 2 0 keypad press device to the transmitter in order to send the information through snd to the cellular radiotelephone system. Moreover, in a convelllional radiot~lephone there are separate lines for analog voice messages and digitsl signals that are to be sent to snd through the cellular radiotelephone 2 5 system from the user inter&ce/input portion of the radiotelel?hone to other portions of the radiotelephon~ A
radiot~leph(ne unit system employing the present invention has the need for separste signal lines to carry information from the user interface portion of the radiotelephone to other 3 0 portions of the radiotelephone ~limin~ted by the digitizing of all analog voice messages input to the radiotelephone at the user interface of the radiotelephone, and the s~n(ling of digitized analog voice samples to the central radio processor portion of a radiotelephone. This radiotelephone unit 3 5 ~ccommndates digital data messages as well, and allows the digitized analog voice s~mples to be processed fast enough to ensure the digitized analog voice are of good audible quality when reooveled by a radiotelephone r~ceiver ~d reconstructed for use by a user of a cellular radiotelephone syst0m.
The ~refell~d P:~nho~liment of the present invention employs a time slokted data bus for sPnfline digital data me~sages and digitized analog voice messages between the user interface portion A~d other function blocks of a radiotelephone (including peripheral devices which may be 1 0 Att~-hPsl to the cellular radiotelephone).
The time slotted data bus, as ~iepicte~l in the format of FIG. 6 employs Bi~ time slots 603 sent over a period of 750 microsecnn~R, cAlled a frame 601. Each time slot is formatted as shown in FIG. 3 and FIG. 4. The data bus utilizes two 1 5 unidirec~;onAl trAnRmiRR~ n~ from the "bus master" ( the central processor 111 in the radiotelephone 113) to other devices with data transfer ap~aldlus to accept messages, or from other devices to the bus master or to other devices.
MesRAges are defined to be either downlink message6 which 2 0 have a message format as shown in FIG. 3, or uplink messages which have a format as shown in FIG. 4. The downlink messages are messages sent from the central signal proceP~ine and co.,lpuli~lg portion (The bus master 111 or 205 is cont~ine~l in this portion of the radiotnlephone unit) 207 of 2 5 the r~-1ioteleph-)nP (In the case of 8 mobile radiotelephone, this portion is cQnt~inecl with the transceiver in a single unit 201 c~-nnecte~l to a user interface unit 203, e.g., a hAn~et ) to other portions of the radiohlephone such as the user interface portion 203 of the radiotelephone, or to peripheral devices 3 0 which may be connected to the central signal procesRine and col.lpuling portions 205 of the radiotelephone .
Referring to FIG. 3, downlin!~ messages provide a format of six fields: a SynchronirAtir)n Field 303; an Acknowledgement (Ack) Field 305; a Time Slot Number Field 3 5 307 which is also used by peripheral devices to synchronize the time slots in a frame; a Register Select Field 309 used to select a particular register within the adclressed data transfer apparatus device; a Destination Address Field 311 used to specify the device cQnn~ctçd over the high speed data bus which is being addressed by the bus master; and a Data Field 5 313 used to send information which will be used by the addressed peripheral device. The Synchroni7~tion Field 303 is used to control time ~lienm~nt on both the uplink and the downlink messages and is sent at the beginning of every downlink time slot.
1 0 Uplink messages are messages sent to the central signal proces~ine and co...~ g portions 201 of the radiotelephone from other portions of the radiotelephone, or from peripheral devices ~tt~rhed to the radiotelephone, over the present invention.
l 5 AB shown in FIG. 4., the uplink message format provides four fields, it has an eight bit Priority Field 403, a four bit Regi~ter Select Field 405, a four bit Source Address Field 407, and a forty-eight bit Data Field 409. All of the fields, including the 48 bit data field, are used to del,e~ e bus cont~nt;on among data transfer apparati which co.. ~inir~qte with each other over the time slotted data bus. This is done by a sequential bit-by-bit c~, Ipal;son scheme in each data transfer apparaLus beginnine with the most ~ienific~nt bit in the 64 bit word (in the Priority Field portion of the word) and 2 5 ending with the least ~ignific~nt bit (in the Data Field 409).
Each 64 bit word is ~ ed in a time slot of the data bus frame 601.
Additionally, unique time slots within the frame 601 of the data bus format are ~lloc~ted by the present invention to 3 0 peripheral devices which accept analog voice messages in order to transmit the digitized voice messages to the central speech proces~ine device 223 (in the logic portion 207 of the radioteleph-)n~ 113, 119) at a rate to ensure that voice messages are adequately transmitted by the radiotelephone 3 5 113, 119 to the cellular system base station 117; peripheral devices means the user interface portion 105, 203 of a v1~

radiotelephone 113,119 as well as peripheral devices e~ternally ~onn~cted to the radiot~l~phnnç, e.g., an external handset 109, a fslr~irnil~ m~hine 107, or similar peripheral dence 511.
As mentioned above, the data bus frame 601 in the 5 plef'elled embo-lim~nt is 750 micro3econds, there are six time slots per frame 601, and forty-eight data bits per time slot, therefore, the throughput of data bits by the present invention is three hundred eighty four thousand bits per second. If the non-data bits are accounted for, the total throughput is based 1 0 on sixty-four bits per time slot and the present invention has a total throughput of five hundred twelve thousand bits per second. In either in~nre, this throughput is an order of magnitude faster than that generally available in conv~n~;on~l cellular radiotelephones This throughput is 1 5 il.lpollallt be~n~e it is much higher than ConvF!nt; ~ l data buses found in current cellular radiotelephnnes This throughput is f~~cessp~ in order that peripheral devices such as a handset for mobile radiotelephnnes can contain digitizing devices ( coder-encoder "codec" 213) and the data transfer 2 0 apparatus 211 can transfer this ~liEit;~e~l information to the main radiotelephon~ processor 205 fast enough for proce~sinE
and storage without a loss of digitized analog voice message information.
In order to ~-commo-l~te leceiving and proCQSSin~
2 5 information signals over the radio frequency link between the base station 117 and radiot~l~phon~ 113, 119 and from the user interface portion 105 of the radiotelephone, the data bus is used in a radiotelephone architect~1re as shown in FIG. 2. In this architecture, analog voice messages may be input at the 3 0 microphone 209, further processed as an analog signal by the audio control .,;r~ , 221 of the radiotelephone, before being digitized by the coder-decoder 213 which provides for the digital-to-analog and analog-to-digital c.,l,vel~iion of speech or other analog ~iEn~l~ The codec 213 converts the received 3 5 analog voice message signals to a stream of binary bits and can be used to recollvt:- ~ stored binary bits to a replica of the original analog ~ign~lR~ such as synthesized speech sign~
APLer the codec 213 has digitized the analog signals into digital me~sage6, it then transmit6 them to the data transfer 5 app~latus 211 where the digitized ~malog mes6age is seql~y~i :~lly shifted bit-by-bit into a 64 bit register within the data transIer apparatus. In the case where the codec 213 is a cvlllpo~lnded codec, six 8 bit frames as shown in FIG. 6 are seql)Pnt;~lly shifted into the 64 bit register (only 48 bits are 1 0 data, the other 16 bits are control bits for the time slot) within the data transfer appaldl,u6 from the codec 213. In the case of a linear codec, which takes larger s~mrlPs and does not cv~l)~ess data, three 16 bit codec frames are seqnPnt;~lly shifted into the 64 bit register as shown in FIG.6. The mPthn~
1 5 described in the ~lererled embo~limçnt is not limited to codecs with these c~l,veiDion rates. If a higher rate of information processinE is npcess~ the frame time period can be shortened accordingly, and higher collve~Dion rate codecs could be used in place of the L~ p~ lPCl and linear codec 2 0 devices. The intro~lnrt;~n of the codec at the user interface portion 203 (for P~mple a mobile radiohlçph~nQ h~n~et i8 such a user intsrf~ce) of the cellular radiotelephone is an i .plov~ ent over previous cellular radiotelephone ~1esiEn~
bec~ e by being able to tbroughput data at the rates that it 2 5 does, it is able to process ~lieit;~P~l analog voice messages which require a much higher acces6 (S~mrlinE) rate than that allowed by previous data buse6 used to co~...e~l the user interface portion 203 of a radiotelephone to the main processor 205 of the radiotelephone, as a result this bus Plimin~te~ the 3 0 need to supply separate analog signal lines and related hal.lwale to carry analog speech signals to the cellular radiotelephone's proces~ g portion from the user interface portion 203 of the cellular radiotelephone. For çY~mple, a c~,...p~-~tlell codec operating at an 8 KHz rate requires a 64 3 5 Kbps data rate. The system of the prefer,ed çmho~imPnt is able to ~ccomrli~h, and furthermore, to ~commodate five ~ - lC~-~9~8783~

user interface (or other peripheral clevices used to input voice messages to a radiotelephone) devices with such data transfer apparati. Furthermore, bec~n~e the system allows all analog voice messages to be ~igiti~ed and sent over a digital data bus, 5 it reduces the number of 8ignal line~s re4u red to connect the user interface (h~n-l~et portion) portion of the cellular radiotelephone from eight lines to four which is an impGI lant fsctor in being able to down size r~lliotelephone equipment.
Flow control bits and other format bits are added to the 1 0 48 bits shifted into the 64 bit register to comprise a bus format as depicted in FIG. 4 for messages that are sent to the central p~ocesr~ e portion of the radiotelephone, which filnrtion~ as the bus master, from other devices which may access the serial data bus.
Peripheral devices and the bus master (the central radiot~lephone plocessor) interconnPctecl over the high speed data bus require the data transfer apl~aldLùs 211, 219 in order to: pl.,pe.ly format data bits of digital data messages and digitized analog messages transmitted over the high speed 2 0 data bus; be ~signed time slots for transmitting over the high speed data bus; del~l~ine bus con~nt;oT~ over the high speed bus; and to receive messages from the bus master. The data transfer appald~us 211, 219 can be used and configured ~or use on the bus master side of the data bus or the peripheral device 2 5 side of the data bus. The data transfer appal al,us 211, 219 can be used to receive or transmit messages over the data bus and it can process digital data messages or digitized analog voice messages.
For e~mple, in the case of analog voice messages input 3 0 to a peripheral device such as a h~n~l~et the data transfer apparatus 211 in a peripheral device allows the radiotelephone data bus to accept an analog voice message from a peripheral device 203 such as a h~n~et as depicted in FIG. 2 after the analog voice message has been digitized by using an 3 5 a~,opliate means such as a coder-encoder (Other types of peripheral devices may also be used vith the present ~87~3'3 invention, for inat~nce FIG. 5 portrays a ~ifferent device, such as a fAr~imile sy6tem 511, which may sen(l information through the data transfer appa~a~s 211). The data transfer apparatus 211, 219 may then send the digitized analog 5 message to the central proces~ing portion 207 of the radioteleph~ne, or some other peripheral device connected to the high speed data bus.
The data transfer h~la~l.i 211, 219 c~)nt~in~l in peripheral devices that ~..n.~ irs~e over the high speed data 1 0 bus (either on the bus master side or peripheral device side of the data bus) i6 depicted in greater detail in FIG. 7, 9, and 10.
The data transfer apparatus as depicted in FIG. 7, 9, and 10 is the same device whether it iB on the bus master side 219 or on the peripheral device side 211 of the data bus. FIG. 7, 9, and 10 1 5 depict dirrel~"t operating condition~ under which the present invention is used, and the variable operations performed by devices within the data ll~n~re. app~ldlus 211, 219 depending on the operations being pelrull.led by a data transfer apparatus, e.g., whether it is on the bus master side or 2 0 peripheral device side of the data bus, whether it is used to transfer digitized voice messages or digital data messages, or whether it is used during start-up of data bus operation or after start-up of data bus operation.
The data transfer apparatus provides a merh~ni~m to 2 5 create a 64 bit word format which is used to send and receive digital data messages and digitized analog voice messages over the data bus. FIG. 7 is a block diagram depicting the mPchs-ni~m used by the data transfer apparatus contsine-l in a peripheral device to determine bus cQntPnt;~n with other 3 0 peripheral devices, also to determine the Peripheral Device address over the high speed data bus.
At the bP~;....;-~g of operation of the high speed data bus (start-up), the data transfer apparatus of each peripheral device assigns itself an address so that it can communicate 3 5 with other devices connected over the high speed data bus.
Because more than one device may be connPcted to the high '~0 ~
~peed data bus at start-up, it is nece~ y to resolve contention among, and between, the peripheral devices to be connected to the high speed data bus at start-up. In order to do this, the entire 64 bit word generated by the data transfer apparatus is 5 used to determine bus contention.
In each peripheral device, at start-up, the first three fields are initialized to the following values in the Audio Header 903 portion of the Transmit Reg~ter 901 of FIG. 9, the Priority E ield 403 (FIG. 4) i6 set to a value of 254, the Register 1 0 Select Field 405 selects the processor register (register "C") in the bus master which is the same as ~n~l~et/~processor Register 1001 (FIG. 10) in a peripheral device, the Source Address Field 407 is set to zero by all the data transfer al pal~Li 211 bec~ e no addresses are det~~l..-if ed until the 15 start-up procedure has been PY~Cnt~l to determine the proper priority that should be given to peripheral devices that are c~nn~ct~l to the data bus, and the Data Field 409 is used to determine bus contention when more than one peripheral device is connecte~ to the data bus. Once such a bug content;nn 2 0 is determined, the peripheral device which gains access to the bus assigns itself an address equal to the number of alle~l ls required to gain bus access.
At the be~;t)n;~g of operation of the high speed data bus (start-up), the data transfer appals~,us of each peripheral device assigns itself an address so that it can &o.. ~-n;r~te with other devices connected over the high speed data bus.
Because more than one device may be connecte~ to the high speed data bus at start-up, it is necess~ry to resolve c-n~ntion among, and between, the peripheral devices to be conn~ctecl to 3 0 the high 6peed data bus at start-up. In order to do this, the entire 64 bit word generated by the data transfer apparatus is used to determine bus cont~ntion In each peripheral device, at start-up, the first three fields are initialized to the following values in the Audio 3 5 Header 903 portion of the Transmit l~gister 901 of FIG. 9, the Priority Field 403 (FIG. 4) is set to a value of 254, the Register - 2~ -Select Field 405 select6 the prOCessDr register (register "C") in the bus master which is the same as ~n~Ret/llprocessor ~egiFtPr 1001 (FIG. 10) in a peripheral device, the Source Address Field 407 is set to zero by all the data transfer 5 aypa!ali 211 bec~qllRç no addre6ses are determined until the start-up procedure has been e~es~ to determine the proper priority that should be given to peripheral devices that are çrmnPcted to the data bus, and the Data Field 409 is used to determine bus contention when more than omP peripheral 1 0 device is connPctecl to the data bus. Once such a bus contention is determined, the peripheral device which gains access to the bus assigns itself an address equal to the number of a~ml,ts required to gain bus access.
The process by which the master selects a register field 1 5 i~ shown in the flo~..,ha,l of FIG. 14A. A delel...;..~f;on is made, at 1401, whether the data is prçsçn~ed from the micf~p.oce3sor port. If yes, the desl;n~t;on register generated by the mi. .o4locessor is used (at 1403) as the register field value. In the p.erel.ed eTnho-limPnt values 7, 8, 9, B, C, and 2 0 E are used. If data is not from the mic.~locessor port, a del~er ..i~-~t;~n is made, at 1405, whether data represent;ng digitized audio is available from the Audio Port. If yes, the master de~ t;n~t;on is sPlFcled (at 1407) to be the Audio register (Register "F", in the p.ef~lled PmhorlimP,nt). If audio data is 2 5 not present, the ~lPPt;n~t;~n is sPlecte~l (at 1409) to be a no act*e register (~çg ~ter 0).
The peripheral selects a register by employing the process of FIG 14B. A determination is made (at 1413 and 1415) whether data is present from the h~n~lRet I/O port or the 3 0 peripheral mic.oplocessor port, respectively, and if it is, the master dest;n~t;on is selected (at 1417 and 1419, ~es~,lively) to be the Rx RP. gi~tPr (Register "C"). If data is not found to be present, a determin~t;~n (at 1421) of whether digitized audio data is present. If yes, the master dest;n~t;on is sPlect~-l (at 3 5 1423) to be the Audio register (R~gi~tnr "F"); if no, the master ~87839 ~les~in~l~;on is 6plecte~ (at 1425) to be no active register (Register "O").
At 6tart up, the data transfer apparatus 211 gets information from a device external to it, such as the EEPROM
5 217, in order to determine bus contentinn The data transfer apparatus transmits this information serially to its Transmit Register 705 where the informet;on is ro~matLed into the 48 bit wide Data Field 409. The EEPROM 217 co~-t~;- c specific information about the peripheral device 203 that . llows the 1 0 bus master microcolllpuLer 205 to deLel"line the peripheral device priority with respect to other peripheral devices attempting to access the high speed data bus. At start-up, the F'~;ol;ly Counter 701 in all data llansrel apl,alaLi 211 aLl~ Ling to access the bus is set to one.
1 5 The specific hlrul.,-aLion con~o;n~tl in the EEPROM 217 within the perirheral device 203 is plo~l~ed so that the data transfer app~Li 211 can co ,pa~e (through the operation of the data bus) the value it has rece*ed from EEPROM 217 with the same specific information stored in 2 0 EEPROMs of other peripheral devices when more th. n one device is c~ P.Lçd to a cellular radiotelPph-~nP so that when there is bus content;~-n, the peripheral device with the highest value number stored in its EEPROM 217 will gain acces6 to the data bus. To pelr.,l~ the start up bus arbitration, the 2 5 EEPROM data is transferred into the Transmit Re~i~tçr 705 of the data transfer ap~a~dLi 211. The first three fields (16 bits) are initialized as previously described. Then the entire 64 bit word is transferred to the TX/RX Shift Register 707. Aflcer proper encoding (through the M~nrhester ~.nrollpr 709) of the 3 0 bits sent to the T~/Rx Shift Rçgi~ter 707, the data transfer apparatus 211 does a bit-by-bit co,llp~;60n of the 16 bit header 411 and the 48 bit data field through an Exclus*e-Or gate in the Collision Detect circuit 713 with a signal (data bus state signal) derived from the M~nrhester F.nr,orl~r 709 output 3 5 (through buffer circuits) of the data transfer ap~aldLu6 211 wired to the M~nrh?~tçr F.nro~r ouLl,ut~ of other data 2 ~
transfer apparati attempting bus access. If the data bus state 6ignal and the M~nrhester Encoder 709 output are not the same for any bit, then the output of the Exclusive-Or function and the Collision Detect 713 circuit is a logic "1" which 5 inrlir,~te~ a collision on the bus has occurred and the data transfer apparatus which de~ects the "1" will not gain access to the bus. The data transfer al pa.alus which detects the "1"
will stop its attempt to access the data bus and it will increment its Priority Counter 701 by value of 1. All data 1 0 transfer apparati which do not detect a "1" will continue attempting to gain access to the data bus by cont;nlling to shift M~nrhester enro~le(l data bits and data bus state signal bits to the Collision Detect 713 circuit until only one data transfer a~,~alalus has a zero output from the Collision Detect 713, this 1 5 r~m~ining data transfer apparatus will obtain access to the data bus and will assign itself the address equal to the value in its Priority Counter 701, which is one. The other data transfer appalali which failed to gain access will increment their Priority Counters 701 by one and the same procedure outlined 2 0 above in this paragraph will be followed until a second data transfer appalatus gains access to the data bus and assigns itself an address. This start-up p-ocedule is repe~te~i until each data transfer apparatus gains access to the bus and assigns itself an address. Each failed ~ttemrt to access the 2 5 data bus results in the Priority Counter 701 incr~m~nt;ng itself by one in each peripheral data transfer apparatus which fails to gain access to the data bus.
The process followed by each peripheral device is shown in the flowchart of FIG. 15. After power is turned on for the 3 0 peripheral, memory is read and the address count is set at an initial "1", at 1501. Following a wait for the start of a time slot (at 1503), the unique serial number is sent on the bus bit by bit starting at bit number 64 (at 1505). At each bit, contAntion for the bus iB chprk~ at 1507. If a ~olli~ion is ~letecte~l, a test of 3 5 the state of the ack field is made, at 1509. A result of a busy condition returns the process to wait for the start of the next - 2'; -7 r~3~
time slot; a result of a not busy condition results (at 1511) inthe incrçmPntinE of the address count by one, a ces~Ation of the current ~erial num-ber trAn~mii~iPn~ and a return to wait for the start of the next time slot. Lf a rolliPi~,n is not d-~tecten7 5 in the rh~inE step 1507, the state of the ack field is tested (at 1513) and the current address count is loaded (at 1515) for the peripheral. If a busy conr7.it;on is noted from the ack field, the process return~ to wait for the start of the next time slot.
FIG. 11 depicts the bit-by-bit timing diagram of the 1 0 clock, and two 8 bit sequences which are MAnrhe6tçr anrod, t7.
by the clock. One sequence of pulses 1103 is of the M~7nrh~ster code for the value 254, the other set of pulses CG-- 9C~on~7~ to the vlue 255. The ~li~-ence be~ween the pulse trains being the least ~iEnifisAnt bit.
1 5 In the pref~ ,d _mho~ t of the present invention a convanti~ nAl MAnrhA~ter F.nrodar 709 is used to encode data sent out over the high speed data bus. The MAnchast.,r ~nroner 709 output of the data transfer a~paldtuS is i~7.~ntirAl to the clock used to derive the MAnrh9ster code if the data bit 2 0 sampled is a zero, and it is inverted from the clock if the data bit in the s~mpled interval is non-zero. The MAnrhaster F.nronar 709 output is one of the two inputs to the Collision Detect 713, an Exclusive-Or function gate.
The other input to the Collision Detect 713 is derived 2 5 from all MAnrhester F.nr,on~r 709 ouLI~uls of peripheral devices which are connected to the cellular radiotelephone by their data transfer apparati through data bus driver 715 and compa.ator 711. The reslllting uplink data bus line forms a wired-AND configuration of the MAnrhe~ter li'nro~7Pr ouLlJuls 3 0 from all attached peripheral devices. The Exclusive-Or f77nrtion is then performed with the two inputs, and if the MAnrhester çnro-7rn data bit mAtrh.qs the data bus state signal bit, then the Collision Detect 713 circuit output is zero, and the next MAnsh~ster PnCo~7~9d data bit from the Tx/Rx Shift 3 5 Register 707 is snifted into the Manchest,er Encoder 709 and then co~pal~d with the data bus state signal. The original 3 ~
value of the data bits ~tored in the EEPROM 217 is such t-h-at during the 6tar~up ~rocedll,e the peripheral device with the largest value stored in its EEPROM 217, and which is subsequently 6hifted t~rough to the Tx/Rx Shift Register 707, 5 and then out to the data bus, will have a Collision Detect 713 equal to zero for all 64 bits, and therefore it will gain access to the data bus first.
FIG. 12 depicts in a timing diagram the outputs of the Collision Detect 713 circuits of two data transfer apparati 1 0 which are '~cont~n~line~ for the data bus with the values 254 and 255 being output from their respective M~nrhpster .nr,o~ers 709. After gaining access to the data bus, this "winning" data transfer appalalus will send the information in its 64 bit word to the bus master 205 through the bus 1 5 master's data transfer a~,pal al~l6 219. If the Collision Detect 713 circuit output is 1, then there has been a cr~ n ~Ptecte-l, and the data transfer appa,al-ls has "lost" the bus dete-...;f ~t;on and therefore the data transfer apl)aldL-Is can not gain access to the bus. The data transfer apparatus that 2 0 ' ïoses" a bus contçn~ion del,e, ..~ t;on during the start-up procedure, in this m~nnRr, then increments its Priority Co~n~er 701 and does not ~ pt to gain access to the data bus until the next time slot. In this m~nnPr, each data transfer appaldlus 211 which fails to gain access to the data bus 2 5 during any one time slot during the start-up procedure increments its Priority Counter 701. The first data transfer al,l,a~atlls which gains access to the data bus will be given the address collebl u~ ing to the value one when it finally gains access to the bus. This address will be used in its Address 3 0 Field 407 by the device whenever it transmits data, or attempts to transmit data, for the duration of its operation over the high speed data bus. This address value is also the value stored in the Des~;n~t;~n Address 311 of downlink messages which it receives. When the data transfer apparatus 211 gains access 3 5 to the data bus, it transmits zero for the address in its Source Address Field 407 to the central radiotelephone processor - 2 l7 -~7~ ~
regi~ter 1001 in FIG. 10, register "C" in the radiotelephone's bu~ master data trsnsfer apparatul3. This is the infor_ation in the 48 bit Data Field 409, which ori~in~ in the peripheral device EEPROM 217. The central proceasor 205 in the 5 radiotçle~honç 113 will use this information to assign a time slot to the data transfer apparatus 211. The central radiotelephon~ ylocessor (bus master) 205 ~lloc~ter dedicated time slots within each frame 601 for peripheral devices (to send digitized voice messages to the speech coder 223) w-hich 1 0 receive analog voice messages as input, such as a handset 109 for a mobile rArliotPlephnne 113, or the portion of a portable radiotelephone which cont~in~ the m icrophone input 209. The analog voice m~qS6~E~e6 are digitized by a codec 213.
Data transfer a~palal,i which fail to gain access during 1 5 any particular bus co.-t~ ;on in the start-up plocedu-e will retry again with the Priority Counter 701 incrçm~ntR~ by one.
Again, the data transfer apparati atl enlplillg to gain access to the data bus will break the bus con~*. .~ ;on by doing a bit-by-bit co ,~a~;son between their respective ~nrh~ster ~.nroder 709 2 0 oulpu~ and the data bus state signal through the Collision Detect 713 circuit. A peripheral device's data transfer a~pa~a~us 211 which fails to gain access to the data bus will stop trying to gain access to the bus when the output of a M~qnrh?~t~r ~nro~ bit fails to match the data bus state 2 5 signal through the Exclusive-Or fi-nrtion of the Collision Detect circuit 713. FIG. 12 depicts the output of the Collision Detect circuit 713 when a collision is detected in the eighth bit transmitted resulting in a "1" value from the Collision Detect circuit 713. Accordingly, the second data transfer apparatus 3 0 which gains access to the data bus will assign itself a value of two for its address on the bus. Again the 48 bit data field iB
transmitted to the bus master 205 (central radiotelephone processor), and if the peripheral device cont~ining the data transfer apparatus is an analog voice message input 3 5 peripheral device such as a radiotelephone h~n~et 109, then a dedicated time slot will be ~llor~tçd in each frame 601 so the s~

data transfer appaldius 211 can transmit to the bus master 205. In ~e ~lere-.ed ~mhorlimtqnt~ there is a m~ulll of five such time slots which may can be ~qRiEnpd to voice message input peripheral devices such as h~n-lRetq 109 for mobile 5 r~liot~lerhon~ 113. The sixth time slot is a general use time slot which is used to send non-voice digital data (digital data) messages ~nd control messages for the data bus.
This start-up procedure ~et~iled a~ove continues until all of the devices a~ g to gain access to the data bus have 1 0 gained acce6s to the data bus; have s-RRign~13 tllçmqçlves addresses; and have sent the specific peripheral device inform~tinn, used to est~hliRh data bus access priority (by which the central radio processor may assign de~lic~ted time slots) for the duration of the operation of the data bus, to t_e 1 5 bus master 205. The Transmit Regi~ter 705 serves as a buffer during the start-up l,locedu.e so in the case where data bits are no longer available in the TxlRx Shift RegiRtçr 707 for the next attempt to gain access to the data bus, by a data transfer apparatus 211 which has previously failed to gain access, the 2 0 data bits can be shifted into the Tx/Rx Shift Register 707 from the Transmit l?egi~tçr 705.
During normal operation, and during the çYecl~til-n of the start up ~,ocedufe, the bus master 205 will flow control digital data messages. The bus master 205 will not flow 2 5 control digitized analog voice messages. The digitized voice messages are routed to the speech coder 223 for procePRing The speech coder 223 is used to control audio fi~n--t;on~
through the Audio Control function 231. The digital data messages are routed to the bus master 205 for l.~oceR~ E.
3 0 Therefore since the digitized voice messages are not actually processed by the bus master, the bus master 205, which has the speech coder 223 under its control, allows messages destin~l for the speech coder to be sent without "holding off' (stopping and starting tr~nRmiRRion to the speech coder 223 3 5 for some variable time sequence) the digitized voice messages.
Digital data messages which are to be processed by the bus - 2'~-master 205 can be "held o~' until the bus master 205 i~ not busy proces.~ing message6. The bus master 205 holds off these message6 by sen(ling the Ack E'ield 305 with a value of "1."
When the bus master 205 is not busy proce~ing messages, it 5 will send out the Ack Field 305 with 8 value of zero, and peripheral devices wishing to send messages which are to be processed by the bus master may then attempt to access the bus master. A depiction of this flow control to and from peripheral devices is con~inp~l in the flowcharts of FIGS. 13A
1 0 and 13B.
After addresses have been ~signe~l to all data transfer apparati attempting to access the data bus, the bus master 205 and speech coder 223 can commllnicate with all peripheral devices connP~te~l over the radiotelephone data bus. In normal 1 5 operation the key merh~ni.~m~ of the data transfer al,~aldLus when it i6 going to transmit data out to another data transfer apparatus connPcted to it over the data bus are depicted in FIG. 9.
The data transfer apparatus 211 within each peripheral 2 0 device can process either digital data signals or digitized analog ~ien~l~, digitized analog voice messages being of particular i~pOI lance in cellular radiotelephone applications.
In the preferred Rmho~1imPnt, the information sent in the Priority Field 403 of a peripheral device 203 inpuLLing digitized 2 5 analog voice messages to the radiotelephone 113 over the data bus will be such that the data transfer apparatus 211 of the peripheral device 203 will normally be able to acceRs the data bus for at least one time slot 603 during every frame 601 of the data bus operation. This is because digitized analog voice 3 0 messages are not flow controlled by the bus master 205, moreover, the bus master 205, because of the information (originally stored in the EEPROM 217) transmitted to it from a particular peripheral device 203 (which inputs digitized analog voice messages) during the start-up procedure, will 3 5 allocate at least one time slot 603 to each OI such peripheral devices 801 depicted in FIG. 8, during each ~rame 601, up to a - 3~D -7~3~
x.. lY~ of five dedicated time slots in the present invention.
Time slots which are not ~le-lic~tetl to peripheral devices which input analog message6 are shared in a time multirl~Ye~ m~nnPr by data bus Control Messages 803 transmitted from the bus master 205 to peripheral devices for controlling information flow on the data bus and messages transmitted to and from peripheral devices 805 which do not have ~le~lir~tçd time &lots.
The data bus controls bus access for messages which are not digitized voice messages by trant~ ,h~g downlink header 411 il~lma~ion in each timeslot with time slot ~.yllchro~ t;on information and by setting or clearing the Ack Bit Field 305, thereby giving peripheral devices permiRRion to send (or to hold off) such messages on the data 1 5 bus. Each data transfer apparatus 211 has a particular address which as ment;one~l above, was del~ hled during the start-up plocedu~e acco~Lng to particular information c~nt~ine-l in EEPROM 217 which resolved the start-up bus content;on.
2 0 If the peripheral device is a peripheral device which receives analog voice messages at its input, such as a h~ntlRet 109 for a mobile cellular radiotelephone or the user interface portion of a portable riq~iotPlçphnne, the data transfer apparatus 211 will allocate itself a priority with respect to 2 5 other peripheral devices that will ensure the peripheral device normally has access to a time slot during every data bus frame 601 so that it can send information to the speech coder 223. For peripheral devices 203 which are used to input analog voice messages, this is done by writing a Priority Field 403 3 0 with a value of two-hundred fifty-four into the eight bits ~lloc~ted to the Priority Field 403 c-~nt~in~d in the 64 bit word constructed by the data transfer apl,aralus 211.
In the process of flow control, data messages are sent to the bus master miclo~locessor only when the state of the 3 5 acknowledgement field indicates a not busy condition. Voice messages, however, are not subject to control depçntlent upon ~a~r~3~
the state of the acknowledgement field. Since the voice me~Bage iB not delayed, the real time procçsRine of the voice me~sage is qnhsln~ed becP~n~e the voice mes6age is directed to the speech coder wit~out delay. A6 shown in the flowchart of 5 FIG. 13A, the data transfer apparatus for the peripheral device waits for the start of the downlink ~im~slot at 1303. A
deter nin~tion of whether a voice message or a data message is to be sent i6 made at 1305. If the message is a voice message, digitized voice mes6age information is sent on the 1 0 DSC bus to the Audio R~gis~r, at 1307, and the proces6 returns to wait for another downlink timeslot. However, if the dete~ tion i6 that a data message i6 to be sent, a dete~ ...i..~t;on of the state of the acknowledgement (ack) field is made, at 1309. If the ack field indicates a not busy condition 1 5 (ack=0), data is sent to the bus master mi~o~vcessor 205, at 1311. If the ack field intlir~tes a busy state, the process waits for another downlink timeslot and delays the trs3nRmiRRion of the data message until the ack field in(li~P.t~s a not busy state.
In the opposite direction, the peripheral receives 2 0 messages directed to it from the data bus. As shown in the process of FIG. 13B, the ir~cQming message is ~leço~lçd (at 1315) and a tlele~ ...i,.s~t;on iS made (at 1317) whether a data or a voice message has been received. If the received message iB a data message, the data is routed (at 1319) to the sçlectec 2 5 register identified in the downlink message.
Flow control of messages received by and transmitted from the master as shown in the flowcharts of FIG. 13C and FIG. 13D. The master receives a meSR~ge from a peripheral and decodes the message, at 1323. Again, a determination is 3 0 made (at 1325) whether a data message or a voice message was received. If the message was a voice message, the voice message is routed (at 1327) to the Audio ~egi~tçr. If the received message was a data message, the state of the ack field is determined, at 1329, and if the ack field inflic~teR a not-3 5 busy state (ack=0) the data is routed to the m icroprocessor, at 1331. Otherwise the rece*ed data is ignored by the busy - 3~2 -2~87~ ~
mi.;..,~locessor and the process returns to await the ne~t received message.
A tr~nRmissil>n from the master follows the flow control process of FIG.13D. The process waits ~or the start of a 5 timeslot, at 1335, and del~ es, a~t 1337, whether the message to be sent is a data message or a voice message. If the message is a voice message, the digitized voice message is sent (at 1339) to the specific peripheral Audio RPgiFter. If the message iE~ a data mpssaee~ it is sent (at 1341) to the specific 1 0 peripheral.
Referring to FIG. 9 which depicts the throughput path of messages sent through the data transfer apparatus during poEt-st~rt up procedure operation, all ~igit;~e~l analog voice messages such as those ori~inAt;ng at a microphone 209 input 1 5 to a radiotelephone hAn~cet 203 whic_ are subsequently digitized by a codec 213, as in the ~. Çel.ed emho-limPnt come into the data transfer ap~a~a~us 211 at the Trans_it Regi~tp-r 901 where the data bits are serially shifted into the 48 bit Tx Register Bits 705, and the Audio Header 903 iB added to make 2 0 up the 64 bit word used over the data bus. The Priority Field cont~inR the value "254" which is applied as shown in FIG.
16A. All digitized analog voice messages are processe~l in this ms~nnPr through the Transmit Register 705. The data bits 905 which contain the ~ligit;7e~1 analog voice message bits are 2 5 then parallel loaded through a tri-state buffer 907. Then the internal routing of the data transfer appalat~ls 211 gates the tri-state buffer 907 to the final output register, l~x Shift l~giPter 707. From there, the 48 data bits (plus the Audio Header 903 bits) are serially transmitted to the M~nrh~ster 3 0 ~nrorler 709 then out on the data bus as described in the start-up procedure. In the case of peripheral devices used to input analog voice messages to the r~-liot41ephone (such as hsln~lRetc 109), the priority value in the Priority Field 403 is such that it will normally gain the bus over any other 3 5 peripheral device attempting to access the bus. Moreover, since it is a voice input device, the bus master 20~ will have - 3~3 -.~ s~ r~ ~ 3 synchronized the peripheral device 211 to a dedicated time slot BO that no bus cnrltentinn with another voice message input peripheral device should arise, and if bus contention does anse with another non-voice message peripheral device, the 5 high priority value of 254 will normally ensure that the voice input device "win6" a bus contention deterrninAtinn (gains access to the data bus to send its mlessage). The 16 bit Audio Header 901 which co.~ the Priority Field 403 with a value of 254 for a voice device, such as a hP.r~ et 109 for a cellular 1 0 mobile radiotelephone 113, is routed in parallel to a Header Mux 911, then to the tri-state buffer 907, where the 16 bit header is stored with the 48 bit data field until the intsrnAl lou~ing bus of the data transfer a~l,al~lus 211 gates the 64 bit word int~ the Tx/Rx Shift Register 707. In addition to a Priority 1 5 Field 403 value of 254, the Header Mux 911 loads the ~2egirtqr Select Field 405 with the value "F" BO that digitized analog voice messages are routed to the Receive Audio Register 1007 in the data transfer apparatus, shown in FIG. 10, which receives the message. This register 1007 may be con~inp~l in a 2 0 data transfer apparatus used to transfer information into the central proce~cine portion 207 of the bus master 205 or in the data transfer appa.atus 211 of a peripheral device which can rece*e digitized voice messages from the central proc~ss~i*g portion 207 of a radioteleI?hr nP The last field loaded by the 2 5 Header Mux is the Source Address Field 407 which was dete~ ed during the start-up procedure and iB stored in the Control Register 901 from where it iB loaded into the Header Mux 911. From the TxlRx Shift Re~ r 707, the 64 bits are serially sent to the M~nrh?~t~r ~nro~3er 709 then out on the 3 0 data bus and to the Co~ on Detect 713 circuit. In the case of a voice input device, such as a h~n~l~et 109 for a cellular mobile radiotelephone, the bits oriEin~t;nE in the Audio Header 901 are routed through the Header Mux 911 and the tri-state buffer 907 without motlifir~t;on, then to the Tx/Rx Shift 3 5 l~egi~ter 707 and then to the M~nrh~ster Encoder 709. From the M~nrhrster Encoder 709, the Priority Field 403 bits are ? 9 t~en shi~ed s2rially to the data bus and the Collision Detect circuit 713 as in the Bta~-Up procedu:re. The 16 bit header word output of the M~nr.ht~eter Encoder 709 is bit-by-bit compared as in the start-up procedure. The Manchester 1i~nrol3er 709 output is one input to tlne Collision Detect 713 Cil CUit and the other input i8 the data bus state signal as in the start-up p~ocedule. In this manner, the priority value of 254 which was $1!~RigllPd to the digitized analog voice messsge by the Audio Header 901 and which makes up the PIiority 1 0 l?ield 403 of the digitized analog voice message is serially transmitted to the data bus and the Collision Detect circuit 713. As in the start-up procedure, the Collision Detect circuit 713 does a bit-by-bit c~,Lupa~;son between the output of the M~n~hester ~.nroller 709 and the data bus state signal. The 1 5 Priority Field 403 i8 the first portion of the 16 bit header word which is compared by use of the Exclusive-Or function within the Collision Detect circuit 713. In the case of a voice input device, t-h-e Priority Field 403 has a value of 254. Because of the mPrh~ni~m~ employed by the Collision Detect circuit 713, 2 0 M~nrh?rter Encoder 709, and means used to generate the data bus state signal, the peripheral device with the hiehest value in its Priority Field 403 will gain access to the data bus when there is bus contqnt;on During the bit-by-bit comparison, at a particular bit, a peripheral device which does not have the 2 5 hiehest value in its Priority Field 403 will detect a colli~ic.n and stop attempting to access the data bus. Similar to the procedure described in the start-up procedure (except only the header 411 portion of the time slot is used to deterine bus contention proceeding from the most ~ignific~nt bit), the 3 0 peripheral device with the highest value in its Priority Field 403 will gain access to the data bus. If the priority fields are equal, then the Register Select Fields 405 and Source Address Fields 407 are processed through the bit-by-bit comparison to determine the data bus con~ntion, as in the start-up 3 5 procedure. In the case of a voice input device, the voice input device will normally "win" the data bus determination in the - 3.; -~ ~ 7 ~
first ~ bit6 of the bit-by-bit co ,pal;son (the Priority Field 403) bec~ e the s~alue, 254, of the Priority Field 403 i8 normally greater than all o~her values that c,m be stored in the Priority Field, except for one value (255). T]he message accordingly 5 takes priority over all mes6ageF. seeking bus ~llor~t;r~n of a lower priority, less than 254.
A6 depicted in FIG. 9, a Prio;rity Field 403 di~a~ t from the value 254, ~ign~cl to digitized analog voice messages in the Audio Header 903, is ~ rP~l to other types of mes6ages 1 0 which are not routed t]hrough the Transmit Regi6ter 705.
These other types of messages are digital data messages routed into the data transfer alJ~ald~us 211 at the VO Buffer 915, one byte at a time. Two types of data are routed t~hrough this I/O Bu~fer 915: one type is data which does not require the 1 5 high speed real time s~mrlinE of digitized analog voice messages, this type is routed with an initial priority value of one in the Pr;(,l;Ly Field 403; the other type is for data messsges which require a priority value, 255, higher than that of digitized analog voice messages (254) for messages of 2 0 the highPst priority.
For example, the lower priority messages (Priority Field value is less than 254) may include data bits serially inputted from a keypad 215 of a portable cellular radiotelephonP or the keypad 215 of a h~n~et of a cellular mobile radiotelephone, or 2 5 digital data ori~in~t;nF from a f~r~imile m~rhinP 107, which needs to be time slotted and frame 601 formatted for the high speed data bus so the messages can be sent to the radiotelephone'6 main processing block 207 without the high speed s~mpling required for digitized analog mes6ages. The 3 0 data transfer a~ald~u6 211 of the present invention can be conts.in~(3 within peripheral devices such as a f~r~imile m~rhinP 107, cellular mobile radiotelephone h~n-l~et 109, the user interface portion 203 of a portable or mobile cellular radiotelephone, or other devices which may be connçct~l to a 3 5 cellular radiotelephone's main proces6ing block 207, so that ~7839 info~nation may be transmitted by the cellular radiotaleph-ne 113 through the cellular system.
In the case of keypad 215 information (The data routing outline here applies to other information which does not 5 require the higher priority of digitized analog voice message6.), the keypad sample is leceived as a single byte of information at the VO Bu~fer 915. The data is then tested to ensure a valid key press has oc, ~.1 l ed and built into a 33 bit word in the Deboullce-RegiPter fimrt;nn 917, where the 33rd bit 1 0 is a swit~hhook in~lir~tor which inAic~tes whether the cellular radiotelephone handset is in its hang-up cup or not.
The Debounce-Regi~ter fimrt;on 917 colllpalc:s a sample of the ~-~mrle-l key presg byte transmitted from the VO Buffer 915 with a previous s~mrle~ and after comp~;l-g several 1 5 sequential s~mples to verify that a valid press has occurred, the key press inform~t;~n is for_atted into a 33 bit word and transmitted in parallel to the Tx/Rx Shift Register 707 as a 48 bit word into the data field bits through the Tri-state 907, the additional 15 bits in the 48 bit data field being configured as 2 0 invalid bits. Appended to the 48 bit data field created in the Header-Mux function 911 are the Source Address Fields 407 and RegiP~er Select Fields 405 along with the Priority Field.
In the case of the data fields, for these digital data messages with priority lower than 254, created in the 2 5 Debounce-Register filnr~;on 917, the Register Select Field 405 c- n~in~ the address of the ~n~Ret/~L~loces3or register 1001, see FIG. 10,(Register "C") in the data transfer appaldlu6 219 conn~ctPd to the central p~oce~ g portion 207 of the radiotelephone from where the bus master processor 205 3 0 retrieves data sent to it over the data bus. The Source Address Field 407 as determined during the start-up pl~ocedule is a~l wa~ls conQt~nt in the Debollnre-Register filnrt;on 917 and cont~in~ the address determined during start-up in the 4 bit field Source Address Field 407. The Source Address Field 3 5 407 and Register Select Field 405 are transmitted to the Header Mux 911, and the 48 bit data field is tr~nQmittecl to the Tri-state ~ J~ J ~
buffer 907. The priority value, initialized to one in a Priority Counter 701 i8 ~ppenlled in the Priority Field 403 to make-up the 16 bit header of the 64 bit data bus word in the Header Mux 911, and after the Priority Field 403 is added to the 16 bit 5 header,1~he entire 16 bit header is then transmitted into the Tri-state 907 from the Header Mux 911in parallel, where it i6 comhinPcl into a 64 bit word. The entire 64 bit word.is subsequently tr~nRmitt~(l to the Tx/Rx Shift Register 707.
Af'ler the 64 bit word is in the Tx/Rx Shift RegiPt~Pr 707, the 1 0 data transfer apparatus a~ pl s to shift t,he word onto the data bus in the next app.op~;ate time slot, which is a general use time slot 803 or 805, and not a time slot 801 ~llor~trvd to a voice input device. In the case of a digital data message with a priority lower than the value of a digitized analog voice 1 5 message (254), such as key press inform~t;on the data transfer apparalus 211 will a~,le~p~ to gain access to the high speed data bus every time slot. The mechs~nism for g~inine access is similar to that used in the start-up procedure, the M~n~h?~ter ~.nro~ler 709 output is compared to the data bus 2 0 state signal (plockR,~ from the most si~nific~nt bit to the least si~nific~nt bit of the header 411) for thel6 bit header word to determine if there is data bus contention, and if the Collision Detect circuit 713 detects a colliRion, the data transfer appa.atus 211 will stop trying to access the data bus.
2 5 As in other bus contant;on scenarios ~iiRcll~se~l above, a bit-by-bit co--,pa-;son is done by each peripheral device's data transfer apparatus attempting to gain access to the data bus.
When a data transfer apparatus loses the bus con~ent;on to another data transfer apparatus, the Collision 3 0 circuit 713 output is routed to the Internal Bus Arbitrator 923 within the data transfer apparatus 211 which then increases the value of the the data transfer apparatus' Priority Field 403 by a value of one. The Internal Bus Arbitrator 923 sends a clock signal to the Priority Counter 701 in order to increase the 3 5 value of the Priority Field 403 by value of one. The initial value in the Priority Counter 701 is one at the be~innine of the bus - 3~3 -2 ~
access attempt by the data transfer apparatus. After a single failed attempt the Priority Counter '701 has a value of two which will be loaded into the Header Mux 911 as the Priority Field 403 from the Priority Counter 701 the next time the data transfer apparatus 211 attempts to gain access to the data bus.
This next attempt will occur when the next time slot becc~mes available. Iteratively, this procedure continues until only one data trar~sfer app&.atus is left attempting to gain access to the high speed data bus, this r~m~ining data transfer ~pp~ lus 1 0 will gain acce6s to the data bus. Af~er a particular data transfer apparatus gains access to the high speed data bus, the Internal Bus A.l,i~la~o~ 923 will reset the Priority Counter 701 of the data transfer apl,ald~.ls which gains access to the lowest value, one. A data transfer apparatus that was unable 1 5 to gain access will try to gain access to the data bus when the next time slot bec~m~ available. Again, if more than one data ~l~rer appald~.,B is ~ r~ E to gain access to the data bus, the bus contenti~n will be determinP~l as before, there iB a bit-by-bit col,lpal;son of the Mslnr.h~st~r F.nro~r 709 outputs 2 0 with the data bus state signal (after being passed through a comparator to ensure a proper digital signal is available) through the Collision Detect circuit 713 to detel~lle the bus cQn~snt;on As before, in this case where the priority value is less than 254, when the output of the MP~n~hl?~t~r ~.nrocler 709 2 5 does not match the data bus state signal, a colli~ion will be ~etect~l and the particular data transfer apparatus which detects a bus colliRion will increment its Priority Counter 701 and wait for another time slot in order to try to access the data bus.
3 0 As m~n~inned above there is a type of digital data message ~igne-l a priority value higher than the value of 254 assigned to digitized analog voice messages. This type of digital data message (high speed message) is also input to the data transfer apparatus I/O Buffer 915. This high speed 3 5 message requires faster access to the bus than any other information sent to the data transfer apparatus 211. The ~7~39 routing for t~is data i6 as described above for data which starts with a priority value of 001 in the Priority Counter 701, except that the high priority data begins with a priority value of 255 loaded into the Priority Counter 701. With this value of 255 loaded into the P~;o~;~y Counter 701,after the Dat_ Field 409, Register Select Field 405, and Source Address Field 407 are ~e~s.qmhle~l in the Debounce-Rç~i~F~er function 917, the Data Field 409 is transmitted in parallel to the Tl; st~Ate buffer 907, and the RegiFter Select 405 and Source Address Field 407 are 1 0 sent to the Header Mux 911 where the Priority Counter 701 loads the value 255 into the Priority Field 403 bits. Once the Priority Field 403, Re~ietçr Select Field 405, and Source Address Field 407 are loaded into the Header Mux 911, the 16 bits are trAnRmitted to the Tri-state buffer 907. Once both the 48 1 5 bit data field and the 16 bit header field are in the Tri-state buffer, the 64 bit field ie. shifted in parallel to the Tx/R~ Shift giFt~r707. Therefore, when the next time slot access OppOl lullil.y occurs, the data transfer apparatus will attempt to access the data bus. During the bit-by-bit comparison of the 2 0 Priority Field 403, a data transfer apparatus with the value 255 stored in its Priority Field 403 will gain access to the data bus at the next available time slot unless there is another data transfer apparatus with an equal value in its Priority Field 403, in which case the bus contention will be determined by 2 5 e~l~cee~linE bits in thel6 bit header as described above: the e-l-~cee~lin~ bits of the M~nrhçster çncollp(l 16 bit header word will be bit-by-bit co,ll~ared (from most ~ignifir~nt bit to least ~ienifi~qnt bit) with the data bus state signal to d~te~ e the bus c~ntention. As previously discussed, each bit of the 16 bit 3 0 header word the data transfer apparatus has in the Tx/Rx Shift Register 707 will be shifted into the M~nrhester ~.ncorlPr 709 and the data transfer apparatus will determine if at any instance a bus rolliRion has occurred. If a collision has been detected for any of the header bits, a message with a priority 3 5 value of 25~ will not gain access to the bus, and it will wait for - 4() -the next time 610t when it will try to access the bus with the value of 255 loaded into its Priority Field 403.
Thus, for a data transfer apparatus which is attempting to transmit data over the high speed data bus, 5 there are at least three priority levels which the data transfer apparatus may load into its Priority Field 403 to try and gain access to the data bus, they are: a priority level of 255 for high speed messages which allows the data transfer apparatus to send out the message on the next available time slot 1 0 regardless of whether the next available time slot is allocated to it or not; a priority level of 254 for digitized analog voice messages which allows these real-time messages to be s~mple-l and tr~nsmitt~d to the central proces~inE~ portion 207 of the radiot~l~phonP 113 in a message time slot nllor~te~l to it 1 5 in every frame 601 by the bus master (The central p.oc~se:g portion 207 of the r~rliote!ephnne cont~in~ the bus master 205 for the radiotelephonP; memory devices such as RAM 229, ROM 227, AND EEPROM 225; and the speech coder 223 processor for ~ligit;7Pd analog voice messages); and finslly a 2 0 priority level less than 254 which allows messages with slower s~mpling lc:qui.c,~llents than real time voice messages to be input at the I/O Bu~er 915 and transmitted over a general use time slot of the data bus frame 601. The process of setting a priority count of"255" or "253" is shown in FIG. 16B.
2 5 The data transfer apparalus 211 is also able to r0ceive data transmitted to it over the data bus. The same data transfer apparatus can be used to receive messages as either a data transfer a~paldtus 219 on the bus master side of the data bus or peripheral device 211 side of the dsta bus. (On the 3 0 peripheral side, the data transfer apparatus 211 can be used to send digital data messages to devices such as a display 233 for the radiotelephone 113.) A block diagram of the means used to accomplish this i6 depicted in FIG. 10. The data is processed serially through the Comparator 1003 then decoded in the 3 5 M~nrhPster Decoder 1005, and then serially shifted into the T~/Rx Shift Register 707. The Mz-nrh~ster Decoder 1005 is 78~
well known in the art and serve6 to recover the data bits Il ~S.R~,;lled frorn the Tx/~ Shift ~E!iP~Pr 707 and MAnrh~Pster çnco~le~l for trAnRmi~ion over the data bus to the receiving data transfer akpa~d~us.
For example, in the case where the data transfer apparatus i~ used by the radiotelephone bus master 205 to receive data from peripheral devices, the M~nrhPster decoded data is shifted into T~/Rx Shift RPgiPtPr 707 and after the first 16 bits are decoded, the data transfer al,l alc~ s 219 is able to 1 0 determine for which of the addressable registers within the data transfer apparatus 219 the data is int~nde~l This is done by reading the ~egiFter Select Field 405 of the i..r~ g message using the ~giPte~ Select Decoder 1011. There are three main registers which may be addressed by Anot}lP.r data 1 5 transfer a~palalus, these are the ~An~lliet /llP l~eiPt~r 1001 (register "C"), the Rx Audio Register 1007 (register "F"), or the Control R~gPt~r 1009 (register "E") of the data transfer appalatus. When data is written into register "C" 1001 to the data transfer apparatus 219 used by the bus master 205, the 2 0 bus master 205 sends out a downlink message 301 with the Ack Field 303 bit set high so that all peripheral devices are prevented from attempting to write to register "C" by the bus master 205. Conversely, register "F" 1007 within any data transfer apparatus may be addressed by another data transfer 2 5 appal a~us during any timeslot without regard to flow control.
RegiPter "F" 1007 is used to route digitized analog voice messages sent by a voice input device to the speech coder 223 through the bus master's data transfer appal~l,us 219. Again, digitized analog voice messages are allowed to be w~itten to 3 0 RegiPter "F", the Receive RegiPter 1007, without regard to the setting of the Ack Field 303 bit to a high value.
In the case where the ~eceiving data transfer apl)aldtus 211 is located in a peripheral device, the m~-~h~ni~m for receiving messages from the bus master central proces,sing 3 5 portion 207 of the radiotelephone is very similar to the case for leceivhlg message when the data transfer apparatus 219 - ~L2 -reCeiVeB meB6age6 for ~he central processing portion 207 of the radiotelephone. When the peripher~l device shifts in the 16 bit header ~rom the M~nrhester Decoder 1001 to the 1~ Shift Reg-~ter707, the data tran6~er appalalus iB able to determine 5 which register within the data transfer apparatus 211 will receive the data, the Control Register 1009, the ~ntlset/~lP
R~giFtPr 1001, or the lReceive Audio ~eei~ter1007. Then depending on which of ~he registers has been selected (by reading the Register Select Field 309), the Tx/R~ Shift l?~gi ster 707 will parallel load the destination register with di~elent size fields. If the Control l~gistçr 1009 has been selected, a 32 bit field from the data bits in the l~ Shift Register 707is shifted to the Control ~egiFtçr 1009. If the Receive Register 1007 has been ~lectP-l, then a 48 bit field is loaded into the 1 5 Receive Audio Register. If the ~nrl~et/~ egiFtPr 1001 is selected, then the entire 64 bit word in the Tx/~ Shift Register will be parallel loaded into the ~nl1Ret/~ egiFter 1001.
The p,erell~ d PmhorliTnent of the present invention uses a data bus which Plimin~t~s the need for separate signal lines 2 0 to carry analog information from the user interface portion of a radiotelephone to the main processing portion of a radiotelephone. Moreover, the system of the pl efel~ed embo~limPnt is able to accommodate five voice message input devices and enables the radiotelephone to process the 2 5 information without a ~ienifirAnt degradation of the voice message. The system is able to ~rçommodate digitized voice messages and digital data messages by use of a time multiplex scheme which gives a higher priority and ~ lic~qte time slots to digitized analog voice messages. The p~are..ad 3 o ~mhotliment of the present invention flow controls digital data messages which are processed by the central radio processor, but it allows digitized voice messages to pass without flow controlling such messages. A hardwa~e apparatus is impl~mented to determine bus contention by devices 3 5 attempting to access t~e data bus simultaneously. The hardware apparatus is also used at the start of the operation - 4~ -i~87839 of the data bus to determine bus contention which results in the ~110c~tiQn of addresae6 to all peripheral devices connecte~l over the data bus to the radiotelephone. The entire word ~ormatted by the data transfer apparatus of the p~efell~,d 5 emho-liment. iB uged to dete~ e bus contention, including the data field. Also, the system of the l)lefelled embodiment operates on the order of a magnitude faster than data buses found in current cellular radiotelephonPs.
As ~liRcll~se~l previously, digital speech iB needed at a 1 0 constant data rate and flow controlling it will adversely affect audio quality. Since speech messages are h~nllle(l by a sepalate proces6ing unit in the bus master, not flow controlling speech will not affect the operation of the main processor. Flow control is accompli~hPd by using a one bit 1 5 field which is sent from the master to all peripherals every timeslot. When this bit is set active, the bus master is busy and cannot receive any data or control messages, however, speech messages are unilltell ~p~ed. When the bit is cleared, the master is ready to receive the next data or control 2 0 message. This bit can be set and cleared by two methods.
One, the bit is set ~sllt~m~t~ ly whenever a message is recei~ed by the master. The bit remains asserted until the master has read the message, at which time the bit is s~llt~msltirs~lly cleared allowing further c~ tion to take 2 5 place. .qecontl~ at any time, the master can set the bit to stop data or control messages from being sent. The master must then clear the bit to allow further commllnic~tion. When the bit is set, any data or control messages which are currently being sent are ignored. The data already sent will be 3 0 discarded by the master without ~ff~cting the previously received message. The peripherals trying to send these messages will attempt to re-send the message in every subsequent timeslot, until the flow control bit is cleared.
One possible scenario of the activity on the bus of the 3 5 present invention is shown in the timing diagram of FIG. 17.
In timeslot TSn the bus master is not transmitting any data and also the flow control bit (fc) is clear, allowing the in~ nmine control message to be completely received by the master.
In TSn+l the master is busy procesRing the previous 5 control message and is unable to service the bus, therefore fc iB set. The peripheral ~ ...p~:..g to send the data message ~enses that the fc bit i~ set and retains the message to retry in the next t;meElot The information that is transmitted to the master is discarded without ~ffect;ng any previously received 1 0 messages.
In TSn+2 the master iB still busy processing the previously l~eceived control message and fc is still set.
However, a peripheral which is al~emp~ing to send speech infom ~t;r.n i6 able to con pl~t~ly transmit its information.
15 Notice the master can transmit information to peripherals while fc i6 Bet or cleared.
In TSn+3, the master is still busy procesRing the control message and fc is still set. The master is again transmitting a message during this timeslot. The peripheral trying to send 2 0 the data message again senses that the fc bit is set and will try to send its data message in the next timeslot.
In TSn+4, the bus master has fini~hel1 proces~ing the control message and is now ready to receive messages. The peripheral atl~ g to send data finally senses that the fc bit 25 is cleared and completes its tr~n~mic~ion.
Note that whether the bus master is actively ~1 p.lh...;~ :..g a message or is idle has no affect of the operation of the flow control.

30 We claim:

Claims (7)

THE EMBODIMENT OF THE INVENTION IN WHICH AN EXCLUSIVE
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A data transfer apparatus for a radiotelephone unit which conveys digitized analog messages and digital data messages from a peripheral to a processing portion of the radiotelephone unit, said messages being sent in message timeslots of a message frame, the data transfer apparatus comprising:
means for processing analog information into a digitized analog message;
means for inputting messages and distinguishing between said digitized analog message and a digital data message;
means, at the peripheral, for detecting a first time slot allocated by the processing portion of the radiotelephone unit for conveying at least a part of the digitized analog message;
means, responsive to said means for distinguishing for sending said at least a part of the digitized analog message to the processing portion of the radiotelephone unit in said detected first timeslot;
means, at the peripheral for detecting a second time slot;
means for determining if said second time slot is marked busy by the processing portion of the radiotelephone unit; and means for sending at least a part of said digital data message in said detected second time slot when said second time slot is not marked busy.
2. A method of conveying digitized analog and digital data information messages from a peripheral to a processing unit of a radiotelephone unit, said messages being sent in message timeslots of a message frame, the method comprising the steps of:
processing analog information into a digitized analog message;
inputting messages and distinguishing between said digitized analog messages and a digital data information message;
detecting, at the peripheral, a first timeslot allocated by the processing portion of the radiotelephone unit for conveying at least a part of said digitized analog message;
sending, in response to said distinguishing step, said at least a part of said digitized analog message to a processing portion of the radiotelephone unit in said detected first timeslot;
detecting, at the peripheral, a second time slot;
determining if said second time slot is marked busy by the processing portion of the radiotelephone unit; and sending at least a part of said digital data message in said detected second time slot when said second time slot is not marked busy.
3. A data transfer apparatus for a radiotelephone unit which conveys digitized analog messages and digital data messages from a peripheral to a processing portion of the radiotelephone unit, the digitized analog and digital data messages beingconveyed in timeslots of a message frame, at least one of the timeslots being a general data timeslot, the data transfer apparatus comprising:
means for inputting messages and distinguishing between a digitized analog message and a digital data message;
means responsive to said means for distinguishing finding a digitized analog message, for inserting at least a portion of said digitized analog message into at least one timeslot of a message frame;
means responsive to said means for distinguishing finding a digital data message, for determining when the general data timeslot is not busy; and means, responsive to said means for determining, for inserting at least a portion of said digital data message into the general data timeslot.
4. A data transfer apparatus for a radiotelephone unit which conveys digitized analog messages and digital data messages from a processing portion of the radiotelephone unit to a peripheral, said messages being sent in message timeslots of a message frame, wherein each frame further contains a general data timeslot, the data transfer apparatus comprising:
means for processing analog information into a digitized analog message;
means for inputting messages and distinguishing between said digitized analog message and a digital data message;
means, responsive to said means for distinghishing, for prioritizing said digitized analog message to a higher priority than said digital data message;
means for allocating at least one of a plurality of the timeslots in a message frame to said digitized analog message; and means for reserving at least one of the timeslots in the message frame to a general data message timeslot for the message frame.
5. A method of conveying digitized analog messages and digital data messages from a processing portion of a radiotelephone unit to a peripheral said messages being sent in message timeslots of a message frame, wherein each frame further contains a general data timeslot, the method comprising the steps of:
processing analog information into a digitized analog message;
inputting messages and distinguishing between said digitized analog message and a digital data message;
prioritizing said digitized analog message to a higher priority than said digital data message in response to said distinguishing step;
allocating at least one of a plurality of the timeslots in a message frame to said digitized analog message; and reserving at least one of the timeslots in the message frame to a general data message timeslot for the message frame.
6. A data transfer apparatus for a radiotelephone unit which conveys digitized analog messages and digital data messages from a peripheral to a processing portion of the radiotelephone unit, said messages being sent in message timeslots of a message frame, the data transfer apparatus comprising:
means for extracting a message from a message frame;
means for inputting messages and distinguishing between a digitized analog message and a digital data message from a timeslot of said message frame;
means for processing said digitized analog message when said digitized analog message is distinguished;
means for detecting a busy condition and a non-busy condition of said timeslot of said message frame; and means for processing said digital data message when said digital data message is distinguished and said non-busy condition is detected.
7. A method of conveying digitized analog messages and digital data messages from a peripheral to a processing portion of a radiotelephone unit, said messages being sent in message timeslots of a message frame, the method comprising the steps of:
extracting a message from a message frame;
inputting messages and distinguishing between a digitized analog message and a digital data message from a timeslot of said message frame;
processing said digitized analog message when said digitized analog message is distinguished;
detecting a busy condition and a non-busy condition of said timeslot of said message frame; and processing said digital data message when said digital data message is distinguished and said non-busy condition is detected.
CA002087839A 1991-07-18 1992-07-14 Prioritized data transfer method and apparatus for a radiotelephone peripheral Expired - Fee Related CA2087839C (en)

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