CA2095156A1

CA2095156A1 - Multi-bit dac with dynamic element matching

Info

Publication number: CA2095156A1
Application number: CA002095156A
Authority: CA
Inventors: Bosco Leung
Original assignee: University Of Waterloo (The); Bosco Leung
Current assignee: University of Waterloo
Priority date: 1992-05-01
Filing date: 1993-04-29
Publication date: 1993-11-02
Also published as: US5406283A; GB9209498D0

Abstract

ABSTRACT

A sigma-Delta converter, comprising means for receiving an input digital signal; a digital loop filter and quantizer having an input and an output; a summer having a first input connected to the means for receiving, a second input connected to the output of the digital loop filter and quantizer, and an output connected to the input of the digital loop filter and quantizer for subtracting from the input digital signal an output digital signal from the digital loop filter and quantizer, and in response generating a difference signal for application to the input of the digital loop filter and quantizer; and digital-to-analog converter having a plurality of unit elements with minor mismatching therebetween, for receiving and converting to analog the output digital signal from the digital loop filter and quantizer, and in response generating an output analog signal, where the digital-to-analog converter comprises means for cyclically selecting successive difference permutations of the unit elements for converting each value of the output digital signal thereby cancelling the mismatching between unit elements.

Description

SENT BY: ; 4-29-93; 5:32PM; 4165951163 ~ ~6~4) 6~1-5756;# S

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~U~TI~ OVERSAMPLED D U WIT~ DYNAMlC E~EMEN~
~A~HING

Th4 pr~ent ~nvention r~lat~l~ t n general to over~ampllng conv~rters, and mor- ~artiGularly to a multl-~it (D/A~ digltal-to-analoguo oonvertor with dynamlc lu~ent ~atchlng.
~pakground of the InY~ntion Ovo~a~pllng m thod~ aro kno~n in the art Or AJD and D/A eonv r~ion for ovarcomlng probl~mo ~ocl~ted with th~
us~ of analogua low-p ss filter~ ln conv-ntional pul~s code modulatlon. Nor~ p~rt$cul~rly, in aonv8ntional ~y~tom~, low-p~a~ ~iltero must ~e u~ed ~o l~m~t alia~lng nois~ in A/D aonverelon and to ~ooth the output ar.~lOgNe slgnal in D/A con~rexsion. How-v4r, VI18I doe~ not lend ~t~elf w~ll to ~h- fabrication o~ h~gh-preci~lon ~n~logue clrcult3.
Rocont advances in ov~raa~pling t~chniqus~ are ~iecu~-d ln a pap~r entitled Over~mpl~ng Methodo ~or A/D ~nd DtA Converoion by JDmea C. Candy ~nd Gabar C.
T~mo-. Candy and ~e- dl~ou~ a num~er o~ embodimenta Or Slgma-D41la modulator~ ~or ov~r~ampling conv-r~lon. One proble~ di~cu~oed by Candy ~n~ Tem s lc th~ provi~ion o~
r~o ~ ~olc D/A convert-r in ~ultl-blt ~ D~ convoxter~.
~poal~lc~lly, the conv r~lon error in tho ~eed~ck ~/A
2~ conv-rter mu~t bo v~ry ~all (~.e. 1~ th~n h~lf the least ai5~ni~1cant bit o~ th- flnal output digltAl ~or~ hi~ 1~
l~a~u~o any DIA conver~lon error which 15 ~ded to thQ D/A
output ~ign~ diroatly cubtrAct-d ~rom the lnput 6ignal to the ~ig~-D~lt~ converter ~o a~ to appa~r ln th- dlgital ou~put of th- convorter. Candy and ~moa di~cu~ a number o~ atrA~egl4c ror ovorco~lng the probl~m o~ DfA error in Del~a-81gma modul~tor~, ~uoh a~ trlmmlng o2 D/A aonvertar el~ont~, ranao~izatlon o~ error~ intro4uc~ by miamatchlng or aompon-nt~, ~n~ digital aorrootlon of the D/A oonver~ion error.
How-v~r~ the prior art appro~ch o~ trimmlng co~pon-nt~
ha~ ~e-n found to be extrQ~ely exp-n-lve, ~nd the u~e o~
diqit~l rror corr~atlon re~ultc ~n A req~lr~nt ~or xtra oorroot~on hardwar~, aff de-crlb~a ln R.~. Walden, SENT ~Y: ; 4-29-93 5:33PM; 41~5951163' (604) 6~-5756;~ ~
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Cattletyp~, C C ~eme6, ~Arch~t-cturso ~or hlgh-oraer multl~lt s-A ~odulators," Pro¢oedlngs or tho 1990 IEEE
Intornation~l Sympo~lum On Circuit~ and By~te~, pp 895-898 ~May, 1~90) The u~e of r~ndom av~raglng iff xno~n to reeult ~n a r-ducod signal-to-nol~e r~tlo t8NR) b~cau~e all the h~r~onlc dl~tortlon~ have be~n tr~n~l~ted lnto whlte nol~o that fAll~ partly in~d4 th~ paecb~nd, a~ de~arlbed in a Carley , ~A Nol~e-BhApln~ Codor ~opology ~or 15~ B~t ConVertQr~ EES Journal o~ Solid-9ta~e ~lrcults, pp a6~-273 tApr~l, 1989~ ~tralg~tforward appllaatlon of clock-d ~veraging result6 in tones falllng ineide the passband, J
w ll ~8 an ~ncrQaee ~n pa~b~nd noi~, a~ d~cu~od in gre~ter detail below and A~ disou~d in YAshul S~klna, P,~r~y, ~Multl-blt ~ nalog to digital ooDverter~ with nonllnoarity aorr-ction u~ing dynam~o barrol h$ftlng,"
Maet-r Th ~le, pp 24-32 (~un 1990) & ~ Leung, ~'Arahitectur-- for Multi-bit Ovor~ampling ~tD ~on~erter ~qploying Dynam~c Elomont M~tohlng Technlgue~, n 1991 IE~
Int~rnational Sympo~lum on Ciro~t~ and 8y~toma, pp. 1657-~0 1660 (M~y, ~991).Su~mary o~ t~e Inventlon Aocordlng to the pre~ent lnvontlon, A novel ala~ o~
~ynamlo al-~en~ ~atchln~ t-chnlque~ 1- appliad to mu~t$-blt ~lg~A-D-ltA convertor~ ror tran~ating ~he h~rmonlo di~tortlon component- or the non-ideal r4~db~0k DIA
40nvorter to hlqh rreq~e~cy oompon~nt~ whlQh can t~en b~
rilt~r~d out bY u-e ot ~ deoimation rilt~r.
Moro partlcularly, ~ novel ~aodbaok DIA oonverter ic provided ~or u~e ~ithin ~ Slgma-Delta AID converter ln whloh indivl~ual l-v~l averag~ng i~ provld~d ~or converting diotortlon aompon~nt8 cau--d by el~en~ mlsmatch in the ~o~dbacX D/A converter to hlgh ~requency noi-- lylng outs~de oS tho pa~k~nd. ~hi~ nolao~ which i~ du~ to el~2-nt ~lo~atch, h~o a cimil~r ~roguenay behaviour a~
quantlzation nol~e. Con-eq~n~ly, the accuracy r~qulre~onte on tho ~eedbac~ D~A conver~er o~ the pre~ont lnv~n~ion ar- r~luoed wi1:hout $nor~-1ng tho ba~eb~nd noi~-SENT BY: ; 4-29-93 ; 5:34PM ; 4165~51163' ~B04) B9q-575B;# 7 apprecl~bly.
Accordlng to a ~eaond dynamia ~l-nont ~tchlng techniqu~ of the pre~ent 1nv~ntlon, ~ipolining and perlodlo capac~tor averaging t-chnlque~ are used for tsan~latlng the 5 harmonlc di-tortlon oomponent~ of tbe non-ideal ~IA
oonverter in un ov~r~a~pled Sigm~-Delt- D/A converter to ~-quQncy co~ponente ln the vlcinity o~ ~,/2, where f,i~ the sampling fregu~nay. These ~requency component~ oan then b~
~iltered out utillzing an analog lowpa~ ~nti-i~aqing-~$1t~r. compared to oonv-ntional elocked Averaging schome~
a~ dlccu~-od below, the toneQ gen-rated utiliz$ng pipellnlng with ~paoitor ~v r~ging are ~igni~aantly ~urther from th pa~band.

15A d~t~lled d~oription o~ prlor art ~onventlonal clocked ~veragin~ 6y~tem~ and the ~y~t~m o~ the pre~ent i montion ar~ provlded hereln below with re~erenoe to t~e ~ollowlng dr_wlng6, in whidh:
Figure 1 i~ a ~i~pll~lsd ~lock diaqram of a multi-bit 20 ~lgma-Dalt~ A/D convsrter ~ccording to the prlor art;
Flgura 2~ ~how~ for th- A/D convert~r of Figu~e 1, the trancrer charact-rlotlc~ or a two ~it, three level l~al r4~dback D/A con~-r~-r ~ nd the tran~r ohAr~at~ri~tic~ wh re there 1~ a ~l~mAtch between unlt el~ment~ in th- fe~d~acX DIA convert~r ~11) and ~111)~
Flgure 2b ehows the output ~nl of ~h~ ~odback D/A
eonver~Qr o~ P~gure 1 with V~(n) equal 0 2~ rOr ~ n ideal D/A conv~rter, tli~ a non-ld-al D~A converter, (iil~ a DIA
oonvlrter with cloc3c d averaging, and ~lv~ A D/A aonve~ter wlth indlvldual aver~ging~
Figure 3 le a bloak diagram of an ln~ernal D/A
conv t~r lncorporating lndivldual l~vel av~ragingt Flguro 4 lo a ~chem~tlc r~pr~-ntA~lon or a three-bit clooked rlipplng ~chem rOr the D/A oonverter o~ Flsure 3t 35Figure 5 a~pear~ out o~ routln- or~er rollowlng Flgure 3, And show~ ~ ~lock dlagram Or ~ ~econd or~er three~
~/A co~verter applying indiv4duAl l~vel averaging accord~ng .... _ .. , .. _.. , . , ... . .... ,.. , ._, .. _.. , _ .. , .. . .. . , _ , .. . . .

SENT ~Y: ; 4-29-~3; 5:35PM; 41~5951169'` ~6C4) ~ 5756;# 3 2 0 9 ~

to ~h- pr~ent lnvçntlon;
Figure 6 1~ ~che~atla dlagr~ o~ a ~wlt~h~d capacitor arr~y ~or i~pl~menting th thr~s-blt DIA
converter o~ Figur~ 3 and 5; and Fig~re 7ta) to ~d) ~how a ~wltchlng ~chemo and aircult for i~pl-menting a ~ultlply-~y-~wo ~ircuit wlth eapA4itor averaging ~ccording to an alternativ e~hodl~e~t o~ the invention.

Ono or tho main con~id-ration~ for incorpor~tinq A
multi-bit ov r ~ ~ingl~-blt quantizer ln~lde the feedbacX
loop or a 51gma-D~lta convert-r iB th~ pr~vRntlon Or o~erloading an~ thu~ th~ provi~ion o~ ~tabil$ty. ThiB
allowo th- u-o o~ h$gher ord~r cod~r~ whiah aan provid4 a ~uch high-r SNR for the ~ame ov~r~mpllng r~tlo. In additlon, eadh extra bit in th- quanti~er provldo- ~ 6dB
inaroa~e in the SNR.
Figura 1 ~how~ a typical, ~l~plif1ed bloe~ diagrAm of a multl-blt 8igma-Delta AID con~ r~or according to the prlor art, comprl-lng a ~umm~r 1 rOr rec lvlng an input analog olgn~l V~n~. An output of oummer 1 iB conn~ct~d to tho ~np~t o~ A loop ~lter 3 having a tran~fer ~unction H~z). An outpu~ o~ loop ~ilt~r 3 i- aonnact~d to the input o~ ~n N-blt AID conv~rter 5, Th- output lgnal V~n) from AID con~rter 5 lC ~-d bac~ ~18 N-~lt D/A oon~erter 7 to the n-ga~lve input o~ ~ummo~ 1.
Ac 4n exanplo, ln the ~rst or~r o~ Si~a-Del~a convert~r of Flgure 1 the D/A oonvortor 7 ~ay b~ oon~d~r-d AC h~vl~g two unlt ~leN nts, ~or gener~tlon throe an~log output l~v-lc Vf(n) ~ "0~ and "1~ hown in Figure 2atl) .
I~ there ie a ~i-mA~C~ betwe-n the two element~ ~UCh th~t their values ~ro l~l.l" and "1.2'l, th~ D/A converter 7 wlll hav~ thr~ vel~ corre~pondlng tos ~0~, "1.1/2.3' ~nd "1~ . tran~or ¢hAracteristio ~1~ a~ ~hown ln Flqur~
~a (li). If unlt element ~llpplng i~ done a~ a olock rrequenoy ~k, then ~t every clock cycl~, the trAnsrer SENT BY; ; 4-29-93; 5:~6PM; 4165951163~ ~6~4) B9~-5756;# 9 209~

c~r~ctorietic 3~ 0~ P~A conv~rter 7 will be ~hown in Flgurs 2a~11i), whoee l-v l~ are "o~, ~1.2~2.3~ ~nd Nln. I~ for axampl~ a dc input V~(n) of ~0.25U 1~ ~plied to V~(n) o~
the first order ~-~ modulator oi! ~i~ure 1 with an ide~l db~ck D/~ con~erter 7, the output V~n) wlll aon~ir~t of ~ p-rio~lc digltal ~equenco uOo~ Ho~ oO", l~o~ tc, resultlng $n p~rlodie D/A output requonce V~tn): I-on, "lJ2", "0~, ~lJ2~ a~ shown in Figur~ ~b~$). Thi~ ~-quen~e will produa~ an ~vor~g- o~ ~0.25U~ whloh ir~ ldentieal to the input.
For the norm~l non-ideal f~sdbacX D/a conv~rter 7, th-reedback ~ignal v~(n) w$11 no longer ~e p-rlo~ia. ~o ~nalyze the behavlor o~ thQ clrcuit con-ider the rlr~t ~our eycler~ t~e inltlal v~luo of th~ integrator in the flr~t order aoder (i.-. loop filter 3) i~ ~e~u~ed to bo zsro, then ~-~ coder outpu~ 00", "01", ~00~ 01" ~or th- rir~t ~our ayale~. Thererore V~(n) will con~ist of ~0", /a~3~ Ou~ ~1.1/2.3 u a~ ~hown in Flgure 2~(il). It ~ n that even though the ~eedb~ck ~ignal V~(n) 1B
interpolating b-tw~on th~ input ~ignal of no 25~, th-aves~g- value o~ ~(n) ;B ~-a- than Uo~a~n and ~ convorolon error 1~ cr-ated Thi~ oonv r~lon ~rror le ~-d bac~ to tho input o~ th~ aod~r, and ~tor-d in th~ inte~r~tor In the ~tuat~on conoldored ~bov~, a po6it~V~
2~ aonv-rclon orro~ wll~ ~e 6tor-d ln tho lnt~grator ~n~ wh-n the ab~olut- v~luo o~ the aco~mul~t-d ~rror 16 l~rg-r th~n 1 ~SB of the ~orward A/P converter 5 and extra no~ wlll b~ gener~tcd A~ tter of ~aot, ~inc~ the av~rhge v~lue o~ ths ~e~dbac~ ~lgnal Vf~n) 1~ ~orced to be the ~m~ ~ the lnput V,tn) valu- due to the n~gatlv ~o-dback a~tion o~ D/A
con~erter 7, th~ value ~1 1/2 3~ Will be ~enerated mor~
than SO% o~ th~ tlmo to co~pon~ate ~or the error Ihl~
r-ault~ in tho output aod~ ¢h~nglng rrOm a p~rlodla ~oqu-nae oS noon~ l~o~ 'oo~, "ol" to ono aon~l~t~ng o~ a~
oxtra ~oln At pr~etermlned int~rv~lo, Tho conv ntlonal aloakba averAglng approac~ enao~vors 40rroct thi~ conver~lon ~rror by av~raglng th~ E~c (2rror SENT ~`~' ; 4-29-93; 5;3~PM; 41659511~3 ' ~604) 637-5~56;#10 2 ~

of thB internal DfA oonvQrter 7). However, lt ha~ ~sen found that th~ avoraglng meahanism p~ovlaed by the ~Qedbnck loop of the S-~ conver~er can int~raot wlth the averaging m~chani~u providod ~y th~ clock-d av Æaging appro~cn. The foed~ack ~e~uenco V~tn) for tha Clo~kQ~ av~r~ging algorithm i~ 6hown in ~iqure 2b~ gAln i~ l~ ascumed t~at v~n~, ~nd bena~ the DAC lmpact Or D/AI aonverS4r 7, is~OOH, ~01~ 00~, nOl" ~or the first four cycle~, then ~ nOO" ~nd the 3~ aurvo 0~ FigUre 2a(11~ ctivated.
~h~e~ore V~(1)=nOn. Next, V~(2~=~0~ ~nd th~ ourva ~2 of Figure 2~tiii) 1~ ~ctivAted, giYing a Vt~2) o~ ~'1.1/2.3'l.
A~ n=3 ~h~ ourvo 3 1 1~ aativated~ How~v~r dus to the interpolation natur~ o~ the s-~ modulator, ~he ~odulator output V~n) ~oes not atay con~tant. In~t~ad, ~3) le "00", rs~ultin~ i~ a V1~3) oi~ ~IO~. Finally, at n~4 the curva 32 i~ actlvatea again. Again V~(n) has been chan~d and V~(4)=nO1", ro~ulting in a D/A output V~4) o~
~1.2/2.3H. ~t will bQ noted that this i~ ldsntical to V~z) and thsre~or~ no cancellation has ~een achleved.
~0 ~on~eque~tly thA ~ar~ge value o~ V~tn) ~l~rer~ ~rom 0.25, ~n~ liXe the ca6e di~ou~a~d above ln Whidh there ie not ~nit elemont ~llpping, a ~onver~lon error ia introduc~d.
Howev~r, in th~ pre-ent ca~e, the conYer~ion error ~tor~d ln the lnt-grator i~ negative. Again, when the ~ol~ts value o~ ~h~ Gon~Qreion error i~ largor than 1 ~59 o~ the forw rd A/D conve~ter 5, ~n ~xtr~ n ~01l will b~ ~nBrA~d .
It c~n be ~e~n that canoellation a~ any D/A lev l d p-nds on the rolativ~ timing ~etw~n the ln~eFpolating wn~ for~ Vf~n) a the ~eedback node and the fllpp~ng Wave~orm ~or ~electing betw~n the twe unit el~m~nt8 ChAracteriz~d by tran~S-r ~unctione 3 1 an~ 32. ~n the cae9 when the input i8 ~ ~lne WA~e inste~d of a dc slgnal, ~he interpol~t;ion wa~e~orm V~(n~ is a pul~e density mo~ula~d repr~entatlon of ~he ln~tant~neous valua o~ the input.
3S ThereSor~, given an input elnu wave at a partlcul~r Srequency, ~h~ intorpol~ting ~av~Sor~ c~n ~nteraot with t~e ~llpping operation in V~n). Tha low ~ro~uency portion of .. _.. . __. ,_ _, .. . . " , . _ _ . _... ~ . ... .... .... ... ... .

SENT ~Y: ; 4-29-93; 5:3ePM; 4165g51163 ' (B54~ 687-5q5~;#11 2~5~

the re~ulting ~ignal, whioh i~ o~talned by tim~ averagin~
~h- ou~p~ of D/A conv~rt r 7, will t~en be distorted fro~
the origi~al ~n~ wavo. Furth~rmore th- r~ultlng ~l-tortlon, whl~h ~ d p~ndent on the ~mount o~
canosllAt~on, le selat~d to t~e fllpplng ~re~uonay. ~hl~
d~tortion oan genera~e t~ne~ tnat ~re runotlons o~ th-$nput ~requency ~n~ rlipplng freguency, ~e dl~ou~s~d ln B.
~ eung, ~Archltect~res ~or Hulti-bl~ Overa~pl~ DAC
Eaployin~ Dyna~lc El~ent M~tcbing Teohnlques, n 1991 ~EEE
Int rn~tlonal 8y~po-~um on c~rcuite and 8y~tem~, p~. 1657-1660 (M~r, 199~).
To ~n~ure th~t the ~erag~ng action ocour~ regardle~-o~ the n~ture o~ the lnt~rpolating ~voform, the individu~l lovel avexaging ~yetom according to the proeent invention el~ ent~ u~o~ to repree-nt and ~ndlviduAl dig~tal code.
Wlth re~-rence to the f lr6t orq~r modulator of Figure 1, where V~n) ror the ~lr~t ~our cyc}e~ ia ag~n a~um~d to ~e ~OoN~ Nolu~ ~oonJ~oll~r th- D/A converter 7 output V~n) i~ ~hown ln Flgure 2b~1v). At n-l~ Y~ 00ll and th-~o curve 1 lc ~oleated, or Vr~l) wll~ b "0~ Th~ r~ct th~tth~ ~1 curv- h~ besn ue-d ~or th- 40d- "oo~ i~ now r-turned ln ~-mory, ~ ai-cuoeed ln greater dsta$1 b-low wlth re~r-nco to F~gure 3. At n-2, V~(2)-UOlH and t~o ourv~ ~ ie ~olect-a, which mean~ th~t Vtt2) w~ll b-~5 ~1.1/2.3~. AgAln th~ ~Act th~t ~l ourv- ha~ ~oon u~d for cod- ~01" ~ ~tor~d ln ~emory. At n-3, V~3)-~00~. ~$nc-~t n-l the aurve ~1 hae b-en u-~d, ~hi~ tlm the 32 aurve le e-leot~d. Wlth V~3)=nO0U and ~2 curvo, V~(3)~on.
Fln~lly ~t n-4, V~4) le ~01~l. Again, ~inoe at n-2 the ourve ~1 ~ac b- n ueed, th~ff tlme tho ~ curve le eeleot-d And Vt~4)~l1. 2~2.3~. Th~re~oro, both th0 value~ ~'1.1/2~3~' . and nl.zla.3~ hav- b-~n utillsed to r-pr-~ent ~h~ digltal cod ~01~, giving an aver~g~ valu~ o~ ~1/2n. Con~-quently, tho aV rAg- v~luo o~ V~n) i~ n0.2~. Thl~ la id-ntical to 35 th- input valuo and no oonv~r~lon orror ~ gen~r~t-d.

The DUtpUt ~egu-nca~ V~n) ~or ~he dlr~-r-nt Ca~Q~ aro now cusm~rlsed in ~bl~ I.

SENT aY: ; 4-29-93; 5:39PM; 4165g511B3~ (604) B97-5756;~12 2 0 9 ~

T~bl- I~ D~C Output Yf~n) For Diff~r nt Averaglng Algorlth~
~-~ C ~d ~ ~ Uni t El~ ~ont- _ n-l n- ~ ~ ~vg ~rro Ideal _ O 0.5 o 0.5 o.a~ o INo A~araging O 1 1O .1 0.239 1 ~L~ ~ o ~ ~L~
ndlvidu~l Level Av~r~in~ ~ 1.1 O 1.2 O.25 O
~ l ~ ..,.., ~_ _ __ I
T~e output cequ~nce~ V~n) ~or the dlfrerent Ca~B are now ~um~arized ln T~bl- 1.
0 T~W , ~ooording to the pr~on~ $nvention, th~
av r~glng ~o~lvity ~ppll-d to the ~/A conv~rt-r 7 do-- not lnter~er~ wlth the aver~g~ng actlvity provlded ~y the nega~lve feedback aotlon o~ the S-~ ood-r. Thi~ in t~rn eneuree th~t canc lla~ion Or the ~rror ~ c c~n be ~chlev d r~q~rdl~o~ o~ th~ lnterpol~tlon w~v-~orm Acao~d~ng to the mbodim nt o~ Figure ~, ~ D
oon~ rtor ~ pro~id~ ~or implem-ntlng ~he lndlv1dual l~vol a~ra~ing approach of th- pre~ent lnv-ntlon A di~lt~l lnput aignal L lo Appli~d to ~ th~rmomet-r-type enooder g ~nd to ~ m~mory lmple~nted by polnter~ ~nd updat~ olrcult~
11, ~hloh aan be l~pl-~nt-d ao a aet of regl~t~r~. T~e cnhoder 9 eet~ hlgh the numb-r Or out~ut line~ M thor~o~
e~u~l to the digltal codo ~ ~ho d~coded Jlgnal M ~nd ~n M-~lt polnt-r ~lgn~l ~ro~ circultc 11 arc applie~ to MxN
2S ~iteh 13 whlCh in r~pon~e oelects ~r-doterminsd oneo Or M unlt elsm~nt- lS Th~ outputs o~ unlt ele~ents 15 ~r-appll~d to an out~ut analog ~ummer 17 Thu~, ~ccor~lng eo the ~IA cOnv rt-r o~ Figure 3, ~ ory 1J lntroduood ~or ~adh traneter aurv~ o~ the D/A conv~t-r a~ ~aoh l~vel Thl~ will en~ur~ that all transt~r curvee corrc~pondlng to ..... . ... .. .

SENT BY: ; 4-29-93; 5:40PM; 41658511~3~ ~B~4) B87-575B;#13 _ 9 _ e~oh digital code ~re exercl~d in tho r-pr-oent~ion of that particul~r digltal ood~ I~ thl~ ~ppro~ch ls applied to the rir~t ord cOaer ex~pl- ou~lln~d akGve, the output o~ th ~ir~t four aycle~ wlll aga~n be Oo, 01, 00, 01 At 5 T~, t~ input cod~ lc 00 And the ~mon ~orreopondlng to th- l~vel 00 wlll provide the point-x th~t eel~ct~ th-appropri~te DJA conv rt-r tron~er curve The Algorlthm beqin~ wlth the curve ~ ~Figure 2~(11)) Yhlch ~e~n6 ~h~t the DJA ConV rtQr output Yill be 0 ~ho ~e~ory 11 lo oorre~pondlng to lnput code 00 lo th-n updAt~d and point~
to curv e~ ~t 2T~, the input coae ~- 01 and a dlf~erent m~mory loc~tion oorr~onding ~o the lev~l 01 provide~ the po~nter ~or ~elect$ng the ~ppropriAte DJA conv rter tr~n~f-r curve Agaln atarting off th- wlth curve ~ th-5 PJA oonverter output wlll be 1 ~, whlc~ ~- dl~erent ~rom tho clocX d av r~glng ca-e when th~ cu~v- Q~ i8 80l~0~e~ and a value o~ L-2 i~ generated Th~ m~mory aorro~pond$n~ to the l~v-l 01 1~ now updAt-d and point~ to the curve k~ At ~, thQ lnput code ~ 00 slnce at T~ th- ~mory aorro~pond~ng to 00 WA~ updat~d, th- curv~ oleoted thl- t~m~ and ~ 0 18 g-nor~ted Fln~lly, at 4T~ the lnput cod- ~- 01 Agaln, cinc- A~ 2T~ the ~emory 11 w~s updat~d, the curve ~ el-ctsd ~nce the DIA aonvert-r ha~ an output vAlu- o~ Th4r~or~ bo~h tho v~lus6 L~ and 1 2 ~ 3 2 3 2 3 havo k~n utlllzed to r4pr-~nt th- logic hlgh portlon of digltAl oode L
Thu-, ~or ~ glven aod~, th~ me~ory 11 provide~ a polnter to th~ ~ltoh ~atrlx M ~hlch in ~urn provlde~ the n xt eet o~ unlt lem~nt~ 15 Tho polnter le then updat~d Flnally, t~e M - 2' elements are aotlvat~d a~d ou~m-d to ~orm the analogue output a~ dl~cu~d Above, t~e uni~ el-m-n~ 15 are ~l~ppcd wlth re~peat to one ano~her ~or r-duclng di~tortion in th-output l~nAl ~or a olnuso~dal in~ut An ~ampl~ o~ the propo~cd ~l~pping ~ch-~ rOr thu A/D conv~rt-r o~ Fi~ur~ ~

., ........... .__, ,. ,_.. .. .. ,, . ._.. ... ..... , .. , . ~ .. .... . .

SENT BY: ; 4-29-93; 5:41PM; 41659511B3-~ (604) B~7-5756;$~14 2 Q ~

having three hitB ~l.e. oight unit olemen~ lg) 1~ ~hown ln Figure 4. ~ere ~nO...In7 repre~ent elgh~ unit el~ment~ of the DIA eonverter that ha~e ~ ~light ml~tch a~ong them.
Ou~...Out~ i~ a lin~r ~rray Or unit element~ whlch generate the ~in~l an~log v~lu~ corre~pondlng to ~ glvsn input alqital code. ~he clock-d ~llpping algorithm worX~
~y flipplnq th~ tran~for charaat~rlct~c- o~ the DJA
oonvert~r ~B ro~
Firet Or all, the top n/2 elom~ntc ar~ ~wapped with the 0 bottom n/2 lem~nt~ at a rate of f~. Secondly, the top n/4 ~lementa ar~ cwapp-d w~th ~he nex~ nJ4 elem~nt~ at t~e rat~
o~ ~. At th~ samQ time th~ bottom two parti~ion6 o~ ~f4 ~ en~e ar~ sw~pped a~ong t~em~lv~o. Finally, ad~cent p~ir~ o~ ol~m~nt~ are w~pped at th~ rate of ~olkJ4.
The ~lipping Rlgorlt~ 1~ ~mpl-mented in the pres~nt lnvention ky th~ D/A convorter shown ln Figuro 3, ~nd ~he frequency apectrum o~ th4 output indicates that t~
har~onic di-tort~ona have be~n ~odulated to ~requenci~e around multiple~ of f/8, inatesd o~ to white nois~. A
co~parl~on to th~ r~ndo~ Av-raglng caae indloatos that thl-approaah oan lnGre~ae tho 5NR perfor~Ance by l5ds for ~
0.1~ y~t~matlc lin~ar gradient ~l~mateh bet~een the lom-nt~ in the 3-~lt D/A aonverter.
For the a~ove approAoh r-sldual noise ia g-nerated in th b~--band due to ~noo~plste canc-llatlon.
In ord~r to get complet~ aanaellatlon ~or a given dlgit~l lnput o~ DIA conv~ter 7 ~Flgura 3), a complete ~et o~
an~log output~ ~orr~6pond ~o the dlgltal input h~6 to ~e eeloc*e~. In the 2-~lt ca~ oonsldered above, for tho dlglt~l aode al, th~ c~t has two slemen~e~ 1.1/2.3 snd 1.2/2.3. The number of el~m~nto in thi- oet ia r~4rrsd to ~t th~ "o~nc~ tlon cycle". As shown ln T~ble 1, if th~
input V~ i~ 0.25 the output o~ D/A onverter 7 la O, 1.1/2.3, 0, l.a/~.~ for ~h- flr~t rO~r aycle~ v~
change~ it~ v~lue ~t, for exnmpl~, cycle four, then DJA
con~erter 7 ha~ not ex rci--d all o~ the analog output-¢orr~ponding to t~e digital code ol ~n~ error~ wlll be SENT BY; ; 4-29-93 i 5:4ZPM; 4165951163 ' ~604~ 681-5756;#15 2 ~

~on~rat~. Con~guently, to r~duc- ~he error ~ue to i~p rf~ct canG-llatlon cyel~ should be kept small.
~owev-r, thQ canQollation cycle ror ~ D/A convert~r with N
~lem~nt~ 1- dep~n~ent in th~ digit~l lnput. A~ an examplo~
conolaer a 2-blt D/A converter whid~ ae four olQ~ent~ wlth valu-e: 1.1, 1.2~ 1.3, ~.4. For ~n lnput code o~ 01, four D/A output lgnal- 1.1/5, 1.2~5, 1.3/5, 1.415 hav~ to bo genQrated to n uro thAt the hver~g- analoçl output 1 exactly 1/~, ~hich ~ean~ that th Canc ll~lon cycl~ i8 4.
~0 on the otherhand, ~ith an ~nput cod~ o~ 10, th~r- ~re again ~our po~ible D~A output elgnal-. 1.1+1.2/5, l.a+l.3fs~
1.311.4/5, 1~4~1.1/5. In this oa~-, only a ~qu~nc~ o~ two D/A output~ ne~d~ to ~e ~leated, nam~ly 1.111.2/5 and 1.3~1.~/5 or 1.2+1.3J5 an~ 1.4+1.1/S, to en~ur~ that tho ~ rage ~nalog output 1~ i/2. T~er d or-, tho c~ncellation ayole ln thla ca~ only t~o. 81nce the c~nc~llatlon cycle ia input depend-nt, th ~lgorithm whlch per~or~ th-D/A output oelectlon~ ror ~ given dlgital aode should do o with the mln~um canc-llation cyc~e. Co~parad to the o~se when a ~ix~d c~nc-llatlon cyole ~ ~pplied for ~1~ t~e lnput cod ~, thl~ lnput depend-nt ~d ection sahem~ ra~ult-ln a ~maller Ha~-rage~ oanc~llation cycle. ~lmul~tion~
have con~irmed thAt thie t~c~nlgue can lmprovQ the ~ignal to noi-~ ratlo Or ~ thlr~ ord-r S-~ con~-rter by up to 7d.8 2~ ~lth ~n over~a~pling ratlo o~ 32 and ~ 3-bit lnternsl, hAvlng ~ ~yet-matlc llne~r gradlent ml~matoh of 0.1%.
Plgur- 5 how~ the topology o~ a thr~-blt oecond-ord~r ~ul~l-loop S-~ D/A convert~r, Th- d~g~t~l lnput, l.e. PCM cod~ ubtraated in ~um~er 18 by th~ three-bit fQd-b wk cod~, and the dirference 16 ~ppl~-d tc a dlgit~l lntegr~tor 19. ~h- output o~ the rlr-t lnteg~r 19 i~
~ubtrActed f~o~ the thr~-blt f-d-~Ack oode ln 8 furth~
o~ mer 21, and the ~ummer output ~ Appl~ -d 'co a s~cona integr~tor 23. Th~ output or tho c-cond lnt~grator a3 i~
truna~ted with the digit~l quantlzer 2~ t~ obtaln the thr- -blt output oode. Tho thr---blt pul-a-den~ity mo~ulated cod~ fro~ th~ quantizer 25 i6 ~od lnto ~ thr~e-SENT BY: ; 4-29-g3 ; 5:43PM ; 4165951163~ ~6~4~ 6~7-5756;~1 b~t intornal D/~ converter of the ~orm ~plct~d ln FigurQ
3. A ~eaond order ~A9~ D/A converter with a 3-blt lntern~l D/A converter aAn al~o be lmpl-m-nt~d.
A fully dl~rerenti~l ewltched ~apacltor array m~y be u~ed to inplsm~nt the thr~--b~t int rnal D/A aonvert~r of t~e pre~ont inv~ntion. T~e ~impll~ied circuit dL~grA~ o~
th~ D/A convert~r accordlng to t~ preferr~d ~mbcdLm-nt 1~
shown ln Flgure 6. The thermomete~ code 1- i- qeneratod ~rom th- two l~8B~ and bo Or r4b2,b~ bo. The N~B }~
u-e~ to ~elect t~ r-~r~nce voltaqe, v~ and V~ ~or ~he dl~Serent~al ~tructur-, while the blt~ ~0, S~, 81 ~nd 63 are encoded aooordlng to th~ truth t~ble in T~bl~ 2.
~able 2 oceur~noe bL~ ~------------=- -1~ Alwav~ O O O O O O
. _ l~t 0 1 1 0 o 0 2nd o 1 0 1 0 o 3rd 0 1 0 0 1 0 4th 0 1 0 0 0 20 l~t ~ 0 ~
2nd 1 0 0 1 ~ 0 3ra 1 o o o 1 1 ~th 1 0 1 0 0 ~
1~ 1 1 1 1 1 0 2S ~nd 1 1 0 3rd 1 1 1 0 ~th ~ ~ 1 D
Th- d~tall~ o~ opor~tion of the oirauit ~ho~n ~n Flgure 6 would b~ w ll known to ~ person 6~ d ln the ~rt. ~aslc~lly, the elg~t unit ~lem-nt~ sre impl~mented dl~-r-ntl~lly with four unlt ~ ent~ 29-35 connoct~d to the lnv~rting input of ~ dl~erentlAl a~pliller 36 and unit sl~m~nt~ 37-43 conn-ct~d to the noninv4rtlng ~nput of ~
~lrrer-ntl~l ampli~ior 36. Tho un~t element~ Qnd th~ ~ and 3~ - output~ ol di~er-ntlAl ampll~iQr 36 ar~ clook~d v14 non-o~erl~pping clook~ c~ ~nd oll. Thu-, ln the a~ae o~ a thr---bit a~gltal code ~ - 001, th~n bl.o, And ~
A¢aording to the truth tablo illu~ratod ln Tabl~ 2, on~ of .. . .. , , . _.. _, ,, .. , .. , .... ... _ __, . .. "__;. "._.. . . .. .. .

SENT ~Y: ; 4-29-9~ ; 5:44PM ; 4165951163 ' 16~4) 687-5756;#17 2~g~i r?~

th~ decoded ~t~ con~rol ~ignal~ ~0, ~l~ J~ ~nd ~3 W~ll be at A logic high level. since ~,0, then the lower voltag~ rRil i~ ~n~ d for applying Vr- and Vr~ to the l~t ~nd right aapaaitor charging g~te~, re~pectively, ~r th~ top ro~ o~
unit l-m-nte 29-35, ~nd Vrl and vr- to th~ t ~nd right eh~rg$nq ga~oa, re~peatlvely, o~ t~e lower row Or unit el~entc 37-43. D~pcndlng on ~hloh ooourrence o~ th- cod-~ b~ ~ pred~t~rmlned p~ir 29,37 or 31,3g or 33,41, or35,43 ~ill b tlected ror applying differentl~l oh~rge to the ampl$~ier 36. For example r 1~ ~aeh unlt element i~
oon~ldered to h~vo a v~lu~ or l, then ror the ~lr~t o~eurrence of bl, bb, unlt element~ 29 ~nd 37 will b~
charged to 1 and -1, re~pectlv-ly, wh~l~ unit lem~nte 31-35 ~re oh~rged to -1 ~na unit elements 3~-43 ar~ charqed to 1.
Ir the next dig~tal lnput code 1- ~ o10, then a pr~dot4rmlned two palr~ o~ tho upp-r and lower unlt el m nt~ will be eharged to -1 and tho r malning two p~ir~
o~ element~ will be chargod to 1, dependinq on th-occurrence o~ 0.
Ir on th next olocX oyale, the digital input aoder-turn~ to L-001, th-n, ~ince thl- i~ th~ ~cond ocoUrrenc~
ol bl, b~, th-n ~ , whil- ~D~ ~ anA ~ ar4 all O reaultlng ln un$t l~ment6 31 nd 3g charglng to 1 and -1, 2~ r-~octi~oly, whlle unlt lem-nt~ 29, 33 an~ 35 e~ah ah~rge to -~ and un$~ el-m nt~ 37, 41 ~nd 43 eaah c~arg~ to 1. In thi~ w~y, by perouting the D/A oonvort~r unit ~lement~ on a par lev l ~a~l~, all l-m~nt6 U~-d to reprea-nt~d an indlvldual d$gital code are exercl~ed ~equ~ntially ~o that ~rror du to ~ nt mlam~tch ha~ a hlgh ~raquonoy ~p-etru3, in~t-~d of ~ white ~atrum, ~8 xhlbit~ by con~ntional r~ndom averaging.
The thre--bit ~-~ DAC h~ boen l~pl-mcntQa wlth ~ l~a~
m CN09 doublo-polyldoubl4-m~tal t~ohnology, u~ing ~oth ~ln~le-ende4 an~ dl~erential design-. T~t ro~ult~ w~re obtained wlth th- lngle-ended ver~lon. The chlp w -t-~ted ~t a alock ratQ o~ 200K~ wlth an 800 Hz lnput .. __ .... . _.. . _ .. ...... _ _, . ___ _ .. ;_ .. _ . .. . . .. . . . .... .

SENT ~ ; 4-29-9~ ; 5:44PM ; 4165951163 ~ (6~4~ 687-5756;#13 u ~ignal In th~ actua~ ~ea~urement~ capacltor 1~ ~roun~
40dB down ~rom th fundAmental ~h~ equivalent to around 1~ oapacltor ml~matdh Wh~n ~lf~erent ~yna~ia olom nt matehlng teobniqu~ wero ~pp~led, aon~ld~ra~la h~monlc dl-~ort$on ~uppre~lon wa~ obt~lned For tbe lndlvidual lev~l nveraglnS~ teohnlgue, ~ 24dB l~prov~ment o~
haraonlo di~tortlon ~uppr~lon was ~chi~vo~ Tbe 8N*~
~lgnal-to-nolse ratio~) of ~oth multi-loop ~nd ~A8H
~truoturs~ for conv ntlon-l r~ndo~ ~veraging an~ lndivldual l-vel ~v r~g~ng t-ohniqu - wlth an gulvalent oapaoitor m~ tch o~ 1~ are ~bown ln T~ble 3 Table 3 ~ompari~on o~ SNR ror Dirrerent Archlte¢tur~
A~-Oo ~Iw w h~ ~;W l Muitl-Loop 53dB 59dB
~AfiH 51ds 61ds ~_ lS The lntornal C /A ror lmple~ nt mS
AVOraging can ~ reallzed u~ing swl~ched oapaoitor l~pl-~ nt~tlon eo th~ the over~ll lln~arity i- limited by non-la~l e~rect- o~ the oubblooX~ ~rom oaah ~tag~, ae dl~ou--ed ln F. Wang, O. $em-J, ~. ~aw, "A Qu~ P~aoive CM09 P~p-l~n- ~/A Convorter,~ IE~ Journ~l o~ 801id-9tAt-Clrouit-, pp. 1~52~1755 lDeaemb~r, 19~9). Th~o non l~alltl-s t-m ~rom ~rror~ due to non-ideal opnmp~, ewltch-~ and c~paaitor~. UnllXe a pipelined A/D convcrter, a pipellnod D/A ¢onv-rt-r, extr~ clrcul~ry tor dlgital 26 ~rror correction i- not needed, a~ dl30uooed ln Y. ~in, B.
X~m, P. Gray, nA 13-b 2.5 NHz sel~-cal~bratQd Pip~linod AJD
Convort~r ln 3-u~ CMOS," IEE~ Journal o~ 801id-9tato Clroult~, pp. 628-636 (April l99l). Th~ over~ll lln~arlty 1~- ltmited by 1~ ollowing error~ Or th- lh~!llvldual st~g -:
1~ D/A oubconve ~ er error related to capacltor ml~match.
2) Su~ing crror rel~tod ~o ~lnite opamp galn, oh~rg-~eedthrough, in~-ction, opn~p of~oct.
3~ ~ultlplylng error r~lated t~ ~inlte op~p qain, c~paoltor ~ism~tch.

SENT BY: ; 4-29-93 : 5:45PM ; 4165~51163t (604) 6~1-5~56;#19 20~

The DIA ~ubconvart~ error due to a~pacitor ml~match c~n b~ limlnat~d i~ only 1 bit la resolved p~r ~tage. For ~n N-bit D~A convert~r ~ m~ans thQ number Or stage~
equals N and ths mult$ply oirouit~ become mNltlply-by-two circultc. For ~n overo~pled DIA ~onv~rt~r ev~nt though t~- ov r~ alutlon 1- hig~, the re~olutlon N ~or the internal D~A oonvert~r le ~mall, typioal~y on t~o ord-r oL' t~ree to rour. Con~eguently the inc~ea~e ln hard i9 not prohibitlve ~or thl~ appliaat~on. Furthoroore, i~ l-bit Dl~ conv-rt~r $~ uacd wlth ~ully dlfferential arch$tecture, ths o~cet ~rror i8 eliminated.
all ~harge circuits ba~ed on opampc txans~er eharge~
bctwecn c~p-cltor~ rath~r than Lmper~o~ly becau~e of ~Lnlt- ~mpll~l-r galn. Finite opamp galn error~ can b-oo pen~ted for u~lng alrcuit t-chnlqu-~ lLk- c~libration, but th~ cimple6t way i~ to maintain a high DC g~ln, a~
~l~ou~ed ln x. 8ult, G. Gcelen, ~ F~st-Settllng CMOS Op A~P with 90d~ DC C~ln and 116 MH~ ~nlty-Galn F~equency, n Digeet lr Teahnical Paper6, Int-rn~tional Solid-State Clreuit~ Con~erenoe 19~0~ pp 108-109 ~F-~rua~y 1990) T~e o~awp o~ t rror 1~ auto~atiaally canoelled b~cauoe the ~gnal is ~mpled on th~ input c~pacltors by connocting the opa~p ln A unlty-gain aon~iguration ~he dlr~erentlal oharge lniection c~n be llmin~t-d by 4~ploylng a oorrelate~ doublc s~mpllng teohnlquQl a~ di wu~d ln ~
Bon~ M To~p~ett, et al , ~A 12-bit l~ mple/~ C~pacltor ~rror-Av-raglng Pipelined A/D ~onvertor," IEE~ Journ~l of ~olld-~tat- Cirouita, pp ~24-1333 ~Deaember, 1988).
Con-id~ring tho th$rd error ~ource which rs~ult~ rrOm aapacitor m~sm~tch, in the pa~t a tochniqu~ nas beon ~pplied t~ Nyquist rate pip~lined aonverter~ th4~ lm olYe~
u~ln~ an eYtr~ olook pha~e to avsrag~ the ~rror due to c~p~oit~r ~ls~atoh, For ~ DIA aonverter thi~ ~ch-mo wlll re~ult in xtr~ aolay ~nd reduoe the oonver~ion ~po~d ~hB
prce~nt inventlon att~mpt~ to elim~natQ this delay by explolting the ~act that th~ d~gital lnput o~ th~ intern-l D/A aonverter ~or an over6A~pled D/A oonv rter ~tAyo ... ... _ .. . . . ,, . ., ., .. . . . , ... _ , .... . . .. .

SENT ~Y: ; 4-29-93 i 5:46PM i 4165~51163 l (604~ 637-575B;#20 rel~tively const~nt durlnq ~d~ac~nt clock cyol~e.
Con--quontly~ ln-tead of u~ing an xtra olock pha~ the preeent approach d1~tribut40 the ~ver~glng aotlon over two ad~aaent clock cycl~ hown in Flgure~ 7~a) ~o (d). Th-5 c~pacltor- in Flgure 7 ~re a~um~d to have ui~tch~o a~
fOllOWB 5 Cl-l+a C,~
C~ 2 wher- ~, ~c~1.
T~- oircuit of Flgure 7 forms a ~ultiply-by-2 circult 15 wlth cap~citor averaq~ng ~uoh thAt tn the firctclock p~ae~
(Figure 7 (a)) ~n), b~(n)V~/2N i- ~mpl-d, And v~(n) lc r-e-~ to o . For 32~n+~), tFlgure 7(b) ~rom ch~rg~
conver-atlon V (nll/2) - (21a~+~)bhtn)V~/2N. In the ~econd clock phaoo ~F1gur- 7(o)) ~n~l), bh~n~1~ V~ J~mpled and V~ tn~) r---t to 0. For 3~ ~n+1~, ~Flgure 7~d)), from charge oonv r~ion Y~(n~3~2)~(2-a~ )bN~n~l)V~2N.
~rom ~he rr-qu-ncy do~aln poin~ of vlew the propoecd oho- mo~ulat-a tho h~rmonlo dl~tortion 003pon4nt~ to r~l2-~n~x~. It ~hould b not-d th~ thle teohnIque 1~
2~ ~ppli~d to ~ ~yqul~t rat- pl~-lln~d D/A oonver~e~, the modulated h~r nlc dl~tor~lon co~ponent~ will fall into the p~band and g n-r~to und-~ir~ble tonee. For tho overoa~pl-d D/A aonvert¢~, ln ~d~ltlon to tho modul~tion o~
ha~monlc di~tortlon componento the ~verAging aotion lnoreAse- th- b~ and nol~ bacause tho hlgn rrequency quantlsationnpose ic b~lng modulat~ ln~o th- pa~band.
For ~ ~ultiply-by-t~o clreult only 2 unit oa~acltoro aro lnvolv d. Con~-qu-ntly only two al-m nt- nGed to be av r~god ana th~ harmonic dl~tortion components will alway~
3~ bo modulated to frequ~nc~-- around ~/2, as opposod to rr-qu-nci-o ~round ~/M, ~ ln th~ ~on~ntlonal clocXed avernglng ~pproaoh. Fro~ ~lmul~tlono ~h- propo~-d .. . _ .. ... , .. _ .. ........ . . .. ... ; .. ... __.. __ .. .... . . .

SENT B~': ; 4-Z9-93; 5:47PM; 4165951163 ' ~B34) 637-5756;#21 - 17 - .
inv ntion n~oys ~ lOdb lmprovam~nt ovor the rando~
aV~r~ging approach in dynamlc range fo~ a third ord ov~roa~pl~d ~A con~c~r ~lth a 3-bit p$pellned internal ~/A convert~r havln~ a 0.~% random m~ toh.
Oth~r ~bodiment~ and v~riation~ ~ the lnvent~Dn ar-pos~iblo wlthln the ~phero and ~copo o~ the doao~lption h~r~in.

.... _ . .. . . ..

Claims

1. A Sigma-Delta converter, comprising:
a) means for receiving an input digital signal;
b) at least one digital loop filter and quantizer having an input and an output;
c) at least one summer having a first input connected to said means for receiving, a second input connected to said output of said at least one digital loop filter and quantizer, and an output connected to said input of said at least one digital loop filter and quantizer for subtracting from said input digital signal an output digital signal from said at least one digital loop filter and quantizer, and in response generating a difference signal for application to said input of said at least one digital loop filter and quantizer; and c) a digital to analog converter having a plurality of unit elements with minor mismatching therebetween, for receiving and converting to analog said output digital signal from said at least one digital loop filter and quantizer, and in response generating an output analog signal, wherein said digital-to-analog converter comprises means for cyclically selected successive difference permutations of said unit elements for converting each value of said output digital signal thereby cancelling said mismatching between unit elements.

2. The Sigma-Delta converter of claim 1, wherein said means for cyclically selected further comprises:
d) means for receiving and encoding each said value of said output digital signal and in response generating an encoded digital signal;
e) means for receiving said output digital signal and in response generating and updating a pointer signal for each value of said output digital signal;
f) a crosspoint switch for receiving said pointer signal and in response transmitting said encoded digital signal to a predetermined one or more of said unit elements according to said successive different permutations; and g) an analog summer for summing respective signals output from said unit elements and in response generating said analog output signal.

3. The Sigma Delta converter of claim 2, wherein said plurality of unit elements further comprise a switched capacitor array and said analog summer further comprises a differential amplifier having inverting and non-inverting inputs connected to respective portions of said array.

4. The Sigma-Delta converter of claim 1, wherein said digital-to-analog converter comprises one or more series connected multiply-by-two circuits each incorporating capacitor averaging means.