CA2102506A1

CA2102506A1 - A device with bonded conductive and insulating substrates and method therefore

Info

Publication number: CA2102506A1
Application number: CA002102506A
Authority: CA
Inventors: Shiuh-Hui Chen; Carl Ross; Roseann M. Tomasello; Anita G. Brandes
Original assignee: Individual
Current assignee: Motorola Solutions Inc
Priority date: 1992-04-02
Filing date: 1993-03-17
Publication date: 1993-10-03
Also published as: EP0587850A4; EP0587850A1; US5365790A; WO1993020423A1

Abstract

A device with bonded and conductive substrates is disclosed. This device includes a conductive substrate (509) having an electrically insulating layer (515) disposed on a portion thereon. An electrically conductive layer (519) is disposed on the electrically insulating layer (515). Then an insulating substrate (101) having a first surface (103) and an opposing second surface (105) with an electrically conductive coating (516) disposed on a portion thereon is provided. Finally, the insulating substrate (101) is bonded to the electrically conductive layer (519).

Description

~ ~ 0 2 ~
--~wo 93/20423 Pcr/US93/02417 ., A DEVICF WlIH B{)NDED CONDUCI [VE AND ~JSIJLAT~G ` ~
SUBSTRATES AND MEl~OD ~REFOR -~ .
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Field of ~e Inven~on This inven'don is generally directed to ~e field of devices `
having bonded conductive and insulating substrates and more particularly to an apparatus and me~od for providing an .
improved device having bonded c~nduc~ve and insulating 10 substrates. These devices may be usefully applied to construction of capautivepressure sensors. ;

Background of the Invention 15 ; Devices h~ving bonded c~nductive and insula~ng substrates are fabncated un~ many different materials. Some of ~hese devices require a sealed cha~ber wi~ an external elect~ical contact to an inte~àl elè~trically conductive element. Devices ~at ~pically have a requir~nent for ~is type of structure hclude 20 capac tive pressure sensors. Considering ~e silicon variety of capacitive pressure sensors, one feature 80me have in common is a pr~surized chamber ~or stonng a referenoe pressure. This ~ber is typically~ formed dunng the ab~ica~don process and includes a passageway to tbe e~nal surface of ~e chamber. Tt 25 passaw is~used to ext~d~an electrical contact from ~e inside of ~he ctwnber, where a~ elec~rical element is !ocated, to ffle outside of ~e chamber wh~re it can be ~onnected to an external - ~ ~ meas=t cira~ Dunng manuf;lchre the passageway to ~e ~ must be sealed af~ a reference pressu~2 is provided in 30~ ~ ~e;chanher. ~This pass~geway must ~both electrically conductive and ~ed, to capture ~e~aforementioned referenoe pressure. A
a~r.nbir~tion of metal and glass materials are often uæd to create ~hese sealed ch~ambers and attendant passageways. These materi:als :~ ~: `:

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. ', are fused into a s~ucture by many different proce~ses. Ihese processes can include ~e disposing of a liquefied ~etal into a glass struch~re having a passageway ~erein, and then ~e solidifica~don of ~e metal forming a fused interfaQe sealing ~e chamber.
All of ~ese metal and glass s~uctures can suffer from a com~
mon problem. This probl~n is the failure of the fused interface, dlereby leaking ~e stored reference pressure f~om ~e chamber.
This happens when the metal and ~lass structures are subjected to a large temperature transi'don, or many large temperature transitions. These failures occur because of the difference in the thermal coefflcient of expansioI~ of metal and glass. For example, - if the metal is solder, ~e solder will shrink to a much greater e~ctent ~n the glass during a falling temperature transi'don. This results in 'a large strain at ~e fused interface, caus~g a crack in ~e g~ass, a crack direc~y between the solder and ~e glass, or a crack ~e solder. In some cases many ~ermal ~ansitions may be neoessary before these failures occur.
In FIG. 1 a specific example is ilh~s~ated. This figure shows a ~ ~ -cross section of a` device h~ving a sealed chamber with an external electrical ~onhct to an internal ~lec~ically conductive ele~nent"n ~is case a prior art capacitive pressure sensor. This sensor uses a metal and glass strlacture to seal a first passageway 107 between a pressur~ed sealed chamber 125, in which a referenoe pressure is stored, and a first surfaoe 103 of a glass substrate 101, where electrical interconnec~on to 1~e c~paci~ve element is provided. ` ;
The glass substrate 101 u~i~ ~e first surfaoe 103 ha~ an opposing ~d surfaoe 105. The first passageway 107, and a se~vnd -passageway 109 are provided through t~e glass substrate 101. The first passageway 107 is ~en prooesæd to inc:lude a metal lay~ 111 t hat e~tends to a first p_ area 113 on ~e opposirlg ~; ' ;
second surfaoe 105. The second passageway 109 is also pro~essed to include a metal layer 115 ~at extends to a se~ond predetennined area 117 on ~e opposing second suraoe 105 of ~e g~ass substrate 101. " .'.-. :.:

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A semiconductor substrate 119 is then attached to the QppOSiIlg second surface 105 of ~e glass subs~ate 101 at loca'dons shown by reference number 121 and to ~e second predetermined area 117. - : ~-This attachment between ~e glass on ~e opposing second surface 105 and the s~niconductor subs~ate 119, at loca~dons shown by ref~
~r~noe nv;mb~r 121, is perfonned by anodic, or elech-ostatic, bonding. This anodic bond seals ~e glass and semiconductor substrate at locations shown by reference number 121. The bond betwe~en ~e metal layer 115 ~at extends to the second prede~
terrnined area 117 and the semicnn~uctor substrate 119, indicated by referenoe number 129, is the result of a chemical reac~on ~at fuses the semiconductor substrate 119 and ~e metal layer 115 with heat and pressure.
The c~lamber 125 is pre&suAzed and then a quan~ty of solder 123, 127 is melted into the first and second passageways 107, 109.
The solder 123 in ~e f;rst passageway, wh01 oool, forms a ~terface for s~aling ~e chamber 125 and provides an elec~ical contact to an ~ement of a capa:itor, fonned by ~e me~l layer 111 covering the first prede~mined area 113. The solder lD in the second passageway 109 provides an elec~ical connec~on to a second el~
ment of the capacitor fonned by the semiconductor substrate 119. ~ ~:
l~e solder 123,127 formed in the first and second passageways 107, 109 is used to connect the capacitor to an exb~al measurement arcuit. W~en ~is capacitor is subiected to differing pressures, a portion of the s~niconductor subshate 119 is displaoed, in :
relationship to t~e metalized first predetermined area 113, causing a ~hange in distance between the elen ents of ~e capacitor and thus capacitance.
The construction and s~aling of the f~rst passageway 107 is of par8cular concem. The temperature coefficient of solder and glass :
is substantially different When the solder and glass struch~res are ~ ~:
subjected to a temperature transition ~ey expand or contract at different rates because of differing t~ennal a~aents of expansion. The differing rates cause stress to build up in the solder ~ :

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123, par~ ly at ~e location denoted by referen~e number 102, and the glass substrate 101. This is undesirable because during large temperature transi~dons, at ~e loca~don denoted by reference number 102, ~e gla~s substrate 101 a~d solder 123 will ~e over 5 stressed and eid~er or bo~ will crack This cra~king causes the seal to be broken. When ~is seal is broken the referea~oe pressure stored in chamber 125 is released and the sensor no longer can hmction as designed. Similar cracks in ~e glas~solder interface for ~e second passageway 109 have no effect on ~e chamber 125 10 because of ~e anodic bond at the locations shown by reference number 121. This anodic bond isolates the chamber 1~5 from any breaches in the second passageway 109.
What is needed is~an improved device having a sealed chamber with an ext~nal electrical contact to an internal 15 electrically conduc~ve element.

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-~vo 93/20423 2 t ~ ~ ~ n ~ PC~r/~S93/02417 suurLm ary of ~he ~nYen~on A de~ioe wi~ bonded and conductive substrates is disc losed.
This devioe includes a conductive subs~ate havLng an elec~ically insulating layer disposed on a portion ~ereon. An elecLrically conductive layer is disposed on ~e elec~ically insula'dng layer.
I~en an insula'dng subs~ate having a first surfaoe and an opposing second surface with an electrically conductive coating disposed on a portion ~ereon is provided. Finally, ~e insula~dng substrate is bonded to ~e electrically conductive layer.
In a more specific embodiment a devioe having a sealed ~hamber with an ext~nal electrical contact to an internal ele~ically conductive element is disclosed. l~is device includes a conductive subs~ate having a first top surfaoe wi~h an el~cally ins~lating layer located on a portion of the first top surface. The el~cally insula~ng layer has a second top surhce spaced apart from the first top surfaoe of ~e conductive subs~ate. An ele~ically conductive layer is located on ~e elec~ically insulaJdng layer and has a ff~ird top surfaoe spaoed apart from the second top surface of the elec~ically însula~dng layer. The ~hird top surface d~ines a boundary for a first electrically conductive contact area.
An insulating substrate is provided wi~ a first surfaoe and an opposing second surface, the opposing second surface has an eleckically conduc~ve coaffng located ~ereon and provides an inbe~nal electrîcally conductive ~lement. The elech~ically -~
conductive coating is connected, via a conductive feed~rough passageway, ~hrough ~e wulating subsh~te to the first surface of the wulating substrate and pro~ndes an external ~lectrical contact.
A por~on of ~e electrically ~onductive coa~g, located on ~he opposing second surfaoe of 1he insula~ng substrate provides a second electrically ~onductive oontact area. The insulating su~
strate is bonded to ~e ~ ically conductive layer, and lthe first electrically conductive contact area of the electrically condustive layer and the second elechically conductive contact area of ~e .

Wo 93/204232 ~ O ?~ 3 0 6 ` PCI/US93/02417 electrically conductive coa~ing locatecl on ~e insulating substrate ar~ connected fo~ing an electrical cormec~on locatecl apart from a sealed chamber, ~e sealed chamber located between ~e first top ::
surface of ~e conductive substrate and ~e opposing second 5 surface of the insula~ng subs~ate. Preferably, ~e internal e~ectrically conducti~e element formed by ~e electlically conductive coating e~ctends into the sealed c~ber. Additionally a method for fabrica~ing such devioes is disclosed.

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' ~ ., ~ .'., ~1VO 93/20423 21 0 2 ~ ~ 5 ` pcr/us93/o2417 - Brief Description of ~e Drawings FIG. 1 is a schema~dc dL~agram of a priDr art ~aled pressure ænsor as described in ~e ba~ground.
5 PIG. 2 is a sc hema~dc diagram illus~ating vaIious p~ocess steps for providing a first capacitive element su~s~ate useful in a sealed pressure sensor constructed in accordance unth ~e inven~don.
FIG. 3 is a schematic diagram illustra~dng ~anous process steps for p~oviding a second capaci~ve element ~ubs~ate useful in a 10 ~ealed pressure sensor constructed in acco~dance with ~e invention.
FIG. 4 is a schema'dc diagra~ illustrating various process steps for conlbis~ing the first capacitive element substrate described in FIG. 2 and the se~ond capaGtive elem~nt subs~ate descnbed in 1~ FIG. 3 to provide a sealed pressure sensor.
PIG. 5 is a schemaJdc diagram of the improved sealed pressure sensor ~at r~sults from the process steps shown in ~G. 4 in accortance wi~ the in~en~don.
FIG. 6 is a schematic tiagram of a portion of a n etalizet glass ZO passageway, useful in a sealed pressure sensor, constructed in ac~
cordance with the invention.

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Detailed DescIip'don of a Preferred Embodiment In ~lG.'s 2, 3, and 4 a me~od is Dlus~ated to teac~h a fabrica~on p~ooess ~o make a capaci'dve pressure sensor w~ nproved :
interf~ce between ffie pressurized ~hamber and ~e ext~nal : ~ : :
eleckical oontacts. ~is embodiment overcomes ~e d~iciencies of . .
the prior art because the fragile glass and solder interface for ~e -passageway 107 is no longer required to provide a seal. The apparatus resulting from the application of ~e present me~od is ~ :
shown in FIG. S and will be described first. . ::
.. . .
~IG. 5 illus~ates a capaci~ve pressure sensor 500 with a æaled . :
pressure chamber 125. Note that reference numbers used in E~G.'s :

2, 3, 4, 5, a~d 6 that are identical to ~e reference numbers used in FIG. 1 are used to identify iden'dcal corresponding elements.
Howeve~, note that ~e passageway 107 ~n FIG.'s 3, 4, and 5 is located in a different position in subs~ate 103 than as shown in ~:
FIG. 1.
A silicon substrate 509 is pro~nded wi~ a first top surfaoe 511.
This siliaon substrate 509 forms a first electrode of a capacitor.
O~her conductive substrates, including o~er ~niconductor sub- :~
strates, may be wed for this function. An electrically wulating :
layer 515, in this case an o~ade, or silia~n dio~ade, layer, is disposed :
on the hrst top surface 511 of the silic~n subs~ate 509. The silicon dioxide layer 515 }us a second top surface 510 s~aced apart from ~e first top surfaoe 511 of the silia~n su~s~ate 509. This silicon diox~
ide layer 515 has a lower ~ aperture 521, and a feed~rough aperh~e 517 located ~erein. Bo~h the lower chamber aperture 521, and t~e feed~rough aperture 517 origis~ate on *~e second top ~ :~
~urfaoe ~10 of ~e silicon dioxide layer 51~ and conc lùde on ~e ~irst top surface 511 of ~e silicon substrate 509.
In the pref~rred embodiment a chemical vapor d~posi~on pr~
oess ~s used bo dispose *le s~ia;)n dioxide layer 515 and later to dis-pose a polysilicon layer 519. Various types of ~hemical vapor d~
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-vo 93/20423 Pcr/US93/0~417 posi~don, induding high pressure deposi~on us~ul in fabricaJdng a ~ -capaa~dve pressure ser~;or in ac~ordance with ~e inYen'don are - ~:
reviewed in the textbook "VISI TECHNOLC)GY" edited by S. M. ~ :
Sze and pubL~shed by McGraw-Hill Book Company in 1983. See : ~ ~
pages92-95andlS~151. ~ :
An electrisally c~nductive, in ~is case polysilicon, layer 519 is disposed on ~e seaond top surface 510 of ~e silicon dio~ade layer 515. The polysilicon layer 519 has a ~ird top surfaoe 512 spaced :;
apart from the se~nd top surfaee 510 of ~e silicon dio~ade layer 515. The polysilicon layer 519 extends ~rough the feed~rough aperture 517 of ~e silicorl dio~ade layer 515 and is disposed on and conductively con'cacts ~e silicon subs~ate 509.
A c hamber aperture 599 is locabed between ~e third top surface 512, of the polysilicon layer 519 and ~e second top surface 510 of the silicorl dio~de layer 515. Fur~er, an isol~tion trench 525 is disposed in the polysilicon la~er 519. The isola~on trench 525 origulates at the ~ird top surface 512 of the polysilicon lay~r 519 and tern~inates at ~e se~ond top surface 510 of the silicon dio~ade layer 515. This iæolation trench 525 d~nes a boundary for a first elech~ically conductive contact area 522 on ~e third top surface 512 of the polysilicon layer 519. This isolation tren~h 525 is used to electrically disconnect ~e first electrode of ~e capacitor, represented by the silicon substrate 509, ~om a second elec~ode of the capacitor deæcribed later.
Note that during the prooessing of the polysilicon layer 519 a lower i~olation trench 598 extends ~e isol~tion ~rench 525 through ffle silicon dio~ade layer 515. This is ~e result of bhoosing an effident p~ocess and is not actually requ~red because the isolation trench 525 in the polysilia~n l~yer 519 isolates the first and second capacitive elements. However, ~e extension of ~e isolation trench 525 ~rough ~e silicon dio~ade layer 515 with the lower isolation tre~ch 598 doesn't adveræly ~ect ~e operation of the capaative pressure sensor. ;

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A por8on of the polysilicon layer 519, disposed separated from ~he ~rst elec~ically conduc~ve corlhct area 522, pro~ndes a ~:
se~nd ele~ically conduc~ve oontact asea 524.
Fur~er, an essen~ally planar glass substrate 101 is provided 5 and has a first surface 103 and an opposing second surface 105. A
first lase~ drilled passageway 107 ori~tes at a first orifioe 501 on the first surface 103 and con~nues to a third or oe 505 located on ` : :;;
the opposing second surface 105. The purpose of ~e first laser drilled passageway 1û7 is to provide an electrical contact to ~e sec~
ond ele~ctrode of the capacitor. The first passageway 107 has a first ;: :
inner surfaoe 508. A first metal layer 111, composed of successive layers of c~rornium, nic kel vanadium, and gold, is disposed on the ~ ;
first inner surfaoe 508 star~ng at ~e first orifice 501. This first metal layer 111 ~en ~c~nds ~rough ~e first passageway 107 and 15 continues along ~e first inner surface 508 to ~e third orifice 505 on the opposing second surface 105 of ~e glass subs~ate 101. :
The metals can be attached us~g many known methods. In the preferred embodiment a sputtenng proc~s is ~. Various ~:
~rpes of sputter deposi'don are reviewed in ~e textbook "VLSI
20 TEC~OLOGY" edited by S. M. S~e and published by McGraw~
Hill Book Company in 1983. See pages 358~
A second metal layer 516, ~lechically connected to the first metal layer 111, is aomposed o~ successive layers of chromium and :;:
gold. It starts at ~e third orifice 505 and oon'dnues on ~e oppo~
25 ing second surface lû5 to a first predetermined area 113. The æcond metal layer 516 located at ~is first prede'lermined area 113 - :~
serves as ~he second el~e o;f ~e capaator, and aiso provides a third electrically conductive ~nhct area 534, adjacent to the third orifice ~û5. Ihe use of ~e t~ird ~lect~ically conductive contact area 30 534 wil1 be described below.
A se~ond las~ drilled passageway 109 originates at a se~ond on- :
fioe 503, on ~e first surfaoe 103 and ~ntinues to a four~ o~ifice 507 on ~e opposing seo~nd surface 10~. The purpose of ~e second las~ drilled passageway 109 is to provide an elec~ical con~act to 2 1 ~
.. W093/20423 Pcr~s93/02417 ~e f;rst elec~ode of ~e capacitor. I~e second pa~sageway 109 has a second inner surface 513. A third metal l~yer 115, composed of suc~essive layers of chromium, r~ickel vanadium, and gold~ is dis-posed Oll the second inner surfaoe 513 star8ng at ~e second orifice 5 503. This ~ird metal layer 115 ~en e3~tends ~rough ~e second passageway 109, along ~e second ~er surface 513, and continues to the four~ or~fice 507. A ~our~ metal layer 518, electrically connected to ~e ~ird metal layer 115, is ~mposed of successive layers of ~lromium and gold. It star~ at the four~ orifice 507 and 10 oontinues on ~e opposing seo~nd surface 105 to a predeterminecl area 117. Ihis predetenr~ined area 117 provides a four~
elec~isally conduc~ve conhct area 536 ~at will be described be~ow.
The ol~posing second surface 105 of the glass substrate 101 is bonded, in this case anodically or electrosh~dcally, as shown at ref-15 erence number 121, to the polysilicon layer 519. This bonds ~eglass substrate 101 to ~e polysilicon layer 519 and fonns a sealed chamber 125, including ~he chamber aperh~re 599 of the polysilicon layer 519, the lower ~hamber aperture 521 of ~e silicc~n di~x~de layer 51~" the isola~don trench 525 and the lower isolation trench 20 598, all located between ~e opposing se~ond surface 105 of said glass substrate 101 and the first top surface 511 of the silioon substrate 509, in which a reference pressure is stored. During this anodic bonding process the second metal layer 516, located at the t~d electrically conductive oontact area 534, and the first ~
25 cally oondu~ve ~ntact area 522 o the ~lysilicon layer 519 are . This anodic bond as shown at referenoe nilmber 121 and ~e *Ising of ~e second me~l layer 516, located at ~e third electrically o~nduc~ve contact area 534, and the first elec~ically oonduc~ve contact area sæ of the polysilicon layer Sl9 provide a barrier 30 between ~e first surface 103 of the glass subs~ate 101 and dle ~hamber 125. This is because the passageway 107 and ~e orifice 505 ar~ spaoed away from the chamber 125, unl~e the passageway 107 in the sensor shown in FIG. 1. Fl~e~, ~e four~ metal layer 518, located at ~e four~ electrically conductive contact area 536, -~

WO 93/20423 2 1 0 2 ~ ~ ~ PCl/US93/02~117 .'- ~ ~,.'-and the secolld el~c~ically conductive contact area 524 of the . ~ ~ ;
polysilicon layer 519 are fused. This provides an elec~ical corule~on between ~he first surfaoe 103 of ~e glass substrate 101 and ~e polysilicon layer 519 and the first elec~ode of t~e capacitor 5 re~resented by the silicon subs~ate 509.
Since the anodic bond as shown at reference number 121, ~efusing of ~e second metal layer 516 losated at ~e ~ird elec~ically conduclive contact area 534 and the first electrically conductive conhct area 522 of the polysilicon layer 519 provide a seal for the chamber 125 and there is no need to rely on the solder to proYide a - ~:
seal in the fi~st passageway 107 as t~e prior art did. If c~a~ks in solder 123 in the passageway 107 in the glass substrate 101 occur they are inconsequen'dal to the sealing of the chamber 125. - ~
A first external elec1rical ~ontact 568 to the first electrode of ~e ~ ~ :
15 capacitor, represented by ~e silicon substrate 509, is provided at ~e first s~ rface 103 of the gl~ss substrate 101. To ud cormection a portion of solder 127 is melted into the seoond passageway 109 at :
the secondl orifice 503. A second exte~nal ~lec~rical contact 567 to ::
~e second electrode of ~e capacitor, represented by the first metal ooating 516, is provided at the first su~face 103 of ~e glass subs~ate ; :
101, spaced apart from ~e f;rst external electrical contact 568. To aid connection a portion of solder 123 is melted into the first : :
passageway 107 at the first olifice 501. The apparatus in FIG. 5 embodies the inventive design. Next the fabrication method is discussed.
~G.'s 2, 3, and 4 provide ~e illus~ations for ~e fab~ica~on me~od tutorial. Star~ng in ~IG. 2, a first step 200 is to provide a silicon subs'aate 509. This silicon substrate 509 has a first top surfa~e 511. Then in step 202 a silicon dio~ade layer 515 is disposed on ~he first 'cop surface 511 of ~e silicon subs~ate 509. As mentioned earlier, a ~hemical vapor deposi'don process is used i~
this embodiment. I~is silicon dio~de layer 515 is ~en patterned and ~he result is shown in step 2~4. The patten~ing opens a feedthrough ap~e 517 ~rough the silicon dio~ade layer 515, to ., ~ ' ~;

21 02~06 - ' -`VO 93/20423 PCI /US93/0241 7 the first top surface 511 of ~e silicon subs~ate 509. The patterning process used in ~is embodiment is a photoli~ograp~ic process of applying photoresist, exposing and developing dle photoresist, etching the su~face on which the photoresist was applied, and then removing ~e photoresist. This process is commonly known to ~-those of ordinary skill in ~e art.
The next step 206, is to dispose a conductive polysilicon layer 519 on the silicon dioxide layer 515. Note ~at because a feedthrough aperture 517 was patterned in step 204 ~e polysilicon layer 519 disposes ~rough ~e feed~roug~ aperture 517 and conductively contacts ~e silicon subs~ate 509.
Then the ~omposite subs~ate 201 is patterned to open ~e ~hamber ~aperture 599, ~e lower chamber aperture 521, an isola~don llsench 525, and a lower isolation ~enc}~ 598 through ~e polysili~n la~re$ 519 and ~e sili~on dioxide layer 515 to the silicon subs~a~e 509. The result is shown in step 208.
Refe~Ting to FIG. 3, a next step 300, is to provide a ~ass substrate 101 havisLg an first surface 103 and an op~sing second surface 105.
The next step 302, is to provite a first passageway 107 and a s~-ond passageway 109, disposed between the first surface 103 and ~e opposing secondL surfaoe 105 of ~e glass substrate 101. This is done by lase~ ~ng through the glass subs~ate 101. Of cousse, other p~ocesses may be used.
The next step 304"s to di~ose a metal layer 301 on the first su~-faoe 103, ~e opposing se~ond surfaoe 105 and ~ e first and ~nd passageways 107,109 of ~e glass substrate 101. Por ~he capaci~ve pressure sensor being constructed, successi~e layers of chromium, nickel vanadium and gold are used on ~e first surhce 103 and ~e first and second passageways 107,109 and suc~essive lay~rs of chromium and gold are used on ~e opposing second sur~
faoe lO5. Of ~ourse, o~er metals can be used.
Then ~e glass subs~ate 101 is patte~ned to remove ~e excess metal layer on ~e ~irst surface 103 and ~e opposing second surface : .

Wos3/2w23 2102505 Pcr/US93/02417 "~

105. This step 306 provides a first metal layer 111 star~ng at the first orifice 501 and continuing along the first inner surface 508 of the first passageway 107 and extending to ~e ~ird oFifice 505 on the opposing second surfaoe 105. This step 306 also provides a se~ond metal layer 516, connected to the first me~al layer 111 at the - ~:
third o~ifioe 505 and cc~n~nuing on ~e opposing second surface 105 to a f;rst predetermined area 113, fo~g a second electrode of ~e capacitor and providing a 1~ird electrically conductive contact area 534, adjacent to ~e ~ird orifice 505. This s~ep 306 also provides a ~ird metal layer 115 star~ng at ~e second orifice 503 and oontim~ing along ~e seaond inner surface 513 of ~e second ~ :
passageway 109 and e~*enting to the four~ orifioe 507 on ~e : :
opposing second surfaoe 105. This step 306 also provides a four~
metal laye~ 518, connected to ~e second metal layer 115 at ~e fourth orii~ioe 5W and co~1inuing on ~e opposing secoIld surface - - -~
105 to a second predetermined area 117, and providing a four~
elec~ically conductive conhct area 536. I~is results in a second capacitive element s~lbstrate 303 s~own in ~;IG. 3r Refemng to FIG. 4, a next step 400, is to anodically bond ~e first capacitive element substrate 201 to the second capaci'dve element :-subs~ate 303. A predetermi~ed referenoe pressure, in this case a vacuum, is applied outside the first capacitive element substrate 201 and the second capacitive ~lement subs~ate 303. This is done ~ ~
by plaang both substrates 201 and 303 in a bell jar and evaalating :
it l~en the anodic bond is made, as shown by referenoe number 121 in FIG. 4 step 400. As mentioned earlier, duIing ~e anodic bonding prwess the second metal layer 516, loc~ted at dle ~ird electrically oonductive co~tact area S34, and ~e first elec~ically aonduc~ive contact area 522 of' ~e polysilicon layer 519 are fused.
This anodic bond as shown at ref~r~noe numb~ 121 and the fusing of ~e second metal layer 516, located at the third elec~ically conductive contact area 534, and the f;rst elecb~ically ~onduc~ve contact area 522 of the polysilicon layer 519 provide a ~amer between ~e f;rst surface 103 of ~e glass subs~rate 101 and ~e ,~:

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` ~VO 93/20423 PC~r/US93/02~17 chamber 125, ~ereby storing ~e predeterlIuned reference pressure.
In a next sbep 402, a po~on of solder in ~e form of solder balls 401 and 403 are disposed in ~e first passageway 107 and ~e second 5 passageway 109.
Finally, in step 404, the anodically bonded and fused first capacitive element substrate 201 and second capaciJdve element substrate 303 is heated, melting the solder balls 401, 403 disposed in ~e ~st and second passageways 107,109. Then the assembly is 10 cooled forming the final capaci'tve pressure sensor apparatus shown in FIG. 5.
O colarse, persons of ordinary ~kill in ~e art will realize that the prease sequence of each step of this process may not be critical and other sequenoes could also ~e used to form ~is struchare.
In ~:IG. 6 ~he first metal layer 111 of the first passageway 107 is detailed as being co~npoæd of several m~ laye$s as revealed earlier. The subs~¢ate 101 is pTeferably coated wi~ successive lay-ers of chromium 601, nickel vanadium 603, and gold 605. These ~ ;
materials are useful in constmcting a capacitive pressure sensor.
The geometries of the constituent elements, induding the :
silicon substrate 511, the silicon dioxide layer 515, ~e polysilicon layer 519, the glass substrate 101 and ~e various pattems 521, 522, 598, 599, 525, 534, and 536 illus~ated her~n, are suitable for a capacitive pressure sensor. Of o~urse, o~er geometries may also be used to take advantage of the inventive prooess described. .
Alt~ough ~ emb~ nent details seaL;ng a capacitive pressure sensor, this invention can be applied to other æaling problems where an insulated ele~ical contact is required.

30 What is claimed is~

. ~ ~

Claims

1. A device with bonded and conductive substrates comprising:
a conductive substrate;
an electrically insulating layer disposed on a portion of said conductive substrate;
an electrically conductive layer disposed on said electrically insulating layer; and an insulating substrate having a first surface and an opposing second surface, the opposing second surface having an electrically conductive coating disposed on a portion thereon, said insulating substrate bonded to said electrically conductive layer.

2. A device in accordance with claim 1 wherein the opposing second surface of said insulating substrate is bonded to said electrically conductive layer.

3. A device in accordance with claim 2 wherein the bond between the opposing second surface of said insulating substrate and said electrically conductive layer comprises an anodic bond.

4. A device in accordance with claim 3 further comprising a bond between the electrically conductive coating disposed on a portion of the opposing second surface of said insulating substrate and said electrically conductive layer.

5. A device having a sealed chamber with an external electrical contact to an internal electrically conductive element comprising:
a conductive substrate having a first top surface;
an electrically insulating layer disposed on a portion of the first top surface of said conductive substrate and having a second top surface spaced apart from the first top surface of said conductive substrate;
an electrically conductive layer disposed on said electrically insulating layer and having a third top surface spaced apart from the second top surface of said electrically insulating layer, the third top surface defining a boundary for a first electrically conductive contact area; and an insulating substrate having a first surface and an opposing second surface, the opposing second surface having an electrically condutive coating disposed thereon for providing an internal electrically conductive element, the electrically conductive coating connected via a conuctive feedthrough passageway through said insulating substrate to the first surface of said insulating substrate and providing an external electrical contact, wherein a protion of said electrically conductive coating, located on the opposing second surface of said insulating substrate providing a second electrically conductive contact area, and wherein said insulating substrate is bonded to said electrically conductive layer, and wherein the first electrically conductive contact area of said electrically conductive layer and the second electrically conductive contact area of the electrically conductive coating disposed on said insulating substrate are connected forming an electrical connection located apart from a sealed chamber, the sealed chamber located between the first top surface of said conductive substrate and the opposing second surface of said insulating substrate.

6. A device in accordance with claim 5 wherein said electrically insulating layer comprises a silicon oxide material.

7. A device in accordance with claim 5 wherein said electrically conductive layer comprises a polysilicon material.

8. A device in accordance with claim 5 wherein said insulating substrate bonded to said electrically conductive layer comprises an insulating substrate anodically bonded to said electrically conductive layer.

9. A device in accordance with claim 5 wherein said insulating substrate comprises a glass substrate.

10. A device in accordance with claim 5 wherein the electrically conductive coating disposed on said insulating substrate is electrically isolated from said conductive substrate.

11. A device having a sealed chamber with an external electrical contact to an internal electrically conductive element comprising:
a conductive substrate having a first top surface, an electrically insulating layer disposed on a portion of the first top surface of said conductive substrate and having a second top surface spaced apart from the first top surface of said conductive substrate, said electrically insulating layer having a feedthrough aperture disposed therein and originating at the second top surface of said electrically insulating layer and conclud-ing at the first top surface of said conductive substrate;
an electrically conductive layer disposed on a portion of said electrically insulating layer and having a third top surface spaced apart from the second top surface of said electrically insulating layer, said electrically conductive layer extending through the feedthrough aperture of said electrically insulating layer and conductively contacting said conductive substrate, said electrically conductive layer having a chamber aperture disposed therein and originating at the third top surface of said electrically conductive layer and terminating at the second top surface of said electrically insulating layer, said electrically conductive layer having an isolation trench disposed therein ant originating at the third top surface of said electrically conductive layer and terminating at the second top surface of said electrically insulating layer and defining a boundary for a first electrically conductive contact area on the third top surface of said electrically conductive layer; and an insulating substrate having a first surface and an opposing second surface, the opposing second surface having an electrically conductive coating disposed on a portion thereon for providing an internal electrically conductive element, the electrically conductive coating connected via a conductive feedthrough passageway through said insulating substrate to the first surface of said insulating substrate and providing an external electrical contact, wherein a portion of said electrically conductive coating located on the opposing second surface providing a third electrically conductive contact area, and wherein said insulating substrate is bonded to said electrically conductive layer and providing a sealed chamber, the sealed chamber including the chamber aperture and the isolation trench, both located between the opposing second surface of said insulating substrate and second top surface of said electrically insulating layer, and wherein the first electrically conductive contact area of said electrically conductive layer and the third electrically conductive contact area of the electrically conductive coating disposed on the opposing second surface of said insulating substrate, are connected forming an electrical connection at a location separate from the sealed chamber.

12. A device in accordance with claim 11 further comprising:
a second electrically conductive contact area located on the third top surface of said electrically conductive layer and electrically isolated from the first electrically conductive contact area;
a fourth electrically conductive contact area located on the opposing second surface of said insulating substrate electrically isolated from the third electrically conductive contact area of the electrically conductive coating;
a second conductive feedthrough passageway disposed through said insulating substrate and contacting the fourth electrically conductive contact area on the opposing second surface of said insulating substrate and providing an additional external electrical contact located on the first surface of said insulating substrate, and wherein the second electrically conductive contact area of said electrically conductive layer and the fourth electrically conductive contact area located on the opposing second surface of said insulating substrate, are connected forming an additional electrical connection at a location separate from the electrical connection.

13. A device in accordance with claim 12 wherein second conductive feedthrough passageway is spaced apart from said sealed chamber.

14. A device in accordance with claim 12 further comprising a portion of solder disposed in said first and second conductive feedthrough passageways.

15. A device in accordance with claim 12 wherein said first conductive feedthrough passageway and said second conductive feedthrough passageway comprise a first metal coated passageway and a second metal coated passageway

16. A device in accordance with claim 11 wherein said electrically insulating layer comprises a silicon oxide material.

17. A device in accordance with claim 11 wherein said electrically conductive layer comprises a polysilicon material.

18. A device in accordance with claim 16 wherein said electrically conductive layer comprises a polysilicon material.

19. A device in accordance with claim 11 wherein said insulating substrate bonded to said electrically conductive layer comprising an insulating substrate anodically bonded to said electrically conductive layer.

20. A capacitive pressure sensor comprising:
a conductor substrate having a first top surface, wherein said semiconductor substrate is used as a first electrode of a capacitor;
an oxide layer disposed on a portion of the first top surface of said semiconductor substrate and having a second top surface spaced apart from the first top surface of said semiconductor substrate, said oxide layer having a feedthrough aperture disposed wherein and originating at the second top surface of said oxide layer and concluding at the first top surface of said semiconductor substrate;
a polysilicon layer disposed on a portion of said oxide layer and having a third top surface spaced apart from the second top surface of said oxide layer, said polysilicon layer extending through the feedthrough aperture of said oxide layer and conductively contacting said semiconductor substrate, said polysilicon layer having a chamber are disposed therein and originating at the third top surface of said polysilicon layer and terminating at the second top surface of said oxide layer, said polysilicon layer having an isolation trench disposed therein and originating at the third top surface of said polysilicon layer and terminating at the second top surface of said oxide layer and defining a boundary for a first electrically conductive contact area on the third top surface of said polysilicon layer, a portion of said polysilicon layer disposed separated from the first electrically conductive contact area providing a second electrically conductive contact area; and an glass substrate having a first surface and an opposing second surface, the opposing second surface having a first metal coating disposed on a portion thereon for providing a second electrode of a capacitor, the first metal coating connected via a first conductive feedthrough passageway through said glass substrate to the first surface of said glass substrate and providing a first external electrical contact, wherein a portion of the first metal coating, located on the opposing second surface, providing a third electrically conductive contact area, and wherein a second metal coating is disposed on the opposing second surface of said glass substrate separate from the first metal coating, the second metal coating connected via a second conductive passageway through said glass substrate to the first surface of said glass substrate and providing a second external electrical contact, wherein a portion of the second metal coating, located on the opposing second surface, providing a fourth electrically conductive contact area, and wherein said glass substrate is bonded to said polysilicon layer and providing a sealed chamber, including the chamber aperture and the isolation trench, both located between the opposing second surface of said glass substrate and second top surface of said oxide layer, and wherein the first electrically conductive contact area of said polysilicon layer and the third electrically conductive contact area of the first metal coating disposed on the opposing second surface of said glass substrate, are electrically connected, and the second electrically conductive contact area of said polysilicon layer and the fourth electrically conductive contact area of the second metal coating disposed on the opposing second surface of said glass substrate, are electrically connected.

21. A capacitive pressure sensor in accordance with claim 20 wherein the first and second conductive passageways comprise a first and second metal coated passageways.

22 A capacitive pressure sensor in accordance with claim 21 further comprising a portion of solder disposed in said first and second metal coated passageways.

23. A capacitive pressure sensor in accordance with claim 20 wherein a reference pressure is stored in said sealed chamber.

24. A method for fabricating a device with bonded and conductive substrates comprising the steps of:
providing a conductive substrate;
disposing an electrically insulating layer on a portion of conductive substrate;
disposing an electrically conductive layer on the electrically insulating layer;
providing an insulating substrate having a first surface and an opposing second surface, the opposing second surface having an electrically conductive coating disposed on a portion thereon;
and bonding said insulative substrate to said electrically conduc-tive layer.

25. A method for fabricating a device in accordance with claim 24 wherein said bonding step comprises bonding the opposing second surface of said insulating substrate to said electrically conductive layer.

26. A method for fabricating a device in accordance with claim 24 wherein said bonding step comprises the step of:
anodically bonding the opposing second surface of said insulating substrate to said electrically conductive layer.

27. A method for fabricating a device in accordance with claim 26 further comprising the step of:
bonding the electrically conductive coating disposed on a portion of the opposing second surface of said insulating substrate to said electrically conductive layer.

28. A method for fabricating a capacitive pressure sensor comprising the steps of:
providing a conductive substrate forming a first electrode of a capacitor;
disposing an electrically insulating layer on said conductive substrate;
opening a feedthrough aperture area through the electrically insulating layer to the conductive substrate;
disposing an electrical conductive layer on the electrically insulating layer and through the feedthrough aperture;
opening a chamber aperture and an isolation trench through said electrically conductive layer to said electrically insulating layer and forming a first capacitive element substrate;
providing an insulating substrate having an first surface and an opposing second surface;
opening a first passageway in the insulating substrate between the first surface and the opposing second surface;
opening a second passageway in the insulating substrate be-tween the first surface and the opposing second surface;
disposing metal layers on the first surface, the opposing sec-ond surface and in the first and second passageways;
removing excess said metal layers on the first surface and the opposing second surface of the insulating substrate and providing a second metal layer on the opposing second surface of said insulating substrate adjacent to the first passageway forming a second electrode of the capacitor and providing a third electrically conductive contact area connected to the second metal layer and removing excess said metal layers on the first surface and the opposing second surface of the insulating substrate and providing a fourth electrically conductive contact area on the opposing second surface of said insulating substrate adjacent to the second passageway thus forming a second capacitive element substrate;

disposing said second capacitive element substrate onto said first capacitive element substrate;
applying a predetermined pressure to sad capacitive element substrate and said second capacitive element substrate;
and then bonding said first capacitive element substrate and said second capacitive element substrate and forming a sealed interface there between with a sealed pressure chamber provided between the first capacitive element substrate and second capacitive element substrate.

29. A method for fabricating a capacitive pressure sensor in accordance with claim 28 wherein said step of bonding said first capacitive element substrate and second capacitive element substrate comprises anodically bonding of said first capacitive element substrate and second capacitive element substrate.

30. A method for fabricating a capacitive pressure sensor in accordance with claim 28 wherein the step of disposing an elec-trically insulating layer on said conductive substrate comprises the step of high pressure deposition of an electrically insulating layer on said conductive substrate.

31. A method for fabricating a capacitive pressure sensor in accordance with claim 28 wherein the step of disposing a metal layer on the first surface, the opposing second surface, and in the first and second passageways comprises the steps of:
disposing a chromium layer on the first surface, the opposing second surface, and in the first and second passageways;
disposing a nickel layer on the first surface, and in the first and second passageways;
disposing a gold layer on the first surface, the opposing second surface, and in the first and second passageways.

32. A method for fabricating a capacitive pressure sensor in accordance with claim 28 wherein the step of applying a prede-termined pressure comprises applying at least a partial vacuum.