CA2103780A1 - Virtual packet bus concept with distributed arbitration - Google Patents
Virtual packet bus concept with distributed arbitrationInfo
- Publication number
- CA2103780A1 CA2103780A1 CA002103780A CA2103780A CA2103780A1 CA 2103780 A1 CA2103780 A1 CA 2103780A1 CA 002103780 A CA002103780 A CA 002103780A CA 2103780 A CA2103780 A CA 2103780A CA 2103780 A1 CA2103780 A1 CA 2103780A1
- Authority
- CA
- Canada
- Prior art keywords
- bus
- module
- coupled
- bup
- arbitration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
- G06F13/372—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a time-dependent priority, e.g. individually loaded time counters or time slot
Abstract
ABSTRACT
A computer bus for transferring data among a plurality of modules coupled thereto, and having flexible, distributed bus arbitration. A
plurality of data lines is operable to transfer bits of data among modules attached to the bus. A single arbitration line is coupled to each module, and is used to indicate whether the bus is available for the next bus cycle.
A bus packet clock, called a BUP clock, is used to divide the bus into cycle periods called BUP time slots. An access time clock further divides these BUP time slots into time access slots. The BUP time slot is the unit of time for which a module will be granted access to the bus. The BUP
time slot is selected so that modules will be granted access to the bus for a length of time defined by a packet length. Each module on the bus is provided with arbitration circuitry for determining whether that module will be granted access to the bus for the next BUP time slot. The arbitration circuitry counts the number of accessed time slots and compares the counter value to a module priority value and outputs a comparison time pulse when the values compare. A module with a lower priority number will pull the arbitration line low and claim the bus for the next BUP time slot if this module is requesting the bus for the next BUP
time slot. Once a module has pulled the arbitration line low, no other module will be granted access to the bus for the next BUP time slot.
When the next BUP time slot occurs, the module granted access to the bus for that period will be given access, and the counters of each module will be reset, and the priority of each module updated.
A computer bus for transferring data among a plurality of modules coupled thereto, and having flexible, distributed bus arbitration. A
plurality of data lines is operable to transfer bits of data among modules attached to the bus. A single arbitration line is coupled to each module, and is used to indicate whether the bus is available for the next bus cycle.
A bus packet clock, called a BUP clock, is used to divide the bus into cycle periods called BUP time slots. An access time clock further divides these BUP time slots into time access slots. The BUP time slot is the unit of time for which a module will be granted access to the bus. The BUP
time slot is selected so that modules will be granted access to the bus for a length of time defined by a packet length. Each module on the bus is provided with arbitration circuitry for determining whether that module will be granted access to the bus for the next BUP time slot. The arbitration circuitry counts the number of accessed time slots and compares the counter value to a module priority value and outputs a comparison time pulse when the values compare. A module with a lower priority number will pull the arbitration line low and claim the bus for the next BUP time slot if this module is requesting the bus for the next BUP
time slot. Once a module has pulled the arbitration line low, no other module will be granted access to the bus for the next BUP time slot.
When the next BUP time slot occurs, the module granted access to the bus for that period will be given access, and the counters of each module will be reset, and the priority of each module updated.
Description
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~TUAL PACKET B~JS CONCEPT
WIT~ 1~ISrr~RD3UTED ARBl~IION
BACKGRC)UND9F T~IE INVEN IION
S 1. Field of tlhe Xnvention _ _ The present invention lelates generally to computer bus architectures, and more specifically to a virtual packet bus for packeti~ed communications including a distributed arbitration technique with ~exible prioritization.
2~ ~elated ~t III digital computer systems having a plurality of modules, such as processor modules, controller modules, communications interface (relay) modules, etc., a medium is employed whereby these modules can transfer data among each other. I~pically, the medium employed is a physical data chanDel known as a bus. The bus is connected to a communications port on each module. In typical da~ bus architectllres, in~o~mation is conveyed over the bus one word at a time. In addition, since ~ere are multiple modules sharing the same bus, the 3nodules must contend for bus ac~ess for each word sen~
A computer bus ~ypically compnses multiple lines ~or transfelTing and for controlling the t;ransfer of ~ifferent 1~pes of infoImation among the modul~s attached to the bus. Conventional bus architectures include a parallel data bus structure and multiple control lines. The data bus is ~ypica31y N bits wide, where N is the number of bits per word.
Temporally, the bus is divided into a series of time slots known as bus cycles. A bus cycle is the period of time for which a module is granted access to the bus. In conventional bus ~rchitectures, the bus c~cle . ~
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is the same length as a clocl~ c~cle. Thus, in conventional systems, one N-bit word is transferred by a module oll each clock ~cle.
A Gommon scenario in a computer system with a convelltional bus architecture will now be descrlbed. ~1irst module has a word or series S of words that it wishes to send (or ~aDsfer) to a seoond module over ~e data bus. The ~rst module signals that it wishes to access the bus. A
means for arbitrating access to the bus detelmines whlether ~he fî~st ~module will be granted access on ~e ue~t bus c~le. If access is not ~anted to the first module, the first module must repeat its request un1il as~ss is granted. On~e bus access is gra~ted to the first module, it may send the fir~t word to the second module via the bus. The same process must repe~t again ~or each subsequent word the first module wishes ltO
send. In some cases, limited forms of mu~ple word transfers by one module may be pelmitted.
Conventional bus architectures are limited in two respects. First, th~y are limited in that they allow only single-word transi~e~s (or limited multiple-word traDsfers) for each bus cycle. Seoond, ~ey are limited in the a~bitra'don techniques employed to colltrol access to the bus by the various modules.
These oonventional bus architectures having siDgle-word bus ac~ss provide tlhe computer system with o~ly limited communications ~exibili~r, and do 311ot prov~de optimum system performance in all environments. In certain en~ironments, the computer system may be required to interface with various telecommunicatiolls networks. For example, the computer systelal may be implemented as a communications c~ntroller, controlling communications among the networks-interfaced at a node. As an alternative e~sample, the computer system may be used for scientific or business purposes and simply interfaced to the networks to sbtain data.
2.~3~9 Regardless < f the underlying function of the coIrlputer in these environments, the computer is required to take data from, and sometimes put data on$o, the various tel~;ommunications net~orlcs to which it inter~aces. These teleco~unications networXs ~pically operate o~ a 5 packet level. That is, the networks brans~er data in UllitS defined as packets. The charactensties of ~e packet are dei~ned according to the particular communicatiolls standard followed. Packets are typically de~ned as ~ specific llumber of bits in length, or a spe~ific number ~f octe~. For e~mple, ~e A~ynchronc~us Transfer Mode (ATML) 10 c~mmunications specification has defined a 53-octet packe~
One word or lTmited multiple word trans~ission schemes implemeuted in conventional bus arc~itectures are not directly compatible with these packet-level communica~ons standards. If, ~or example~ a packet of data is received at a ne~work inte~face card, that packet cannot 15 be directly sel~t across ~e conventional computer bus. Instead, the data mwst be 'depacketized' (removed from the packet), sent across ~e bus one N-bit word at a time, and, if destined for further communica~ons across ano~er network, reasse~led into packets. This incornpatibilit~
leads to a requirement for additional circuit~y in ~e interface modules.
20 This additioDal circuitty must allow inter~ace cards to depacketize the data, reassemble the data into packets, and operate at both the packet level and ~e word level.
Conventional bus architectures are limitcd in their arbitration techniques. In many conventioIlal systems, bus arbitration is handled by 25 a central arbiter. In these systems, each module has a bus access reques~
line and a line sîgnalling the module when acces~ is granted. Often, other control lines are added to provide additional information such as the state of the arbitration system. In systems using cen~alized arbitration, each rnodule sencls a bus access request to the central arbiter. Each access .
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, 21~37~3 - 'I -period9 the central ~rbiter grants bus access to a module based on the priority of the requesting modules.
Other arbitration schemes have distributed the arbiitration unction to ~e modules attached to the bus. In these s~stems, arb.itrati.on circuitly 5 is contained in each module, thus allowing the mt)dules themse~ves to determine whether they are allowed access to tlhe bus. Often these s~stems require arbitration busses to enable dis1~1)uted aTbitration. 'Illese ar~ ation busses are t~pically Y or 2Y lines wide, where Y is ~e number of madules. As with a centralized s~stem, contention is resolved by 10 evaluating ~e priori1y of the requesting syst~ms and gran'dng aa~ess to the requesting module with the highest prior;ty.
Conventional arbitration techniques are limited in the ma~nel in whi~h module priorit~ is assigned, ~us rest~icting the ile~ibility of computer bus operations. This limitation is present in bo~ centralized 15 and distributed arbitration schemes. In conventional systems, priorities are assigned in various ways. First, priorities may be assigned based on a physical address, a bus location, or the card-slot location oiE the ~module.
These priorities are fixed and cannot be ~hang~d unless the module is relocated or its address changed. Conventional arbitration sc~hemes using 20 this fi~st ~rpe of prioritization technique sometimes allow ~ex~bili~ by rotating the order of priority among the modlule locations.
A seeond method of assigning lpriorities in conventional systems is by malcing an initial assignment, and then rotating the priority of each module at the start of each subsequent bus cycle. In this method, each 25 module starts with an initial priori~y. Each Jdme access is grallted to a module, module priorities shift. In som~ schemes, the priorities of each module are all incremenled or decremented in a iixed marmer.
Thus, convention~l bus architectures are limited in ~wo respects.
They aTe limited in that they ~llow only for the 9ransfer o~E a single word , ~ .... . . . .
~.n3~0 o~ data for each bus c3~cle. ~ley are also limited in thal: thc arbitration techniques employed provide l~mited ~l~cibility in assigDme:nt and revision of module pnorities. Additionally, conventiollal distributed arbitration techniques lrequire arbitration buses with multiple sigDal paths, or the S number of signal paths propor~onal to the number of modllles on the bus.
Thus, convent;onal bus architectures are limited in the ~lexibili~y they provide for inter~cing to e~:ternal communicatiorl networks and are limited in their arbitration and module priority assignment technia~ues.
SUM~ OF TJHE INVI~ N
The present invention provides a system and method ~or bus communications at the packet level, including fle~ible, distlibuted bus arbi~ation. The bus according to the present invention is structured to ~ansfer data in lmits of paeke~s, wherein packets eomprise a plurali~ of wor~s N bits in length, where N is the wid1~ of the data bus.
The arbitration scheme according to ~e presellt inventi{~n is a dis~ibuted a~bitra~on te~hnique, whereby each module corltending for bus access is provided with bus arbitration logie. ~ single bus arbitration line is provided to interface to each modllle's arbitration circuit. The bus arbitration iogic comprises logic ~or deten~ming the module's priority and 2~ ~or dete~ining when the module is to be granted bus access based on ~e module's priority.
Accordi~g to the preseDt invention, the bus is divided in ~me in$o bus c3rcle periods known as Bus Packet, or BUP time slots. A BUP ~ne slot defines the time period for which a module is grarlted access. A~cess 25 ~or each BUP time slot is arbitrated by the arbitration circuit~r. ~e BUP
time slot is further divided iDto access time slots using an access time clock signal.
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According to the present inv~ntion, a digital counter is reset at the beginning of the BUP time slot USillg a BUP cloc~ l~he digital counter begins counting pulses of the access time cloclc~ thereby coun~ng access ~e slots. 'rhe counter output value is out~ut to a comparator.
A state machine indicates the priority of the module and OUtp a prion~y value to the comparator. 'rhe comparator compares the pIiori~
value to tlle counter value, and when these values are equal, the comparator provides a comparison time pulse. Fl~e comparison ~ne pulse is used to ultimately cla~m access to t he bus.
~e comparator of each module is comparing the number s~f access time slots counted to the module's priority ~alue. ~hus, a comparison ~me pulse will be generated sooner for a module with a lower priori1 number (i.e., a higher priori~). The first module to request bus access and to generate a comparison time pulse will ultimately pull the arbitration line low thereby den~g access to the other modules.
If a module wi~ a higher priorit~ (lower pr~ori1y number) ~has not already requested access to the bus and pulled the arbi~atioll line low, the comparison time pulse of a request~ng module is used to generate a bus available signal if this module is requesting the bus. This bus available signal is then used to pull the arbi~ation line low thus inhibiting other rnodules from obtaining bus aecess.
Bus arbitration takes place duTing a cunent BIJP time slot to detelmine which module will have access to the bus for the next BUP
time slot. At the beginning of each BUP time slot, a counter value is reset to its initial value and the prioril~ of the module call be updated based on a number of prioritization schemes. A number of prioritization schemes can be used to establish the priority of the modules for each ~UP ~me slot. Irhe ability to implement diflerent priority schemes provides maximum system flexibility.
- 2~37~3 Further features and advantages of the present in~ention, as well as the s~ucture and opera$ion of various ~mbodiments ,of the present invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers indicate S identical or functional similar elements. Additionally, tht' leftmost digit of a reference number identif ies the drawing in wbich a reerence number i~rst appears.
BRIEF DESCRIPTION OF T~[E DRAYYl~GS
The present invention will be descnlb~d with ~eference to the accompanying drawings, wherein:
FIG. 1 is a block diagram illus~atiug a computer ~stem functioning as a network communicatiorls node that is an example en~onment of the present invention.
FIG. 2A is a block diagram illus1~a'dng the structure of ~e virtual packet bus aocording to ~e present i~lvention.
FIG. 2B is a ~ming diagram illustra~n~ divisio~ of the virtual packet bus into BUP ~e slc~ts.
EIG. 3 is a circuit diagram illust~ting an e~bodimellt s:)f the present inven1ion.
l;IGs. 4A and 4B compnse a ~ow char;t illustra~ng the operation of the present invention.
~IG. 5 is a timing diagram illustrating ~e temporal placement of key timing signals of an arbitration circuit according to an embodiment of t~e present illvention.
~G 6 is an alternative embodi~ent of the present invention implemented without a counter.
FIG. 7 is a block diagram illustrating arbitration among modules arranged in groups of modules.
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FIG. 8 is a di~gram illus~rating implementatio~l of the arbitration ~ircuit according to the present invention with an optical fiber arbitration line.
DEl[AILED D~(~RIPTION OF l~ PREFEP'RED
EMBODIMENTS
TABL~ OF C~
O~renriew o~ ~e Present ln~n~on ~ Sample E~viro~ment 3. T~e Bus 10 4. Bus A~bitration 5. Plrio~ onTecihniques 6 ~ension of ~e Module Capac~
7. Operatio~l at ~Iigh Speeds 1. Ovemew of ~e Present Invention ~e present invention provides a systen: and method for paclce~ized bus communica~ons including fle3cible, distributed bus arbitration. T~e bus according to the present invention is structured to handle data transfers in llDitS of packets. The packets comp~ise M ~ords, where e~ch of ffle M words is N lbits in length. N is the wid~h of the ~data b~s.
The bus uses a dis~ibuted arbitra~on æheme, whereby each module ~ontending Ior bus access has bus arbi~ ion logic. I~e bus arbi~ation lo~c comprises logic for determming t;lhe module's pnori1y, and ~or detelmining when the module is granted bus access based on the module's priority.
~e bus arbitration logic is capable of providing ~e~ble priontization æhemes. According to ~e present il:lvention, a n~mber of alterna~ve priontization schemes may be employed. Through these schemes, system ~ex:ibility and adapt~ are enhanced.
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Thus, arbitratioll according to the present i~vention, call be implemented using only a single bus arbi~ation line ~onnected to each module. This single bus arbi~ation line is used to indicate whether another module has already been granted access to thc bus during ~he S next bus c~c~e.
Sample Envi~onment The present inven~on was developed ~or use in a computer system that functions as a network packet switc~. lFIG. 1 is a block diagram illustra~ng a computer sys~m configured as a neh~vorlc packet switch 100 10 and its typical inter~aces. Re~ening to FIG. 1, the sample environment will now be desclibed. A network packet switch 100 o tlhe sample environment mcludes two separate busses. A Virtual Packet Bus 102 (referred to as VPB lûV is a high speed, Virtual ~ynchrollous l~ans~er Mode (VA~) bus ac~ording to the present inve~tion. A standard ~/llF.
15 bus lW, ~or handling local, low speed status and control info~rma~oll, îs also provided.
T-1 frame relay modules 106 accept up to four T 1 ~ame ~elay channels, and packetize the data from ~ese channels into AThlI
(A~ynchronous Transfer Mode) packets. Trunlc interl~ce modules 108 20 accept ATM pac}cets from VPP~ 102. nunlc interface modules interface the ATM pacl~ets ~nth standard T-3 or SONET fo~mats for transport Processor modules 110 provide network element management and interface to an external ethe~net network 114. External ethernet network 114 provides the node ~nth a network management interface. A dual 25 redundant power supply module lL12 pro~ides system power.
~ e ~lnction of networlc packet switch 100 is to receive data packets origina~ng with users of networ3k data services such as Frame lRelay Selvice and Switched Multi-megabit Data Sen~ice (S~fDS), and , - , .. .. . . . . . . .. .. . . . .
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route these data packets to other ne~work nodes in accordance with the address of the packets. Additionally, ne1:work packet switch 100 ~eoeives data packets f~om other nodes addressed to the location of the packet switch. VPB 102, which is the subject of this i~v~n1ion, provides tdhe 5 inte~al communica~on path for the dat~ packets betwee3l user access modules such as ~e T~ e relay module m6 and mter-llodal communica~ons links, ¢ommon~ called trumks, such as ~unk inter~ace modules 108. Packets ongina1ing at a user inter3~ce ~n one of a mul~plicity of ~ame ~elay moslules 106 may be routesl over ~he 1bus to a:~y 10 one of the trunk modules 108 or to other local users through frame ~elay modules 106.
3. l[he Bus FIG 2A illusbrates VPB 102 according to ~e present LDvelltion.
3Refer~ing to FIG. 2, VPB 102 comprises a data bus 202~ a co~non bus arbitra'don line 204 aIId a bus packet ( 13UP) clock line 206. III a prefe~ed ~mbodiment, VPB 102 is a backplane bus to which a plurality of modules 208 a~e in~r~aced. Modules 208 call be circuit cards tha~ are pluggesl in~o backplane VPB 102using car~-edge comlectors. Modules 208 can include modllles such as processor module 110, and trunk interf~ee module 108, 20 as discussed in the Sample Enviromment Subsec1ion of this application.
In a preferred embodiment, data bus 202 is 64 bits wide (i.e., N is 64). This width malces VPB 102 compa~ble with a 53 octect packet standard and still allows additional bits for other system ~n¢tions. ~he preferred embodiment of the virtual packet bus uses 53 octet AXM:
25 packets. With a 64 bit wide data bus, seven (7~ bus transfers are required i~or each packet leaving 3 octets available as extra bits (7 bus traIIsfers -8 octets per transfer - 53 octets). These additional bits may be used for a variety of purposes such as carrying error correcting parity information ' .: . : ' ' . . .
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to detect packet errors, to carry stabus in~olm a~on alld so for~h. Other embodiments ~re contemplaLed wherein data bus 20Z is o~ a width other than 64 bits.
A unique feature of ~P~ 1027 according to the present inveD~ion, S is that it allows data ~ansfer in groups of words (packets). A packet is de~ined as haviRg a length of M words. In a preferred em bodirnen~ the packetlength is sev~n words (i.e~ M is 73. To handle da~a t~anser in units ofpack~ thelength of~he bus cycle ~ def~led to c~ve~the packet length. Thus, ~rPB 102, aoc3rd mg to the presentinven~on~ uses a packet 10 t~ning concept to def~le the bus cycle~
FIG. ~B i~ustrates the packetb~ning concept of ~PB 102 according to the present invention. Referrmg to ~IGs~ 2A and 2B, the packet timing concept will now be described. BUP clock line 206 provides ;a BUP clock signal 2~6 to all modules 208 on VPB bus 102. BUP cla~k signal 226 te[nporally par~tio~s VPB 102 into bus ~rcle periodæ These bus c3rcle periods are called BUP time slot~. BUP clock signal 226 is a ~IIliDg pulse that marks the s~ f each BlUP ~e slo~ 'rhe leng~ of tlle BUP ~me s1~t L is sufficient to handle ~e bus packet len~ M. 13us packet length L is the lnin~um data transer ~ne UII;t of 'VPlB 102. All 20 packet t~ansfers on VPB 102 are made within the B~ ~me slot as defined by BIJP elock signal æ6.
Thus, in a preferred embodiment where M = 7, bus packet leDgth L is chosen such ~at seven N-bit bus words 228 can be tra~sferred within ~hat time. I~us, data bus 202 can be defined in terms of a width of N bits 25 and periods of length defined by the bus packet length L.
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2~ ~37~0 4 Bus ~lbibration According to ~e present invention, bus arbitration is handled on a distlibuted basi~s. Each module on the bus is provided ~w~th arbitration CilCUitly to dctemline dunng 1he current BUP time slot whe1her its S module can access the bus durillg the next 13UP time slot. Arbitration circuit~y includes logical elements for determining the current module priority, and for dete~ g wh~er ~us access will be allowed based on ~at priority. CircuitIy is also provided for updating the module pIiori~y.
Arbitration circuitly is p~ovided with BUP clock 226 andl with an access time clock.
During the current BUP time slot~ the arbitration circuitly be~s counting pulses of the a~xess ~me clock signal. I~e arbitration circuitly compares the c~unted value to ~e current module priority. When ~e counted value equals 'lhe module priori1y, the modulé will be granted access to the bus during the ne~t B~JP time slot if two conditions are met.
The two eonditions are: (i) the module must be requesting a~ess; and (ii) the bus lllllSt not alrea~y ha~e been claimed by a module with a higher priority. When a module is granted access to the bus, that module pulls the arbibation line low until ~e current BUP time slot has e~pired.
2a When the ar~ ation line is low, no other module will be granted access for the next BUP ~me slot.
FIG. 3 ;s a schematic diagram illust~a~ng the arbitration circuitIy according to the present invention. Referring to FIG. 3, a bus arbiter 300 is interfaced to common bus arbitration line 204, to arl access 1ime clock 308, and to BUP clock sigDal 226.
Bus arbiter 300 comprises seveTal logic components. ~ese components will now be described. Bus arbiter 300 includes a state machine 3V2. State machine 302 is used to indicate the priori~r of the module in the digital fonn. Bus arbiteT 300 also include(s a counter 304 - . - . . .
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and a comparator 306. Counter 304 counts edges of access time clock 308. In a preferred embodiment, counter 304 begins at an initial value, increments its value on each posit~ve transition of access time clock signal 308, and ~e counter value is ou~ut as a counter value signal 354.
Counter 304 is reset lo its initial value by BIJP dcsclc signal æ6.
Alternative embodiments may be considered where:in counter 304 deerements as opposed to increments, ~nd where counter 304 responds to nega~ve ~ansitions.
Comparator 306 compares ~e pnori1y o~ the module as indicated by s1~te machine 302 against couDter value sig~al 354.
A bufler 310 is used to monitor arbitration line 204 to dete~ e if access to t~e bus is still available for the ne~t BVl:' time slot. If arbitra'don line 20~ is high, the bus is s~ll available for ~e ne~t BUP ~e slot. If, however, arbitration line 204 is low, anoffler module has already 15 claimed the bus ~or the next ~me xlot.
A flip ~op 314 is set when counter 3M ~eaches ~e module's prion1~r as indic~ted by state machine 302 if ~e bus is still available at the ne~t BUP time slo~ When flip llop 314 is set and the module is reques~ng Ibus access f~r the next BUP 1ime slot, a transistor 316 is 21) turned on. When transistor 316 is turned on, arbitration line 204 is pulledIow, thus disabling other modules from a~ssing the bus on ~e next BUP
time slot:
State machine 302 is loaded with an mitial value, indicating the initial pnority of the module, via an initial value signal 366. The priority 25 value o the module can be updated ~or each BIJP ~e slot by an update signal 368. . --FIGs. ~ and 4B comrpise a flow chart illustra~ing the operationof bus arbiter 300 according to 1he present intrention. FIG. S is a timing diagram illustrating the temporal relationships among lhe various signals 2~Q378~
of bus arbi~er 300 of the present invelltis)n. I~e~erring to FIGs. 3, 4A and 1~, and 5, the operation of bus arbiter 300 wiII now be described. The operation of bus arbiter 300 of a sample module will be described with respect to events occu~Ting in bus arbiters 300 of other .modules. Bus arbiter 300 for each raodule operates in a similar fashion~
In a step 402, at a time ~ = 0, a BUP ~lock pulse 502 of BUP clock signal 2~6 marks ~e beginnLng of a current BIJP time slot. The ~me duling this current BUP time slot will be used to detelm~ne which module will Ibe ~nted access to ~e bus dur~ng the uext BIJP time slot The next BUP 1ime slot beg~ns at a time ~ = 2. ~dditionally, BUP clock pulse 502 rese~ counter 304 to an initial value, and resets ilip flop 314. In addition, BIJP clock pulse 502 sets state machine 302 to an initial pnorit~ value as determined by initial value signal 366 or to an updated priority value as detennined by update signal 368.
In a step 404, counter 304 be~s coun~ng pulses 504 of access ~dme clock 308. Access time clock 308 ~uns at a rate higher ~an BUP
cloc~c 226. Thus, counter 304 essentially ~vides each BI~P time slot into a distinct number of shorter ~me slots as illustrated in FIG. 5. The leng~h o~ these time slots is dei ined by ~e period of access ~e ~lock 308. For example, if aocess ~me cloclc 308 is 16 times higher in rate than BIJP
clock 226, counter 304 will increr~ent (or decrement) 16 ~mes within the BUP ~me slot. Thus, in this example, counter 304 will divide the Bl[JP
time slot into 16 segments.
Counter 304 begins cc)unting pulses 504 of access time clock 308 :Irom its ini~al value, and outputs eo~mter value signal 354 $o comparator 306. Counter 304 continues colmting pulses 504 until the next BUP clock pulse 502 rese$s counter 304 to its initial value. Once reset, coun$er 304 begins anew, counting f~om its initial value. In a preferred embodiment, counter value signal 354 is in the forrn of a digital word. l~e width of the . .. : : . . : : - , - - , ' . ~
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word is chosen to accommodate the ma~mum value reached by counter 304. This maximum value may be dehned by ~e ratio of access time clock ~equency 308 to BUP clock 226 freque3lcy.
State machine 302 indicates the pno~r of the module continuously S throughout the BUP ~me slot period. Sta~e machille Qll'qpUtS a module p riori~y value si~nal 352 (referred to as time aecess, state 352) to comparator 306. E~ach module Oll the bus has a unique tiime access state 352 at any given BUP ~me slot. In a preferred embodmlent, the module 1ime aocess state 352 is indicated in the ~olm of a digital wor~ ~e w~dth 10 o l~is digital word is chosen to be wide eIIough to allow a ~nique time access state 352 to be represented ~or each module.
As c~unter 304 i5 counting pulses 504, comparator 306 is compaling counter value signal 354 to time access state 352 as indicated by state machine 30æ
In a step 406, when counter value signal 354 is equal to time access state 352 (ie. ~e priority value), comparator 306 sends a comparison time pulse 506 over a comparator ou~ut signal pa~dh 356. Compariss~ ~ne puJse 506 indicates that the module's time aocess state 352 has been ~eached 7by counter 304. The ~Irrence of ~is ~vent is denoted by a 20 ~e ~ = 1 in FIG. 5.
If, as in the e~ample above, access ~me clock 308 divides the BUP
~me slot into 16 segments, 16 dis~nct counts are produced by counter 304 in one BUP time slot. Thus, in this example, ~6 modules can have unique ~dme access states 352. Each of these unique ~me access states 352 ~5 defines a unique time access window in a BIJP time slo~
In a step 408, if another module.having a higher priority tha~ the subject module has requested access to the bus ~or the next BUP ~ime slot, arbitration line 204 will already be at a low state (to be described), and the arbitration process is complete. The subject module is Ilot 2l037~a granted access for the next time slo~ ~he arbi~a1ioII process will begin again at step 402 with the next BUP clock pulse 502 of 13UP cloek 226.
If, on the other hand, the bus is s~ll availalble for the next BUP ~ime slot, bus arbiter 300 con~nues the process at a step 410. Step 408 is discussed S in greater detail below.
In step 410, compalison time pulse 506 is input to i~lip ~op 314 at an i~nput port S. Companson time pulse 506 sets an ou~ut port Q of filip 91Op 314 high. This results in a iaip iElop output signal 360 ~ansitioning to a ~igh state.
In a step 412, if ~e module is not requesting access to ~e bus for ~e ne~t arbit~tion period, a bus request signal 362 is low and ~e arbi~ation process for fflis module is IEi~shed. ~bitration will begin a~un at step 402 with the ne~t BUP cloclc pulse 502 of BIJP clock æ6.
l[f, however~ the module is reques~dng access to thê bus ~or ~he next 1~ a~bitration period, the module asserts a high bus reqllest signal 362. In a step 414, the high ilip ilop ou13put signal 360 and ~he high bus request signal 362 mput to an AND gate 320 cause bu5 available signa1364 to hansition to high. When bus availab1e signal 364 is high, ~ansistor 316 tun~s on. The oollector of transistor 316 is connected to bus arbitration 20 Line 204 and the source is coD~ected to ground. Bus arbitration line ~04 is kept lhigh ~nth a pull-up ~esistor 3æ to Vcc. 'rhus, when transistor 316 is tu~ned Oll by a bus available signal 364 at its base, bus arbitration line ~04 is pulled to ground. When bus arbitration lline 204 is low, no other module will be granted access to the bus.
2S In addition, bus available signal 364 indicates to ~e module that the module has lbeen granted access to the bus for the next BUP ~me slot.
he preferred embodiment transistor 316 is a bipolar kansistor.
- As will be clear to one of ordinary slcill in the art, any l~rpe of electric~l switching device which is sufficiently ~ast can perform the same function 2~Q37~9 as t~ansistor 316. Altel~ative switching devices include MOS field eflEect ~ansistor devices or stalldard logic gates capable of pulling the arbillation line to gro-md.
Ln a step 416, at a time ~ = 2, the module granted ;access se.nds its 5 paclcet across the bus. At this time th~ arbitration process begins again at s~ep 402. Pulse 502 of BIJP clock æ6 rese~s counter 30~ to its initial value, updates (or, alternatively, resets) the priori1y of stalte ma~hine 302 and ~esets flip ~lop 314. Wllen ~ip flop 314 is reset, illip iElop output signal360 is set low. This causes bus available signal 364 to go low, turning off t~sis~or 316. With ~ansistor 316 o~, bus arbitra~on line 204 is 3pulled high by pull-up resistor 3æ.
As discussed above in step 408, the subject module will not be granted access to the bus unless no other higher priori~ modules a~e reques~ng access. The mamler in which this detelmina'don is made will now be descnlbed in more detail. Counter 304 ~or each module counts pulses 504 of aocess time clock 308. In aII example embodiment, counter 304 YS impleme~ted as an up counter and begins its co~m~ from an ini~al value of zero. I~hus a module wi~ a lower ~e access state 352 will gene~ate its comparison time pulse 506 before a module with a ~igher time access state 352. The fi~ module to generate comparison time pulse 505 and re~uest the bus wi~ a high bus request signal 362 will pull aTbit~at;on line 204 low as discllssed a~ove. Ac~ss will be granted to ~at moduie for ~e next ~BIJP time slot. Therefore, aocess to all other modules must be disallowed.
Once a module has pulled arbitration line 204 low, a buffer 310 on each bus arbiter 300 asserts a low bus bllsy signal 358 to an input to an AND gate 318. This low bus busy signal 358 inhibits comparison time pulse 506 from setting flip flop 314. Thus, once a module pulls arbitration line 2~ lowg no other module may set its flip flop output ;,' ~ ' ~
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signal 360 high, gencrate a high bus available signal 3S4, and access the bus ~or the next BUP ~me slo~
~ dditional embodiments caII be conceived as encomp~ssing a]te~na1~ve implemen~tions of bus arbiter 300. ~or e~ample, ~lip f lop 314 5 could be a JK flip fl~p clocked by comparison ~dme pulse 506. The input in ~is embodimeIIt would be bus request sig;nal 362. T~us when bus ~equest signal 362 is high and companson ~ne pulse 5()S occurs~ the Q ou~ut is a high signal. The JK tip fl~ would still be reset by BUP
clock æ6.
An addi'donal alte~native embodiment for bus arlbiter 30S) can be nnplemented by replacing counter 3M with a st~te ma~hine and elhnina~ng state machine 302. FIG. 6 is a diagram illustra~g this altemative embodiment of bus arbiter 300. l~efe~g to FI~. 6, a lmodule access number 652 is hardwired into Gomparator 306. Module access number 652 is unique for each module. Each module initializes a state machine 602 wi~ a unique initiali~on ~iralue 656. Pulses of aocess time clock: 308 ~loclc state machine 602 A~ each pulse ~ access ~dme cloclc 308, state machine output 654 increments. Comparator 306 compares state ma~hine output 654 with module access number 652. When ~e ~umbers aglree, a c~mpalison time pulse 506 is ~generated. Compa~ison time.pulse S06 is used to pull bus arbitration line 204 low as in the pre:~erred embodimen~ A pulse 502 of BU~ clock signal æ6 increments the state machine to a new state at the begimling of each new BUP time slo~
l~eferring again to FIG. 3, another alternative embodiment may be considered wherein bus busy signal 358.is routed directly to counter 304 (instead of to AND ga$e 318 as ilustrated). In this embodiment, cc~unter 3~ is inhibited from coun~ng whe~ bus busy signal 358 is low. Thus, AND gate 318 is not required.
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2~37~ 3 In still another alternative embodiment of bus arbiter 300, bus request signal 362 is input to AND gate 31~ thus enabling or inhibiting bus access without the need for AND gate 320.
These a}terna~ve embodmlents se~ve as e~amples of ~e l~umerous 5 ~unctionally equivalent embodiments of the bus arbi~-a~oll çircuit~y according to the present ~ven~on.
5. Prioritiza~on Tec~niques - Blls arbitra~on aocording to ~e presellt invention pro~qdes ~e~ility in assigning and updating module prionty. Nlmlerous 10 prioritization techniques are contemplated whereill module prio rities are determined. Different prioritization schemes can be impl~mented Ibased on the requirements o~ the compute~ system, thus op~mizing system pe~formance. E~amples of such prioritization techniques are ou~ned in ~e text ~at ~EO11GWS.
]?.efening a~ to PIG. 3, as previous~y mentiolled, ~he priori1~r of a module is controlled by state machine 3~2. State machine 302 out~uts a time access state 352 indicating the 3module pnori~y. In its simplest configuratioll, s~te maclline 30~ is a gï~ed, hard-wired number. In ~his ¢onfiguTation, eaeh module is assigDed al uniqlle, fixed pri~rity number 20 (tdme a~cess state 352,). ~e priority may be assigned according to a number of diflerent strategies. For e~ample, the priorily llumber ~Eor each module may be assigned according to the location of the module on the bus.
In a preferred embodiine~, state machine 302 is implemented in 25 such a manner that it is updated at each BUP clock pulse 50~. This allows the priori~ of each module to be altered ~or each BIJP ~ne slo~
State mach~es 302 in all modu~es must be synchroni~ed and be identical such that time access state 352 is unique for each module.
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2 L a 3rl,'30 A variety of priori~ schemes for determining module pnority at each BUP cloclc pulse 502 can be implemented. llmplementation o~ ~ese var~ous schemes is accomplished by changing the mamler in which state machine 302 is imple~ented. ~s an e~ample, a simple prio~ty scheme S c~ be impl~men~d by using a modulo-N counter as st~te machine 302.
In this scheme, ~e modulo-N count~r is initialized with 1~he module lllumber. Ini~aliza'don takes place by sendi~ an ini~alization signal 36fi to s~te machine 302. Once initialized, all modules' modulo-N counters are decremented at each BUP slot by BUP clock pulse 50æ Thus after 10 each BUP t~me slot each module's p~ori~y is incre~sed by ~lle. If a module requests the bus and acquires it du~g one ~3UP ~me slot, the module time aocess wDldow 352 is moved one access ~me later when BUP
clock pulse 502 decrements the modul~N counter. I~e module ~hat had ~he lowest pnority 1ime acces~s st~te is moved to the highest pliori1y and 15 all other modules decrease in pl~ority.
Alternat~vely, a "round robin" scheme can be implemented by mo~ring the access state of ~e module acquinng the VPB to ~e lc~west pnori~y (last time access) and incrementing the prion~y o~ all modules which had a lower p~iori~r. In this case, any module wi~ an access state 2S) later ~an ~e module acquiling ~e bus woulld increment ~eir states, those with higher pliori'des would remain în the curren~ state, and the most recent bus ~lær would move to the last access time. I~e update line to the state machine would control the state machine.
A pseudo random sequence (PRS~ generator cc)uld also be used to 25 generate th¢ access time state. If all modules have identical PRS
generators and each module ini~ializes ~-e generator with a unique state, such as it's module nun~ber, then all PRS generators are incremented at each BUP slot, giving all modules ~he same long telm average bus priority. The state machine can be any machine which produces a ullique .
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:. , ' state for each module and which can be synchronized by the irlitialization.
This can include table lookup methods.
~TUAL PACKET B~JS CONCEPT
WIT~ 1~ISrr~RD3UTED ARBl~IION
BACKGRC)UND9F T~IE INVEN IION
S 1. Field of tlhe Xnvention _ _ The present invention lelates generally to computer bus architectures, and more specifically to a virtual packet bus for packeti~ed communications including a distributed arbitration technique with ~exible prioritization.
2~ ~elated ~t III digital computer systems having a plurality of modules, such as processor modules, controller modules, communications interface (relay) modules, etc., a medium is employed whereby these modules can transfer data among each other. I~pically, the medium employed is a physical data chanDel known as a bus. The bus is connected to a communications port on each module. In typical da~ bus architectllres, in~o~mation is conveyed over the bus one word at a time. In addition, since ~ere are multiple modules sharing the same bus, the 3nodules must contend for bus ac~ess for each word sen~
A computer bus ~ypically compnses multiple lines ~or transfelTing and for controlling the t;ransfer of ~ifferent 1~pes of infoImation among the modul~s attached to the bus. Conventional bus architectures include a parallel data bus structure and multiple control lines. The data bus is ~ypica31y N bits wide, where N is the number of bits per word.
Temporally, the bus is divided into a series of time slots known as bus cycles. A bus cycle is the period of time for which a module is granted access to the bus. In conventional bus ~rchitectures, the bus c~cle . ~
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is the same length as a clocl~ c~cle. Thus, in conventional systems, one N-bit word is transferred by a module oll each clock ~cle.
A Gommon scenario in a computer system with a convelltional bus architecture will now be descrlbed. ~1irst module has a word or series S of words that it wishes to send (or ~aDsfer) to a seoond module over ~e data bus. The ~rst module signals that it wishes to access the bus. A
means for arbitrating access to the bus detelmines whlether ~he fî~st ~module will be granted access on ~e ue~t bus c~le. If access is not ~anted to the first module, the first module must repeat its request un1il as~ss is granted. On~e bus access is gra~ted to the first module, it may send the fir~t word to the second module via the bus. The same process must repe~t again ~or each subsequent word the first module wishes ltO
send. In some cases, limited forms of mu~ple word transfers by one module may be pelmitted.
Conventional bus architectures are limited in two respects. First, th~y are limited in that they allow only single-word transi~e~s (or limited multiple-word traDsfers) for each bus cycle. Seoond, ~ey are limited in the a~bitra'don techniques employed to colltrol access to the bus by the various modules.
These oonventional bus architectures having siDgle-word bus ac~ss provide tlhe computer system with o~ly limited communications ~exibili~r, and do 311ot prov~de optimum system performance in all environments. In certain en~ironments, the computer system may be required to interface with various telecommunicatiolls networks. For example, the computer systelal may be implemented as a communications c~ntroller, controlling communications among the networks-interfaced at a node. As an alternative e~sample, the computer system may be used for scientific or business purposes and simply interfaced to the networks to sbtain data.
2.~3~9 Regardless < f the underlying function of the coIrlputer in these environments, the computer is required to take data from, and sometimes put data on$o, the various tel~;ommunications net~orlcs to which it inter~aces. These teleco~unications networXs ~pically operate o~ a 5 packet level. That is, the networks brans~er data in UllitS defined as packets. The charactensties of ~e packet are dei~ned according to the particular communicatiolls standard followed. Packets are typically de~ned as ~ specific llumber of bits in length, or a spe~ific number ~f octe~. For e~mple, ~e A~ynchronc~us Transfer Mode (ATML) 10 c~mmunications specification has defined a 53-octet packe~
One word or lTmited multiple word trans~ission schemes implemeuted in conventional bus arc~itectures are not directly compatible with these packet-level communica~ons standards. If, ~or example~ a packet of data is received at a ne~work inte~face card, that packet cannot 15 be directly sel~t across ~e conventional computer bus. Instead, the data mwst be 'depacketized' (removed from the packet), sent across ~e bus one N-bit word at a time, and, if destined for further communica~ons across ano~er network, reasse~led into packets. This incornpatibilit~
leads to a requirement for additional circuit~y in ~e interface modules.
20 This additioDal circuitty must allow inter~ace cards to depacketize the data, reassemble the data into packets, and operate at both the packet level and ~e word level.
Conventional bus architectures are limitcd in their arbitration techniques. In many conventioIlal systems, bus arbitration is handled by 25 a central arbiter. In these systems, each module has a bus access reques~
line and a line sîgnalling the module when acces~ is granted. Often, other control lines are added to provide additional information such as the state of the arbitration system. In systems using cen~alized arbitration, each rnodule sencls a bus access request to the central arbiter. Each access .
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, 21~37~3 - 'I -period9 the central ~rbiter grants bus access to a module based on the priority of the requesting modules.
Other arbitration schemes have distributed the arbiitration unction to ~e modules attached to the bus. In these s~stems, arb.itrati.on circuitly 5 is contained in each module, thus allowing the mt)dules themse~ves to determine whether they are allowed access to tlhe bus. Often these s~stems require arbitration busses to enable dis1~1)uted aTbitration. 'Illese ar~ ation busses are t~pically Y or 2Y lines wide, where Y is ~e number of madules. As with a centralized s~stem, contention is resolved by 10 evaluating ~e priori1y of the requesting syst~ms and gran'dng aa~ess to the requesting module with the highest prior;ty.
Conventional arbitration techniques are limited in the ma~nel in whi~h module priorit~ is assigned, ~us rest~icting the ile~ibility of computer bus operations. This limitation is present in bo~ centralized 15 and distributed arbitration schemes. In conventional systems, priorities are assigned in various ways. First, priorities may be assigned based on a physical address, a bus location, or the card-slot location oiE the ~module.
These priorities are fixed and cannot be ~hang~d unless the module is relocated or its address changed. Conventional arbitration sc~hemes using 20 this fi~st ~rpe of prioritization technique sometimes allow ~ex~bili~ by rotating the order of priority among the modlule locations.
A seeond method of assigning lpriorities in conventional systems is by malcing an initial assignment, and then rotating the priority of each module at the start of each subsequent bus cycle. In this method, each 25 module starts with an initial priori~y. Each Jdme access is grallted to a module, module priorities shift. In som~ schemes, the priorities of each module are all incremenled or decremented in a iixed marmer.
Thus, convention~l bus architectures are limited in ~wo respects.
They aTe limited in that they ~llow only for the 9ransfer o~E a single word , ~ .... . . . .
~.n3~0 o~ data for each bus c3~cle. ~ley are also limited in thal: thc arbitration techniques employed provide l~mited ~l~cibility in assigDme:nt and revision of module pnorities. Additionally, conventiollal distributed arbitration techniques lrequire arbitration buses with multiple sigDal paths, or the S number of signal paths propor~onal to the number of modllles on the bus.
Thus, convent;onal bus architectures are limited in the ~lexibili~y they provide for inter~cing to e~:ternal communicatiorl networks and are limited in their arbitration and module priority assignment technia~ues.
SUM~ OF TJHE INVI~ N
The present invention provides a system and method ~or bus communications at the packet level, including fle~ible, distlibuted bus arbi~ation. The bus according to the present invention is structured to ~ansfer data in lmits of paeke~s, wherein packets eomprise a plurali~ of wor~s N bits in length, where N is the wid1~ of the data bus.
The arbitration scheme according to ~e presellt inventi{~n is a dis~ibuted a~bitra~on te~hnique, whereby each module corltending for bus access is provided with bus arbitration logie. ~ single bus arbitration line is provided to interface to each modllle's arbitration circuit. The bus arbitration iogic comprises logic ~or deten~ming the module's priority and 2~ ~or dete~ining when the module is to be granted bus access based on ~e module's priority.
Accordi~g to the preseDt invention, the bus is divided in ~me in$o bus c3rcle periods known as Bus Packet, or BUP time slots. A BUP ~ne slot defines the time period for which a module is grarlted access. A~cess 25 ~or each BUP time slot is arbitrated by the arbitration circuit~r. ~e BUP
time slot is further divided iDto access time slots using an access time clock signal.
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2~37'~Q
According to the present inv~ntion, a digital counter is reset at the beginning of the BUP time slot USillg a BUP cloc~ l~he digital counter begins counting pulses of the access time cloclc~ thereby coun~ng access ~e slots. 'rhe counter output value is out~ut to a comparator.
A state machine indicates the priority of the module and OUtp a prion~y value to the comparator. 'rhe comparator compares the pIiori~
value to tlle counter value, and when these values are equal, the comparator provides a comparison time pulse. Fl~e comparison ~ne pulse is used to ultimately cla~m access to t he bus.
~e comparator of each module is comparing the number s~f access time slots counted to the module's priority ~alue. ~hus, a comparison ~me pulse will be generated sooner for a module with a lower priori1 number (i.e., a higher priori~). The first module to request bus access and to generate a comparison time pulse will ultimately pull the arbitration line low thereby den~g access to the other modules.
If a module wi~ a higher priorit~ (lower pr~ori1y number) ~has not already requested access to the bus and pulled the arbi~atioll line low, the comparison time pulse of a request~ng module is used to generate a bus available signal if this module is requesting the bus. This bus available signal is then used to pull the arbi~ation line low thus inhibiting other rnodules from obtaining bus aecess.
Bus arbitration takes place duTing a cunent BIJP time slot to detelmine which module will have access to the bus for the next BUP
time slot. At the beginning of each BUP time slot, a counter value is reset to its initial value and the prioril~ of the module call be updated based on a number of prioritization schemes. A number of prioritization schemes can be used to establish the priority of the modules for each ~UP ~me slot. Irhe ability to implement diflerent priority schemes provides maximum system flexibility.
- 2~37~3 Further features and advantages of the present in~ention, as well as the s~ucture and opera$ion of various ~mbodiments ,of the present invention, are described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers indicate S identical or functional similar elements. Additionally, tht' leftmost digit of a reference number identif ies the drawing in wbich a reerence number i~rst appears.
BRIEF DESCRIPTION OF T~[E DRAYYl~GS
The present invention will be descnlb~d with ~eference to the accompanying drawings, wherein:
FIG. 1 is a block diagram illus~atiug a computer ~stem functioning as a network communicatiorls node that is an example en~onment of the present invention.
FIG. 2A is a block diagram illus1~a'dng the structure of ~e virtual packet bus aocording to ~e present i~lvention.
FIG. 2B is a ~ming diagram illustra~n~ divisio~ of the virtual packet bus into BUP ~e slc~ts.
EIG. 3 is a circuit diagram illust~ting an e~bodimellt s:)f the present inven1ion.
l;IGs. 4A and 4B compnse a ~ow char;t illustra~ng the operation of the present invention.
~IG. 5 is a timing diagram illustrating ~e temporal placement of key timing signals of an arbitration circuit according to an embodiment of t~e present illvention.
~G 6 is an alternative embodi~ent of the present invention implemented without a counter.
FIG. 7 is a block diagram illustrating arbitration among modules arranged in groups of modules.
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FIG. 8 is a di~gram illus~rating implementatio~l of the arbitration ~ircuit according to the present invention with an optical fiber arbitration line.
DEl[AILED D~(~RIPTION OF l~ PREFEP'RED
EMBODIMENTS
TABL~ OF C~
O~renriew o~ ~e Present ln~n~on ~ Sample E~viro~ment 3. T~e Bus 10 4. Bus A~bitration 5. Plrio~ onTecihniques 6 ~ension of ~e Module Capac~
7. Operatio~l at ~Iigh Speeds 1. Ovemew of ~e Present Invention ~e present invention provides a systen: and method for paclce~ized bus communica~ons including fle3cible, distributed bus arbitration. T~e bus according to the present invention is structured to handle data transfers in llDitS of packets. The packets comp~ise M ~ords, where e~ch of ffle M words is N lbits in length. N is the wid~h of the ~data b~s.
The bus uses a dis~ibuted arbitra~on æheme, whereby each module ~ontending Ior bus access has bus arbi~ ion logic. I~e bus arbi~ation lo~c comprises logic for determming t;lhe module's pnori1y, and ~or detelmining when the module is granted bus access based on the module's priority.
~e bus arbitration logic is capable of providing ~e~ble priontization æhemes. According to ~e present il:lvention, a n~mber of alterna~ve priontization schemes may be employed. Through these schemes, system ~ex:ibility and adapt~ are enhanced.
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Thus, arbitratioll according to the present i~vention, call be implemented using only a single bus arbi~ation line ~onnected to each module. This single bus arbi~ation line is used to indicate whether another module has already been granted access to thc bus during ~he S next bus c~c~e.
Sample Envi~onment The present inven~on was developed ~or use in a computer system that functions as a network packet switc~. lFIG. 1 is a block diagram illustra~ng a computer sys~m configured as a neh~vorlc packet switch 100 10 and its typical inter~aces. Re~ening to FIG. 1, the sample environment will now be desclibed. A network packet switch 100 o tlhe sample environment mcludes two separate busses. A Virtual Packet Bus 102 (referred to as VPB lûV is a high speed, Virtual ~ynchrollous l~ans~er Mode (VA~) bus ac~ording to the present inve~tion. A standard ~/llF.
15 bus lW, ~or handling local, low speed status and control info~rma~oll, îs also provided.
T-1 frame relay modules 106 accept up to four T 1 ~ame ~elay channels, and packetize the data from ~ese channels into AThlI
(A~ynchronous Transfer Mode) packets. Trunlc interl~ce modules 108 20 accept ATM pac}cets from VPP~ 102. nunlc interface modules interface the ATM pacl~ets ~nth standard T-3 or SONET fo~mats for transport Processor modules 110 provide network element management and interface to an external ethe~net network 114. External ethernet network 114 provides the node ~nth a network management interface. A dual 25 redundant power supply module lL12 pro~ides system power.
~ e ~lnction of networlc packet switch 100 is to receive data packets origina~ng with users of networ3k data services such as Frame lRelay Selvice and Switched Multi-megabit Data Sen~ice (S~fDS), and , - , .. .. . . . . . . .. .. . . . .
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route these data packets to other ne~work nodes in accordance with the address of the packets. Additionally, ne1:work packet switch 100 ~eoeives data packets f~om other nodes addressed to the location of the packet switch. VPB 102, which is the subject of this i~v~n1ion, provides tdhe 5 inte~al communica~on path for the dat~ packets betwee3l user access modules such as ~e T~ e relay module m6 and mter-llodal communica~ons links, ¢ommon~ called trumks, such as ~unk inter~ace modules 108. Packets ongina1ing at a user inter3~ce ~n one of a mul~plicity of ~ame ~elay moslules 106 may be routesl over ~he 1bus to a:~y 10 one of the trunk modules 108 or to other local users through frame ~elay modules 106.
3. l[he Bus FIG 2A illusbrates VPB 102 according to ~e present LDvelltion.
3Refer~ing to FIG. 2, VPB 102 comprises a data bus 202~ a co~non bus arbitra'don line 204 aIId a bus packet ( 13UP) clock line 206. III a prefe~ed ~mbodiment, VPB 102 is a backplane bus to which a plurality of modules 208 a~e in~r~aced. Modules 208 call be circuit cards tha~ are pluggesl in~o backplane VPB 102using car~-edge comlectors. Modules 208 can include modllles such as processor module 110, and trunk interf~ee module 108, 20 as discussed in the Sample Enviromment Subsec1ion of this application.
In a preferred embodiment, data bus 202 is 64 bits wide (i.e., N is 64). This width malces VPB 102 compa~ble with a 53 octect packet standard and still allows additional bits for other system ~n¢tions. ~he preferred embodiment of the virtual packet bus uses 53 octet AXM:
25 packets. With a 64 bit wide data bus, seven (7~ bus transfers are required i~or each packet leaving 3 octets available as extra bits (7 bus traIIsfers -8 octets per transfer - 53 octets). These additional bits may be used for a variety of purposes such as carrying error correcting parity information ' .: . : ' ' . . .
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~1~37~
to detect packet errors, to carry stabus in~olm a~on alld so for~h. Other embodiments ~re contemplaLed wherein data bus 20Z is o~ a width other than 64 bits.
A unique feature of ~P~ 1027 according to the present inveD~ion, S is that it allows data ~ansfer in groups of words (packets). A packet is de~ined as haviRg a length of M words. In a preferred em bodirnen~ the packetlength is sev~n words (i.e~ M is 73. To handle da~a t~anser in units ofpack~ thelength of~he bus cycle ~ def~led to c~ve~the packet length. Thus, ~rPB 102, aoc3rd mg to the presentinven~on~ uses a packet 10 t~ning concept to def~le the bus cycle~
FIG. ~B i~ustrates the packetb~ning concept of ~PB 102 according to the present invention. Referrmg to ~IGs~ 2A and 2B, the packet timing concept will now be described. BUP clock line 206 provides ;a BUP clock signal 2~6 to all modules 208 on VPB bus 102. BUP cla~k signal 226 te[nporally par~tio~s VPB 102 into bus ~rcle periodæ These bus c3rcle periods are called BUP time slot~. BUP clock signal 226 is a ~IIliDg pulse that marks the s~ f each BlUP ~e slo~ 'rhe leng~ of tlle BUP ~me s1~t L is sufficient to handle ~e bus packet len~ M. 13us packet length L is the lnin~um data transer ~ne UII;t of 'VPlB 102. All 20 packet t~ansfers on VPB 102 are made within the B~ ~me slot as defined by BIJP elock signal æ6.
Thus, in a preferred embodiment where M = 7, bus packet leDgth L is chosen such ~at seven N-bit bus words 228 can be tra~sferred within ~hat time. I~us, data bus 202 can be defined in terms of a width of N bits 25 and periods of length defined by the bus packet length L.
. .
- . . .
.... .
:. . . : -, ' . - ' ' ~
2~ ~37~0 4 Bus ~lbibration According to ~e present invention, bus arbitration is handled on a distlibuted basi~s. Each module on the bus is provided ~w~th arbitration CilCUitly to dctemline dunng 1he current BUP time slot whe1her its S module can access the bus durillg the next 13UP time slot. Arbitration circuit~y includes logical elements for determining the current module priority, and for dete~ g wh~er ~us access will be allowed based on ~at priority. CircuitIy is also provided for updating the module pIiori~y.
Arbitration circuitly is p~ovided with BUP clock 226 andl with an access time clock.
During the current BUP time slot~ the arbitration circuitly be~s counting pulses of the a~xess ~me clock signal. I~e arbitration circuitly compares the c~unted value to ~e current module priority. When ~e counted value equals 'lhe module priori1y, the modulé will be granted access to the bus during the ne~t B~JP time slot if two conditions are met.
The two eonditions are: (i) the module must be requesting a~ess; and (ii) the bus lllllSt not alrea~y ha~e been claimed by a module with a higher priority. When a module is granted access to the bus, that module pulls the arbibation line low until ~e current BUP time slot has e~pired.
2a When the ar~ ation line is low, no other module will be granted access for the next BUP ~me slot.
FIG. 3 ;s a schematic diagram illust~a~ng the arbitration circuitIy according to the present invention. Referring to FIG. 3, a bus arbiter 300 is interfaced to common bus arbitration line 204, to arl access 1ime clock 308, and to BUP clock sigDal 226.
Bus arbiter 300 comprises seveTal logic components. ~ese components will now be described. Bus arbiter 300 includes a state machine 3V2. State machine 302 is used to indicate the priori~r of the module in the digital fonn. Bus arbiteT 300 also include(s a counter 304 - . - . . .
' ,. ,,, ~ .
- .
.
':: .
, ~10378~
and a comparator 306. Counter 304 counts edges of access time clock 308. In a preferred embodiment, counter 304 begins at an initial value, increments its value on each posit~ve transition of access time clock signal 308, and ~e counter value is ou~ut as a counter value signal 354.
Counter 304 is reset lo its initial value by BIJP dcsclc signal æ6.
Alternative embodiments may be considered where:in counter 304 deerements as opposed to increments, ~nd where counter 304 responds to nega~ve ~ansitions.
Comparator 306 compares ~e pnori1y o~ the module as indicated by s1~te machine 302 against couDter value sig~al 354.
A bufler 310 is used to monitor arbitration line 204 to dete~ e if access to t~e bus is still available for the ne~t BVl:' time slot. If arbitra'don line 20~ is high, the bus is s~ll available for ~e ne~t BUP ~e slot. If, however, arbitration line 204 is low, anoffler module has already 15 claimed the bus ~or the next ~me xlot.
A flip ~op 314 is set when counter 3M ~eaches ~e module's prion1~r as indic~ted by state machine 302 if ~e bus is still available at the ne~t BUP time slo~ When flip llop 314 is set and the module is reques~ng Ibus access f~r the next BUP 1ime slot, a transistor 316 is 21) turned on. When transistor 316 is turned on, arbitration line 204 is pulledIow, thus disabling other modules from a~ssing the bus on ~e next BUP
time slot:
State machine 302 is loaded with an mitial value, indicating the initial pnority of the module, via an initial value signal 366. The priority 25 value o the module can be updated ~or each BIJP ~e slot by an update signal 368. . --FIGs. ~ and 4B comrpise a flow chart illustra~ing the operationof bus arbiter 300 according to 1he present intrention. FIG. S is a timing diagram illustrating the temporal relationships among lhe various signals 2~Q378~
of bus arbi~er 300 of the present invelltis)n. I~e~erring to FIGs. 3, 4A and 1~, and 5, the operation of bus arbiter 300 wiII now be described. The operation of bus arbiter 300 of a sample module will be described with respect to events occu~Ting in bus arbiters 300 of other .modules. Bus arbiter 300 for each raodule operates in a similar fashion~
In a step 402, at a time ~ = 0, a BUP ~lock pulse 502 of BUP clock signal 2~6 marks ~e beginnLng of a current BIJP time slot. The ~me duling this current BUP time slot will be used to detelm~ne which module will Ibe ~nted access to ~e bus dur~ng the uext BIJP time slot The next BUP 1ime slot beg~ns at a time ~ = 2. ~dditionally, BUP clock pulse 502 rese~ counter 304 to an initial value, and resets ilip flop 314. In addition, BIJP clock pulse 502 sets state machine 302 to an initial pnorit~ value as determined by initial value signal 366 or to an updated priority value as detennined by update signal 368.
In a step 404, counter 304 be~s coun~ng pulses 504 of access ~dme clock 308. Access time clock 308 ~uns at a rate higher ~an BUP
cloc~c 226. Thus, counter 304 essentially ~vides each BI~P time slot into a distinct number of shorter ~me slots as illustrated in FIG. 5. The leng~h o~ these time slots is dei ined by ~e period of access ~e ~lock 308. For example, if aocess ~me cloclc 308 is 16 times higher in rate than BIJP
clock 226, counter 304 will increr~ent (or decrement) 16 ~mes within the BUP ~me slot. Thus, in this example, counter 304 will divide the Bl[JP
time slot into 16 segments.
Counter 304 begins cc)unting pulses 504 of access time clock 308 :Irom its ini~al value, and outputs eo~mter value signal 354 $o comparator 306. Counter 304 continues colmting pulses 504 until the next BUP clock pulse 502 rese$s counter 304 to its initial value. Once reset, coun$er 304 begins anew, counting f~om its initial value. In a preferred embodiment, counter value signal 354 is in the forrn of a digital word. l~e width of the . .. : : . . : : - , - - , ' . ~
2 L 0 3 7 8 ~
word is chosen to accommodate the ma~mum value reached by counter 304. This maximum value may be dehned by ~e ratio of access time clock ~equency 308 to BUP clock 226 freque3lcy.
State machine 302 indicates the pno~r of the module continuously S throughout the BUP ~me slot period. Sta~e machille Qll'qpUtS a module p riori~y value si~nal 352 (referred to as time aecess, state 352) to comparator 306. E~ach module Oll the bus has a unique tiime access state 352 at any given BUP ~me slot. In a preferred embodmlent, the module 1ime aocess state 352 is indicated in the ~olm of a digital wor~ ~e w~dth 10 o l~is digital word is chosen to be wide eIIough to allow a ~nique time access state 352 to be represented ~or each module.
As c~unter 304 i5 counting pulses 504, comparator 306 is compaling counter value signal 354 to time access state 352 as indicated by state machine 30æ
In a step 406, when counter value signal 354 is equal to time access state 352 (ie. ~e priority value), comparator 306 sends a comparison time pulse 506 over a comparator ou~ut signal pa~dh 356. Compariss~ ~ne puJse 506 indicates that the module's time aocess state 352 has been ~eached 7by counter 304. The ~Irrence of ~is ~vent is denoted by a 20 ~e ~ = 1 in FIG. 5.
If, as in the e~ample above, access ~me clock 308 divides the BUP
~me slot into 16 segments, 16 dis~nct counts are produced by counter 304 in one BUP time slot. Thus, in this example, ~6 modules can have unique ~dme access states 352. Each of these unique ~me access states 352 ~5 defines a unique time access window in a BIJP time slo~
In a step 408, if another module.having a higher priority tha~ the subject module has requested access to the bus ~or the next BUP ~ime slot, arbitration line 204 will already be at a low state (to be described), and the arbitration process is complete. The subject module is Ilot 2l037~a granted access for the next time slo~ ~he arbi~a1ioII process will begin again at step 402 with the next BUP clock pulse 502 of 13UP cloek 226.
If, on the other hand, the bus is s~ll availalble for the next BUP ~ime slot, bus arbiter 300 con~nues the process at a step 410. Step 408 is discussed S in greater detail below.
In step 410, compalison time pulse 506 is input to i~lip ~op 314 at an i~nput port S. Companson time pulse 506 sets an ou~ut port Q of filip 91Op 314 high. This results in a iaip iElop output signal 360 ~ansitioning to a ~igh state.
In a step 412, if ~e module is not requesting access to ~e bus for ~e ne~t arbit~tion period, a bus request signal 362 is low and ~e arbi~ation process for fflis module is IEi~shed. ~bitration will begin a~un at step 402 with the ne~t BUP cloclc pulse 502 of BIJP clock æ6.
l[f, however~ the module is reques~dng access to thê bus ~or ~he next 1~ a~bitration period, the module asserts a high bus reqllest signal 362. In a step 414, the high ilip ilop ou13put signal 360 and ~he high bus request signal 362 mput to an AND gate 320 cause bu5 available signa1364 to hansition to high. When bus availab1e signal 364 is high, ~ansistor 316 tun~s on. The oollector of transistor 316 is connected to bus arbitration 20 Line 204 and the source is coD~ected to ground. Bus arbitration line ~04 is kept lhigh ~nth a pull-up ~esistor 3æ to Vcc. 'rhus, when transistor 316 is tu~ned Oll by a bus available signal 364 at its base, bus arbitration line ~04 is pulled to ground. When bus arbitration lline 204 is low, no other module will be granted access to the bus.
2S In addition, bus available signal 364 indicates to ~e module that the module has lbeen granted access to the bus for the next BUP ~me slot.
he preferred embodiment transistor 316 is a bipolar kansistor.
- As will be clear to one of ordinary slcill in the art, any l~rpe of electric~l switching device which is sufficiently ~ast can perform the same function 2~Q37~9 as t~ansistor 316. Altel~ative switching devices include MOS field eflEect ~ansistor devices or stalldard logic gates capable of pulling the arbillation line to gro-md.
Ln a step 416, at a time ~ = 2, the module granted ;access se.nds its 5 paclcet across the bus. At this time th~ arbitration process begins again at s~ep 402. Pulse 502 of BIJP clock æ6 rese~s counter 30~ to its initial value, updates (or, alternatively, resets) the priori1y of stalte ma~hine 302 and ~esets flip ~lop 314. Wllen ~ip flop 314 is reset, illip iElop output signal360 is set low. This causes bus available signal 364 to go low, turning off t~sis~or 316. With ~ansistor 316 o~, bus arbitra~on line 204 is 3pulled high by pull-up resistor 3æ.
As discussed above in step 408, the subject module will not be granted access to the bus unless no other higher priori~ modules a~e reques~ng access. The mamler in which this detelmina'don is made will now be descnlbed in more detail. Counter 304 ~or each module counts pulses 504 of aocess time clock 308. In aII example embodiment, counter 304 YS impleme~ted as an up counter and begins its co~m~ from an ini~al value of zero. I~hus a module wi~ a lower ~e access state 352 will gene~ate its comparison time pulse 506 before a module with a ~igher time access state 352. The fi~ module to generate comparison time pulse 505 and re~uest the bus wi~ a high bus request signal 362 will pull aTbit~at;on line 204 low as discllssed a~ove. Ac~ss will be granted to ~at moduie for ~e next ~BIJP time slot. Therefore, aocess to all other modules must be disallowed.
Once a module has pulled arbitration line 204 low, a buffer 310 on each bus arbiter 300 asserts a low bus bllsy signal 358 to an input to an AND gate 318. This low bus busy signal 358 inhibits comparison time pulse 506 from setting flip flop 314. Thus, once a module pulls arbitration line 2~ lowg no other module may set its flip flop output ;,' ~ ' ~
' . . . .
.
, 2~0~
signal 360 high, gencrate a high bus available signal 3S4, and access the bus ~or the next BUP ~me slo~
~ dditional embodiments caII be conceived as encomp~ssing a]te~na1~ve implemen~tions of bus arbiter 300. ~or e~ample, ~lip f lop 314 5 could be a JK flip fl~p clocked by comparison ~dme pulse 506. The input in ~is embodimeIIt would be bus request sig;nal 362. T~us when bus ~equest signal 362 is high and companson ~ne pulse 5()S occurs~ the Q ou~ut is a high signal. The JK tip fl~ would still be reset by BUP
clock æ6.
An addi'donal alte~native embodiment for bus arlbiter 30S) can be nnplemented by replacing counter 3M with a st~te ma~hine and elhnina~ng state machine 302. FIG. 6 is a diagram illustra~g this altemative embodiment of bus arbiter 300. l~efe~g to FI~. 6, a lmodule access number 652 is hardwired into Gomparator 306. Module access number 652 is unique for each module. Each module initializes a state machine 602 wi~ a unique initiali~on ~iralue 656. Pulses of aocess time clock: 308 ~loclc state machine 602 A~ each pulse ~ access ~dme cloclc 308, state machine output 654 increments. Comparator 306 compares state ma~hine output 654 with module access number 652. When ~e ~umbers aglree, a c~mpalison time pulse 506 is ~generated. Compa~ison time.pulse S06 is used to pull bus arbitration line 204 low as in the pre:~erred embodimen~ A pulse 502 of BU~ clock signal æ6 increments the state machine to a new state at the begimling of each new BUP time slo~
l~eferring again to FIG. 3, another alternative embodiment may be considered wherein bus busy signal 358.is routed directly to counter 304 (instead of to AND ga$e 318 as ilustrated). In this embodiment, cc~unter 3~ is inhibited from coun~ng whe~ bus busy signal 358 is low. Thus, AND gate 318 is not required.
, :: . . . ..
.
.. .
, . ' ,: , :
2~37~ 3 In still another alternative embodiment of bus arbiter 300, bus request signal 362 is input to AND gate 31~ thus enabling or inhibiting bus access without the need for AND gate 320.
These a}terna~ve embodmlents se~ve as e~amples of ~e l~umerous 5 ~unctionally equivalent embodiments of the bus arbi~-a~oll çircuit~y according to the present ~ven~on.
5. Prioritiza~on Tec~niques - Blls arbitra~on aocording to ~e presellt invention pro~qdes ~e~ility in assigning and updating module prionty. Nlmlerous 10 prioritization techniques are contemplated whereill module prio rities are determined. Different prioritization schemes can be impl~mented Ibased on the requirements o~ the compute~ system, thus op~mizing system pe~formance. E~amples of such prioritization techniques are ou~ned in ~e text ~at ~EO11GWS.
]?.efening a~ to PIG. 3, as previous~y mentiolled, ~he priori1~r of a module is controlled by state machine 3~2. State machine 302 out~uts a time access state 352 indicating the 3module pnori~y. In its simplest configuratioll, s~te maclline 30~ is a gï~ed, hard-wired number. In ~his ¢onfiguTation, eaeh module is assigDed al uniqlle, fixed pri~rity number 20 (tdme a~cess state 352,). ~e priority may be assigned according to a number of diflerent strategies. For e~ample, the priorily llumber ~Eor each module may be assigned according to the location of the module on the bus.
In a preferred embodiine~, state machine 302 is implemented in 25 such a manner that it is updated at each BUP clock pulse 50~. This allows the priori~ of each module to be altered ~or each BIJP ~ne slo~
State mach~es 302 in all modu~es must be synchroni~ed and be identical such that time access state 352 is unique for each module.
.
2 L a 3rl,'30 A variety of priori~ schemes for determining module pnority at each BUP cloclc pulse 502 can be implemented. llmplementation o~ ~ese var~ous schemes is accomplished by changing the mamler in which state machine 302 is imple~ented. ~s an e~ample, a simple prio~ty scheme S c~ be impl~men~d by using a modulo-N counter as st~te machine 302.
In this scheme, ~e modulo-N count~r is initialized with 1~he module lllumber. Ini~aliza'don takes place by sendi~ an ini~alization signal 36fi to s~te machine 302. Once initialized, all modules' modulo-N counters are decremented at each BUP slot by BUP clock pulse 50æ Thus after 10 each BUP t~me slot each module's p~ori~y is incre~sed by ~lle. If a module requests the bus and acquires it du~g one ~3UP ~me slot, the module time aocess wDldow 352 is moved one access ~me later when BUP
clock pulse 502 decrements the modul~N counter. I~e module ~hat had ~he lowest pnority 1ime acces~s st~te is moved to the highest pliori1y and 15 all other modules decrease in pl~ority.
Alternat~vely, a "round robin" scheme can be implemented by mo~ring the access state of ~e module acquinng the VPB to ~e lc~west pnori~y (last time access) and incrementing the prion~y o~ all modules which had a lower p~iori~r. In this case, any module wi~ an access state 2S) later ~an ~e module acquiling ~e bus woulld increment ~eir states, those with higher pliori'des would remain în the curren~ state, and the most recent bus ~lær would move to the last access time. I~e update line to the state machine would control the state machine.
A pseudo random sequence (PRS~ generator cc)uld also be used to 25 generate th¢ access time state. If all modules have identical PRS
generators and each module ini~ializes ~-e generator with a unique state, such as it's module nun~ber, then all PRS generators are incremented at each BUP slot, giving all modules ~he same long telm average bus priority. The state machine can be any machine which produces a ullique .
` ` ' ' : ` ' :
.
:. , ' state for each module and which can be synchronized by the irlitialization.
This can include table lookup methods.
6. E~Ltensioll of ~e Module Ca~
~ccording to the arbitration technique ~s described above, ~e S number of modules which can contelld or bus access is 31imited by the ratio of ~e access ~me clock to ~e BUP clock. III ot3her words, tlhe number of modules which can contend ~or bus access is limitecl to the nu:mber of access 1ime windows which can be created within one lbus ~ne slot From an imple[nentation perspective, itis desirable to minimize the ratio of the access time clock to the BUP ~dme clock. I~is however has the effect of limiting the number of modules w3hich can be configured ~n the s3~stem.
This limitation can be overcome by implementing modules in 15 grollps of modules. ~ this implementation, a single arbi~ation line is provided for each group of modules. ~he ar~i~ration lines a~e used to detelmine group priori~r as w~ll as individll~l module priori~y.
FIG 7 illustrates two modules, one module for each of two groups l~e concept of group priori~y will be described wi~ two groups of 20 modules. It will be obvious to one of ordinaly skill in ~e alt how this concept can be expanded to any number of groups of modules. ~Refernng to FIG. 7, a module A1 is illustrated as belonging to a group,~4.
module B1 is illustra~ng as belonging to a group B. ~o arbitralion li~es 704A, 704B, are interf aced to all of ~he modules in group A and in group 25 B. Only one module is shown in each group for simplici~.
Each module inclu~es group priority logic 702. Group priori~
logic 702 is used to resolve bus contention conflicts among the groups.
~037~0 - 2~ -A p:riority si~nal 732 is input into group priori~r l<)gic 702. Priority signal 732 indicates the pliori~y of the group. Each group has a unique priority value represented by priority sigllal 73æ
All modules in group B cc)ntend for a~s ~o ~e bus in a mallmer S as described in the preferred embodiments above. Assuming group B has the highest prio~i1y, once a module in group B is granted access to the bus, arbitration line 704B is pulled low by transistor 706. Once albi~a~o line 704 B is pulled low, a low signal is recenred by a bufEer 708A in group A, and this low signal is input to group priori1y logic 702A at an input Q.
This low sigllal at input Q of group plion~r logic 702A has the eiiEect of disabling a module in group A from tuming ()n ~ansistor 706A and pulling arbitration line 704~ low.
~ccording to the arbitration technique ~s described above, ~e S number of modules which can contelld or bus access is 31imited by the ratio of ~e access ~me clock to ~e BUP clock. III ot3her words, tlhe number of modules which can contend ~or bus access is limitecl to the nu:mber of access 1ime windows which can be created within one lbus ~ne slot From an imple[nentation perspective, itis desirable to minimize the ratio of the access time clock to the BUP ~dme clock. I~is however has the effect of limiting the number of modules w3hich can be configured ~n the s3~stem.
This limitation can be overcome by implementing modules in 15 grollps of modules. ~ this implementation, a single arbi~ation line is provided for each group of modules. ~he ar~i~ration lines a~e used to detelmine group priori~r as w~ll as individll~l module priori~y.
FIG 7 illustrates two modules, one module for each of two groups l~e concept of group priori~y will be described wi~ two groups of 20 modules. It will be obvious to one of ordinaly skill in ~e alt how this concept can be expanded to any number of groups of modules. ~Refernng to FIG. 7, a module A1 is illustrated as belonging to a group,~4.
module B1 is illustra~ng as belonging to a group B. ~o arbitralion li~es 704A, 704B, are interf aced to all of ~he modules in group A and in group 25 B. Only one module is shown in each group for simplici~.
Each module inclu~es group priority logic 702. Group priori~
logic 702 is used to resolve bus contention conflicts among the groups.
~037~0 - 2~ -A p:riority si~nal 732 is input into group priori~r l<)gic 702. Priority signal 732 indicates the pliori~y of the group. Each group has a unique priority value represented by priority sigllal 73æ
All modules in group B cc)ntend for a~s ~o ~e bus in a mallmer S as described in the preferred embodiments above. Assuming group B has the highest prio~i1y, once a module in group B is granted access to the bus, arbitration line 704B is pulled low by transistor 706. Once albi~a~o line 704 B is pulled low, a low signal is recenred by a bufEer 708A in group A, and this low signal is input to group priori1y logic 702A at an input Q.
This low sigllal at input Q of group plion~r logic 702A has the eiiEect of disabling a module in group A from tuming ()n ~ansistor 706A and pulling arbitration line 704~ low.
7. Opelation at ~lGgh Speeds The sp~ o~the arbi~ation line is a key~ctorin ~he overall speed of ~e virtual packet bus according to ~e present invention. The arbitra~on line can be implemellted using an optical fiber to increase band~dth. FIG. 8 illustrates an implelmenta1ion of an arbitration line using an optical 3 iber. Refer~ g to PIG. 8, the optical :~e~
implementation will now be described. Albitration line 802 is :20 implemented using an optical fiber. T~e optical fiber can be implemented as an incoherent optical fiber or simply, as an optical light pipe. The optical fil~er arbi~ation line 802 is connected to ~e arbitration circuit using an op1ical coupler 804. A photodiode (Light Emiffing Diode, LED) 808 transforms electrical cuITent into an optical signal 810. Optical signal 810 is coupled onto arbitration line 802 by optical coupler 804. Thus when transistor 316 is turned on by a high bus available signal 364 (as in the above-described embodiment), curreDt fl~ws through LED ~08. ~e resultant light rom L~D 808 is coupled onto arbitration line 802. Hence, . . . . .
.,',. ': . , ' ~ ~ ' .
.
:. , .~ .
2~ ~37~
when a module is granted access for the next BIJP time slot, light is present on arbitration lille 802.
A photodiode 812 receives optical energy ~om optical coupler ~04.
The absence of light on arbitlation line 802 causes current in photodiode 5 81~ to decrease to a level known as ~e dark current level. At the darlc current le~el, current ~om Vcc cannot be passed ~ ground, and a logic high is presented at the input o~ buffer 310.
If, on ~he other hand, light is present on arbitration line 802 photodiode 812 passes Vcc to ground, thereby presenting a low signal to 10 the input of buf~er 310.
implementation will now be described. Albitration line 802 is :20 implemented using an optical fiber. T~e optical fiber can be implemented as an incoherent optical fiber or simply, as an optical light pipe. The optical fil~er arbi~ation line 802 is connected to ~e arbitration circuit using an op1ical coupler 804. A photodiode (Light Emiffing Diode, LED) 808 transforms electrical cuITent into an optical signal 810. Optical signal 810 is coupled onto arbitration line 802 by optical coupler 804. Thus when transistor 316 is turned on by a high bus available signal 364 (as in the above-described embodiment), curreDt fl~ws through LED ~08. ~e resultant light rom L~D 808 is coupled onto arbitration line 802. Hence, . . . . .
.,',. ': . , ' ~ ~ ' .
.
:. , .~ .
2~ ~37~
when a module is granted access for the next BIJP time slot, light is present on arbitration lille 802.
A photodiode 812 receives optical energy ~om optical coupler ~04.
The absence of light on arbitlation line 802 causes current in photodiode 5 81~ to decrease to a level known as ~e dark current level. At the darlc current le~el, current ~om Vcc cannot be passed ~ ground, and a logic high is presented at the input o~ buffer 310.
If, on ~he other hand, light is present on arbitration line 802 photodiode 812 passes Vcc to ground, thereby presenting a low signal to 10 the input of buf~er 310.
8. Conciusion While va~ious embodiments of the present inven~on hav~ been descr~bed above, it should be Imderstood ~Lhat they have been presellted by way of example only, and not limita~don. Thus, ~e breadth and scope 15 ~ the prese~t invelltion should not be limited by ~y of ~e above-desc~bed e~:emplaly embodiments, bnt should be defined only in accoldance with the following claims and 'dheir equivalents.
Claims (19)
1. A computer bus for transferring data among a plurality of modules coupled thereto, comprising:
(a) a plurality of data lines coupled to each module operable to transfer bits of words;
(b) a single arbitration line coupled to each module;
(c) a bus packet (BUP) clock, coupled to each module;
operable to temporally divide the bus into cycle periods called BUP time slots;
(d) an access time clock, coupled to each module, operable to divide said BUP time slots into access time slots; and (e) an arbitration circuit for each module on the bus, coupled to said BUP clock, to said arbitration line, and to said access time clock, configured to arbitrate contention for the bus among the plurality of modules.
(a) a plurality of data lines coupled to each module operable to transfer bits of words;
(b) a single arbitration line coupled to each module;
(c) a bus packet (BUP) clock, coupled to each module;
operable to temporally divide the bus into cycle periods called BUP time slots;
(d) an access time clock, coupled to each module, operable to divide said BUP time slots into access time slots; and (e) an arbitration circuit for each module on the bus, coupled to said BUP clock, to said arbitration line, and to said access time clock, configured to arbitrate contention for the bus among the plurality of modules.
2. The computer bus of claim 1, wherein said BUP time slots are of a sufficient length of time such that a packet comprising a multiplicity of words can be transferred among modules during one said BUP time slot.
3. The computer bus of claim 1, wherein said arbitration circuit of each module comprises:
(1) a state machine having an input coupled to said BUP clock, and an output coupled to a comparator;
(2) said comparator having an input coupled to said state machine and an output coupled to a flip flop and configured to provide a comparison time pulse;
(3) said flip flop having a first input coupled to said comparator and responsive to a bus busy signal provided by said arbitration line, and an output to provide a bus available signal;
and (4) a transitor having a base coupled to said flip flop output, an emitter coupled to ground and a collector coupled to the arbitration line, operable to pull the arbitration line low when the module asserts said bus available signal;
(1) a state machine having an input coupled to said BUP clock, and an output coupled to a comparator;
(2) said comparator having an input coupled to said state machine and an output coupled to a flip flop and configured to provide a comparison time pulse;
(3) said flip flop having a first input coupled to said comparator and responsive to a bus busy signal provided by said arbitration line, and an output to provide a bus available signal;
and (4) a transitor having a base coupled to said flip flop output, an emitter coupled to ground and a collector coupled to the arbitration line, operable to pull the arbitration line low when the module asserts said bus available signal;
4. The computer bus of claim 3, wherein:
said arbitration circuit further comprises a counter having a first input coupled to said BUP clock, a second input coupled to said access time clock and an output coupled to said comparator, the counter configured to count pulses of said access time clock, reset on pulses of said BUP clock, and provide a counter value signal; and said state machine is configured to provide a priority value signal to said comparator.
said arbitration circuit further comprises a counter having a first input coupled to said BUP clock, a second input coupled to said access time clock and an output coupled to said comparator, the counter configured to count pulses of said access time clock, reset on pulses of said BUP clock, and provide a counter value signal; and said state machine is configured to provide a priority value signal to said comparator.
5. The computer bus of claim 4, wherein said arbitration circuit further comprises an AND gate coupled to said flip flop, responsive to a bus request signal and responsive to said output of said flip flop, to provide said bus available signal only when the module is requesting bus access
6. The computer bus of claim 4, wherein said comparator is coupled to said flip flop via an AND gate, and said AND gate has an input coupled to said arbitration line.
7. The computer bus of claim 3, further comprising a buffer coupled to said arbitration line configured to provide said bus busy signal.
8. The computer bus of claim 3, wherein said comparator further has an input configured to receive a module access number, and said state machine is configured to provide an incremented output, and wherein said state machine is further configured to receive an initialization value.
9. The computer bus of claim 8, wherein said arbitration circuit further comprises all AND gate coupled to said flip flop and to said transitor, responsive to a bus request signal and responsive to said output of said flip flop, to provide said bus available signal only when the module is requesting bus access.
10. The computer bus of claim 8, wherein said comparator is coupled to said flip flop via an AND gate, and said AND gate has an input coupled to said arbitration line.
11. The computer bus of claim 8, further comprising a pull-up resistor coupled between said arbitration line and Vcc1 configured to maintain said arbitration line at a high level unless said transistor is turned on.
12. The computer bus of claim 3, wherein said arbitration line is a fiber optic cable, and said arbitration circuit further comprises:
(5) a first photodiode coupled between Vcc and said transistor, configured to emit light when said transistor is turned on by said bus available signal;
(6) a second photodiode coupled between Vcc and ground, configured to provide a low bus busy signal when said second photodiode is turned on by light on the fiber optic arbitration line; and (7) optical couplers for coupling light from said first photodiode into the fiber optic arbitration line, and for coupling light out of the fiber optic arbitration line to said second photodiode.
(5) a first photodiode coupled between Vcc and said transistor, configured to emit light when said transistor is turned on by said bus available signal;
(6) a second photodiode coupled between Vcc and ground, configured to provide a low bus busy signal when said second photodiode is turned on by light on the fiber optic arbitration line; and (7) optical couplers for coupling light from said first photodiode into the fiber optic arbitration line, and for coupling light out of the fiber optic arbitration line to said second photodiode.
13. The computer bus of claim 1, further comprising a plurality of arbitration lines coupled to each of the modules, to provide arbitration among groups of modules, and wherein said arbitration circuit further comprises group arbitration logic coupled to at least one of said arbitration lines.
14. A method for arbitrating contention among a plurality of modules, for a computer bus having an arbitration line, comprising the steps of:
(1) temporally dividing the bus into bus cycles blown as a BUP
time slot, wherein the length of said BUP time slot is defined using a BUP clock;
(2) further dividing said BUP time slot into a plurality of access time slots using an access time clock, wherein the frequency of said access time clock is a multiple of the frequency of said BUP clock;
(3) for each module, comparing a priority value of the module with a value representing the number of access time slots the have occurred;
(4) providing a comparison time pulse when said priority value is equal to said value representing the number of access time slots that have occurred;
(5) providing a bus available signal based on said computer time pulse, bus availability, and a bus request signal, and (6) pulling the arbitration line low using said bus available signal.
(1) temporally dividing the bus into bus cycles blown as a BUP
time slot, wherein the length of said BUP time slot is defined using a BUP clock;
(2) further dividing said BUP time slot into a plurality of access time slots using an access time clock, wherein the frequency of said access time clock is a multiple of the frequency of said BUP clock;
(3) for each module, comparing a priority value of the module with a value representing the number of access time slots the have occurred;
(4) providing a comparison time pulse when said priority value is equal to said value representing the number of access time slots that have occurred;
(5) providing a bus available signal based on said computer time pulse, bus availability, and a bus request signal, and (6) pulling the arbitration line low using said bus available signal.
15. The method of claim 14, further comprising the step of updating said priority value of each module at the beginning of said BUP time slot.
16. The method of claim 14, wherein said BUP time slot is of sufficient length to allow transfer of data in packets.
17. A computer bus for transferring data among a plurality of modules coupled thereto, comprising:
(a) a plurality of data lines coupled to each module operable to transfer bits of words;
(b) a single arbitration line coupled to each module;
(c) a bus packet (BUP) clock, coupled to each module;
operable to temporally divide the bus into cycle periods called BUP time slots;
(d) an access time clock, coupled to each module, operable to divide said BUP time slots into access time slots; and (e) means for arbitrating contention among the modules for access to the computer bus, coupled to said BUP clock, to said arbitration line, and to said access time clock.
(a) a plurality of data lines coupled to each module operable to transfer bits of words;
(b) a single arbitration line coupled to each module;
(c) a bus packet (BUP) clock, coupled to each module;
operable to temporally divide the bus into cycle periods called BUP time slots;
(d) an access time clock, coupled to each module, operable to divide said BUP time slots into access time slots; and (e) means for arbitrating contention among the modules for access to the computer bus, coupled to said BUP clock, to said arbitration line, and to said access time clock.
18. The computer bus of claim 17, wherein said means for arbitrating comprises:
(1) first means for counting pulses of said access time clock, and for providing a first signal representing the number of said pulses counted;
(2) second means for comparing said first signal with a number representing a priority of the module, and for providing a comparison time pulse;
(3) third means for providing a bus available signal, couple to said second means, and responsive to a bus busy signal, and responsive to said comparison time pulse; and (4) fourth means for pulling said arbitration line low, coupled to said third means, and coupled to said arbitration line, responsive to said bus available signal.
(1) first means for counting pulses of said access time clock, and for providing a first signal representing the number of said pulses counted;
(2) second means for comparing said first signal with a number representing a priority of the module, and for providing a comparison time pulse;
(3) third means for providing a bus available signal, couple to said second means, and responsive to a bus busy signal, and responsive to said comparison time pulse; and (4) fourth means for pulling said arbitration line low, coupled to said third means, and coupled to said arbitration line, responsive to said bus available signal.
19. The computer bus of claim 18 wherein said means for arbitrating further comprises fifth means for initializing and updating said module access number, coupled to said second means.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/929,445 | 1992-08-14 | ||
| US07/929,445 US5430848A (en) | 1992-08-14 | 1992-08-14 | Distributed arbitration with programmable priorities |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2103780A1 true CA2103780A1 (en) | 1994-02-15 |
Family
ID=25457872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002103780A Abandoned CA2103780A1 (en) | 1992-08-14 | 1993-08-10 | Virtual packet bus concept with distributed arbitration |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US5430848A (en) |
| JP (1) | JPH07295924A (en) |
| CA (1) | CA2103780A1 (en) |
| DE (1) | DE4326964A1 (en) |
| DK (1) | DK92893A (en) |
| FR (1) | FR2694828B1 (en) |
| GB (1) | GB2269728B (en) |
| SE (1) | SE9302626L (en) |
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-
1992
- 1992-08-14 US US07/929,445 patent/US5430848A/en not_active Expired - Fee Related
-
1993
- 1993-08-02 GB GB9315988A patent/GB2269728B/en not_active Expired - Fee Related
- 1993-08-10 CA CA002103780A patent/CA2103780A1/en not_active Abandoned
- 1993-08-11 DE DE4326964A patent/DE4326964A1/en not_active Withdrawn
- 1993-08-12 DK DK092893A patent/DK92893A/en not_active Application Discontinuation
- 1993-08-13 FR FR9309962A patent/FR2694828B1/en not_active Expired - Fee Related
- 1993-08-13 JP JP5201652A patent/JPH07295924A/en active Pending
- 1993-08-13 SE SE9302626A patent/SE9302626L/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| FR2694828A1 (en) | 1994-02-18 |
| DE4326964A1 (en) | 1994-02-17 |
| US5430848A (en) | 1995-07-04 |
| GB2269728A (en) | 1994-02-16 |
| GB2269728B (en) | 1996-06-12 |
| FR2694828B1 (en) | 1995-03-31 |
| SE9302626D0 (en) | 1993-08-13 |
| GB9315988D0 (en) | 1993-09-15 |
| DK92893A (en) | 1994-02-15 |
| DK92893D0 (en) | 1993-08-12 |
| SE9302626L (en) | 1994-02-15 |
| JPH07295924A (en) | 1995-11-10 |
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Legal Events
| Date | Code | Title | Description |
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| FZDE | Discontinued |