CA2104073A1 - Integrated single frame buffer memory for storing graphics and video data - Google Patents
Integrated single frame buffer memory for storing graphics and video dataInfo
- Publication number
- CA2104073A1 CA2104073A1 CA002104073A CA2104073A CA2104073A1 CA 2104073 A1 CA2104073 A1 CA 2104073A1 CA 002104073 A CA002104073 A CA 002104073A CA 2104073 A CA2104073 A CA 2104073A CA 2104073 A1 CA2104073 A1 CA 2104073A1
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- CA
- Canada
- Prior art keywords
- video
- graphics
- port
- data
- random access
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/393—Arrangements for updating the contents of the bit-mapped memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/12—Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
- G09G2340/125—Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels wherein one of the images is motion video
Abstract
An Integrated Single Frame Buffer Memory For Storing Graphics and Video Data ABSTRACT OF THE DISCLOSURE
The present invention provides an integrated display system for multi.-media workstations wherein graphics image and video data are merged in a single frame buffer.
The integrated display system employs 3-port VRAMs with a first serial access port for display data output, and a random access port for graphics data, a second serial access for video data input. The display system includes a single frame buffer memory system for a multi-media workstation which operates compatibly with display systems and logic designed for dual frame buffer systems and it uses the 3-port VRAM in combination with a means incorporating improved input locking, video update or refresh, and encoded video data input stream.
The present invention provides an integrated display system for multi.-media workstations wherein graphics image and video data are merged in a single frame buffer.
The integrated display system employs 3-port VRAMs with a first serial access port for display data output, and a random access port for graphics data, a second serial access for video data input. The display system includes a single frame buffer memory system for a multi-media workstation which operates compatibly with display systems and logic designed for dual frame buffer systems and it uses the 3-port VRAM in combination with a means incorporating improved input locking, video update or refresh, and encoded video data input stream.
Description
~ YO9-02-093 :1.
210~073 An Integrated ~ingle Frame Buffer Memory For Storing r~raphics an~l Video Data FIELD OF THE INVENTION:
The present invention relates to display devices, and more particularly to a multi-media workstation based display device wherein graphics data and video data are merged and stored in a single frame buffer memory BACKGROUND OF THE INVENTION:
In multi-media work station di~plays, it is known that two independent rasters, such as a standard TV video and high resolution computer generated graphics video may each be displayed on a high resolaltion graphics monitor by the use of dual frame buffers. A TV frame buffer includes a dual port VRAM, with the serial and random ports operating asynchronously. The primary port receives incoming TV video synchronously as it comes in, and the secondary port reads the TV video out synchronously with the high resollltion graphics monitor.
A high resolution frame buffer in a computer is utilized to store high resolution graphi.cs which is read out synchronously with the high resol.lltion graphics monitor.
A switching mechanism selects wh;ch of the TV video and the high resolution graphics video is to be displayed at a given time. The TV frame buffer includes an on screen and off screen portion. The computer provides computer data, including high resolution graphics data and audio data to the TV frame bt1ffer, w~th t.he graphics data being stored in the on screetl portion ~nd the audio data being stored in the off screetl portion. The audio data is read out to an audio circtlit for replay. The graphics data is combined with the TV vi.deo for p~lrposes of windowing.
Dual buffers of this type are costly on both space and production. Also, it i.s diffictllt to edit the merged graphics and video for separate frames.
:, ~ Y09-02-093 ~ 210~07~
s An example of a dual frame buffer display system is 3 described in U.S. Patent ~,994,9]~ issued February 19, s 1991 to Lumelsky et al. and entitled AUDIO VIDEO
INTERACTIVE DISPLAY.
;- In addition to dual frame buffers having cost and space and graphicæ/video data merger drawbacks, it is difficult to extend displays in dual frame buffer systems for higher spatial reso]altion or higher frame refresh rate and it is difficu]t to develop drivers for inconsistent buffer sizes, different data formats and the like.
There are several other previo~ls]y known approaches to combining video with high resoluti.on graphics. Some methods double the scan rate of the incoming video through the use of a ].ine buffer, reading out each video i line twice for each line of the high-resolution screen.
This method has several drawbacks. First, it assumes that the high-resolution display is exactly twice the scan rate of th incoming video. This is seldom the case, and always requires a gen-lock circuit at the very least to force this strict relationship between the video and the graphics. It also fails to provide random access to the video information from the host workstation, since there is no frame buffer to ,store the video information.
Another method involves convertinq -the video and graphics information into a common format ~nd storing the two into a single, common frame buffer. Wlli]e this may at first seem to be an advantage in that only one frame buffer is needed, this buffer require.q far more memory than having two separate dedicate~ bllffers. Tn the prior art, in ~ order to use a single frame buffer to store both types of i3 vlsual data, a very l~rge frame hllffer i~ required that ~ is both "wide" and "deep".
. .
i SUMMARY OF THE IMVENTION
.,.
It is an object of the present invention to provide an integrated display system for multi-media workstations ,.
!
~':
., ~
~ Y09-02-093 3 210~073 wherein graphics image and video data are merged in a ~ingle frame buffer.
Another object of the present invention is to provide an integrated display system for multi-media workstations which employs 3-port VRAMs with a first serial access port for display data o~ltput, a second serial access port for video data input, and a r~ndom access port for graphics data.
. :~
A further object of the present invention is to provide a '',--, single frame buffer memory system for a multi-media ~, ', workstation which operates compatibly with display systems and logic deæigned for dual frame buffer systems. ,,~,' A ~till further object of the present invention is to provide a ~ingle frame buffer memory system for a multi-media work~tation employing a 3-port VRAM
incorporating improved input locking, video update or ~ ~
refresh, and encoded video data inpllt stream. ~' ,-. ~-BRIEF D~SCRIPTION OF THE DRAWINGS
Fig. 1 is a schematic b]ock diagram illustrating logic and display elements for ~ typical multi-media workstation;
, ~
Fig. 2 is a schematic hlock diagram illustrating a dual frame buffer memory or separate]"y storing graphics and video data according to the prior art; ;;
Fig. 3 i~ a ~chematic hl.ock di~gram of a single frame buffer memory using ~-port VRAM~ with multiplexing according to the prior art;
Fig. 4 is a schematic block diagram illustrating an embodiment of single frame buffer memory using 3-port ~-VRAMs according to the pri,nci,ples of the present invention; ,~
~i YO9-02-093 4 Fig. 5 is a schematic block diagram ill-lstratlng a singlè
frame buffer memory u~ing 3-port VRAM~ for graphics, video and display data and 2-port VRAMs for control functions;
Fig. 6 is a schematic block diagr~m illustrating a data path for an implementation of an input locking eature ' incorporated in the present inventi,on; '~ ''' Eig. 7 is a schemati,c b]ock diagram illustrating an implementation of an i,nput lock;ng feature incorporated in the present inventioll;
Fig. 8 is a diagram used in exp],a,ining a typical memory access pattern of the present invention.
DESCRIPTION O~ THE PREFERRRD EMBODIMENT
The present invention i 9 incorporated into and provides an improvement to a multi-media workstation. In contrast to personal workætations, a multimedia workstation ~, consists of a processing unit, input devices, storage devices, and a display unit for visual output and other output devices. The multimedi,a data handled by workstations takes different forms including text, graphics, image, video, and speech via various input modes. When video is ;ntroduced into the workstations, the real time nature of the vi,deo data, and the mixing of video graphics data, e.g. graphi,cs overlay on video, scrolling text on video, etc. have to be considered. The video of a given frame size has to be displayed at the fixed input rate such a~ 24 or .~n frames per second. To achieve this, present,l,y known architecture uses two separate frame buffers, one for video and the other for graphics and mixes bot.h video signals at the output side using a technique called chroma-key,ing.
In Fig. 1, a schematic illu.stration of an IBM XGA
subsystem, typical disp]ay architecture for merging video into a graphics workstat;on is shown using separate frame .~ . ,.
:` YOg-02-093 5 2iO4073 buffers for video and graphi.cs data. To display live video in a window, a particular color (chroma-key color) is selected as the background color to paint the window in the graphics buffer 10. During display time, for each pixel location (screen locatlon), the pixel data is obtained from the VGA Graphics frame buffer lO via the Video Feature Bus, and compares the pixel data (in this case, color index) wit.h the chosen chroma-key color (color index). If they match, the pixel data from the Video buffer 12 is displayed; otherwise, the data from Graphics buffer lO is di.splayed. For a graphics overlay on the video in the window, the graphics data can be written on the graphics buffer lO using any color besides the chosen chroma-key backgroun~ co]or. The system of Fig. l has the drawbacks that i.t i.s difficult to extend displays for a higher spati.al resolution or a higher frame refresh rate, i.t is not an efficient hardware platform for programmer to edit the merged graphics and video data and it is cumbersome to develop drivers for inconsistent buffer sizes, different data formats, etc.
In Fig. 2, a typica]. prior art single frame buffer technique for displaying graphi.c and video data is shown wherein the random access port of the video random access memory (VRAM) is shared by mu]tiplexing the graphics and video data. In this technique the video input consumes fairly high input bandwi.dth available from the VRAM frame buffer. In a window.ing envi.ronment, this implementation could not guarantee the real time display of the video data. Also, the graphics perfoxmance wil]. suffer because of the sharing of the same VRAM access port by graphics and video.
The present lnvention overcomes ~he drawbacks of the use of dual frame buffers and the 11~e of a single frame buffer in systems of the prior art by providing an integrated single frame buffer system for multi-media work stations that employs a ~-port VRAM means for handling both graphic data and video data and which includes an improved locking mechanism feature, the use ~-;" Y09-02-093 6 210~073 of a refresh feature to allow video update to the frame buffer, and an encoded video data J nput stream.
Referring to Fig. 3, a multi-media video subsystem is illustrated including a processing unit 14 and a display unit 16 with disp]ay ~Init 16 also having an input from CPU 18. Comparing the processinq unit of Fig. 3 with the processing unit of the prior art 2-port VRAM system of Fig. 2 is it seen that they are the same. In fact, the basic distinction o the system of Fig. 3 is the VRAM is a 3-port device. In addition to the usual serial access port for display output, the 3-port VRAM 20 of Fig. 3 includes a second serial access port with masked register video input.
Triple port VRAMs are available in the art for use in -~
multi-media work stations. Such devices are manufactured and marketed by Micron Technology, Inc.
In the system illustrated in Fig. 4, structure for three improvement techniques are provided. The first technique is referred to as input locking. Referring to Fig. 6, a schematic illustration of a data path for the implementation of input locking is illustrated, and in Fig. 7 the implementation of the input lock bit mechanism of the present invention is operated as in output locking in a dual frame buffer approach for compatibility. ~-Chroma-keying has been traditionally used as in the art an output lock among multiple frame buffers, where one frame buffer (e.g. graphics) serves as keying or the master, while the other frame b~lffer~ (e.g. video(s)) are displayed as keyed or slaves. ~lltptlt ].ock as mentioned requires all slave frame buffers be synchronized pixel-by-pixel with the master one, in addition to a destination (or called transparent) color compare circuitry and a digital/analog multiplexer operating at -~
pixel rates. ;~;
~~ Yo9-02-093 7 21Q~07~
Input lock, on the other hand, req~lires only one frame buffer and one keying buffer. ~ll devices, including both master and slaves, must refer to the data on the keying buffer for writing the frame buffer. However, the master can also modify the data on the keying buffer.
The updating of the keying buffer can be made transparently, if implemented using a source color compare circuitry, and separate storages for frame buffer and keying buffer. Additional f~lnctions, such as area (window) editing, multiple window clipping, graphics/text overlay and/or scrolling over vid~o, can be incorporated if more keying buffer is used. To extend further, the keying buffer can be in line with ~ buffer, alpha buffer, window ID buffer, etc., as extensions of (pixel) frame buffer.
In Fig. 6, although the implementation is shown external to the graphics control]er, the ]ogic used can be incorporated within a graphics controller design.
In the implementation, two lock (or keying) bits per pixel are used. Two modes of operations are supported~
in-band and out-band. In an in-band mode, the input lock bits are set or reset resulting from a compare between the graphics pixel data and a transparent color (programmed ahead), as seen in chroma-keying. The compare operation is performed on the fly during each memory write operation to (pixel) frame huffer. As described, the keying buffers addressed transparently in an in-band mode. In an out-band mode, the input lock bits are set or reset by the programmed data sent via an I/O data port.
This mode of operation floes not llse any transparent color for comparison, but req~lires ~ sep~rate I/O operation.
By analogy with a cache memory implementation, this implementation caches addresses hy comparing the graphics controller's pixel d~ta, whi]e the cache memory implementation caches data by comparing the processor's addresses. More specif]cally, the tag memory is to cache memory as the input ]ock to frame huffer.
.. , . , . . . .. ~ . , . , ... . , . ~ . , " ... . . . .
~~ Y09-02-093 21~073 The access mechanism, transparen~ to user~, involves two aspects: the manip-llation of lock bits and the data integrity.
The manipulation of lock bitæ is based on chroma-keying.
The chroma-keying has been used in the dual frame buffer approaches, as previously discussed, to multiplex graphics and video data onto the screen. The existing approaches using chroma-keying as destination color compare have been classified and their drawbacks discussed. In the integrated frame buffer of the present invention, the source color compare for chroma-keying is used. The graphics data of an address being accessed is compared against a pre-programmed color code or index (chroma-key). The lock bit of the address is set to "1"
if they compare and "O", otherwise.
The implementation of the input locking technique to in~ure data integrity is an important aspect of the mechanism due to the sharing (or integration) of the frame buffer for both graphics and video data. The incon#istency can develop if the video controller refers to an out-of-date copy of lock bit. For example, the graphics controller update~ the lock bit with a non-transparent color, which will reset the associated lock bit to "O". In the mean while, the video controller has maintained a local copy of the lock bit, which was "1". The local copy i 6 maintained within the serial acce~s memory. What would then appear on the screen is video data, taking the place of graphics data just updated.
Since the video is transient data, the sy~tem provides that graphics data has priority over video data in case of inconsistency. As a part of access mechani~m, a detection circuitry of inconsistency has been incorporated. Once occllrred, the updating of video would be void. As depicted in Fig. 7, the system detects for each memory access of graphics data whether or not (1) its address falls in the same range to which the local ; ~ YO9-02-093 9 , copy of lock bits refers,2~Q ~)7 13ts data do not compare (or its associated ].ock bit i.s bei.ng updated to "0").
If both condition l and 2 are sati.sfied, the updating of video will be then voi.d. It should be noted that the information of current address range of lock bits (whose data has been ]cept locally by the video controller) is constantly updated and store i.n min-max registers, ~hown in Eig. 7 for comparators of high and low limits.
The use of the feature of the additional lock bit per pixel, functions such as multi-window clipping, and graphic~/text scrolling over video can be employed. In multi-window clipping, two video windows (A & B) can be incorporated, each window having i.ts own keying buffer, e.g.. bit 0 for window A and bi.t l for window B. The priorlty can be pre-determined and specified in the operation code, eg A ~ B, if opcode= "00l". So, when the window A is accessing the keyi.ng buffer with opcode=
"00l", the video pixel can address the pixel data buffer, if bit l, 0 = "l", "l", or "0", "l". On the other hand, the window B can only address the pixel frame buffer when bit l, 0 = "0","l".
In graphics/text scroll.i.ng over vi.deo (doubled buffering) the graphics/text scroJI. can be facilitated when both lock bits are u~ed alternative.ly for a window. Assuming that at the moment, bi.t 0(1) is used, containing locationc of graphics/text data and bit l(0) has been cleared. When it comes the time to scroll the graphic~/text, bit 1(0) wi].l be used at the next moment, while the bit 0(l) is bei.ng cleared.
Other functions, such as logical AND (shrink), OR
(expand), 0 (all disabled) and 1 (all disabled), can all be similarly implemented.
:
Another feature of the present invention is the use of ::
refresh logic to allow video update to the frame buffer. ~:
~"~ YO9-02-093 ~ n In using a three port video RAM (VRAM) the normal mode of operation of the video input is to serially #hift the video data into the serial port o~ the VRAM which results in writing data to the static memory portion. Once the static memory haæ been fi]led or a predefined boundary has been reached it is necessary to move the contents of the static memory into the dynamic memory. In order to accomplish this it is neceæsary to retain exclusive use of the dynamic memory for the period of time that it takes to move the data from the static to the dynamic memory and consequently from the dynamic to the static memory. This implies that there needs to be a mechanism in place which provides accesæ to the dynamic memory without interference. The device which controls the access to the VRAM ports is the graphic processor engine.
It controls the parallel port accesses for graphics updates and lt controlæ the serial port to the display unit for the display operation. If the graphic_ controller is designed to handle the video port it also controls the third fferial port for video updates as needed. However, most graphics processors are not de_igned for supporting a video data stream and therefore require another mechanism to allow video updates. In the ca_e that the graphics processor is designed to handle arbitration by other devices for access to the VRAM the problem can be solved by the arbitration mechanism. In thi_ ca_e the arbitrat;ng device, which handles video, can gain access to the VRAMs parallel port as well as the serial video port to allow it video updates. The problem that exlsts with the XGA graphics controller as well as many other graphics controllers is that they were deslgned in such a way that they assume exclusive ownership of the VRAM ~nd do not. provide either a video interface control nor an arbitration mechanism.
, , In the present invention, a technique is provided to allow video updates without interfering with normal ~-graphic# operations. A mechanism which can provide this capability is through the manip~llation of the refresh ~-interface between the qraphics processor and the VRAM.
' ` Y09-02-093 210~073 In the case of the I~M XGA graphics controller a refresh operation occurs once very 9.8 microseconds. It is necessary to refresh ~56 rows of the VRAM every 4 milliseconds, which means 'that ~ refresh has to occur every 15.6 microseconds. Due to the use in the page mode access of memory the TBM XGA controller provides more refreshes than necessary to maintain valid data in the VRAM. That is, it provides up to 408 refreshes every 4 milliseconds where only 256 are requlred, leaving up to 152 extra refresheæ that are not necessary. As a result it is possible to steal, some of the extra refresh cycles from the graphics processor and uge them for updating the incoming video. This can be accomplished as long as there are fewer refresh cycles stolen than are necessary to maintain the VRAM. ~or the case of video updates it is necessary to steal ~ne refresh cycle for every line update. In the worst case scenario there are up to 768 lines of video that C~tl be displayed. Assuming that the video rate is no more than 30 frames per second, this works out to be approx,imately 103 stolen refresh cycles every 4 milliseconds. This sti]l leaves an excess of 49 refresh cycles every 4 milliseconds which ensures that the VRAM has a sufficient number of refresh cycles.
The stealing of the refresh cycl~s is accomplished by channelling the VRAM control signals, generated by the graphics processor, through some h,igh speed logic on the card. The purpose of -this hi,gh speed logic is to detect a refresh operation generated by the graphics processor and if there is a penAing l,lpd~t~ request by the video controller, to block the refresh ~peration and generate a video update operati,on tn its place. If there is no pending request rom ~,he v,ide~ controller, then all refresh operations are simp]y passed through this logic without interference. Tn addition, all normal read and write operations generated by the qraphics processor are always passed through regardle~s of pending video request. The detection of refresh operations in the case of the XGA graphics controller is accomplished by simply detecting a Column Address Strobe (CAS) occurring before ` Y09-02-093 :1~
2i0~073 a Row Address Strobe (RAS). This i.s one standard way of refreshing the dynamic memory wi.thin the VRAM chip. This mode of refresh has the advantage that the refresh counter on the VRAM i.s used and an external refresh need not be generated. If a refresh operation is blocked by the external logic, then the counter i8 simply not incremented until a legi.timate refresh operation occur#.
This i8 advantageous s;.nce it does not require any additional hardware to keep the refresh address count so that no addresses are i.nadvertent].y skipped. In the case that a refresh operation is blocked due to a pending update request, a block write operation is executed in its place. The RAS or CAS addresses for the write operation are generated by the external logic and placed on the address bus. The control. logic to the VRAM is regenerated with some delay. It is important that the delay through the external ci.rcultry is minimized in order not to exceed the timing requirements to the VRAM.
In some cases, as with the IBM XGA or the TI 34-020 graphics controllers, the refresh timing parameters can be programmed. If this is the case, then it is a simple matter to program the refresh operations to be long enough to absorb any del.ays incurred through the external logic.
Once the serial Stati.c RAM tn t-he VRAM becomes filled with video data, a reguest is mada by the video control logic to move the data from SRAM to the DRAM portion on the memory. Because the move of the data can not be performed until a refresh operati.on from the graphics proce~sor iB executed, there is ~ome elapsed time during which additional incoming video data has to be handled by the video controller. Sitlce the video data cannot be held off and the SRAM i.s full, some additional storage has to be provided to temporar.ily hold the incoming video data until the SRAM becomes avai.lable. The size of the temporary data buffer is a functi.on of the incoming video data rate as well as th.e maximum amount of time that the hardware has to wait for a refre~.h operation to occur.
For example, if the i.ncoming video data rate is ~09-02-Og3 :1 ~
approximately 20 Mbytes/second an~l the maxlmum amount of time between refreshes iR 9.8 microseconds, the bufer has to hold up to l96 bytes of data. Additional buffering is needed ~o ensure the continuous incoming video stream has a place to be he]d while the existing 196 bytes are moved from the buffer to the SRAM in the VRAM. By using a standard ] K byte first in first out (FIF0) a worst case operational environment is insured.
Still another feature of the present invention is the technique wherein the video data input stream is encoded.
Upon receiving incoming video ~ata, an 18-bit wide synchronous FIF0 device is used as an input buffer. Two extra bits are used for encoding the video input stream.
The Horizontal Sync plllse triggers a flip-flop which generates a state bit that indicates the ætatus of a video scanline while the Vertical Sync pulse generates another state bit to indicate the status of video frame.
By reading the status change from these two extra encoded bits, a flag for sequence change or frame change can be raised. These flags signal the need of writing a line of data to the DRAM pixel Buffer from the dedicated serial port or the need of gettin~ new window address;
therefore, generate the memory access request to XGA
memory controller accordingly. These two possible memory acce#s requests would grab a memory refresh cycle as soon a# it becomes available. We have observed that more than enough DRAM refresh cycles have been issued by the memory controller. The requests from the new line or the new frame, steal excessive memory refresh cycles to load the window address or to write the data that is already in the serial port to the nRAM side of the VRAM buffer.
The two concurrent memory accesses include #erial port to DRAM write for the previous scan line and lock-bit memory read for the current scanline The lock-bit of the current scanline is stored in a d~lal-ported memory while the video data of the previo~ls scanline is stored in a three-ported memory. ~or every token that has been ~ Yo9-02-093 2ll40 ~ o 7 3 granted for memory access, there are two events taking place at the same time The first event i8 to write the previous scanline that a~.ready resides in the dedicated serial port into DRAM; and the second event is to read the current scanline's control lock-bit from DRAM port of the 2-ported keying buffer (lock-bi.t) to its serial port.
This i8 a look ahead scheme for video and graphic~
windows overlay operation, which i~ prepared for the next serial port to DRAM Pixel Buffer operation.
This is being executed i.n a parallel fashion for each granted cycle steal. Between two tokens granted for memory cycle steal, one of two serial ports on the 3-ported VRAM keeps receiving the video data output from the EIFO; while the lock-bit data on the 2-ported VRAM
has been read from .its serial. por~ as illustrated in Fig.
8.
While the invention has been part.icularly shown and described with respect to a preferred embodiment thereof, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the scope and spirit. of the invention.
210~073 An Integrated ~ingle Frame Buffer Memory For Storing r~raphics an~l Video Data FIELD OF THE INVENTION:
The present invention relates to display devices, and more particularly to a multi-media workstation based display device wherein graphics data and video data are merged and stored in a single frame buffer memory BACKGROUND OF THE INVENTION:
In multi-media work station di~plays, it is known that two independent rasters, such as a standard TV video and high resolution computer generated graphics video may each be displayed on a high resolaltion graphics monitor by the use of dual frame buffers. A TV frame buffer includes a dual port VRAM, with the serial and random ports operating asynchronously. The primary port receives incoming TV video synchronously as it comes in, and the secondary port reads the TV video out synchronously with the high resollltion graphics monitor.
A high resolution frame buffer in a computer is utilized to store high resolution graphi.cs which is read out synchronously with the high resol.lltion graphics monitor.
A switching mechanism selects wh;ch of the TV video and the high resolution graphics video is to be displayed at a given time. The TV frame buffer includes an on screen and off screen portion. The computer provides computer data, including high resolution graphics data and audio data to the TV frame bt1ffer, w~th t.he graphics data being stored in the on screetl portion ~nd the audio data being stored in the off screetl portion. The audio data is read out to an audio circtlit for replay. The graphics data is combined with the TV vi.deo for p~lrposes of windowing.
Dual buffers of this type are costly on both space and production. Also, it i.s diffictllt to edit the merged graphics and video for separate frames.
:, ~ Y09-02-093 ~ 210~07~
s An example of a dual frame buffer display system is 3 described in U.S. Patent ~,994,9]~ issued February 19, s 1991 to Lumelsky et al. and entitled AUDIO VIDEO
INTERACTIVE DISPLAY.
;- In addition to dual frame buffers having cost and space and graphicæ/video data merger drawbacks, it is difficult to extend displays in dual frame buffer systems for higher spatial reso]altion or higher frame refresh rate and it is difficu]t to develop drivers for inconsistent buffer sizes, different data formats and the like.
There are several other previo~ls]y known approaches to combining video with high resoluti.on graphics. Some methods double the scan rate of the incoming video through the use of a ].ine buffer, reading out each video i line twice for each line of the high-resolution screen.
This method has several drawbacks. First, it assumes that the high-resolution display is exactly twice the scan rate of th incoming video. This is seldom the case, and always requires a gen-lock circuit at the very least to force this strict relationship between the video and the graphics. It also fails to provide random access to the video information from the host workstation, since there is no frame buffer to ,store the video information.
Another method involves convertinq -the video and graphics information into a common format ~nd storing the two into a single, common frame buffer. Wlli]e this may at first seem to be an advantage in that only one frame buffer is needed, this buffer require.q far more memory than having two separate dedicate~ bllffers. Tn the prior art, in ~ order to use a single frame buffer to store both types of i3 vlsual data, a very l~rge frame hllffer i~ required that ~ is both "wide" and "deep".
. .
i SUMMARY OF THE IMVENTION
.,.
It is an object of the present invention to provide an integrated display system for multi-media workstations ,.
!
~':
., ~
~ Y09-02-093 3 210~073 wherein graphics image and video data are merged in a ~ingle frame buffer.
Another object of the present invention is to provide an integrated display system for multi-media workstations which employs 3-port VRAMs with a first serial access port for display data o~ltput, a second serial access port for video data input, and a r~ndom access port for graphics data.
. :~
A further object of the present invention is to provide a '',--, single frame buffer memory system for a multi-media ~, ', workstation which operates compatibly with display systems and logic deæigned for dual frame buffer systems. ,,~,' A ~till further object of the present invention is to provide a ~ingle frame buffer memory system for a multi-media work~tation employing a 3-port VRAM
incorporating improved input locking, video update or ~ ~
refresh, and encoded video data inpllt stream. ~' ,-. ~-BRIEF D~SCRIPTION OF THE DRAWINGS
Fig. 1 is a schematic b]ock diagram illustrating logic and display elements for ~ typical multi-media workstation;
, ~
Fig. 2 is a schematic hlock diagram illustrating a dual frame buffer memory or separate]"y storing graphics and video data according to the prior art; ;;
Fig. 3 i~ a ~chematic hl.ock di~gram of a single frame buffer memory using ~-port VRAM~ with multiplexing according to the prior art;
Fig. 4 is a schematic block diagram illustrating an embodiment of single frame buffer memory using 3-port ~-VRAMs according to the pri,nci,ples of the present invention; ,~
~i YO9-02-093 4 Fig. 5 is a schematic block diagram ill-lstratlng a singlè
frame buffer memory u~ing 3-port VRAM~ for graphics, video and display data and 2-port VRAMs for control functions;
Fig. 6 is a schematic block diagr~m illustrating a data path for an implementation of an input locking eature ' incorporated in the present inventi,on; '~ ''' Eig. 7 is a schemati,c b]ock diagram illustrating an implementation of an i,nput lock;ng feature incorporated in the present inventioll;
Fig. 8 is a diagram used in exp],a,ining a typical memory access pattern of the present invention.
DESCRIPTION O~ THE PREFERRRD EMBODIMENT
The present invention i 9 incorporated into and provides an improvement to a multi-media workstation. In contrast to personal workætations, a multimedia workstation ~, consists of a processing unit, input devices, storage devices, and a display unit for visual output and other output devices. The multimedi,a data handled by workstations takes different forms including text, graphics, image, video, and speech via various input modes. When video is ;ntroduced into the workstations, the real time nature of the vi,deo data, and the mixing of video graphics data, e.g. graphi,cs overlay on video, scrolling text on video, etc. have to be considered. The video of a given frame size has to be displayed at the fixed input rate such a~ 24 or .~n frames per second. To achieve this, present,l,y known architecture uses two separate frame buffers, one for video and the other for graphics and mixes bot.h video signals at the output side using a technique called chroma-key,ing.
In Fig. 1, a schematic illu.stration of an IBM XGA
subsystem, typical disp]ay architecture for merging video into a graphics workstat;on is shown using separate frame .~ . ,.
:` YOg-02-093 5 2iO4073 buffers for video and graphi.cs data. To display live video in a window, a particular color (chroma-key color) is selected as the background color to paint the window in the graphics buffer 10. During display time, for each pixel location (screen locatlon), the pixel data is obtained from the VGA Graphics frame buffer lO via the Video Feature Bus, and compares the pixel data (in this case, color index) wit.h the chosen chroma-key color (color index). If they match, the pixel data from the Video buffer 12 is displayed; otherwise, the data from Graphics buffer lO is di.splayed. For a graphics overlay on the video in the window, the graphics data can be written on the graphics buffer lO using any color besides the chosen chroma-key backgroun~ co]or. The system of Fig. l has the drawbacks that i.t i.s difficult to extend displays for a higher spati.al resolution or a higher frame refresh rate, i.t is not an efficient hardware platform for programmer to edit the merged graphics and video data and it is cumbersome to develop drivers for inconsistent buffer sizes, different data formats, etc.
In Fig. 2, a typica]. prior art single frame buffer technique for displaying graphi.c and video data is shown wherein the random access port of the video random access memory (VRAM) is shared by mu]tiplexing the graphics and video data. In this technique the video input consumes fairly high input bandwi.dth available from the VRAM frame buffer. In a window.ing envi.ronment, this implementation could not guarantee the real time display of the video data. Also, the graphics perfoxmance wil]. suffer because of the sharing of the same VRAM access port by graphics and video.
The present lnvention overcomes ~he drawbacks of the use of dual frame buffers and the 11~e of a single frame buffer in systems of the prior art by providing an integrated single frame buffer system for multi-media work stations that employs a ~-port VRAM means for handling both graphic data and video data and which includes an improved locking mechanism feature, the use ~-;" Y09-02-093 6 210~073 of a refresh feature to allow video update to the frame buffer, and an encoded video data J nput stream.
Referring to Fig. 3, a multi-media video subsystem is illustrated including a processing unit 14 and a display unit 16 with disp]ay ~Init 16 also having an input from CPU 18. Comparing the processinq unit of Fig. 3 with the processing unit of the prior art 2-port VRAM system of Fig. 2 is it seen that they are the same. In fact, the basic distinction o the system of Fig. 3 is the VRAM is a 3-port device. In addition to the usual serial access port for display output, the 3-port VRAM 20 of Fig. 3 includes a second serial access port with masked register video input.
Triple port VRAMs are available in the art for use in -~
multi-media work stations. Such devices are manufactured and marketed by Micron Technology, Inc.
In the system illustrated in Fig. 4, structure for three improvement techniques are provided. The first technique is referred to as input locking. Referring to Fig. 6, a schematic illustration of a data path for the implementation of input locking is illustrated, and in Fig. 7 the implementation of the input lock bit mechanism of the present invention is operated as in output locking in a dual frame buffer approach for compatibility. ~-Chroma-keying has been traditionally used as in the art an output lock among multiple frame buffers, where one frame buffer (e.g. graphics) serves as keying or the master, while the other frame b~lffer~ (e.g. video(s)) are displayed as keyed or slaves. ~lltptlt ].ock as mentioned requires all slave frame buffers be synchronized pixel-by-pixel with the master one, in addition to a destination (or called transparent) color compare circuitry and a digital/analog multiplexer operating at -~
pixel rates. ;~;
~~ Yo9-02-093 7 21Q~07~
Input lock, on the other hand, req~lires only one frame buffer and one keying buffer. ~ll devices, including both master and slaves, must refer to the data on the keying buffer for writing the frame buffer. However, the master can also modify the data on the keying buffer.
The updating of the keying buffer can be made transparently, if implemented using a source color compare circuitry, and separate storages for frame buffer and keying buffer. Additional f~lnctions, such as area (window) editing, multiple window clipping, graphics/text overlay and/or scrolling over vid~o, can be incorporated if more keying buffer is used. To extend further, the keying buffer can be in line with ~ buffer, alpha buffer, window ID buffer, etc., as extensions of (pixel) frame buffer.
In Fig. 6, although the implementation is shown external to the graphics control]er, the ]ogic used can be incorporated within a graphics controller design.
In the implementation, two lock (or keying) bits per pixel are used. Two modes of operations are supported~
in-band and out-band. In an in-band mode, the input lock bits are set or reset resulting from a compare between the graphics pixel data and a transparent color (programmed ahead), as seen in chroma-keying. The compare operation is performed on the fly during each memory write operation to (pixel) frame huffer. As described, the keying buffers addressed transparently in an in-band mode. In an out-band mode, the input lock bits are set or reset by the programmed data sent via an I/O data port.
This mode of operation floes not llse any transparent color for comparison, but req~lires ~ sep~rate I/O operation.
By analogy with a cache memory implementation, this implementation caches addresses hy comparing the graphics controller's pixel d~ta, whi]e the cache memory implementation caches data by comparing the processor's addresses. More specif]cally, the tag memory is to cache memory as the input ]ock to frame huffer.
.. , . , . . . .. ~ . , . , ... . , . ~ . , " ... . . . .
~~ Y09-02-093 21~073 The access mechanism, transparen~ to user~, involves two aspects: the manip-llation of lock bits and the data integrity.
The manipulation of lock bitæ is based on chroma-keying.
The chroma-keying has been used in the dual frame buffer approaches, as previously discussed, to multiplex graphics and video data onto the screen. The existing approaches using chroma-keying as destination color compare have been classified and their drawbacks discussed. In the integrated frame buffer of the present invention, the source color compare for chroma-keying is used. The graphics data of an address being accessed is compared against a pre-programmed color code or index (chroma-key). The lock bit of the address is set to "1"
if they compare and "O", otherwise.
The implementation of the input locking technique to in~ure data integrity is an important aspect of the mechanism due to the sharing (or integration) of the frame buffer for both graphics and video data. The incon#istency can develop if the video controller refers to an out-of-date copy of lock bit. For example, the graphics controller update~ the lock bit with a non-transparent color, which will reset the associated lock bit to "O". In the mean while, the video controller has maintained a local copy of the lock bit, which was "1". The local copy i 6 maintained within the serial acce~s memory. What would then appear on the screen is video data, taking the place of graphics data just updated.
Since the video is transient data, the sy~tem provides that graphics data has priority over video data in case of inconsistency. As a part of access mechani~m, a detection circuitry of inconsistency has been incorporated. Once occllrred, the updating of video would be void. As depicted in Fig. 7, the system detects for each memory access of graphics data whether or not (1) its address falls in the same range to which the local ; ~ YO9-02-093 9 , copy of lock bits refers,2~Q ~)7 13ts data do not compare (or its associated ].ock bit i.s bei.ng updated to "0").
If both condition l and 2 are sati.sfied, the updating of video will be then voi.d. It should be noted that the information of current address range of lock bits (whose data has been ]cept locally by the video controller) is constantly updated and store i.n min-max registers, ~hown in Eig. 7 for comparators of high and low limits.
The use of the feature of the additional lock bit per pixel, functions such as multi-window clipping, and graphic~/text scrolling over video can be employed. In multi-window clipping, two video windows (A & B) can be incorporated, each window having i.ts own keying buffer, e.g.. bit 0 for window A and bi.t l for window B. The priorlty can be pre-determined and specified in the operation code, eg A ~ B, if opcode= "00l". So, when the window A is accessing the keyi.ng buffer with opcode=
"00l", the video pixel can address the pixel data buffer, if bit l, 0 = "l", "l", or "0", "l". On the other hand, the window B can only address the pixel frame buffer when bit l, 0 = "0","l".
In graphics/text scroll.i.ng over vi.deo (doubled buffering) the graphics/text scroJI. can be facilitated when both lock bits are u~ed alternative.ly for a window. Assuming that at the moment, bi.t 0(1) is used, containing locationc of graphics/text data and bit l(0) has been cleared. When it comes the time to scroll the graphic~/text, bit 1(0) wi].l be used at the next moment, while the bit 0(l) is bei.ng cleared.
Other functions, such as logical AND (shrink), OR
(expand), 0 (all disabled) and 1 (all disabled), can all be similarly implemented.
:
Another feature of the present invention is the use of ::
refresh logic to allow video update to the frame buffer. ~:
~"~ YO9-02-093 ~ n In using a three port video RAM (VRAM) the normal mode of operation of the video input is to serially #hift the video data into the serial port o~ the VRAM which results in writing data to the static memory portion. Once the static memory haæ been fi]led or a predefined boundary has been reached it is necessary to move the contents of the static memory into the dynamic memory. In order to accomplish this it is neceæsary to retain exclusive use of the dynamic memory for the period of time that it takes to move the data from the static to the dynamic memory and consequently from the dynamic to the static memory. This implies that there needs to be a mechanism in place which provides accesæ to the dynamic memory without interference. The device which controls the access to the VRAM ports is the graphic processor engine.
It controls the parallel port accesses for graphics updates and lt controlæ the serial port to the display unit for the display operation. If the graphic_ controller is designed to handle the video port it also controls the third fferial port for video updates as needed. However, most graphics processors are not de_igned for supporting a video data stream and therefore require another mechanism to allow video updates. In the ca_e that the graphics processor is designed to handle arbitration by other devices for access to the VRAM the problem can be solved by the arbitration mechanism. In thi_ ca_e the arbitrat;ng device, which handles video, can gain access to the VRAMs parallel port as well as the serial video port to allow it video updates. The problem that exlsts with the XGA graphics controller as well as many other graphics controllers is that they were deslgned in such a way that they assume exclusive ownership of the VRAM ~nd do not. provide either a video interface control nor an arbitration mechanism.
, , In the present invention, a technique is provided to allow video updates without interfering with normal ~-graphic# operations. A mechanism which can provide this capability is through the manip~llation of the refresh ~-interface between the qraphics processor and the VRAM.
' ` Y09-02-093 210~073 In the case of the I~M XGA graphics controller a refresh operation occurs once very 9.8 microseconds. It is necessary to refresh ~56 rows of the VRAM every 4 milliseconds, which means 'that ~ refresh has to occur every 15.6 microseconds. Due to the use in the page mode access of memory the TBM XGA controller provides more refreshes than necessary to maintain valid data in the VRAM. That is, it provides up to 408 refreshes every 4 milliseconds where only 256 are requlred, leaving up to 152 extra refresheæ that are not necessary. As a result it is possible to steal, some of the extra refresh cycles from the graphics processor and uge them for updating the incoming video. This can be accomplished as long as there are fewer refresh cycles stolen than are necessary to maintain the VRAM. ~or the case of video updates it is necessary to steal ~ne refresh cycle for every line update. In the worst case scenario there are up to 768 lines of video that C~tl be displayed. Assuming that the video rate is no more than 30 frames per second, this works out to be approx,imately 103 stolen refresh cycles every 4 milliseconds. This sti]l leaves an excess of 49 refresh cycles every 4 milliseconds which ensures that the VRAM has a sufficient number of refresh cycles.
The stealing of the refresh cycl~s is accomplished by channelling the VRAM control signals, generated by the graphics processor, through some h,igh speed logic on the card. The purpose of -this hi,gh speed logic is to detect a refresh operation generated by the graphics processor and if there is a penAing l,lpd~t~ request by the video controller, to block the refresh ~peration and generate a video update operati,on tn its place. If there is no pending request rom ~,he v,ide~ controller, then all refresh operations are simp]y passed through this logic without interference. Tn addition, all normal read and write operations generated by the qraphics processor are always passed through regardle~s of pending video request. The detection of refresh operations in the case of the XGA graphics controller is accomplished by simply detecting a Column Address Strobe (CAS) occurring before ` Y09-02-093 :1~
2i0~073 a Row Address Strobe (RAS). This i.s one standard way of refreshing the dynamic memory wi.thin the VRAM chip. This mode of refresh has the advantage that the refresh counter on the VRAM i.s used and an external refresh need not be generated. If a refresh operation is blocked by the external logic, then the counter i8 simply not incremented until a legi.timate refresh operation occur#.
This i8 advantageous s;.nce it does not require any additional hardware to keep the refresh address count so that no addresses are i.nadvertent].y skipped. In the case that a refresh operation is blocked due to a pending update request, a block write operation is executed in its place. The RAS or CAS addresses for the write operation are generated by the external logic and placed on the address bus. The control. logic to the VRAM is regenerated with some delay. It is important that the delay through the external ci.rcultry is minimized in order not to exceed the timing requirements to the VRAM.
In some cases, as with the IBM XGA or the TI 34-020 graphics controllers, the refresh timing parameters can be programmed. If this is the case, then it is a simple matter to program the refresh operations to be long enough to absorb any del.ays incurred through the external logic.
Once the serial Stati.c RAM tn t-he VRAM becomes filled with video data, a reguest is mada by the video control logic to move the data from SRAM to the DRAM portion on the memory. Because the move of the data can not be performed until a refresh operati.on from the graphics proce~sor iB executed, there is ~ome elapsed time during which additional incoming video data has to be handled by the video controller. Sitlce the video data cannot be held off and the SRAM i.s full, some additional storage has to be provided to temporar.ily hold the incoming video data until the SRAM becomes avai.lable. The size of the temporary data buffer is a functi.on of the incoming video data rate as well as th.e maximum amount of time that the hardware has to wait for a refre~.h operation to occur.
For example, if the i.ncoming video data rate is ~09-02-Og3 :1 ~
approximately 20 Mbytes/second an~l the maxlmum amount of time between refreshes iR 9.8 microseconds, the bufer has to hold up to l96 bytes of data. Additional buffering is needed ~o ensure the continuous incoming video stream has a place to be he]d while the existing 196 bytes are moved from the buffer to the SRAM in the VRAM. By using a standard ] K byte first in first out (FIF0) a worst case operational environment is insured.
Still another feature of the present invention is the technique wherein the video data input stream is encoded.
Upon receiving incoming video ~ata, an 18-bit wide synchronous FIF0 device is used as an input buffer. Two extra bits are used for encoding the video input stream.
The Horizontal Sync plllse triggers a flip-flop which generates a state bit that indicates the ætatus of a video scanline while the Vertical Sync pulse generates another state bit to indicate the status of video frame.
By reading the status change from these two extra encoded bits, a flag for sequence change or frame change can be raised. These flags signal the need of writing a line of data to the DRAM pixel Buffer from the dedicated serial port or the need of gettin~ new window address;
therefore, generate the memory access request to XGA
memory controller accordingly. These two possible memory acce#s requests would grab a memory refresh cycle as soon a# it becomes available. We have observed that more than enough DRAM refresh cycles have been issued by the memory controller. The requests from the new line or the new frame, steal excessive memory refresh cycles to load the window address or to write the data that is already in the serial port to the nRAM side of the VRAM buffer.
The two concurrent memory accesses include #erial port to DRAM write for the previous scan line and lock-bit memory read for the current scanline The lock-bit of the current scanline is stored in a d~lal-ported memory while the video data of the previo~ls scanline is stored in a three-ported memory. ~or every token that has been ~ Yo9-02-093 2ll40 ~ o 7 3 granted for memory access, there are two events taking place at the same time The first event i8 to write the previous scanline that a~.ready resides in the dedicated serial port into DRAM; and the second event is to read the current scanline's control lock-bit from DRAM port of the 2-ported keying buffer (lock-bi.t) to its serial port.
This i8 a look ahead scheme for video and graphic~
windows overlay operation, which i~ prepared for the next serial port to DRAM Pixel Buffer operation.
This is being executed i.n a parallel fashion for each granted cycle steal. Between two tokens granted for memory cycle steal, one of two serial ports on the 3-ported VRAM keeps receiving the video data output from the EIFO; while the lock-bit data on the 2-ported VRAM
has been read from .its serial. por~ as illustrated in Fig.
8.
While the invention has been part.icularly shown and described with respect to a preferred embodiment thereof, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the scope and spirit. of the invention.
Claims (9)
1. In a multi-media display system of the type providing an integrated display of video, graphics and image data on a display monitor and including a source of digital image signals, a source of graphics signals, a processing unit having an image video processor means, a video capture means scaling means, a stored pre-programmed color index, a display unit having a graphics rasterizer means, a graphics buffer means and a three-port video random access memory structure which functions as a buffer memory;
the improvement characterized in a graphics control means connected to said processing unit and said display unit for providing control signals for writing said digital image video signals into said three-port video random access memory structure and for providing control signals for writing said graphics signals into said three-port random access memory structure;
and an input locking means connected to the output of said control means, including logic operator means for comparing said graphics signals to said stored pre-programmed color index for providing one of two lock bits in response to said comparing function wherein said lock bit is enabled for a compare occurrence and is disabled for a non-compare occurrence.
the improvement characterized in a graphics control means connected to said processing unit and said display unit for providing control signals for writing said digital image video signals into said three-port video random access memory structure and for providing control signals for writing said graphics signals into said three-port random access memory structure;
and an input locking means connected to the output of said control means, including logic operator means for comparing said graphics signals to said stored pre-programmed color index for providing one of two lock bits in response to said comparing function wherein said lock bit is enabled for a compare occurrence and is disabled for a non-compare occurrence.
2. A multi-media display system of the type according to claim 1 wherein said logic operator means of said input locking means includes first, second, third and fourth storage registers, said first and second storage registers containing pre-programmed color index data, a source color comparison means connected to the output of said graphics controller means and to the outputs of said first and second registers, and a multiplexer means connected to the outputs of said third storage register means and said source color comparison means, said source color comparison means being responsive to graphics data from said graphics controller means associated with an address being accessed and also responsive to said pre-programmed color index stored in said first and second storage registers for providing a 1 bit for a compare and a 0 bit for a non-compare.
3. A multi-media display system of the type according to claim 2 wherein said multiplexer means is further responsive to the output of said fourth register for providing a control signal;
and wherein said multi-media display system further includes a two-port video random access memory means connected to the output of said multiplexer means of said input locking means, said two-port video random access memory means functioning as a keying buffer means.
and wherein said multi-media display system further includes a two-port video random access memory means connected to the output of said multiplexer means of said input locking means, said two-port video random access memory means functioning as a keying buffer means.
4. A multi-media display system of the type according to claim 3 wherein said fourth storage register of said logic operator means provides a first, in-band operating mode signal and a second, out-band operating mode signal to said multiplexer wherein said in-band signal provides an indirect update mechanism signal dependent on a comparison operation between graphics data and programmed transparent color data, and Warren said out-band signal provides a direct update mechanism dependent on programmed data provided from an input/output data port.
5. A multi-media display system of the type according to claim 4 wherein said lock bits are enabled and disabled in response to either said compare operation of said in-band mode or ore enabled and disabled in response to said programmed data from said input/output port.
6. A multi-media display system of the type according to claim 3 further including means for connecting said two-port keying buffer random access memory and said fourth storage register to a first serial access input port of said three-port video random access memory means for providing display pixel masking indicators to said three-port video random access memory means functioning as a pixel frame buffer;
wherein said source of video data is connected to a second serial access input port of said three-port video random access memory means;
and wherein said output of said graphics controller means is connected to a random access input port for providing graphics data to said three-port video random access memory.
wherein said source of video data is connected to a second serial access input port of said three-port video random access memory means;
and wherein said output of said graphics controller means is connected to a random access input port for providing graphics data to said three-port video random access memory.
7. In a multi-media display system of the type according to claim 1 wherein said graphics controller means provides a plurality of refresh operations to said three-port video random access memory and wherein said graphics controller can be configured to provide a greater number of refreshes than there are rows requiring refresh in said three-port video random access memory;
the improvement characterizer in means for detecting a refresh operation signal generated by said graphics controller in the form of a column address strobe signal occurring before a row address strobe signal, means for detecting a video update request signal from said video processor means;
and means responsive to said refresh operation signal and said video update request signal for blocking said refresh operation signal. and providing a video update signal in place thereof.
the improvement characterizer in means for detecting a refresh operation signal generated by said graphics controller in the form of a column address strobe signal occurring before a row address strobe signal, means for detecting a video update request signal from said video processor means;
and means responsive to said refresh operation signal and said video update request signal for blocking said refresh operation signal. and providing a video update signal in place thereof.
8. In a multi-media display system of the type according to claim 7 wherein said image video processor includes a video input memory means responsive to said video signals and containing control bits associated with synchronizing information from said video source, a flip-flop means responsive to the systems horizontal and vertical sync pulses, said flip-flop providing a first control bit in response to said horizontal sync pulse for indicating the status of a video scanline and for providing a second control hit in response to said vertical sync pulse for indicating the status of a video frame.
9. In a multi-media display system of the type according to claim 8 responsive to said first and second bits from said flip-flop means for providing a signal indicating a sequence change and a frame change respectively, said sequence change signal providing a first memory request signal to said three-port video random access memory for writing a line, and said frame change signal providing a second memory request signal to the system memory controller of said processing unit wherein said pair of first and second memory request signals provide an indicator signal to cause an update cycle instead of a refresh cycle to said three-port video random access memory.
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| US07/696,649 | 1992-10-30 | ||
| US07/969,649 US5402147A (en) | 1992-10-30 | 1992-10-30 | Integrated single frame buffer memory for storing graphics and video data |
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| CA002104073A Abandoned CA2104073A1 (en) | 1992-10-30 | 1993-08-13 | Integrated single frame buffer memory for storing graphics and video data |
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-
1992
- 1992-10-30 US US07/969,649 patent/US5402147A/en not_active Expired - Fee Related
-
1993
- 1993-08-13 CA CA002104073A patent/CA2104073A1/en not_active Abandoned
- 1993-09-21 EP EP93115166A patent/EP0597218A1/en not_active Withdrawn
- 1993-10-25 JP JP5265955A patent/JPH06208351A/en active Pending
- 1993-10-29 BR BR9304391A patent/BR9304391A/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| US5402147A (en) | 1995-03-28 |
| BR9304391A (en) | 1994-05-24 |
| JPH06208351A (en) | 1994-07-26 |
| EP0597218A1 (en) | 1994-05-18 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Discontinued |