CA2104755A1 - Multirate, Sonet-Ready, Switching Arrangement - Google Patents

Multirate, Sonet-Ready, Switching Arrangement

Info

Publication number
CA2104755A1
CA2104755A1 CA2104755A CA2104755A CA2104755A1 CA 2104755 A1 CA2104755 A1 CA 2104755A1 CA 2104755 A CA2104755 A CA 2104755A CA 2104755 A CA2104755 A CA 2104755A CA 2104755 A1 CA2104755 A1 CA 2104755A1
Authority
CA
Canada
Prior art keywords
data
time slots
memory
time
superframe
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2104755A
Other languages
French (fr)
Other versions
CA2104755C (en
Inventor
Robert Lee Pawelski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of CA2104755A1 publication Critical patent/CA2104755A1/en
Application granted granted Critical
Publication of CA2104755C publication Critical patent/CA2104755C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0407—Selecting arrangements for multiplex systems for time-division multiplexing using a stored programme control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections

Abstract

A time-division multiplex switch (100) switches a hierarchy of data rates. It sets up higher-rate connections not as a plurality of individual lowest-rate connections but as one or more time slots in each one of a plurality of sequential frames (40, 50) that correspond to that higher rate in each superframe (30). A time-slot-interchange switching element (131, 141) of the switch utilizes a plurality of physically or logically distinct double-buffered data memories (301,302, 303) each corresponding to a different one of the superframe and different-size ones of the frames. Reading and writing of each of the data memories' buffers alternates with the corresponding one of the superframe and different-size frames; reading of a data memory's buffer immediately follows writing of that buffer. Information from all incoming time slots is written into each one of the data memories, but only information corresponding to the data rate of an individual data memory's corresponding frame size is read from that data memory into outgoing time slots. A control memory (305) maps memory locations of the data memories to output time slots. A corresponding control architecture in a switching element (1700) of a time-multiplexed switch (120) uses a control memory (1701) that maps input ports to time slots of an output port. <IMAGE>
CA002104755A 1992-10-20 1993-08-24 Multirate, sonet-ready, switching arrangement Expired - Fee Related CA2104755C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US964,537 1992-10-20
US07/964,537 US5323390A (en) 1992-10-20 1992-10-20 Multirate, sonet-ready, switching arrangement

Publications (2)

Publication Number Publication Date
CA2104755A1 true CA2104755A1 (en) 1994-04-21
CA2104755C CA2104755C (en) 1997-04-08

Family

ID=25508664

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002104755A Expired - Fee Related CA2104755C (en) 1992-10-20 1993-08-24 Multirate, sonet-ready, switching arrangement

Country Status (6)

Country Link
US (1) US5323390A (en)
EP (1) EP0594356B1 (en)
JP (1) JP2931188B2 (en)
AT (1) ATE199621T1 (en)
CA (1) CA2104755C (en)
DE (1) DE69329985T2 (en)

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NL9100173A (en) * 1991-02-01 1992-09-01 Philips Nv SUBBAND CODING DEVICE, AND A TRANSMITTER EQUIPPED WITH THE CODING DEVICE.
US5696761A (en) * 1995-08-31 1997-12-09 Lucent Technologies Inc Method and apparatus for interfacing low speed access links to a high speed time multiplexed switch fabric
US5862135A (en) * 1996-10-10 1999-01-19 Lucent Technologies Inc. Simplified interface to a time-division multiplexed communications medium
US5987027A (en) * 1996-11-08 1999-11-16 Alcatel Cross-connect multirate/multicast SDH/SONET rearrangement procedure and cross-connect using same
KR20010052097A (en) * 1997-11-06 2001-06-25 네트 인사이트 에이비 Method and apparatus for switching data between bitstreams of a time division multiplexed network
US6765928B1 (en) * 1998-09-02 2004-07-20 Cisco Technology, Inc. Method and apparatus for transceiving multiple services data simultaneously over SONET/SDH
DE19844732A1 (en) * 1998-09-29 2000-03-30 Siemens Ag Circuit arrangement and method for switching channels in a communication network
US6870838B2 (en) 2000-04-11 2005-03-22 Lsi Logic Corporation Multistage digital cross connect with integral frame timing
US7301941B2 (en) * 2000-04-11 2007-11-27 Lsi Corporation Multistage digital cross connect with synchronized configuration switching
US20030058848A1 (en) * 2000-04-11 2003-03-27 Velio Communications, Inc. Scheduling clos networks
US7260092B2 (en) 2000-04-11 2007-08-21 Lsi Corporation Time slot interchanger
US7113505B2 (en) * 2001-12-17 2006-09-26 Agere Systems Inc. Mesh architecture for synchronous cross-connects
JP3910063B2 (en) * 2001-12-27 2007-04-25 富士通株式会社 Transmission apparatus and data processing method in the transmission apparatus
US7346049B2 (en) * 2002-05-17 2008-03-18 Brian Patrick Towles Scheduling connections in a multi-stage switch to retain non-blocking properties of constituent switching elements
US7177328B2 (en) * 2002-11-27 2007-02-13 Transwitch Corporation Cross-connect switch for synchronous network
US7330428B2 (en) * 2002-12-11 2008-02-12 Lsi Logic Corporation Grooming switch hardware scheduler
US20040156381A1 (en) * 2003-02-10 2004-08-12 Fischer Michael Andrew Partial queuing using an interface with bounded latency
US7362125B2 (en) * 2006-06-14 2008-04-22 Hypres, Inc. Digital routing switch matrix for digitized radio-frequency signals
US8462889B2 (en) 2005-10-04 2013-06-11 Hypres, Inc. Oversampling digital receiver for radio-frequency signals
JP4910893B2 (en) * 2007-06-07 2012-04-04 富士通株式会社 Time slot replacement device
JP5471627B2 (en) * 2010-03-09 2014-04-16 富士通株式会社 Network device, edge router and packet communication system
US8401600B1 (en) 2010-08-02 2013-03-19 Hypres, Inc. Superconducting multi-bit digital mixer

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4485468A (en) * 1982-04-01 1984-11-27 At&T Bell Laboratories Control word generation method and source facilities for multirate data time division switching
US4608684A (en) * 1984-03-26 1986-08-26 Itt Corporation Digital switching systems employing multi-channel frame association apparatus
CA1257675A (en) * 1986-04-01 1989-07-18 Alan F. Graves Switching tdm digital signals
US4704716A (en) * 1985-12-31 1987-11-03 American Telephone And Telegraph Company, At&T Bell Laboratories Method and apparatus for establishing a wideband communication facility through a communication network having narrow bandwidth channels
US4771420A (en) * 1986-12-08 1988-09-13 Dsc Communications Corporation Time slot interchange digital switched matrix
JPH0785547B2 (en) * 1988-07-08 1995-09-13 日本電気株式会社 Frame converter
US4855996A (en) * 1988-08-03 1989-08-08 American Telephone And Telegraph Company Time division multiplex arrangement
US4998242A (en) * 1988-12-09 1991-03-05 Transwitch Corp. Virtual tributary cross connect switch and switch network utilizing the same
US4993016A (en) * 1989-05-08 1991-02-12 At&T Bell Laboratories Network control arrangement for processing a plurality of connection requests
US5040173A (en) * 1989-05-08 1991-08-13 At&T Bell Laboratories Network control arrangement based on topological equivalence
US4991168A (en) * 1989-05-08 1991-02-05 At&T Bell Laboratories Concurrent multi-stage network control arrangement
US5005170A (en) * 1990-01-09 1991-04-02 At&T Bell Laboratories Multi-rate multiplexing arrangement efficiently utilizing multiplexed channel bandwidth
JP3169217B2 (en) * 1990-01-19 2001-05-21 株式会社日立製作所 Time division multiple speed line connection method and apparatus
FR2659813B1 (en) * 1990-03-19 1994-06-03 Cit Alcatel ELEMENTARY SWITCHING UNIT FOR BREWING EQUIPMENT OF MULTIPLEX DIGITAL TRAINS BY TIME MULTIPLEXING OF DIGITAL TRIBUTORS AT DIFFERENT RATES.
US5146455A (en) * 1990-12-17 1992-09-08 At&T Bell Laboratories Wide range mixed rate TDM bus using a multiple of time slot interchange circuit switches

Also Published As

Publication number Publication date
EP0594356A2 (en) 1994-04-27
DE69329985D1 (en) 2001-04-12
EP0594356A3 (en) 1994-12-14
JPH06205480A (en) 1994-07-22
JP2931188B2 (en) 1999-08-09
CA2104755C (en) 1997-04-08
US5323390A (en) 1994-06-21
ATE199621T1 (en) 2001-03-15
DE69329985T2 (en) 2001-09-20
EP0594356B1 (en) 2001-03-07

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