CA2109835A1 - Differential latching inverter and random access memory using same - Google Patents

Differential latching inverter and random access memory using same

Info

Publication number
CA2109835A1
CA2109835A1 CA2109835A CA2109835A CA2109835A1 CA 2109835 A1 CA2109835 A1 CA 2109835A1 CA 2109835 A CA2109835 A CA 2109835A CA 2109835 A CA2109835 A CA 2109835A CA 2109835 A1 CA2109835 A1 CA 2109835A1
Authority
CA
Canada
Prior art keywords
bit lines
pair
high speed
differential
latching inverter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2109835A
Other languages
French (fr)
Other versions
CA2109835C (en
Inventor
Albert W. Vinal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HSM PORTFOLIO LLC
Original Assignee
Albert W. Vinal
Thunderbird Technologies, Inc.
Hsm Portfolio Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/708,459 external-priority patent/US5304874A/en
Application filed by Albert W. Vinal, Thunderbird Technologies, Inc., Hsm Portfolio Llc filed Critical Albert W. Vinal
Publication of CA2109835A1 publication Critical patent/CA2109835A1/en
Application granted granted Critical
Publication of CA2109835C publication Critical patent/CA2109835C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Abstract

A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a pair of symmetrical transfer function output inverters and additional pull-up circuits to enhance high speed operation. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines. The primary bit lines and signal bit lines are coupled to one another during read and write operations and decoupled from one another otherwise. The read and write operations may be internally timed without the need for external clock pulses in response to a high speed address change detection system, and internal timing signals generated by delay ring segment buffers. A high speed, low power random access memory may thereby be provided.
CA002109835A 1991-05-31 1992-05-28 Differential latching inverter and random access memory using same Expired - Lifetime CA2109835C (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US708,459 1991-05-31
US07/708,459 US5304874A (en) 1991-05-31 1991-05-31 Differential latching inverter and random access memory using same
US742,649 1991-08-07
US07/742,649 US5305269A (en) 1991-05-31 1991-08-07 Differential latching inverter and random access memory using same

Publications (2)

Publication Number Publication Date
CA2109835A1 true CA2109835A1 (en) 1992-12-10
CA2109835C CA2109835C (en) 1998-12-22

Family

ID=27108081

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002109835A Expired - Lifetime CA2109835C (en) 1991-05-31 1992-05-28 Differential latching inverter and random access memory using same

Country Status (9)

Country Link
US (1) US5305269A (en)
EP (1) EP0587753B1 (en)
JP (1) JPH06508233A (en)
KR (1) KR100264139B1 (en)
AT (1) ATE129592T1 (en)
AU (1) AU2171692A (en)
CA (1) CA2109835C (en)
DE (1) DE69205682T2 (en)
WO (1) WO1992022067A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5304874A (en) * 1991-05-31 1994-04-19 Thunderbird Technologies, Inc. Differential latching inverter and random access memory using same
JPH08274612A (en) * 1995-03-31 1996-10-18 Nec Corp Semiconductor device
US5910138A (en) * 1996-05-13 1999-06-08 B. Braun Medical, Inc. Flexible medical container with selectively enlargeable compartments and method for making same
US6034886A (en) * 1998-08-31 2000-03-07 Stmicroelectronics, Inc. Shadow memory for a SRAM and method
JP3813400B2 (en) * 1999-11-29 2006-08-23 富士通株式会社 Semiconductor memory device
KR100492801B1 (en) * 2002-11-14 2005-06-07 주식회사 하이닉스반도체 Reset circuit and FeRAM using the reset circuit
JP7282699B2 (en) * 2020-01-21 2023-05-29 キオクシア株式会社 semiconductor storage device

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4354257A (en) * 1980-05-23 1982-10-12 Fairchild Camera And Instrument Corporation Sense amplifier for CCD memory
JPS59178685A (en) * 1983-03-30 1984-10-09 Toshiba Corp Semiconductor storage circuit
EP0139196B1 (en) * 1983-09-07 1989-12-06 Hitachi, Ltd. Semiconductor memory having charge transfer device voltage amplifier
EP0170285B1 (en) * 1984-08-03 1991-04-03 Kabushiki Kaisha Toshiba Semiconductor memory device
JPS61107594A (en) * 1984-10-31 1986-05-26 Toshiba Corp Sense amplifier circuit
JPS61239493A (en) * 1985-04-05 1986-10-24 Fujitsu Ltd Semiconductor memory device
JPS6247897A (en) * 1985-08-28 1987-03-02 Sony Corp Reading amplifier
JP2615011B2 (en) * 1986-06-13 1997-05-28 株式会社日立製作所 Semiconductor memory circuit
JPS63304491A (en) * 1987-06-04 1988-12-12 Mitsubishi Electric Corp Semiconductor memory
US4816706A (en) * 1987-09-10 1989-03-28 International Business Machines Corporation Sense amplifier with improved bitline precharging for dynamic random access memory
US4845381A (en) * 1987-10-01 1989-07-04 Vlsi Technology, Inc. Voltage level shifting circuit
US4843264A (en) * 1987-11-25 1989-06-27 Visic, Inc. Dynamic sense amplifier for CMOS static RAM
KR0141494B1 (en) * 1988-01-28 1998-07-15 미다 가쓰시게 High speed sensor system using a level shift circuit
US4899317A (en) * 1988-02-01 1990-02-06 Motorola, Inc. Bit line precharge in a bimos ram
US4831287A (en) * 1988-04-11 1989-05-16 Motorola, Inc. Latching sense amplifier
JPH02101693A (en) 1988-10-07 1990-04-13 Texas Instr Japan Ltd Input circuit
JPH03242650A (en) 1990-02-20 1991-10-29 Fuji Photo Film Co Ltd Positive type photoresist composition
US5247212A (en) 1991-01-31 1993-09-21 Thunderbird Technologies, Inc. Complementary logic input parallel (clip) logic circuit family
US5547212A (en) 1995-08-22 1996-08-20 Morton International, Inc. Passenger side airbag inflator with flanged mounting adapter

Also Published As

Publication number Publication date
EP0587753B1 (en) 1995-10-25
AU2171692A (en) 1993-01-08
ATE129592T1 (en) 1995-11-15
JPH06508233A (en) 1994-09-14
WO1992022067A1 (en) 1992-12-10
DE69205682D1 (en) 1995-11-30
CA2109835C (en) 1998-12-22
KR100264139B1 (en) 2000-08-16
EP0587753A1 (en) 1994-03-23
US5305269A (en) 1994-04-19
DE69205682T2 (en) 1996-06-13

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Legal Events

Date Code Title Description
EEER Examination request
MKEX Expiry