CA2112528C - Packet switching system for forwarding packets from input buffers using idle/busy status of output buffers - Google Patents
Packet switching system for forwarding packets from input buffers using idle/busy status of output buffersInfo
- Publication number
- CA2112528C CA2112528C CA002112528A CA2112528A CA2112528C CA 2112528 C CA2112528 C CA 2112528C CA 002112528 A CA002112528 A CA 002112528A CA 2112528 A CA2112528 A CA 2112528A CA 2112528 C CA2112528 C CA 2112528C
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- idle
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- packet
- status bit
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/50—Overload detection or protection within a single switching element
- H04L49/505—Corrective measures
- H04L49/506—Backpressure
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L12/5602—Bandwidth control in ATM Networks, e.g. leaky bucket
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services
- H04L49/201—Multicast operation; Broadcast operation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services
- H04L49/201—Multicast operation; Broadcast operation
- H04L49/203—ATM switching fabrics with multicast or broadcast capabilities
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
- H04Q11/0478—Provisions for broadband connections
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5629—Admission control
- H04L2012/5631—Resource management and allocation
- H04L2012/5632—Bandwidth allocation
- H04L2012/5635—Backpressure, e.g. for ABR
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5651—Priority, marking, classes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
- H04L2012/5679—Arbitration or scheduling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
- H04L2012/5681—Buffer or queue management
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
Abstract
A packet switching system comprises input buffers and output buffers, and a self-routing network for routing packets from the input buffers to the output buffers according to the routing information contained in their header. An input controller, associated with each input buffer, includes an idle/busy memory. An output controller, associated with each output buffer, detects the idle space of the associated output buffer and determines if the idle space is greater than a predetermined value. If the idle space is determined to be greater than the predetermined value, an idle status bit is generated and if the idle space is determined to be smaller than the predetermined value, a busy status bit is generated. The idle and busy status bits are broadcast to the idle/busy memory of all input controllers. Each input controller writes an incoming packet into the associated input buffer and reads it onto the self-routing network if an idle status bit is stored in the idle/busy memory corresponding to the routing information of the incoming packet.
Description
, TITLE OF THE INVENTION
2 "Packet Switching System for Forwarding Packets from Input Buffers Using 3 Idle/Busy Status of Output Buffers"
Field of the Invention 6 The present invention relates generally to packet switching 7 systems, and more specifically to a packet switching system of the input-8 output buffering type for switching packets such as asynchronous transfer 9 mode (ATM) cells.
Description of the Related Art 11 In a packet switching system of the input and output buffering 12 type, as described in a paper "A very high-speed ATM switch with input 13 and output buffers", Yukihiko Doi et al, 155'92 pages 231-235, incoming 14 packets are stored in an input buffer and launched onto a self-routing network where it is routed to a destination output buffer according to the 16 routing information of the packets. To achieve high throughput, it is 17 necessary to provide as many high capacity output buffers as possible for 18 bursty traffic and to provide a high speed scheduling algorithm for 19 multicast traffic. It is still desirable to reduce the amount of output buffers required and to simplify the scheduling algorithm for both point-to-point 21 and multicast traffic.
23 It is therefore an object of the present invention to provide a high 24 throughput packet switching system which eliminates the need for high capacity output buffers.
26 Another object of the present invention is to provide a high 27 throughput packet switching system which can be implemented with a 28 simplified scheduling algorithm for both point-to-point and multicast 2 9 traffic.
3 0 According to a broader aspect of the present invention, there is ~r~ NE-562 provided a packet switching system comprising a plurality of input buffers 2 connected respectively to a plurality of incoming links and a plurality 3 output buffers connected respectively to a plurality of outgoing links. A
4 self-routing network is connected between the input and output buffers for s routing packets from the input buffers to the output buffers according to 6 routing information contained in their header. A plurality of output 7 controllers are associated respectively with the output buffers. Each 8 output controller determines the idle space of the associated output buffer 9 which is available for storing additional packets and determines whether 10 the idle space is greater than a predetermined value. If the idle space is 11 determined to be greater than the predetermined value, an idle status bit 12 is generated and if the idle space is determined to be smaller than the 13 predetermined value, a busy status bit is generated. A plurality of input 14 controllers are associated respectively with the input buffers for storing the 15 idle and busy status bits from the output controllers in an idle/busy 16 memory and writing an incoming pacl<et into the associated input buffer.
17 Each input controller reads a packet from the associated input buffer onto 18 the self-routing network if an idle status bit is stored in the idle/busy 19 memory corresponding to the destination of the stored packet.
According to a second aspect of the present invention, there is 21 provided a packet switching system which comprises input buffers 22 connected respectively to incoming links, output buffers connected 23 respectively to outgoing links, and a self-routing network for routing 24 packets from the input buffers to the output buffers according to routing 25 information contained in the packets. A plurality of output controllers are 2 6 associated respectively with the output buffers for determining an idle 27 space of the associated output buffer which is available for storing 28 additional point-to-point packets and additional multicast packets. Each 29 output controller determines whether the idle space of point-to-point 3 o packets is greater than a first predetermined value and determines whether the idle space is greater than a second predetermined value 2 smaller than the first predetermined value, and generates a first idle status 3 bit or a first busy status bit into an idle/busy status memory if the idle4 space is determined to be greater or smaller than the first predetermined s value, respectively, and generates a second idle status bit or a second 6 busy status bit if the idle space is determined to be greater or smaller than 7 the second predetermined value, respectively. A plurality of input 8 controllers are associated respectively with the input buffers for storing the 9 first idle and busy status bits and the second idle and busy status bits in an idle/busy memory and storing an incoming point-to-point packet into the 11 associated input buffer and reading it if a first idle status bit is stored in the 12 idle/busy memory corresponding to the destination of the point-to-point 13 packet, and writing an incoming multicast packet into the associated input14 buffer and reading it if a second idle status bit is stored in the idle/busy memory corresponding to the incoming multicast packet.
17 The present invention will be described in further detail with 18 reference to the accompanying drawings, in which:
19 Fig. 1 is a block diagram of an ATM self-routing switching system according to the present invention;
21 Fig. 2 is a table illustrating the idle/busy status bits generated by 22 an output controller according to different cell types and stored in the 23 idle/busy status memory of each input controller;
24 Fig. 3 is a flowchart of a sequence of instructions performed by a selector of an input controller when a cell is read out of an associated RIRO
2 6 memory; and 27 Fig. 4 is a modified version of the flowchart of Fig. 3.
29 Referring now to Fig. 1, there is shown an asynchronous transfer 3û mode (ATM) switching system according to the present invention. The switching system comprises a plurality of line circuits 111 ~ 1 lN which 2 respectively serve as interfaces between incoming links 1O1 ~ 1ON and 3 input buffers, or random-in-random-out memories 121 ~ 12N. Connected 4 respectively to the line circuits 111 ~ 11 N and RIRO memories 121 ~ 12N
s are input controllers 131 ~ 13N, each of which provides address control 6 on incoming ATM cells to determine their write and read addresses of the 7 associated RIRO memory in a manner as will be described in detail later.
8 A header translation table 14 is connected to the line circuits 111 ~ 11N to 9 translate the VCI/VPI (virtual call identifier/virtual path identifier) field 10 contained in the header of each incoming packet, called "ATM cell" to an 11 outgoing link address (OLA) that specifies the appropriate outgoing link of 12 the switching system in a well known manner. Each incoming cell 13 contains a cell type field in its header to indicate the type of the cell as 14 constant bit rate (CBR), variable bit rate (VBR), a point-to-point, or multicast 15 data or a combination of these. ~ollowing the header translation on an 1 6 incoming ATM cell, each line circuit 11; (where i = 1, 2, N) supplies the 17 cell type (CT) data and the outgoing iink address (OLA) to the associated 18 input controller 13; and the whole contents of the cell to the associated 19 RIRO memory 12; where the cell is stored in a location specified by a write address WA supplied from input controller 13; and eventually read out of 21 the RIRO memory 12; in response to a read address RA from input 2 2 controller 13;.
23 The outputs of RIRO memories 121 ~ 12N are connected to a self-24 routing network 15 which includes a time division bus 16, on which the outputs of RIRO memories 12 are time-division multiplexed, and a plurality 2 6 of address filters 171 ~ 1 7N connected to the bus 16. Address filters 1 7j 27 are provided corresponding respectively to the outgoing links 20; and are 2 8 assigned the output link address (OLA) of the corresponding output link 29 plus two cell type identifiers identifying respectively CBR and VBR cells.3 o Each address filter 17 has two output terminals for respectively delivering CBR and VBR cells to the output buffers of a corresponding pair. ~ach 2 address filter allows passage of those ATM ceils to one of the output 3 buffers of the corresponding pair if it contains the output link address of 4 the address filter and one of the cell type identifiers of the address filter.s The outgoing buffers are implemented with first-in-first-out memories 6 CBR1 ~ CBRN for exclusively storing CBR cells and FIFO memories VBR1 ~
7 VBRN for exclusively storing VRB cells. The outputs of the FIFO memories 8 of each pair are connected together to a corresponding one of outgoing g links 201 ~ 2ON.
1 o A plurality of output controllers 191 ~ 19N are connected to 11 outgoing FIFO memories CBR1 ~ CBRN and VBR1 ~ VBRN, respectively.
12 Each output controller includes an idle space (cell) counters 30 and 32 13 respectively connected to the associated FIFO memories to identify the 14 type of cells stored in the associated FIFO memory using their cell type field and detect the number of cells of particular type that can be stored in 16 each of the associated FIFO memories. Comparators 31 and 33 are 17 connected to the output of idle space counters 30 and 32, respectively, for 18 making a comparison between the idle space count from the respective 19 idle space counter with reference values N and 2N to produce a logic-O
(idle) which indicates that a destination FIFO memory has a sufficient 21 amount of idle space for accepting cells or a logic logic-1 indicating that it 22 has not.
23 More specifically, comparator 31 produces a O if the idle space 24 count in the FIFO memories CBR; (where i = 1, 2, , N) is equal to or 25 greater than N or a 1 if the idle space count is smaller than N.
26 Comparator 31 further produces a O if the idle space count in the FIFO
27 memories CBR; is equal to or greater than 2N or a 1 if the idle space 28 count is smaller than 2N. Likewise, comparator 33 produces a O if the idle 29 space count in the FIFO memories VBR; is equal to or greater than N or a 3 0 1 if the idle space count is smaller than N. Comparator 33 further produces a 0 if the idle space count in the FIFO memories YBR; is equal to 2 or greater than 2N or a 1 if the idle space count is smaller than 2N.
3 A priority selector 34 is further provided in each of the output 4 controllers 19. Priority selector 34 is connected to the FIFO memories of 5 the associated pair for reading a CBR cell first from the CBR memory of 6 the pair if a VBR cell is simultaneously stored in the VBR memory of the 7 pair.
Description of the Related Art 11 In a packet switching system of the input and output buffering 12 type, as described in a paper "A very high-speed ATM switch with input 13 and output buffers", Yukihiko Doi et al, 155'92 pages 231-235, incoming 14 packets are stored in an input buffer and launched onto a self-routing network where it is routed to a destination output buffer according to the 16 routing information of the packets. To achieve high throughput, it is 17 necessary to provide as many high capacity output buffers as possible for 18 bursty traffic and to provide a high speed scheduling algorithm for 19 multicast traffic. It is still desirable to reduce the amount of output buffers required and to simplify the scheduling algorithm for both point-to-point 21 and multicast traffic.
23 It is therefore an object of the present invention to provide a high 24 throughput packet switching system which eliminates the need for high capacity output buffers.
26 Another object of the present invention is to provide a high 27 throughput packet switching system which can be implemented with a 28 simplified scheduling algorithm for both point-to-point and multicast 2 9 traffic.
3 0 According to a broader aspect of the present invention, there is ~r~ NE-562 provided a packet switching system comprising a plurality of input buffers 2 connected respectively to a plurality of incoming links and a plurality 3 output buffers connected respectively to a plurality of outgoing links. A
4 self-routing network is connected between the input and output buffers for s routing packets from the input buffers to the output buffers according to 6 routing information contained in their header. A plurality of output 7 controllers are associated respectively with the output buffers. Each 8 output controller determines the idle space of the associated output buffer 9 which is available for storing additional packets and determines whether 10 the idle space is greater than a predetermined value. If the idle space is 11 determined to be greater than the predetermined value, an idle status bit 12 is generated and if the idle space is determined to be smaller than the 13 predetermined value, a busy status bit is generated. A plurality of input 14 controllers are associated respectively with the input buffers for storing the 15 idle and busy status bits from the output controllers in an idle/busy 16 memory and writing an incoming pacl<et into the associated input buffer.
17 Each input controller reads a packet from the associated input buffer onto 18 the self-routing network if an idle status bit is stored in the idle/busy 19 memory corresponding to the destination of the stored packet.
According to a second aspect of the present invention, there is 21 provided a packet switching system which comprises input buffers 22 connected respectively to incoming links, output buffers connected 23 respectively to outgoing links, and a self-routing network for routing 24 packets from the input buffers to the output buffers according to routing 25 information contained in the packets. A plurality of output controllers are 2 6 associated respectively with the output buffers for determining an idle 27 space of the associated output buffer which is available for storing 28 additional point-to-point packets and additional multicast packets. Each 29 output controller determines whether the idle space of point-to-point 3 o packets is greater than a first predetermined value and determines whether the idle space is greater than a second predetermined value 2 smaller than the first predetermined value, and generates a first idle status 3 bit or a first busy status bit into an idle/busy status memory if the idle4 space is determined to be greater or smaller than the first predetermined s value, respectively, and generates a second idle status bit or a second 6 busy status bit if the idle space is determined to be greater or smaller than 7 the second predetermined value, respectively. A plurality of input 8 controllers are associated respectively with the input buffers for storing the 9 first idle and busy status bits and the second idle and busy status bits in an idle/busy memory and storing an incoming point-to-point packet into the 11 associated input buffer and reading it if a first idle status bit is stored in the 12 idle/busy memory corresponding to the destination of the point-to-point 13 packet, and writing an incoming multicast packet into the associated input14 buffer and reading it if a second idle status bit is stored in the idle/busy memory corresponding to the incoming multicast packet.
17 The present invention will be described in further detail with 18 reference to the accompanying drawings, in which:
19 Fig. 1 is a block diagram of an ATM self-routing switching system according to the present invention;
21 Fig. 2 is a table illustrating the idle/busy status bits generated by 22 an output controller according to different cell types and stored in the 23 idle/busy status memory of each input controller;
24 Fig. 3 is a flowchart of a sequence of instructions performed by a selector of an input controller when a cell is read out of an associated RIRO
2 6 memory; and 27 Fig. 4 is a modified version of the flowchart of Fig. 3.
29 Referring now to Fig. 1, there is shown an asynchronous transfer 3û mode (ATM) switching system according to the present invention. The switching system comprises a plurality of line circuits 111 ~ 1 lN which 2 respectively serve as interfaces between incoming links 1O1 ~ 1ON and 3 input buffers, or random-in-random-out memories 121 ~ 12N. Connected 4 respectively to the line circuits 111 ~ 11 N and RIRO memories 121 ~ 12N
s are input controllers 131 ~ 13N, each of which provides address control 6 on incoming ATM cells to determine their write and read addresses of the 7 associated RIRO memory in a manner as will be described in detail later.
8 A header translation table 14 is connected to the line circuits 111 ~ 11N to 9 translate the VCI/VPI (virtual call identifier/virtual path identifier) field 10 contained in the header of each incoming packet, called "ATM cell" to an 11 outgoing link address (OLA) that specifies the appropriate outgoing link of 12 the switching system in a well known manner. Each incoming cell 13 contains a cell type field in its header to indicate the type of the cell as 14 constant bit rate (CBR), variable bit rate (VBR), a point-to-point, or multicast 15 data or a combination of these. ~ollowing the header translation on an 1 6 incoming ATM cell, each line circuit 11; (where i = 1, 2, N) supplies the 17 cell type (CT) data and the outgoing iink address (OLA) to the associated 18 input controller 13; and the whole contents of the cell to the associated 19 RIRO memory 12; where the cell is stored in a location specified by a write address WA supplied from input controller 13; and eventually read out of 21 the RIRO memory 12; in response to a read address RA from input 2 2 controller 13;.
23 The outputs of RIRO memories 121 ~ 12N are connected to a self-24 routing network 15 which includes a time division bus 16, on which the outputs of RIRO memories 12 are time-division multiplexed, and a plurality 2 6 of address filters 171 ~ 1 7N connected to the bus 16. Address filters 1 7j 27 are provided corresponding respectively to the outgoing links 20; and are 2 8 assigned the output link address (OLA) of the corresponding output link 29 plus two cell type identifiers identifying respectively CBR and VBR cells.3 o Each address filter 17 has two output terminals for respectively delivering CBR and VBR cells to the output buffers of a corresponding pair. ~ach 2 address filter allows passage of those ATM ceils to one of the output 3 buffers of the corresponding pair if it contains the output link address of 4 the address filter and one of the cell type identifiers of the address filter.s The outgoing buffers are implemented with first-in-first-out memories 6 CBR1 ~ CBRN for exclusively storing CBR cells and FIFO memories VBR1 ~
7 VBRN for exclusively storing VRB cells. The outputs of the FIFO memories 8 of each pair are connected together to a corresponding one of outgoing g links 201 ~ 2ON.
1 o A plurality of output controllers 191 ~ 19N are connected to 11 outgoing FIFO memories CBR1 ~ CBRN and VBR1 ~ VBRN, respectively.
12 Each output controller includes an idle space (cell) counters 30 and 32 13 respectively connected to the associated FIFO memories to identify the 14 type of cells stored in the associated FIFO memory using their cell type field and detect the number of cells of particular type that can be stored in 16 each of the associated FIFO memories. Comparators 31 and 33 are 17 connected to the output of idle space counters 30 and 32, respectively, for 18 making a comparison between the idle space count from the respective 19 idle space counter with reference values N and 2N to produce a logic-O
(idle) which indicates that a destination FIFO memory has a sufficient 21 amount of idle space for accepting cells or a logic logic-1 indicating that it 22 has not.
23 More specifically, comparator 31 produces a O if the idle space 24 count in the FIFO memories CBR; (where i = 1, 2, , N) is equal to or 25 greater than N or a 1 if the idle space count is smaller than N.
26 Comparator 31 further produces a O if the idle space count in the FIFO
27 memories CBR; is equal to or greater than 2N or a 1 if the idle space 28 count is smaller than 2N. Likewise, comparator 33 produces a O if the idle 29 space count in the FIFO memories VBR; is equal to or greater than N or a 3 0 1 if the idle space count is smaller than N. Comparator 33 further produces a 0 if the idle space count in the FIFO memories YBR; is equal to 2 or greater than 2N or a 1 if the idle space count is smaller than 2N.
3 A priority selector 34 is further provided in each of the output 4 controllers 19. Priority selector 34 is connected to the FIFO memories of 5 the associated pair for reading a CBR cell first from the CBR memory of 6 the pair if a VBR cell is simultaneously stored in the VBR memory of the 7 pair.
8 The comparators 31 and 33 of each output controller supply 9 their idle/busy status bits to a write circuit 21. Write circuit 21 sequentially 10 selects the output controllers to receive their output signals and produces 11 a write address signal and broadcasts it together with the idle/busy status 12 bits to all input controllers 13.
13 Each input controller 13 includes an input selector 40 and an 14 output selector 44. Connected between the input and output selectors 40 15 and 44 are a plurality of FIFO memories 41, 42, 431 ~ 43N for respectively ~ 6 storing different types (priority and destination) of cells. An idle address 17 queue 45 is connected between an output terminal of selector 44 and an 18 input of selector 40 for storing idle addresses that can be used as a write 19 address for each incoming cell. Further provided in each input controller 20 is an idle/busy memory 46 for storing the idle/busy status bits broadcast 21 from the write circuit 21 as shown in Fig. 2.
22 The selector 40 of each input controller receives the CT and OL~
2 3 fields of an incoming cell from the associated line circuit 11. On receiving 24 the CT/OLA data, selector 40 reads an idle address from queue 45 and 25 supplies it to the write address input of the associated RIRO memory 12 26 for writing the incoming cell into the memory 12. At the same time, it 27 appends the CT/OLA data to the write address to form a read address 28 signal and supplies it to one of the memories 41, 42, 431 ~ 43N according 29 to the type of the cell now stored in the RIRO memory 12.
3 0 CBR cells of either point-to-point or multicast type are stored in queue 41. VBR multicast cells are stored in queue 42 and VBR point-to-2 point cells are stored into one of the memories 431 ~ 43N according to 3 their destinations indicated by their OLA data. Note that CBR cells are 4 given highest priority, VBR multicast cells second priority, and VBR point-to-point cells lowest priority.
6 The operation of the output selector 44 will be described with 7 reference to Fig. 3. Selector 44 receives the system clock to determine the 8 slot timing for reading an address signal (step 50), set a variable Q to zero 9 (step 51), and accesses the output end of queues 41, 42 and 43, starting with queue 41 to determine whether an address signal is stored in that 11 queue (step 52). If there is one, control branches at step 52 to step 53 to 12 read the stored address signal and apply the CT and OLA data of the 13 address signal to the idle/busy memory 46. An idle/busy status bit is 14 therefore read out of a location of the idle/busy memory 46 corresponding to the cell to be read out of the associated RIRO memory 16 12. At step 54, the variable Q is incremented by 1 and, at step 55, control 1 7 determines whether the idle/busy status bit frGm the idle/busy memory 18 46 is 1 or 0. If the idle/busy status bit is 1, control returns to step 52 to 19 repeat the process on the output end of the next queue, and if it is 0, control branches to step 56 to supply the address data retrieved at step 21 53 to the associated RIRO memory 12 as a read address and to idle 22 address queue 45 as an idle address. Control proceeds to step 57 to 23 check to see if the variable Q is equal to K which indicates the number of24 memories 41, 42 and 43. If Q < K, control returns to step 52 to repeat theabove process on the next queue, and if Q = K, it returns to step 50. If the 26 decision at step 52 is negative, step 58 is executed by incrementing the 27 variable Q by 1 and the value of Q is then checked at step 56.
28 In this way, those cells on which decision is made that their 2 9 destination output buffers are not sufficient to accept are left in their 3 0 memories until the destination output buffers are made available.
N'E-562 - 2 ~ ~ 2 5 2 8 ~, The advantageous effect of the present invention is that the 2 storage capacity of each output buffer can be reduced and scheduling of 3 cells to be launched into the self-routing network 15 from each input 4 buffer can be performed at relatively low speed.
A modified embodiment is shown in Fig. 4 in which priorities are 6 assigned to memories 43 by taking into account the number of address 7 signals stored in each of these memories 43 as well as the cell type of the 8 stored address signals. As illustrated, step 60 is provided between steps 9 51 and 52 of flowchart of Fig. 3 for counting the address signals stored in 0 each of the memories 41, 42, 431 ~ 43N and priorities are respectively 11 assigned to these memories according to their stored address counts and 12 their cell types, so that address signals are read from these memories 13 according to the assigned priorities at step 52.
22 The selector 40 of each input controller receives the CT and OL~
2 3 fields of an incoming cell from the associated line circuit 11. On receiving 24 the CT/OLA data, selector 40 reads an idle address from queue 45 and 25 supplies it to the write address input of the associated RIRO memory 12 26 for writing the incoming cell into the memory 12. At the same time, it 27 appends the CT/OLA data to the write address to form a read address 28 signal and supplies it to one of the memories 41, 42, 431 ~ 43N according 29 to the type of the cell now stored in the RIRO memory 12.
3 0 CBR cells of either point-to-point or multicast type are stored in queue 41. VBR multicast cells are stored in queue 42 and VBR point-to-2 point cells are stored into one of the memories 431 ~ 43N according to 3 their destinations indicated by their OLA data. Note that CBR cells are 4 given highest priority, VBR multicast cells second priority, and VBR point-to-point cells lowest priority.
6 The operation of the output selector 44 will be described with 7 reference to Fig. 3. Selector 44 receives the system clock to determine the 8 slot timing for reading an address signal (step 50), set a variable Q to zero 9 (step 51), and accesses the output end of queues 41, 42 and 43, starting with queue 41 to determine whether an address signal is stored in that 11 queue (step 52). If there is one, control branches at step 52 to step 53 to 12 read the stored address signal and apply the CT and OLA data of the 13 address signal to the idle/busy memory 46. An idle/busy status bit is 14 therefore read out of a location of the idle/busy memory 46 corresponding to the cell to be read out of the associated RIRO memory 16 12. At step 54, the variable Q is incremented by 1 and, at step 55, control 1 7 determines whether the idle/busy status bit frGm the idle/busy memory 18 46 is 1 or 0. If the idle/busy status bit is 1, control returns to step 52 to 19 repeat the process on the output end of the next queue, and if it is 0, control branches to step 56 to supply the address data retrieved at step 21 53 to the associated RIRO memory 12 as a read address and to idle 22 address queue 45 as an idle address. Control proceeds to step 57 to 23 check to see if the variable Q is equal to K which indicates the number of24 memories 41, 42 and 43. If Q < K, control returns to step 52 to repeat theabove process on the next queue, and if Q = K, it returns to step 50. If the 26 decision at step 52 is negative, step 58 is executed by incrementing the 27 variable Q by 1 and the value of Q is then checked at step 56.
28 In this way, those cells on which decision is made that their 2 9 destination output buffers are not sufficient to accept are left in their 3 0 memories until the destination output buffers are made available.
N'E-562 - 2 ~ ~ 2 5 2 8 ~, The advantageous effect of the present invention is that the 2 storage capacity of each output buffer can be reduced and scheduling of 3 cells to be launched into the self-routing network 15 from each input 4 buffer can be performed at relatively low speed.
A modified embodiment is shown in Fig. 4 in which priorities are 6 assigned to memories 43 by taking into account the number of address 7 signals stored in each of these memories 43 as well as the cell type of the 8 stored address signals. As illustrated, step 60 is provided between steps 9 51 and 52 of flowchart of Fig. 3 for counting the address signals stored in 0 each of the memories 41, 42, 431 ~ 43N and priorities are respectively 11 assigned to these memories according to their stored address counts and 12 their cell types, so that address signals are read from these memories 13 according to the assigned priorities at step 52.
Claims (8)
1. A packet switching system comprising:
a plurality of input buffers connected respectively to a plurality of incoming links;
a plurality output buffers connected respectively to a plurality of outgoing links;
a routing network connected between said input buffers and said output buffers for routing packets from the input buffers to the output buffers according to routing information contained in the packets;
a plurality of output controllers associated respectively with said output buffers, each of the output controllers determining an idle space of the associated output buffer which is available for storing additional packets and determining whether the idle space is greater than a predetermined value, and generating an idle status bit if the idle space is determined to be greater than said predetermined value or a busy status bit if the idle space is determined to be smaller than said predetermined value; and a plurality of input controllers associated respectively with said input buffers, each of the input controllers including memory means for storing said idle status bit and said busy status bit from said output controllers, and means for writing an incoming packet into the associated input buffer and reading the incoming packet therefrom onto the routing network if an idle status bit is stored in said memory means corresponding to the routing information of said incoming packet
a plurality of input buffers connected respectively to a plurality of incoming links;
a plurality output buffers connected respectively to a plurality of outgoing links;
a routing network connected between said input buffers and said output buffers for routing packets from the input buffers to the output buffers according to routing information contained in the packets;
a plurality of output controllers associated respectively with said output buffers, each of the output controllers determining an idle space of the associated output buffer which is available for storing additional packets and determining whether the idle space is greater than a predetermined value, and generating an idle status bit if the idle space is determined to be greater than said predetermined value or a busy status bit if the idle space is determined to be smaller than said predetermined value; and a plurality of input controllers associated respectively with said input buffers, each of the input controllers including memory means for storing said idle status bit and said busy status bit from said output controllers, and means for writing an incoming packet into the associated input buffer and reading the incoming packet therefrom onto the routing network if an idle status bit is stored in said memory means corresponding to the routing information of said incoming packet
2. A packet switching system comprising:
N input buffers connected respectively to N incoming links;
N output buffers connected respectively to N outgoing links;
a self-routing network connected between said input buffers and said output buffers for routing packets from the input buffers to the output buffers according to routing information contained in the packets;
N output controllers associated respectively with said output buffers, each of the output controllers determining an idle space of the associated output buffer which is available for storing additional packets and determining whether the idle space is greater than N, and generating an idle status bit if the idle space is determined to be greater than N or a busy status bit if the idle space is determined to be smaller than N; and N input controllers associated respectively with said input buffers, each of the input controllers including memory means for storing said idle status bit and said busy status bit from said output controllers, and means for writing an incoming packet into the associated input buffer and reading the incoming packet therefrom onto the self-routing network if an idle status bit is stored in said memory means corresponding to the routing information of said incoming packet.
N input buffers connected respectively to N incoming links;
N output buffers connected respectively to N outgoing links;
a self-routing network connected between said input buffers and said output buffers for routing packets from the input buffers to the output buffers according to routing information contained in the packets;
N output controllers associated respectively with said output buffers, each of the output controllers determining an idle space of the associated output buffer which is available for storing additional packets and determining whether the idle space is greater than N, and generating an idle status bit if the idle space is determined to be greater than N or a busy status bit if the idle space is determined to be smaller than N; and N input controllers associated respectively with said input buffers, each of the input controllers including memory means for storing said idle status bit and said busy status bit from said output controllers, and means for writing an incoming packet into the associated input buffer and reading the incoming packet therefrom onto the self-routing network if an idle status bit is stored in said memory means corresponding to the routing information of said incoming packet.
3. A packet switching system comprising:
a plurality of input buffers connected respectively to a plurality of incoming links;
a plurality of output buffers connected respectively to a plurality of outgoing links;
a self-routing network connected between said input buffers and said output buffers for routing packets from the input buffers to the output buffers according to routing information contained in the packets;
a plurality of output controllers associated respectively with said output buffers, each of the output controllers determining an idle space of the associated output buffer which is available for storing additional point-to-point packets and additional multicast packets, determining whether the idle space of point-to-point packets is greater than a first predetermined value, determining whether the idle space of multicast packets is greater than a second predetermined value smaller than said first predetermined value, generating a first idle status bit or a first busy status bit if the idle space is determined to be greater or smaller than said first predetermined value, respectively, and generating a second idle status bit or a second busy status bit if the idle space is determined to be greater or smaller than said second predetermined value, respectively;
and a plurality of input controllers associated respectively with said input buffers, each of the input controllers including memory means for storing said first idle and busy status bits and second idle and busy status bits from said output controllers, and means for writing an incoming point-to-point packet into the associated input buffer and reading the incoming point-to-point packet therefrom onto the self-routing network if a first idle bit from is stored in said memory means corresponding to the routing information of the incoming point-to-point packet, storing an incoming multicast packet into the associated input buffer and reading the incoming multicast packet therefrom onto the self-routing network if a second idle status bit is stored in said memory means corresponding to the incoming multicast packet.
a plurality of input buffers connected respectively to a plurality of incoming links;
a plurality of output buffers connected respectively to a plurality of outgoing links;
a self-routing network connected between said input buffers and said output buffers for routing packets from the input buffers to the output buffers according to routing information contained in the packets;
a plurality of output controllers associated respectively with said output buffers, each of the output controllers determining an idle space of the associated output buffer which is available for storing additional point-to-point packets and additional multicast packets, determining whether the idle space of point-to-point packets is greater than a first predetermined value, determining whether the idle space of multicast packets is greater than a second predetermined value smaller than said first predetermined value, generating a first idle status bit or a first busy status bit if the idle space is determined to be greater or smaller than said first predetermined value, respectively, and generating a second idle status bit or a second busy status bit if the idle space is determined to be greater or smaller than said second predetermined value, respectively;
and a plurality of input controllers associated respectively with said input buffers, each of the input controllers including memory means for storing said first idle and busy status bits and second idle and busy status bits from said output controllers, and means for writing an incoming point-to-point packet into the associated input buffer and reading the incoming point-to-point packet therefrom onto the self-routing network if a first idle bit from is stored in said memory means corresponding to the routing information of the incoming point-to-point packet, storing an incoming multicast packet into the associated input buffer and reading the incoming multicast packet therefrom onto the self-routing network if a second idle status bit is stored in said memory means corresponding to the incoming multicast packet.
4. A packet switching system comprising:
N input buffers connected respectively to N incoming links;
N output buffers connected respectively to N outgoing links;
a self-routing network connected between said input buffers and said output buffers for routing packets from the input buffers to the output buffers according to routing information contained in the packets;
N output controllers associated respectively with said output buffers, each of the output controllers determining an idle space of the associated output buffer which is available for storing additional point-to-point packets and additional multicast packets, determining whether the idle space of point-to-point packets is greater than M greater than N and whether the idle space of multicast packets is greater than N, generating a first idle status bit or a first busy status bit if the idle space is determined to be greater or smaller than M, respectively, and generating a second idle status bit or a second busy status bit if the idle space is determined to be greater or smaller than N, respectively; and N input controllers associated respectively with said input buffers, each of the input controllers including memory means for storing the first idle and busy status bits and the second idle and busy status bits from said output controllers, and means for writing an incoming point-to-point packet into the associated input buffer and reading the incoming point-to-point packet therefrom onto the self-routing network if a first idle status bit is stored in said memory means corresponding to the routing information of the incoming point-to-point packet, writing an incoming multicast packet into the associated input buffer and reading the incoming multicast packet therefrom onto the self-routing network if a second idle status bit is stored in said memory means corresponding to the incoming multicast packet.
N input buffers connected respectively to N incoming links;
N output buffers connected respectively to N outgoing links;
a self-routing network connected between said input buffers and said output buffers for routing packets from the input buffers to the output buffers according to routing information contained in the packets;
N output controllers associated respectively with said output buffers, each of the output controllers determining an idle space of the associated output buffer which is available for storing additional point-to-point packets and additional multicast packets, determining whether the idle space of point-to-point packets is greater than M greater than N and whether the idle space of multicast packets is greater than N, generating a first idle status bit or a first busy status bit if the idle space is determined to be greater or smaller than M, respectively, and generating a second idle status bit or a second busy status bit if the idle space is determined to be greater or smaller than N, respectively; and N input controllers associated respectively with said input buffers, each of the input controllers including memory means for storing the first idle and busy status bits and the second idle and busy status bits from said output controllers, and means for writing an incoming point-to-point packet into the associated input buffer and reading the incoming point-to-point packet therefrom onto the self-routing network if a first idle status bit is stored in said memory means corresponding to the routing information of the incoming point-to-point packet, writing an incoming multicast packet into the associated input buffer and reading the incoming multicast packet therefrom onto the self-routing network if a second idle status bit is stored in said memory means corresponding to the incoming multicast packet.
5. A packet switching system as claimed in claim 1, 2, 3 or 4, wherein each of said input controllers comprises:
an idle address queue;
a high priority queue and a low priority queue;
first selector means for retrieving an address signal from said idle address queue and writing an incoming packet into a location of the associated input buffer specified by the retrieved address signal, and writing the retrieved address signal into one of said high and low priority queues according to priority of the incoming packet;
second selector means for retrieving an address signal from each of said high and low priority queues, retrieving an idle/busy status bit from said memory means corresponding to the retrieved address signal, determining whether the retrieved idle/busy status is 0 or 1, and supplying the retrieved address signal to said idle address queue and to the associated input buffer when the retrieved idle/busy status bit is determined to be 0 for reading a packet from the associated input buffer onto the self-routing network, or leaving the retrieved address signal in said first and second priority queues if the retrieved idle/busy status bit is determined to be 1, each of said output buffers including a high priority memory for storing packets of high priority and a low priority memory for storing packets of low priority, each of the output controllers including means for forwarding a packet from the high priority memory of the associated output buffer to the associated outgoing link earlier than a packet from the low priority memory of the associated output buffer when more than one packet exists simultaneously in said high and low priority memories of the associated output buffer.
an idle address queue;
a high priority queue and a low priority queue;
first selector means for retrieving an address signal from said idle address queue and writing an incoming packet into a location of the associated input buffer specified by the retrieved address signal, and writing the retrieved address signal into one of said high and low priority queues according to priority of the incoming packet;
second selector means for retrieving an address signal from each of said high and low priority queues, retrieving an idle/busy status bit from said memory means corresponding to the retrieved address signal, determining whether the retrieved idle/busy status is 0 or 1, and supplying the retrieved address signal to said idle address queue and to the associated input buffer when the retrieved idle/busy status bit is determined to be 0 for reading a packet from the associated input buffer onto the self-routing network, or leaving the retrieved address signal in said first and second priority queues if the retrieved idle/busy status bit is determined to be 1, each of said output buffers including a high priority memory for storing packets of high priority and a low priority memory for storing packets of low priority, each of the output controllers including means for forwarding a packet from the high priority memory of the associated output buffer to the associated outgoing link earlier than a packet from the low priority memory of the associated output buffer when more than one packet exists simultaneously in said high and low priority memories of the associated output buffer.
6. A packet switching system as claimed in claim 1, 2, 3 or 4, wherein each of said input controllers comprises:
an idle address queue;
a plurality of busy address queues;
first selector means for retrieving an address signal from said idle address queue and writing an incoming packet into the associated input buffer corresponding to the retrieved address signal, and writing the retrieved address signal into one of said busy address queues according to the routing information of the incoming packet; and second selector means for retrieving an address signal from each of said busy address queues, retrieving an idle/busy status bit from said memory means corresponding to the address signal retrieved from said busy address queues, determining whether the retrieved idle/busy status is 0 or 1, and supplying the retrieved address signal to said idle address queue and to the associated input buffer if the retrieved idle/busy status bit is determined to be 0 for reading a packet from the associated input buffer onto the self-routing network, or leaving the retrieved address signal in said busy address queues if the retrieved idle/busy status bit is determined to be 1.
an idle address queue;
a plurality of busy address queues;
first selector means for retrieving an address signal from said idle address queue and writing an incoming packet into the associated input buffer corresponding to the retrieved address signal, and writing the retrieved address signal into one of said busy address queues according to the routing information of the incoming packet; and second selector means for retrieving an address signal from each of said busy address queues, retrieving an idle/busy status bit from said memory means corresponding to the address signal retrieved from said busy address queues, determining whether the retrieved idle/busy status is 0 or 1, and supplying the retrieved address signal to said idle address queue and to the associated input buffer if the retrieved idle/busy status bit is determined to be 0 for reading a packet from the associated input buffer onto the self-routing network, or leaving the retrieved address signal in said busy address queues if the retrieved idle/busy status bit is determined to be 1.
7. A packet switching system as claimed in claim 1, 2, 3 or 4, wherein each of said input controllers comprises:
an idle address queue;
a plurality of busy address queues;
first selector means for retrieving an address signal from said idle address queue and writing an incoming packet into the associated input buffer corresponding to the retrieved address signal, and writing the retrieved address signal into one of said busy address queues according to the routing information of the incoming packet; and second selector means for retrieving an address signal from said busy address queues according priority of packets stored therein, retrieving an idle/busy status bit from said memory means corresponding to the address signal retrieved from said busy address queues, determining whether the retrieved idle/busy status is 0 or 1, and supplying the retrieved address signal to said idle address queue and to the associated input buffer if the retrieved idle/busy status bit is determined to be 0 for reading a packet from the associated input buffer onto the self-routing network, or leaving the retrieved address signal in said busy address queues if the retrieved idle/busy status bit is determined to be 1.
an idle address queue;
a plurality of busy address queues;
first selector means for retrieving an address signal from said idle address queue and writing an incoming packet into the associated input buffer corresponding to the retrieved address signal, and writing the retrieved address signal into one of said busy address queues according to the routing information of the incoming packet; and second selector means for retrieving an address signal from said busy address queues according priority of packets stored therein, retrieving an idle/busy status bit from said memory means corresponding to the address signal retrieved from said busy address queues, determining whether the retrieved idle/busy status is 0 or 1, and supplying the retrieved address signal to said idle address queue and to the associated input buffer if the retrieved idle/busy status bit is determined to be 0 for reading a packet from the associated input buffer onto the self-routing network, or leaving the retrieved address signal in said busy address queues if the retrieved idle/busy status bit is determined to be 1.
8. A packet switching system as claimed in claim 1, 2, 3 or 4, further comprising means for sequentially receiving an idle/busy status bit from each of said output controllers and generating a write address signal and broadcasting the write address signal together with the idle/busy status to all of said input controllers for writing the idle/busy status bit into the memory means of said input controllers.
Applications Claiming Priority (2)
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| JP34502092A JP2655464B2 (en) | 1992-12-25 | 1992-12-25 | Packet switching method |
| JPJP4-345020 | 1992-12-25 |
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| CA2112528A1 CA2112528A1 (en) | 1994-06-26 |
| CA2112528C true CA2112528C (en) | 1999-07-20 |
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| CA002112528A Expired - Fee Related CA2112528C (en) | 1992-12-25 | 1993-12-29 | Packet switching system for forwarding packets from input buffers using idle/busy status of output buffers |
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| EP (1) | EP0603916B1 (en) |
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| US11552737B1 (en) | 2004-08-02 | 2023-01-10 | Genghiscomm Holdings, LLC | Cooperative MIMO |
| US7505405B2 (en) * | 2004-10-08 | 2009-03-17 | International Business Machines Corporation | Method, apparatus, and computer program product for optimizing packet flow control through buffer status forwarding |
| WO2006059384A1 (en) * | 2004-12-02 | 2006-06-08 | Fujitsu Limited | Data buffer device, cache device, and data buffer control method |
| US8315274B2 (en) * | 2006-03-29 | 2012-11-20 | Honeywell International Inc. | System and method for supporting synchronous system communications and operations |
| WO2018054457A1 (en) * | 2016-09-21 | 2018-03-29 | Telefonaktiebolaget Lm Ericsson (Publ) | Methods and apparatus for routing of data packets over a network |
| US10243773B1 (en) | 2017-06-30 | 2019-03-26 | Genghiscomm Holdings, LLC | Efficient peak-to-average-power reduction for OFDM and MIMO-OFDM |
| US10637705B1 (en) | 2017-05-25 | 2020-04-28 | Genghiscomm Holdings, LLC | Peak-to-average-power reduction for OFDM multiple access |
| US11917604B2 (en) | 2019-01-25 | 2024-02-27 | Tybalt, Llc | Orthogonal multiple access and non-orthogonal multiple access |
| EP3915236A4 (en) | 2019-01-25 | 2023-05-24 | Genghiscomm Holdings, LLC | Orthogonal multiple access and non-orthogonal multiple access |
| US11343823B2 (en) | 2020-08-16 | 2022-05-24 | Tybalt, Llc | Orthogonal multiple access and non-orthogonal multiple access |
| WO2020242898A1 (en) | 2019-05-26 | 2020-12-03 | Genghiscomm Holdings, LLC | Non-orthogonal multiple access |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6367047A (en) * | 1986-09-08 | 1988-03-25 | Nippon Telegr & Teleph Corp <Ntt> | Packet switch |
| JP2533103B2 (en) * | 1987-02-25 | 1996-09-11 | 富士通株式会社 | Packet exchange method |
| JPS63227150A (en) * | 1987-03-16 | 1988-09-21 | Nec Corp | Asynchronous time division multiplex exchange system |
| JP2753254B2 (en) * | 1988-04-06 | 1998-05-18 | 株式会社日立製作所 | Packet exchange system |
| CA1320257C (en) * | 1989-04-20 | 1993-07-13 | Ernst August Munter | Method and apparatus for input-buffered asynchronous transfer mode switching |
| US5014265A (en) * | 1989-11-30 | 1991-05-07 | At&T Bell Laboratories | Method and apparatus for congestion control in a data network |
| US5291482A (en) * | 1992-07-24 | 1994-03-01 | At&T Bell Laboratories | High bandwidth packet switch |
-
1992
- 1992-12-25 JP JP34502092A patent/JP2655464B2/en not_active Expired - Lifetime
-
1993
- 1993-12-27 DE DE69333206T patent/DE69333206T2/en not_active Expired - Lifetime
- 1993-12-27 US US08/173,214 patent/US5412648A/en not_active Expired - Lifetime
- 1993-12-27 EP EP93120960A patent/EP0603916B1/en not_active Expired - Lifetime
- 1993-12-29 CA CA002112528A patent/CA2112528C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| EP0603916B1 (en) | 2003-09-17 |
| JPH06197128A (en) | 1994-07-15 |
| EP0603916A2 (en) | 1994-06-29 |
| DE69333206T2 (en) | 2004-07-01 |
| EP0603916A3 (en) | 1996-12-27 |
| CA2112528A1 (en) | 1994-06-26 |
| DE69333206D1 (en) | 2003-10-23 |
| US5412648A (en) | 1995-05-02 |
| JP2655464B2 (en) | 1997-09-17 |
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| EEER | Examination request | ||
| MKLA | Lapsed |