CA2115731C - Dynamically programmable bus arbiter with provisions for historical feedback and error detection and correction - Google Patents
Dynamically programmable bus arbiter with provisions for historical feedback and error detection and correction Download PDFInfo
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- CA2115731C CA2115731C CA002115731A CA2115731A CA2115731C CA 2115731 C CA2115731 C CA 2115731C CA 002115731 A CA002115731 A CA 002115731A CA 2115731 A CA2115731 A CA 2115731A CA 2115731 C CA2115731 C CA 2115731C
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- 230000004044 response Effects 0.000 description 5
- 241001522296 Erithacus rubecula Species 0.000 description 4
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
- G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
Abstract
An arbitration circuit that uses a unique history register that is combined with a value representing bus requests to index into a table. All possible combinations of history register requests are stored in the table along with a corresponding grant. A block of the table is selected by the history register, and then the request is used to index into the block to determine which request receives a grant. The grant is then shifted into the history register. Advantageously, more than one table may be stored in memory which can be selected by an arbiter controller.
Description
2:~~573~
-1_ DYNAMICALLY PROGRAMMABLE BUS ARBTTER WITH PROVISIONS FOR
HISTORICAL FEEDBACK AND ERROR DETECTION AND CORRECTION
Technical Field This invention relates to the field of computer bus arbitration and, more specifically, to the field of providing bus art>itration which takes previous bus usage into account and provides for selectable bus arbitration algorithms.
Background of the Invention As more devices are attached to the main memory bus in a computer system, there is more contention for use of the bus. In response to such contention, many different arbitration circuits have been proposed in order to give either fair access or priority access to the bus and thus, to memory resources.
For example, U. S. Patent No. ~~,195,185, which issued in the name of G. B. Marenin on March 16, 1993, disclose<; an arbitration device which determines bus access based on a priority scheme, and ~~lso has a system to dynamically change the priority of any device. This system doe~~ not, however, provide flexibility in the basic arbitration scheme; it only responds to a device's increase of its own priority.
It also cannot take into account which device previously used the bus in order to give either parity or priority to the other users. Finally, this system is locked into the priority scheme; it cannot be changed from a priority to a parity scheme when appropriate.
A further bus priority scheme is. described in U. S. Patent No. 4,979,100, which issued in the name of Makris, et al., on December 18, 1990. Makris discloses an arbiter circuit which provides two different levels of priority of access to the bus for each processing unit and keeps track of the relative percentages of time of access for the different priority levels. This system provides for interruption of lower priority bus usage by higher priority process units. This system requires complicated overhead to track such bus usage, and is not responsive to previous bus usage by any one system.
Neither of these systems provides for flexible, dynamically changeable arbitration systems which can start in a known state and change from one arbitration scheme system to another as conditions change nor do they react to the past allocation. Therefore, a problem in the art i~; that there is no bus usage arbiter that provides a dynamic priority scheme with provisions for historical feedback in its grant selection.
21 ~ 5~3 ~ a Summary of the Invention This problem is solved and a technical advance is achieved in the art by an arbitration circuit which takes into account previous bus access as part of the decision to service a requester. In particular, it provides a unique history register that generates a value representing past bus requests which is combined with a value representing current bus requests to acce~;s a location in memory. A potential grant is defined and stored in each location in memory for each possible combination of historical requests and current requests. selection of a potential grant is achieved selecting a section of memory by using the history register as the high order bits of memory address, and then using the currc;nt request as the low order bits of the memory address in order to determine thc: one grant output to be awarded. The grant is also shifted into the history register. ~cdvantageously, more than one table may be stored in memory to selectably provide a plurality of algorithms.
In accordance with one aspect of the present invention there is provided a system for providing arbitration of allocation requests from a plurality of requesters based on the history of a plurality of prior grants of requests by such requesters, said system comprising: input means for receiving requests from said plurality of requesters; storage means for defining a plurality of grants, said plurality of grants comprising a grant for each possible configuration of requests and prior requests;
history means for sequentially/recording :;aid plurality of previous grants;
and control means connected to said history means, said input means and said storage means for applying said received requests from said input means and said plurality of previous grants from said history means directly to said storage means and selecting one of said plurality of grants responsive to said received requests and said plurality of previous grants, providing a grant indication representative of said selected grant to one of said requesters.
In accordance with another ;aspect of the present invention there is provided a system for providing arbitration of allocation requests from a plurality of requesters based on the history of a plurality of prior grants of requests by such requesters, said system comprising: i~tput means for receiving requests from said plurality of requesters; storage means for defining a plurality of grants, said plurality of grants comprising a grant for each possible configuration of requests and prior requests; history means for recording saic'. plurality of previous grants, said history -2a- 21 157 3 1 means comprising a register wherein each grant is moved sequentially through said register; a writable mask register, wherein said mask register selectively alters portions of the contents of said history means; control means connected to said history means, said input means and said storage means for applying said received requests from said input means and said plurality of previous grants from said history means to said storage means and selecting one of said plurality of grants responsive thereto, providing a grant indication representative of said selected grant to one of said requesters.
In accordance with yet another aspect of the present invention there is provided a system for providing arbitration of bus allocation requests from a plurality of requester, said system comprising: input means for receiving requests from said plurality of requesters; output means for ~~ommunicating grants to said plurality of requesters; a storage means containing a :plurality of look-up tables, each of said look-up tables having a plurality of grants, each of said plurality of grants 1 S corresponding to each of the possible request inputs; a history register for sequentially recording the history of a plurality of previous bus request grants; and control means connected to said output means, said input means, said history register and said storage means for using said history of from said history register to select one of said plurality of look-up tables, applying said requests directly to said look-up table to select one of said plurality of grants, and providing grant authorization signals representative of said selected grant to ore of said requesters via said output means.
In accordance with still yet .another aspect of the present invention there is provided a system for providing arbitration of bus allocation requests from a plurality of requesters, said system comprising: input means for receiving request from said plurality of requesters; a storage means containing a plurality of look-up tables, each of said look-up tables having a plurality of grants, each of said plurality of grants corresponding to each of the possible request inputs; a history register for recording the history of a plurality of previous bus request grants; a mask register connected to said history register, said m~~sk register being dynamically writable and capable of over-writing said history register to alter said determined arbitration state;
and control means connected to said output means, said input means, said look-up table and said history register for selecting one of said plurality of look-up tables, applying said requests from said input means and said previous bus request grants .,m.;
-2b- 21 157 3 1 from said history register to said look-up table to select one of said plurality of grants, and providing grant authorization signals representative of said selected grant to one of said requesters.
In accordance with still yet ~~nother aspect of the present invention there is provided a method for providing arbitr~~tion of bus allocation requests from a plurality of requesters based on the history of a plurality of prior bus request grants, said method comprising: receiving a plurality of requests for use of said bus;
responsive to said plurality of requests, applying a history register containing said plurality of previous grants in sequential ~~rder to said plurality of requests to determine a selected arbitration state; using said selected arbitration state as an index into an arbitration state table, said arbitration state table comprising a plurality of arbitration states and a corresponding plmrality of grants; and issuing one of said plurality of grants directly indexed by said selected arbitration state to said requesters.
In accordance with still yet another aspect of the present invention there is provided a method for providing arbitration of bus allocation requests from a plurality of requesters based on the history of a plurality of prior bus request grants, said method comprising: receiving a plurality of requests for use of said bus;
responsive to said plurality of requests, applying a history register containing said plurality of previous grants to said plurality of requests to determine a selected arbitration state; using said selected arbitration state as an index into an arbitration state table, said arbitration state table comprising a plurality of arbitration states and a corresponding plurality of grants; and issuing one of said plurality of grants indexed by said selected arbitration state to said rf:questers, wherein said history register is dynamically variable, and wherein applying said history register to said request also includes varying said history register.
Brief Description of the Drawings F1G. I is a block diagram of a computer system, including an arbiter circuit according to an exemplary embodiment of this invention;
FIG. 2 is a block diagram of the arbiter circuit as shown in FIG. 1;
FIG. 3 is a state diagram of the arbiter circuit of FIG. 2;
FIG. 4 is a timing diagram of the arbiter circuit of FIG. 2;
FIG. 5 is an illustration of the history register;
FIG. 6 is an illustration of the history register of an exemplary embodiment of this invention at initialization;
-2c-FIG. 7 is an example of a block of memory illustrating a distribution of grants based on requests; and FIGS. 8-12 are illustrations of the shifting of data through the history register according to an exemplary embodiment of this invention.
Detailed Description FIG. 1 is a block diagram illustrating an exemplary embodiment of this invention in the context of a computer system 5 including a bus 10 and a memory device 12. For purposes of describing the preferred embodiment of this invention, there are four devices that share bus 10 a.nd memory 12. Central Processing Unit (CPU) 14 is a general purpose CPU, whi~~h manipulates and performs other functions as is known in the art on data stored in memory 12. In this exemplary embodiment, there are three Direct Memory Access (DMA) devices 16, 18, and 20 also connected to bus 10. DMA devices 16, 18, and 20 directly read and write locations in memory 12 via bus 10. In order to prevent more than one device from accessing bus 10 at the same time, arbiter circuit 22, according to an exemplary embodiment of this invention, controls access to bus 10 and thus memory 12. Arbiter circuit 22 is not limited to memory access, and may generally control bus access, or access to any device.
When one of devices 14, 16, 18, or 20 wants to access bus 10 (and/or memory 12), it raises a request on request lead 24, 26, 28, or 30, respectively.
Arbiter circuit 22 determines which of the devices' requests will be granted, as will be described later, and in response generate: a grant signal on one of grant leads 32, 34, 36, or 38. In this preferred embodiment, only one grant at a time will be issued.
However, it is within the scope of one skilled in the art that a system could conceivably issue multiple grants. When the device is finished with its bus access, a "done" signal is issued on lead 40. If an ern~r is detected during bus arbitration, arbiter circuit 22 informs CPU 14 on error lead 42, as will be described further, below.
Turning now to FIG. 2, an arbiter circuit 22 according to an exemplary embodiment of this invention is shown. The arbiter 22 of this exemplary embodiment includes an arbiter controller 1n2, arbiter memory 104, which is primarily RAM, but also included a block oi~ ROM 105, a grant latch 106, a history register 108, request latch 110, an initialization device (including ROM in the preferred embodiment of this invention) 112;, an algorithm select register 114, a mask register 116, and a table select register 118. Requests for control of bus 10 arrive at request latch 110 from devices 14, l6, 18, and 20 (FIG. 1) on request leads 24, 26, 28, and 30. In this exemplary E;mbodsment, the arrival of such requests triggers request latch to OR all request leads and sends a signal on ARBREQ
lead 120 indicating to controller 102 that there is a bus request pending.
Controller 102, in response, sends a signal via load line 122 to latch the requests in request latch 110. At this point, the requests, are sent via bus 124 to memory 104.
The data from history register 108 is then available on history bus 126. The generation of data in the history register will be described later.
The value formed by the bits of the request on bus 124 and a value formed by the bits of the history register on history bus 126 are combined and used as an address into memory 104 which outputs the next grant. Each possible combination of history register and request latch values is stored in memory along with the associated grant that follows the selected arbitration algorithm.
Therefore, an algorithm may be implemented simply by determining which combinations of previous grants and current requests requires the next grant.
In this manner, any algorithm may be used for selecting grants. An example is described below with reference to FIGS. 5-12. Advantageously, the value from history register 108 is used to select a section or blcxk of memory 104, which comprises the high order bits of the memory address; and the value form by the requests latched in S request latch 110 comprises the low order bits of the memory address, which is conceptually used to access the block by indexing into it. Memory 104 returns the grant selected by the address on grant bus 128.
A portion of memory 104 comprises ROM 105. ROM 105 contains at least one algorithm comprising all possible states of history register 108 and request latch 110. Alternatively, ROM 105 may be small and comprise a grant algorithm addressable by the four bits from request latch 110. ROM 105 can be used whenever an error is detected by controller 102, in order to go to a known state, and, optionally, at initialization.
Memory 104 causes the selected grant output to be placed on grant bus 128 and delivered to controller 102, history register 108, and grant latch 106.
The outputs consist of 1 of N bits (in this exemplary embodiment, N=4) asserted which defines the selected grant. When controller 102 receives the arbitration request on ARBREQ line 120, it provides a grant latch enable signal on line 130 to allow the grant to be passed to grant lines 3:', 34, 36, and 38. Controller 102 also asserts shift line 132 to cause the history register to shift the contents of grant bus 128, in parallel, into history register lOF~, and shifts the oldest previous grant out, as will be described further below. When the device that received the grant has completed its memory access, it asserts "done" line 40 which is received by controller 102, and starts a new cycle.
Mask register 116 is writable from the data portion of bus 10. The value in mask register 116 is used to mask the shirting of a particular bit through history register 108. This has the effect of erasing the history of a previously asserted grant.
Mask register 116 may be written by any device in order to alter the installed algorithm Advantageously, memory 104 contains.more than one arbitration algorithm Mask register 116 is also connected to a table select register 118.
Table select register 118 may be updated by data on the data portion of bus 10 through mask 116, in order to select a portion of memory 104 containing the algorithm desired. One table may be configured as a priority scheme and another may be configured as a parity scheme, thus providing flexibility in which type of scheme can be used at any given time.
21 15~ 7 3 1 -5 _ The preferred embodiment of tlus invention also includes a unique error detection mechanism. Optionally, each gra~it in memory 104 may have associated with it a cyclical redundancy check (CRC) value, a parity value, or other mathematical error checking value, as illusti~ated in FIG. 7. This value is sent to controller 102 along with the grant via grant bus 128. Controller 102 may then perform the check necessary and compare it to the value found in memory 104.
If an error is found, an error signal may be raised on error line 42, which is sent to CPU 14 t',FIG. 1 ) for further action.
Arbiter circuit 22 is initialized when an initialization request comes in on reset line 134 and is received at arbiter ir~idalization 112. Arbiter initialization 112 sends reset signals to conty~oller 102, memory 104, history register 108, grant latch 106, mask register 1.16, and request latch 110 over reset signal lines (not shown for clarity). As part of initialization, controller 102 causes a specified allocation algorithm stored in arbiter initialization ROM 112 to be loaded into memory 104 via line load control bus 136. The content of the data to be loaded is controlled by the algorithm select register 114. The select register 114 is loaded by CPU 14 (FTG.1) over the address and data lines of bus 10. Bus 138 provides an index into the arbiter initialization (ROM) 112, to control which arbitration algorithm is downloaded to operational memory 104.
Turning now to FIG. 3, a state machine as found in controller 102 of FIG. 2 is shown, describing the various states and the resultant level of the leads to and from controller 102. Idle state 310 is entered upon initialization.
Controller 102 remains in idle state 310 as long as there are no requests present at request latch 140 (FTG. 2). When one or more requests are received, state machine 300 transitions during the next clock cycle from idle state 310 to state S 1 320. In state S
1, the controller causes the load signal to go low, as will be described below in connection with FIG. 4, and causes the grant enable line 130 to be asserted.
State machine 300 then transitions during the next clock cycle from state S 1 320 to state S2 330. State machine 300 remains in state S2 330 until the "done"
signal is asserted. When the "done" signal is asserted, state machine 300 transitions from state S2 330 to state S3 340, wherein the load signal is asserted and the grant enable signal is released after "done" signal has been released. State machine stays in state S3 340 as long as the "done" signal is asserted. If the "done"
signal is released and the ARBREQ lead is asserted, the state machine transitions back to state S 1 320 because another arbitration request has been received, or conversely because there were a plurality of arbitration requests when the request lead was first asserted. The state machine also transitions from state S3 340 back to idle state 310 when both the "done" and the request leads are no longer asserted.
Turning now to FIG. 4, a timing diagram for state machine 300 of FIG. 3 is shown, wherein the state machine is shown transitioning completely around the exterior of state machine 300. Arbiter circuit 22 receives clock signals over clock bus 140 (FIG. 2). At some point during the idle state, one or more requests are received and the state machine transitions finm the idle state to state S 1.
The controller asserts the shift line 122 and sets the load line to low. At this time, the latched requests and the history register contents are sent to memory 104, and grants are put out on grant line 128, causing grants line to go high. At the same time, it asserts the grant latch line 130 to latch the grant output to lines 32, 34, 36, and 38 (FIGS. 1 and 2). After one clock cycle state. S 1, a transition is made to state S2, where, in response to the grant, the ARBREQ lead 120 goes low and the controller asserts the shift lead 132 for one cycle. The controller then waits in state until the "done" signal is asserted, indicating that the selected device has completed operations, at which time it transitions to smte S3 340 where the load signal 122 is asserted. At some time during state S3 the "done" signal goes low. In response to this, the controller sets the grant latch signal. to low and transitions back to the idle state.
Optionally, an additional field is associated with each grant in memory 120, as illustrated in FIG. 7, stating; the number of cycles that the device receiving the grant will use before asserting done line 40. Controller 102 uses this information to count clock cycles (from clock line 140) and starts the next state slightly before the done signal is asserted. In this manner, an arbitration circuit according to an exemplary embodiment of this invention, may be made in a pipelined configuration.
The operation of the history circuit and memory will now be explained in connection with FIGS. 5-12. In this exemplary embodiment, history register (FTG. 5) comprises twenty bits divided into ;five groups of four bits each.
Each of four sets of four bits represents a previous g~~ant. In FIG. 5, HO is the last grant. H1 is the grant previous to H0, H2 is the grant previous to H1, and H3 is the grant before H2. As each grant is made, it is shifted into H0. HO is then shifted into H1, etc., and H3 is shifted out of the history register. The final 4 bits are the "re:quest"
bits from the request latch. These are the index bits.
_,_ The history register of FIG. 5 is used to address a block of memory containing grant bits. The "index" bits maF~ directly on the request bits from the devices, as found at request latch 110. Assume, for this discussion, that only one bit in each of the previous grants of the history register is set at a time, and that all non-addressable addresses in this scheme generue an error signal. In HO-H3, only one bit in each group can be set because only one grant is given at a time in this exemplary embodiment. Optionally, these vfour registers (HO-H3) can also be encoded to save address space and make thE: RAM smaller.
In operation, the requests are entered into the system (by devices 14, 16, 18, and 20) and produce an address to the memory 104, is shown in FIG. 6 as "xxxx." This address consists of 16 possible entries. The address identifies a location in RAM that contains 4 bits of gra~its. These grants are set up according to a specific algorithm, such as that shown in 1~IG. 7. FIG. 7 illustrates a block of memory that contains a simple priority grant algorithm; however, the arbitration scheme is not required to be the "priority" scheme shown. Note also that all variations of the request leads are covered. Each variation results in one grant bit G3 through GO being set (selected) while the others are set to 0 (unselected).
The output of the memory sect7.on is used by the arbiter to grant a request (put onto grant lines 32, 34, 36, and 38, FIG. 1) and is also loaded into the HO address section. Assume that the reque~;t bits were [1001] which, according to the table of FIG. 7, results in grant 0 being ;yet [0001]. The RAM address in the next cycle appears as shown in FIG. 8.
This history register address again addresses a 16 location block of the RAM (but not the same block as illustrated in FIG. 7). One of the 16 locations is selected by the request section of the address. The data in the 16 locations is an example of the round robin algorithm with the stipulation that request 0 was granted in the last cycle. This means that if any other requests are pending, they will be serviced before request 0. In this case the next grant will be chosen from the other requests on a priority basis, although this need not be the case.
Assume the request bit pattern i:or the next cycle is still [1001]. This results in grant 3 being given on this cycle. The RAM address appears as in FIG. 9 on the next cycle. This is a new 16 location section selected by the address in the HO-H3 section of the address. This section ~~ontains the grant for any variation of the request leads possible. The grant bits are selected in this exemplary embodiment using the round robin algorithm with the stipulation that requests 0 and 3 have been granted already. If the next cycle request leads are [ 1010], then the RAM
will 21 157;6 1 _g..
respond with a grant 1 because grant 3 has been granted and grant 1 has not.
The RAM address will now appear as in FIG. 10 below for the next cycle.
These 16 locations are selected because requests 0, 1 and 3 have been previously granted. Note that request 3 was asserted and was not serviced. In the next cycle, the request address is [1100]. Tl~~e RAM responds with a grant 2 [0100]
because request 2 had not been serviced. Note again that request 3 was not serviced because of the round robin algorithm.
The new address for the RAM appears as in FIG. 11 for the next cycle.
All of the requests have been serviced, and if the request address for the next cycle is [1011], the result will be a grant 0 because is was the earliest served. The new RAM
address is then as in FIG. 12.
Each section of the RAM consists of a set of locations that define all of the possible states of the grant bits in accordance with the round robin algorithm.
The algorithm used is up to the system designer. In addition, it is possible to create special algorithms which reflect peculiarities of the machine using the arbitrator. In short, the arbitrator can be as general or as specific as needed, using the same hardware.
It is to be understood that the atbve-described embodiment is merely an illustrative principle of the invention and that many variations may be devised by those skilled in the art without departing from the scope of the invention. It is, therefore, intended that such variations be included within the scope of the claims.
-1_ DYNAMICALLY PROGRAMMABLE BUS ARBTTER WITH PROVISIONS FOR
HISTORICAL FEEDBACK AND ERROR DETECTION AND CORRECTION
Technical Field This invention relates to the field of computer bus arbitration and, more specifically, to the field of providing bus art>itration which takes previous bus usage into account and provides for selectable bus arbitration algorithms.
Background of the Invention As more devices are attached to the main memory bus in a computer system, there is more contention for use of the bus. In response to such contention, many different arbitration circuits have been proposed in order to give either fair access or priority access to the bus and thus, to memory resources.
For example, U. S. Patent No. ~~,195,185, which issued in the name of G. B. Marenin on March 16, 1993, disclose<; an arbitration device which determines bus access based on a priority scheme, and ~~lso has a system to dynamically change the priority of any device. This system doe~~ not, however, provide flexibility in the basic arbitration scheme; it only responds to a device's increase of its own priority.
It also cannot take into account which device previously used the bus in order to give either parity or priority to the other users. Finally, this system is locked into the priority scheme; it cannot be changed from a priority to a parity scheme when appropriate.
A further bus priority scheme is. described in U. S. Patent No. 4,979,100, which issued in the name of Makris, et al., on December 18, 1990. Makris discloses an arbiter circuit which provides two different levels of priority of access to the bus for each processing unit and keeps track of the relative percentages of time of access for the different priority levels. This system provides for interruption of lower priority bus usage by higher priority process units. This system requires complicated overhead to track such bus usage, and is not responsive to previous bus usage by any one system.
Neither of these systems provides for flexible, dynamically changeable arbitration systems which can start in a known state and change from one arbitration scheme system to another as conditions change nor do they react to the past allocation. Therefore, a problem in the art i~; that there is no bus usage arbiter that provides a dynamic priority scheme with provisions for historical feedback in its grant selection.
21 ~ 5~3 ~ a Summary of the Invention This problem is solved and a technical advance is achieved in the art by an arbitration circuit which takes into account previous bus access as part of the decision to service a requester. In particular, it provides a unique history register that generates a value representing past bus requests which is combined with a value representing current bus requests to acce~;s a location in memory. A potential grant is defined and stored in each location in memory for each possible combination of historical requests and current requests. selection of a potential grant is achieved selecting a section of memory by using the history register as the high order bits of memory address, and then using the currc;nt request as the low order bits of the memory address in order to determine thc: one grant output to be awarded. The grant is also shifted into the history register. ~cdvantageously, more than one table may be stored in memory to selectably provide a plurality of algorithms.
In accordance with one aspect of the present invention there is provided a system for providing arbitration of allocation requests from a plurality of requesters based on the history of a plurality of prior grants of requests by such requesters, said system comprising: input means for receiving requests from said plurality of requesters; storage means for defining a plurality of grants, said plurality of grants comprising a grant for each possible configuration of requests and prior requests;
history means for sequentially/recording :;aid plurality of previous grants;
and control means connected to said history means, said input means and said storage means for applying said received requests from said input means and said plurality of previous grants from said history means directly to said storage means and selecting one of said plurality of grants responsive to said received requests and said plurality of previous grants, providing a grant indication representative of said selected grant to one of said requesters.
In accordance with another ;aspect of the present invention there is provided a system for providing arbitration of allocation requests from a plurality of requesters based on the history of a plurality of prior grants of requests by such requesters, said system comprising: i~tput means for receiving requests from said plurality of requesters; storage means for defining a plurality of grants, said plurality of grants comprising a grant for each possible configuration of requests and prior requests; history means for recording saic'. plurality of previous grants, said history -2a- 21 157 3 1 means comprising a register wherein each grant is moved sequentially through said register; a writable mask register, wherein said mask register selectively alters portions of the contents of said history means; control means connected to said history means, said input means and said storage means for applying said received requests from said input means and said plurality of previous grants from said history means to said storage means and selecting one of said plurality of grants responsive thereto, providing a grant indication representative of said selected grant to one of said requesters.
In accordance with yet another aspect of the present invention there is provided a system for providing arbitration of bus allocation requests from a plurality of requester, said system comprising: input means for receiving requests from said plurality of requesters; output means for ~~ommunicating grants to said plurality of requesters; a storage means containing a :plurality of look-up tables, each of said look-up tables having a plurality of grants, each of said plurality of grants 1 S corresponding to each of the possible request inputs; a history register for sequentially recording the history of a plurality of previous bus request grants; and control means connected to said output means, said input means, said history register and said storage means for using said history of from said history register to select one of said plurality of look-up tables, applying said requests directly to said look-up table to select one of said plurality of grants, and providing grant authorization signals representative of said selected grant to ore of said requesters via said output means.
In accordance with still yet .another aspect of the present invention there is provided a system for providing arbitration of bus allocation requests from a plurality of requesters, said system comprising: input means for receiving request from said plurality of requesters; a storage means containing a plurality of look-up tables, each of said look-up tables having a plurality of grants, each of said plurality of grants corresponding to each of the possible request inputs; a history register for recording the history of a plurality of previous bus request grants; a mask register connected to said history register, said m~~sk register being dynamically writable and capable of over-writing said history register to alter said determined arbitration state;
and control means connected to said output means, said input means, said look-up table and said history register for selecting one of said plurality of look-up tables, applying said requests from said input means and said previous bus request grants .,m.;
-2b- 21 157 3 1 from said history register to said look-up table to select one of said plurality of grants, and providing grant authorization signals representative of said selected grant to one of said requesters.
In accordance with still yet ~~nother aspect of the present invention there is provided a method for providing arbitr~~tion of bus allocation requests from a plurality of requesters based on the history of a plurality of prior bus request grants, said method comprising: receiving a plurality of requests for use of said bus;
responsive to said plurality of requests, applying a history register containing said plurality of previous grants in sequential ~~rder to said plurality of requests to determine a selected arbitration state; using said selected arbitration state as an index into an arbitration state table, said arbitration state table comprising a plurality of arbitration states and a corresponding plmrality of grants; and issuing one of said plurality of grants directly indexed by said selected arbitration state to said requesters.
In accordance with still yet another aspect of the present invention there is provided a method for providing arbitration of bus allocation requests from a plurality of requesters based on the history of a plurality of prior bus request grants, said method comprising: receiving a plurality of requests for use of said bus;
responsive to said plurality of requests, applying a history register containing said plurality of previous grants to said plurality of requests to determine a selected arbitration state; using said selected arbitration state as an index into an arbitration state table, said arbitration state table comprising a plurality of arbitration states and a corresponding plurality of grants; and issuing one of said plurality of grants indexed by said selected arbitration state to said rf:questers, wherein said history register is dynamically variable, and wherein applying said history register to said request also includes varying said history register.
Brief Description of the Drawings F1G. I is a block diagram of a computer system, including an arbiter circuit according to an exemplary embodiment of this invention;
FIG. 2 is a block diagram of the arbiter circuit as shown in FIG. 1;
FIG. 3 is a state diagram of the arbiter circuit of FIG. 2;
FIG. 4 is a timing diagram of the arbiter circuit of FIG. 2;
FIG. 5 is an illustration of the history register;
FIG. 6 is an illustration of the history register of an exemplary embodiment of this invention at initialization;
-2c-FIG. 7 is an example of a block of memory illustrating a distribution of grants based on requests; and FIGS. 8-12 are illustrations of the shifting of data through the history register according to an exemplary embodiment of this invention.
Detailed Description FIG. 1 is a block diagram illustrating an exemplary embodiment of this invention in the context of a computer system 5 including a bus 10 and a memory device 12. For purposes of describing the preferred embodiment of this invention, there are four devices that share bus 10 a.nd memory 12. Central Processing Unit (CPU) 14 is a general purpose CPU, whi~~h manipulates and performs other functions as is known in the art on data stored in memory 12. In this exemplary embodiment, there are three Direct Memory Access (DMA) devices 16, 18, and 20 also connected to bus 10. DMA devices 16, 18, and 20 directly read and write locations in memory 12 via bus 10. In order to prevent more than one device from accessing bus 10 at the same time, arbiter circuit 22, according to an exemplary embodiment of this invention, controls access to bus 10 and thus memory 12. Arbiter circuit 22 is not limited to memory access, and may generally control bus access, or access to any device.
When one of devices 14, 16, 18, or 20 wants to access bus 10 (and/or memory 12), it raises a request on request lead 24, 26, 28, or 30, respectively.
Arbiter circuit 22 determines which of the devices' requests will be granted, as will be described later, and in response generate: a grant signal on one of grant leads 32, 34, 36, or 38. In this preferred embodiment, only one grant at a time will be issued.
However, it is within the scope of one skilled in the art that a system could conceivably issue multiple grants. When the device is finished with its bus access, a "done" signal is issued on lead 40. If an ern~r is detected during bus arbitration, arbiter circuit 22 informs CPU 14 on error lead 42, as will be described further, below.
Turning now to FIG. 2, an arbiter circuit 22 according to an exemplary embodiment of this invention is shown. The arbiter 22 of this exemplary embodiment includes an arbiter controller 1n2, arbiter memory 104, which is primarily RAM, but also included a block oi~ ROM 105, a grant latch 106, a history register 108, request latch 110, an initialization device (including ROM in the preferred embodiment of this invention) 112;, an algorithm select register 114, a mask register 116, and a table select register 118. Requests for control of bus 10 arrive at request latch 110 from devices 14, l6, 18, and 20 (FIG. 1) on request leads 24, 26, 28, and 30. In this exemplary E;mbodsment, the arrival of such requests triggers request latch to OR all request leads and sends a signal on ARBREQ
lead 120 indicating to controller 102 that there is a bus request pending.
Controller 102, in response, sends a signal via load line 122 to latch the requests in request latch 110. At this point, the requests, are sent via bus 124 to memory 104.
The data from history register 108 is then available on history bus 126. The generation of data in the history register will be described later.
The value formed by the bits of the request on bus 124 and a value formed by the bits of the history register on history bus 126 are combined and used as an address into memory 104 which outputs the next grant. Each possible combination of history register and request latch values is stored in memory along with the associated grant that follows the selected arbitration algorithm.
Therefore, an algorithm may be implemented simply by determining which combinations of previous grants and current requests requires the next grant.
In this manner, any algorithm may be used for selecting grants. An example is described below with reference to FIGS. 5-12. Advantageously, the value from history register 108 is used to select a section or blcxk of memory 104, which comprises the high order bits of the memory address; and the value form by the requests latched in S request latch 110 comprises the low order bits of the memory address, which is conceptually used to access the block by indexing into it. Memory 104 returns the grant selected by the address on grant bus 128.
A portion of memory 104 comprises ROM 105. ROM 105 contains at least one algorithm comprising all possible states of history register 108 and request latch 110. Alternatively, ROM 105 may be small and comprise a grant algorithm addressable by the four bits from request latch 110. ROM 105 can be used whenever an error is detected by controller 102, in order to go to a known state, and, optionally, at initialization.
Memory 104 causes the selected grant output to be placed on grant bus 128 and delivered to controller 102, history register 108, and grant latch 106.
The outputs consist of 1 of N bits (in this exemplary embodiment, N=4) asserted which defines the selected grant. When controller 102 receives the arbitration request on ARBREQ line 120, it provides a grant latch enable signal on line 130 to allow the grant to be passed to grant lines 3:', 34, 36, and 38. Controller 102 also asserts shift line 132 to cause the history register to shift the contents of grant bus 128, in parallel, into history register lOF~, and shifts the oldest previous grant out, as will be described further below. When the device that received the grant has completed its memory access, it asserts "done" line 40 which is received by controller 102, and starts a new cycle.
Mask register 116 is writable from the data portion of bus 10. The value in mask register 116 is used to mask the shirting of a particular bit through history register 108. This has the effect of erasing the history of a previously asserted grant.
Mask register 116 may be written by any device in order to alter the installed algorithm Advantageously, memory 104 contains.more than one arbitration algorithm Mask register 116 is also connected to a table select register 118.
Table select register 118 may be updated by data on the data portion of bus 10 through mask 116, in order to select a portion of memory 104 containing the algorithm desired. One table may be configured as a priority scheme and another may be configured as a parity scheme, thus providing flexibility in which type of scheme can be used at any given time.
21 15~ 7 3 1 -5 _ The preferred embodiment of tlus invention also includes a unique error detection mechanism. Optionally, each gra~it in memory 104 may have associated with it a cyclical redundancy check (CRC) value, a parity value, or other mathematical error checking value, as illusti~ated in FIG. 7. This value is sent to controller 102 along with the grant via grant bus 128. Controller 102 may then perform the check necessary and compare it to the value found in memory 104.
If an error is found, an error signal may be raised on error line 42, which is sent to CPU 14 t',FIG. 1 ) for further action.
Arbiter circuit 22 is initialized when an initialization request comes in on reset line 134 and is received at arbiter ir~idalization 112. Arbiter initialization 112 sends reset signals to conty~oller 102, memory 104, history register 108, grant latch 106, mask register 1.16, and request latch 110 over reset signal lines (not shown for clarity). As part of initialization, controller 102 causes a specified allocation algorithm stored in arbiter initialization ROM 112 to be loaded into memory 104 via line load control bus 136. The content of the data to be loaded is controlled by the algorithm select register 114. The select register 114 is loaded by CPU 14 (FTG.1) over the address and data lines of bus 10. Bus 138 provides an index into the arbiter initialization (ROM) 112, to control which arbitration algorithm is downloaded to operational memory 104.
Turning now to FIG. 3, a state machine as found in controller 102 of FIG. 2 is shown, describing the various states and the resultant level of the leads to and from controller 102. Idle state 310 is entered upon initialization.
Controller 102 remains in idle state 310 as long as there are no requests present at request latch 140 (FTG. 2). When one or more requests are received, state machine 300 transitions during the next clock cycle from idle state 310 to state S 1 320. In state S
1, the controller causes the load signal to go low, as will be described below in connection with FIG. 4, and causes the grant enable line 130 to be asserted.
State machine 300 then transitions during the next clock cycle from state S 1 320 to state S2 330. State machine 300 remains in state S2 330 until the "done"
signal is asserted. When the "done" signal is asserted, state machine 300 transitions from state S2 330 to state S3 340, wherein the load signal is asserted and the grant enable signal is released after "done" signal has been released. State machine stays in state S3 340 as long as the "done" signal is asserted. If the "done"
signal is released and the ARBREQ lead is asserted, the state machine transitions back to state S 1 320 because another arbitration request has been received, or conversely because there were a plurality of arbitration requests when the request lead was first asserted. The state machine also transitions from state S3 340 back to idle state 310 when both the "done" and the request leads are no longer asserted.
Turning now to FIG. 4, a timing diagram for state machine 300 of FIG. 3 is shown, wherein the state machine is shown transitioning completely around the exterior of state machine 300. Arbiter circuit 22 receives clock signals over clock bus 140 (FIG. 2). At some point during the idle state, one or more requests are received and the state machine transitions finm the idle state to state S 1.
The controller asserts the shift line 122 and sets the load line to low. At this time, the latched requests and the history register contents are sent to memory 104, and grants are put out on grant line 128, causing grants line to go high. At the same time, it asserts the grant latch line 130 to latch the grant output to lines 32, 34, 36, and 38 (FIGS. 1 and 2). After one clock cycle state. S 1, a transition is made to state S2, where, in response to the grant, the ARBREQ lead 120 goes low and the controller asserts the shift lead 132 for one cycle. The controller then waits in state until the "done" signal is asserted, indicating that the selected device has completed operations, at which time it transitions to smte S3 340 where the load signal 122 is asserted. At some time during state S3 the "done" signal goes low. In response to this, the controller sets the grant latch signal. to low and transitions back to the idle state.
Optionally, an additional field is associated with each grant in memory 120, as illustrated in FIG. 7, stating; the number of cycles that the device receiving the grant will use before asserting done line 40. Controller 102 uses this information to count clock cycles (from clock line 140) and starts the next state slightly before the done signal is asserted. In this manner, an arbitration circuit according to an exemplary embodiment of this invention, may be made in a pipelined configuration.
The operation of the history circuit and memory will now be explained in connection with FIGS. 5-12. In this exemplary embodiment, history register (FTG. 5) comprises twenty bits divided into ;five groups of four bits each.
Each of four sets of four bits represents a previous g~~ant. In FIG. 5, HO is the last grant. H1 is the grant previous to H0, H2 is the grant previous to H1, and H3 is the grant before H2. As each grant is made, it is shifted into H0. HO is then shifted into H1, etc., and H3 is shifted out of the history register. The final 4 bits are the "re:quest"
bits from the request latch. These are the index bits.
_,_ The history register of FIG. 5 is used to address a block of memory containing grant bits. The "index" bits maF~ directly on the request bits from the devices, as found at request latch 110. Assume, for this discussion, that only one bit in each of the previous grants of the history register is set at a time, and that all non-addressable addresses in this scheme generue an error signal. In HO-H3, only one bit in each group can be set because only one grant is given at a time in this exemplary embodiment. Optionally, these vfour registers (HO-H3) can also be encoded to save address space and make thE: RAM smaller.
In operation, the requests are entered into the system (by devices 14, 16, 18, and 20) and produce an address to the memory 104, is shown in FIG. 6 as "xxxx." This address consists of 16 possible entries. The address identifies a location in RAM that contains 4 bits of gra~its. These grants are set up according to a specific algorithm, such as that shown in 1~IG. 7. FIG. 7 illustrates a block of memory that contains a simple priority grant algorithm; however, the arbitration scheme is not required to be the "priority" scheme shown. Note also that all variations of the request leads are covered. Each variation results in one grant bit G3 through GO being set (selected) while the others are set to 0 (unselected).
The output of the memory sect7.on is used by the arbiter to grant a request (put onto grant lines 32, 34, 36, and 38, FIG. 1) and is also loaded into the HO address section. Assume that the reque~;t bits were [1001] which, according to the table of FIG. 7, results in grant 0 being ;yet [0001]. The RAM address in the next cycle appears as shown in FIG. 8.
This history register address again addresses a 16 location block of the RAM (but not the same block as illustrated in FIG. 7). One of the 16 locations is selected by the request section of the address. The data in the 16 locations is an example of the round robin algorithm with the stipulation that request 0 was granted in the last cycle. This means that if any other requests are pending, they will be serviced before request 0. In this case the next grant will be chosen from the other requests on a priority basis, although this need not be the case.
Assume the request bit pattern i:or the next cycle is still [1001]. This results in grant 3 being given on this cycle. The RAM address appears as in FIG. 9 on the next cycle. This is a new 16 location section selected by the address in the HO-H3 section of the address. This section ~~ontains the grant for any variation of the request leads possible. The grant bits are selected in this exemplary embodiment using the round robin algorithm with the stipulation that requests 0 and 3 have been granted already. If the next cycle request leads are [ 1010], then the RAM
will 21 157;6 1 _g..
respond with a grant 1 because grant 3 has been granted and grant 1 has not.
The RAM address will now appear as in FIG. 10 below for the next cycle.
These 16 locations are selected because requests 0, 1 and 3 have been previously granted. Note that request 3 was asserted and was not serviced. In the next cycle, the request address is [1100]. Tl~~e RAM responds with a grant 2 [0100]
because request 2 had not been serviced. Note again that request 3 was not serviced because of the round robin algorithm.
The new address for the RAM appears as in FIG. 11 for the next cycle.
All of the requests have been serviced, and if the request address for the next cycle is [1011], the result will be a grant 0 because is was the earliest served. The new RAM
address is then as in FIG. 12.
Each section of the RAM consists of a set of locations that define all of the possible states of the grant bits in accordance with the round robin algorithm.
The algorithm used is up to the system designer. In addition, it is possible to create special algorithms which reflect peculiarities of the machine using the arbitrator. In short, the arbitrator can be as general or as specific as needed, using the same hardware.
It is to be understood that the atbve-described embodiment is merely an illustrative principle of the invention and that many variations may be devised by those skilled in the art without departing from the scope of the invention. It is, therefore, intended that such variations be included within the scope of the claims.
Claims (21)
1. A system for providing arbitration of allocation requests from a plurality of requesters based on the history of a plurality of prior grants of requests by such requesters, said system comprising:
input means for receiving requests from said plurality of requesters;
storage means for defining a plurality of grants, said plurality of grants comprising a grant for each possible configuration of requests and prior requests;
history means for sequentially/recording said plurality of previous grants;
and control means connected to said history means, said input means and said storage means for applying said received requests from said input means and said plurality of previous grants from said history means directly to said storage means and selecting one of said plurality of grants responsive to said received requests and said plurality of previous grants, providing a grant indication representative of said selected grant to one of said requesters.
input means for receiving requests from said plurality of requesters;
storage means for defining a plurality of grants, said plurality of grants comprising a grant for each possible configuration of requests and prior requests;
history means for sequentially/recording said plurality of previous grants;
and control means connected to said history means, said input means and said storage means for applying said received requests from said input means and said plurality of previous grants from said history means directly to said storage means and selecting one of said plurality of grants responsive to said received requests and said plurality of previous grants, providing a grant indication representative of said selected grant to one of said requesters.
2. The system of claim 1 wherein said history means comprises a first in, first out (FIFO) queue, and wherein each grant is moved through said FIFO
queue.
queue.
3. The system of claim 2 wherein said storage means comprises a plurality of blocks, each of said plurality of blocks including a subset of said plurality of grants, wherein said control means selects one of said blocks by using said FIFO
queue as an address and selects one of said grants from said selected block by using said requests to select a location in said selected block.
queue as an address and selects one of said grants from said selected block by using said requests to select a location in said selected block.
4. A system for providing arbitration of allocation requests from a plurality of requesters based on the history of a plurality of prior grants of requests by such requesters, said system comprising:
input means for receiving requests from said plurality of requesters;
storage means for defining a plurality of grants, said plurality of grants comprising a grant for each possible configuration of requests and prior requests;
history means for recording said plurality of previous grants, said history means comprising a register wherein each grant is moved sequentially through said register;
a writable mask register, wherein said mask register selectively alters portions of the contents of said history means;
control means connected to said history means, said input means and said storage means for applying said received requests from said input means and said plurality of previous grants from said history means to said storage means and selecting one of said plurality of grants responsive thereto, providing a grant indication representative of said selected grant to one of said requesters.
input means for receiving requests from said plurality of requesters;
storage means for defining a plurality of grants, said plurality of grants comprising a grant for each possible configuration of requests and prior requests;
history means for recording said plurality of previous grants, said history means comprising a register wherein each grant is moved sequentially through said register;
a writable mask register, wherein said mask register selectively alters portions of the contents of said history means;
control means connected to said history means, said input means and said storage means for applying said received requests from said input means and said plurality of previous grants from said history means to said storage means and selecting one of said plurality of grants responsive thereto, providing a grant indication representative of said selected grant to one of said requesters.
5. A system for providing arbitration of bus allocation requests from a plurality of requester, said system comprising:
input means for receiving requests from said plurality of requesters;
output means for communicating grants to said plurality of requesters;
a storage means containing a plurality of look-up tables, each of said look-up tables having a plurality of grants, each of said plurality of grants corresponding to each of the possible request inputs;
a history register for sequentially recording the history of a plurality of previous bus request grants; and control means connected to said output means, said input means, said history register and said storage means for using said history of from said history register to select one of said plurality of look-up tables, applying said requests directly to said look-up table to select one of said plurality of grants, and providing grant authorization signals representative of said selected grant to one of said requesters via said output means.
input means for receiving requests from said plurality of requesters;
output means for communicating grants to said plurality of requesters;
a storage means containing a plurality of look-up tables, each of said look-up tables having a plurality of grants, each of said plurality of grants corresponding to each of the possible request inputs;
a history register for sequentially recording the history of a plurality of previous bus request grants; and control means connected to said output means, said input means, said history register and said storage means for using said history of from said history register to select one of said plurality of look-up tables, applying said requests directly to said look-up table to select one of said plurality of grants, and providing grant authorization signals representative of said selected grant to one of said requesters via said output means.
6. The system of claim 5 wherein one or more of said plurality of look-up tables may be dynamically updated.
7. The system of claim 5 wherein, when said grant signals are provided by said control means, said control means also performs error checking of said grant signals.
8. The system of claim 7 wherein each entry in said table includes a parity indication, and said error checking includes checking the parity of said grant signals.
9. The system of claim 7 wherein said table includes a cyclical redundancy check value, and said error checking includes performing a cyclical redundancy check on said grant signals.
10. The system of claim 5 wherein said table is contained in a random access memory (RAM).
11. The system of claim 5 wherein said table is contained in a read-only memory (ROM).
12. The system of claim 5 wherein one of said tables is contained in ROM, and the remainder of said plurality of tables is in RAM.
13. The system of claim 12 wherein said control means performs error checking on said grant signals, and, responsive to said control means determining that an error is encountered, said control means applying said determined arbitration state solely to said table in said ROM.
14. A system for providing arbitration of bus allocation requests from a plurality of requesters, said system comprising:
input means for receiving request from said plurality of requesters;
a storage means containing a plurality of look-up tables, each of said look-up tables having a plurality of grants, each of said plurality of grants corresponding to each of the possible request inputs;
a history register for record ing the history of a plurality of previous bus request grants;
a mask register connected to said history register, said mask register being dynamically writable and capable of over-writing said history register to alter said determined arbitration state; and control means connected to said output means, said input means, said look-up table and said history register for selecting one of said plurality of look-up tables, applying said requests from said input means and said previous bus request grants from said history register to said look-up table to select one of said plurality of grants, and providing grant authorization signals representative of said selected grant to one of said requesters.
input means for receiving request from said plurality of requesters;
a storage means containing a plurality of look-up tables, each of said look-up tables having a plurality of grants, each of said plurality of grants corresponding to each of the possible request inputs;
a history register for record ing the history of a plurality of previous bus request grants;
a mask register connected to said history register, said mask register being dynamically writable and capable of over-writing said history register to alter said determined arbitration state; and control means connected to said output means, said input means, said look-up table and said history register for selecting one of said plurality of look-up tables, applying said requests from said input means and said previous bus request grants from said history register to said look-up table to select one of said plurality of grants, and providing grant authorization signals representative of said selected grant to one of said requesters.
15. A method for providing arbitration of bus allocation requests from a plurality of requesters based on the history of a plurality of prior bus request grants, said method comprising:
receiving a plurality of requests for use of said bus;
responsive to said plurality of requests, applying a history register containing said plurality of previous grants in sequential order to said plurality of requests to determine a selected arbitration state;
using said selected arbitration state as an index into an arbitration state table, said arbitration state table comprising a plurality of arbitration states and a corresponding plurality of grants; and issuing one of said plurality of grants directly indexed by said selected arbitration state to said requesters.
receiving a plurality of requests for use of said bus;
responsive to said plurality of requests, applying a history register containing said plurality of previous grants in sequential order to said plurality of requests to determine a selected arbitration state;
using said selected arbitration state as an index into an arbitration state table, said arbitration state table comprising a plurality of arbitration states and a corresponding plurality of grants; and issuing one of said plurality of grants directly indexed by said selected arbitration state to said requesters.
16. The method according to claim 15 further including, before issuing said grant, performing error checking on said grant.
17. The method according to claim 16 wherein said error checking comprises parity checking.
18. The method according to claim 16 wherein said error checking comprises cyclical redundancy checking.
19. The method according to claim 16 wherein said arbitration state table comprises a plurality of state tables and wherein said result is indexed into one of said plurality of arbitration state tables, and wherein, responsive to determining that an error was found, using a different one of said plurality of arbitration state tables.
20. The method according to claim 15 wherein said arbitration state table comprises a plurality of arbitration state tables, said method further including determining which of said plurality of arbitration state tables to use.
21. A method for providing arbitration of bus allocation requests from a plurality of requesters based on the history of a plurality of prior bus request grants, said method comprising:
receiving a plurality of requests for use of said bus;
responsive to said plurality of requests, applying a history register containing said plurality of previous grants to said plurality of requests to determine a selected arbitration state;
using said selected arbitration state as an index into an arbitration state table, said arbitration state table comprising a plurality of arbitration states and a corresponding plurality of grants; and issuing one of said plurality of grants indexed by said selected arbitration state to said requesters, wherein said history register is dynamically variable, and wherein applying said history register to said request also includes varying said history register.
receiving a plurality of requests for use of said bus;
responsive to said plurality of requests, applying a history register containing said plurality of previous grants to said plurality of requests to determine a selected arbitration state;
using said selected arbitration state as an index into an arbitration state table, said arbitration state table comprising a plurality of arbitration states and a corresponding plurality of grants; and issuing one of said plurality of grants indexed by said selected arbitration state to said requesters, wherein said history register is dynamically variable, and wherein applying said history register to said request also includes varying said history register.
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Families Citing this family (40)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07244635A (en) * | 1994-01-14 | 1995-09-19 | Fujitsu Ltd | Circuit and method for bus use right arbitration |
| US6178475B1 (en) * | 1994-12-19 | 2001-01-23 | Advanced Micro Devices Inc. | Multimedia system employing timers to properly allocate bus access |
| FR2737591B1 (en) * | 1995-08-03 | 1997-10-17 | Sgs Thomson Microelectronics | DEVICE FOR ORGANIZING ACCESS TO A MEMORY BUS |
| US6108735A (en) * | 1995-09-29 | 2000-08-22 | Intel Corporation | Method and apparatus for responding to unclaimed bus transactions |
| US5805840A (en) * | 1996-03-26 | 1998-09-08 | Advanced Micro Devices, Inc. | Bus arbiter employing a transaction grading mechanism to dynamically vary arbitration priority |
| US5805838A (en) * | 1996-05-31 | 1998-09-08 | Sun Microsystems, Inc. | Fast arbiter with decision storage |
| US5841994A (en) * | 1996-06-14 | 1998-11-24 | Texas Instruments Incorporated | Portable computer with multiple zoom port interface |
| US5815674A (en) * | 1996-07-15 | 1998-09-29 | Micron Electronics, Inc. | Method and system for interfacing a plurality of bus requesters with a computer bus |
| US5875309A (en) * | 1997-04-18 | 1999-02-23 | 3Com Corporation | Arbitration system using linked table |
| US5884051A (en) * | 1997-06-13 | 1999-03-16 | International Business Machines Corporation | System, methods and computer program products for flexibly controlling bus access based on fixed and dynamic priorities |
| US6006303A (en) * | 1997-08-28 | 1999-12-21 | Oki Electric Industry Co., Inc. | Priority encoding and decoding for memory architecture |
| US6073199A (en) * | 1997-10-06 | 2000-06-06 | Cisco Technology, Inc. | History-based bus arbitration with hidden re-arbitration during wait cycles |
| KR100236948B1 (en) * | 1997-11-28 | 2000-01-15 | 이계철 | Cell bus arbitration method |
| JPH11250005A (en) * | 1998-03-05 | 1999-09-17 | Nec Corp | Bus controlling method, its device and storage medium storing bus control program |
| US6032218A (en) * | 1998-05-28 | 2000-02-29 | 3Com Corporation | Configurable weighted round robin arbiter |
| WO2000034876A1 (en) * | 1998-12-07 | 2000-06-15 | Infineon Technologies Ag | Multi-master bus system and method for operating the same |
| US6487171B1 (en) | 1999-05-19 | 2002-11-26 | 3Com Corporation | Crossbar switching matrix with broadcast buffering |
| US7197589B1 (en) * | 1999-05-21 | 2007-03-27 | Silicon Graphics, Inc. | System and method for providing access to a bus |
| US6574232B1 (en) | 1999-05-26 | 2003-06-03 | 3Com Corporation | Crossbar switch utilizing broadcast buffer and associated broadcast buffer management unit |
| US6718422B1 (en) * | 1999-07-29 | 2004-04-06 | International Business Machines Corporation | Enhanced bus arbiter utilizing variable priority and fairness |
| US6704822B1 (en) * | 1999-10-01 | 2004-03-09 | Sun Microsystems, Inc. | Arbitration protocol for a shared data cache |
| GB9923512D0 (en) * | 1999-10-05 | 1999-12-08 | Koninkl Philips Electronics Nv | Radio local area network |
| US6708240B1 (en) * | 2000-03-31 | 2004-03-16 | Intel Corporation | Managing resources in a bus bridge |
| US6584531B1 (en) * | 2000-04-27 | 2003-06-24 | Lsi Logic Corporation | Arbitration circuit with plural arbitration processors using memory bank history |
| EP1170669B1 (en) * | 2000-07-05 | 2006-03-29 | STMicroelectronics S.r.l. | Arbitration method and circuit architecture therefor |
| US6980519B1 (en) * | 2000-07-14 | 2005-12-27 | Lucent Technologies Inc. | Multi-table based grant generator for improved granularity in an ATM-PON |
| US6631433B1 (en) * | 2000-09-27 | 2003-10-07 | Emc Corporation | Bus arbiter for a data storage system |
| US6665760B1 (en) | 2000-09-29 | 2003-12-16 | Rockwell Automation Technologies, Inc. | Group shifting and level shifting rotational arbiter system |
| DE10116795A1 (en) * | 2001-04-04 | 2002-10-17 | Infineon Technologies Ag | bus system |
| CA2428977C (en) * | 2002-05-16 | 2010-08-10 | Tundra Semiconductor Corporation | Buffer management in packet switched fabric devices |
| US6944698B2 (en) * | 2002-07-08 | 2005-09-13 | International Business Machines Corporation | Method and apparatus for providing bus arbitrations in a data processing system |
| US7051135B2 (en) * | 2002-11-22 | 2006-05-23 | Ess Technology, Inc. | Hierarchical bus arbitration |
| KR100486308B1 (en) * | 2003-08-21 | 2005-04-29 | 삼성전자주식회사 | Arbiter providing programmability of arbitration algorithms |
| US7065594B2 (en) * | 2003-09-23 | 2006-06-20 | Tellabs Petaluma, Inc. | Method and apparatus of allocating minimum and maximum bandwidths on a bus-based communication system |
| US7200732B2 (en) * | 2004-01-23 | 2007-04-03 | Tellabs Petaluma, Inc. | Method and apparatus of adding grant information to a memory |
| US20050246463A1 (en) * | 2004-04-29 | 2005-11-03 | International Business Machines Corporation | Transparent high-speed multistage arbitration system and method |
| US7739436B2 (en) * | 2004-11-01 | 2010-06-15 | Sonics, Inc. | Method and apparatus for round robin resource arbitration with a fast request to grant response |
| US7454546B1 (en) * | 2006-01-27 | 2008-11-18 | Xilinx, Inc. | Architecture for dynamically reprogrammable arbitration using memory |
| US20130019041A1 (en) * | 2011-07-12 | 2013-01-17 | Lsi Corporation | Bit slice round robin arbiter |
| CN108153689B (en) * | 2016-12-06 | 2020-04-24 | 比亚迪股份有限公司 | Method and apparatus for polling arbitration |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4009470A (en) * | 1975-02-18 | 1977-02-22 | Sperry Rand Corporation | Pre-emptive, rotational priority system |
| US4237534A (en) * | 1978-11-13 | 1980-12-02 | Motorola, Inc. | Bus arbiter |
| US4536839A (en) * | 1982-03-30 | 1985-08-20 | Mai Basic Four, Inc. | Memory request arbitrator |
| JPS58225442A (en) * | 1982-06-25 | 1983-12-27 | Toshiba Corp | Priority control circuit |
| US4814974A (en) * | 1982-07-02 | 1989-03-21 | American Telephone And Telegraph Company, At&T Bell Laboratories | Programmable memory-based arbitration system for implementing fixed and flexible priority arrangements |
| JPS59161718A (en) * | 1983-03-07 | 1984-09-12 | Fuji Electric Co Ltd | Control system for common bus jurisdiction |
| US4941086A (en) * | 1984-02-02 | 1990-07-10 | International Business Machines Corporation | Program controlled bus arbitration for a distributed array processing system |
| US4663756A (en) * | 1985-08-29 | 1987-05-05 | Sperry Corporation | Multiple-use priority network |
| JPS63231661A (en) * | 1987-03-20 | 1988-09-27 | Fujitsu Ltd | Precedence controller |
| US4974148A (en) * | 1987-07-06 | 1990-11-27 | Motorola Computer X, Inc. | Bus arbiter with equitable priority scheme |
| JPH01189750A (en) * | 1988-01-25 | 1989-07-28 | Agency Of Ind Science & Technol | Bus arbitration circuit |
| US4979100A (en) * | 1988-04-01 | 1990-12-18 | Sprint International Communications Corp. | Communication processor for a packet-switched network |
| CA1320767C (en) * | 1988-05-11 | 1993-07-27 | Robert C. Frame | Atomic sequence for phase transitions |
| JP2833796B2 (en) * | 1989-10-11 | 1998-12-09 | 日本電気株式会社 | Bus arbitration equipment |
| US5151994A (en) * | 1989-11-13 | 1992-09-29 | Hewlett Packard Company | Distributed fair arbitration system using separate grant and request lines for providing access to data communication bus |
| JPH0452748A (en) * | 1990-06-14 | 1992-02-20 | Koufu Nippon Denki Kk | Bus arbitration circuit |
| JPH0810445B2 (en) * | 1990-09-21 | 1996-01-31 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Dynamic bus arbitration method and apparatus |
| US5291584A (en) * | 1991-07-23 | 1994-03-01 | Nexcom Technology, Inc. | Methods and apparatus for hard disk emulation |
| US5301283A (en) * | 1992-04-16 | 1994-04-05 | Digital Equipment Corporation | Dynamic arbitration for system bus control in multiprocessor data processing system |
-
1994
- 1994-02-15 CA CA002115731A patent/CA2115731C/en not_active Expired - Fee Related
- 1994-05-04 AT AT94303224T patent/ATE191804T1/en not_active IP Right Cessation
- 1994-05-04 EP EP94303224A patent/EP0625753B1/en not_active Expired - Lifetime
- 1994-05-04 DE DE69423928T patent/DE69423928T2/en not_active Expired - Lifetime
- 1994-05-16 JP JP06124712A patent/JP3088241B2/en not_active Expired - Lifetime
- 1994-05-16 CN CN94105517A patent/CN1040586C/en not_active Expired - Fee Related
-
1995
- 1995-04-14 US US08/425,317 patent/US5481680A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN1040586C (en) | 1998-11-04 |
| US5481680A (en) | 1996-01-02 |
| JPH06332841A (en) | 1994-12-02 |
| EP0625753A1 (en) | 1994-11-23 |
| CN1104785A (en) | 1995-07-05 |
| EP0625753B1 (en) | 2000-04-12 |
| JP3088241B2 (en) | 2000-09-18 |
| DE69423928D1 (en) | 2000-05-18 |
| ATE191804T1 (en) | 2000-04-15 |
| CA2115731A1 (en) | 1994-11-18 |
| DE69423928T2 (en) | 2001-07-19 |
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| EEER | Examination request | ||
| MKLA | Lapsed |