CA2121936A1

CA2121936A1 - Simultaneous analog and digital communication using fractional rate encoding

Info

Publication number: CA2121936A1
Application number: CA002121936A
Authority: CA
Inventors: William Lewis Betts; Gordon Bremer
Original assignee: American Telephone and Telegraph Co Inc
Current assignee: AT&T Corp
Priority date: 1993-06-14
Filing date: 1994-04-22
Publication date: 1994-12-15
Also published as: US5859877A; US5684834A; EP0630135A3; JPH0730606A; US5844944A; EP0630135A2

Abstract

Simultaneous Analog and Digital Communication Using Fractional Rate Encoding Abstract Digital data is encoded using a modulus m converter 700 to produce fractionally encoded words, where m is the nearest integer larger than 2c and c is a noninteger. The fractionally encoded words are mapped into a symbol constellation having m symbols to produce a two dimensional data signal 62, 63. The data signal is added to a two dimensional analog signal, which was obtained by encoding an input analog signal, to produce a combined two dimensional signal. The combined signal is modulated using QAM and then transmitted over a communication channel.(FIG. 17).

Description

- 7~ ?~

Simultaneous Analo~ and Digital Communication Using Fractional Rate Encoding Cross-Reference to Related Application Related subject matter is disclosed in the application filed concurrently 5 herewith and assigned to the same assignee hereof entitled "Simultaneous Analog and Digital Communication", inventors Gordon Bremer and Kenneth D. Ko.
Field of the Invention This invention relates to simultaneous transmission of analog and digital signals and, more pardcularly, to simultaneous transmission of analog signa1s and 10 digital signals in a non-muldplexed manner and in a co-extensive frequency band.
Description of the Prior Art In the prior art, when voice and data is transmitted simultaneously over a channel, it is typically transmitted either via frequency-division multiplexing or time-division muldplexing. In frequency-division muldplexing, the data channel 15 and the voice channel are allocated different sub-bands of the channel's bandwidth.
Examples of that are U.S. Patent No. 4,757,495, U. S. Patent 4,672,602, and U. S.
Patent 4,546,212. In dme-division muldplexing arrangements, voice signals are -sampled, digitized and interleaved with digital data to form a single informadonstream which is communicatcd over the available channel. Pracdcally every digital 20 carrier system (e.g. the T1 carrier system) is an example of that.
U.S. Patent No. 4,512,013, issued April 16, 1985, presents an interesdng approach that is close to a frequency division multiplexing arrangement for simultaneous voicc and data. Thc arrangcmcnt filtcrs the speech signal and a~ds thercto a modulated narrowband signal to form the transmitted signal. The 25 narrowband modulated signal derives &om a narrowband digital input signal that is ~ ~ -modulatcd with a carrier, thereby shifdng the narrow-band up in &equency to a posidon in the spectrum whcre there is little spcech energy. At the rcceiver, inrcliance of the fact that the speech power is low in thc narrowband occupied by the modulated digital signal, the digital signal is recovered through appropriate 30 demodulation. Thereafter, the recovered digital signal is remodulated to replicate the transmitter's operadon, adapdvely filtered to account for channel characterisdcs, and subtracted from thc received signal. The result is the received speech. As indicated above, one salient characteristic of that arrangement, as stated in col. 2, lines 13-18, -is that ". . . an entire analog speech signal and a modulated data signal are capable of ;
35 being transmitted over a norrnal analog channel by the muldplexing of the data signal within the pordon of the normal analog speech signal frequency band where 22 ~ 3 the speech signal is present and the power density characteristic thereof is low". As an aside, the 4,517,013 arrangement is half duplex.
In the modem art, digital inforrnation is communicated over a channel by converting the digital information to analog form. In the most basic form, a S modem filters the didtal signal (i.e., shifts it in frequency) to form a band-limited signal and modulates that signal to reside within the passband of the communicadon channe1. In telephony, for example, that passband may be between 300Hz and 3500Hz. To increase the informadon-carrying capacity of the modulated signal, more sophisdcated modems employ quadrature moduladon. Quadrature moduladon 10 is often depicted as a two-dimensional signal space. Use of the signal space to send voice informadon is disclosed in U.S. Patent 5,981,647 issued January 14, 1992.
- Use of the signal space to send data and voice in described is "High Speed Digital and Analog Parallel Transmission Technique Over Single Telephone -Channel", Ajashi et al, IEEE Transactions on Communications, Vol. 30, No. 5, May, 1982, pp. 1213-1218. Unlike prior techniques, where analog and data were segregated into different dme slots (TDM) or different frequency bands (FDM), they -describe separadng analog and data signals into the two different channels of the QAM system. That is, Ajashi et al suggest moduladng the in-phase channel with the analog signal, and moduladng the quadrature channel with the data signal. Building 20 on that descripdon and concerning themselves with channel equalizadon, Lim et al analyze equalizer performance in "Adapdve Equalization and Phase Tracking For ~ -Simultaneous Analog/Digital Data Transmission", BSTJ, Vol. 60 No.9, Nov 1981, pp. 2039-2063. (Thc 1981 BSTJ article cites the informadon of 1982 IEEE article as ~ ~ -"unpublished work"~.
No one has achieved the ability to simultaneously sent both data and voice through both channels of a QAM system, and no one has achiéved the abilityto communicate both by data and analog, simultaneously, and in full-duplex, over a single bidirectional bandlimited communicadons channel.
Summary of the Invention The present invendon simultaneously transmits data signals and analog signals by adding an analog signal to a data signal before transmission. The invendon uses symbol constellations in which the number of symbols are not limited to 2c where c is an integer. Removing this limitation increases the number of symbol constelladons that may be used and thereby permits more efficient use of a 35 communicadon channel's bandwidth.

:--` 3 2121936 :

-A fractional rate encoding technique, disclosed in U. S. patent 5,103,227 ~ -entitled "Modulos Converter for Fractional Rate Encoding", is used to encode a non-integer number of bits per symbol; however, other methods may also be used.
Using a non-integer number of bits per symbol permits using symbol or signal point 5 constelladons in which the number of signal points m, is the nearest integer larger than 2c where c is a fraction which approximates the rado of the bit rate divided by symbol rate, or in other words, c is the number of bits per symbol. The fractional encoding is carried out by partitioning incoming data bits into words with a preselected number of words forming a frame. The frame undergoes a modu1us lO conversion with the number of signal points or symbols composing the constellation -being used as a modulus, and with the number of words composing the frame being -equal to the number of digits that represent the frame after the modulus conversion.
Each of the digits are used to specify a symbol to be transmitted. As a result, a frame comprising x bits that have been divided into y words, can be represented by y lS symbols, where each symbol represents c bits and c is a non-integer that equals x/y.
The invendon provides a communication method that produces a data ~ -signal by mapping data bits into a symbol constellation that has a plurality of symbols. Each of the symbols represent a noninteger number of the data bits. A
second signal, such as an analog signal, is added to the data signal to form a 20 combined signal that is transmitted over a communication channel using orthogonal modulation.
Brief Description of the Drawin~
.
FIG. 1 presents the basic structure of a prior art modem;
FIG. 2 shows the signal space and an illustrative signal constellation for 25 theFIG.l system;
FIG. 3 shows the signal space of a QAM analog system; ~-FIG. 4 shows the signal space of an alternadng digital and analog system;
FIG. S shows the signal space of a combined digitat and analog system;
FIG. 6 presents one embodiment of a transmitter section for a combined digita1 and analog system;
FIG. 7 presents one orthogonal modulation approach;
FIG. 8 depicts the vector addition that forms the signal space of FIG. S;
FIG. 9 illustrates the arrangements that perm~t more than one analog 35 signal source to be transmitted simultaneously;
' ': ':

- FM. 10 details the major elements in a receiver in accordance with the principles of this invention;
FiG. 11 presents a block diagram of a receiver that includes adaptive equalization;
FIG. 12 presents the block diagram of an entire modem;
FIG. 13 presents a slightly different embodiment of the FIG. 12 modem;
FIG. 14 depicts one structure for scrambling analog samples; -FIG. 15 shows a table indicating the fractional data rate and the corresponding number of signal points for various input data rates and symbol rates; -~
FIG. 16 shows how an incoming data bit stream is partitioned into frames of various lengths for various symbol rates;
FIG. 17 shows a block diagram for a fractional rate encoder, and FIG. 18 shows a block diagram for a decoder matching the encoder of l ~ -FIG. 17.
15 Detailed DescriPtion To place this invention in context, FIG. 1 presents a very basic block diagram of a modem that communicates digital data via quadrature modulation techniques. Section 100 is the modem's transmitter section and section 200 is the modem's receiver section. Specifically, in the transmitter section digital data is 20 applied in FIG. 1 to a 1-to-2 mapper 110, and mapper 110 develops two outputswhich typically are referred to as the in-phase and quadrature samples. The in-phase samples are applied via low pass filter 150 to modulator 120, which multiplies the applied signal by a cL~rier -- i.e, sincot in FM. 1. The quadrature samples are applied via low pass filtcr 160 to modulator 130, which multiplies the applied signal 25 by a second carrier. The second carrier is orthogonal to the first carrier, namely, coscot. Filters 150 and 160 must be bandlimited to no more than ~D, in order to avoid aliasing and to at least half the inverse of the output sample rate of mapper 110. The output signals of modulators 120 and 130 are added in element 140 to develop theanalog signal of the modem's transmitter section.
In operation, the digital data applied to the FIG. 1 apparatus is a stream of bits. Element 110 views the incoming signal as a stream of symbols that each comprises a preselected number of consecutive bits, and maps each symbol into anin-phase analog sample and a quadrature analog sample.
Practitioners in the art often describe the operations performed in the 35 FIG. 1 apparatus by means of a signal space diagram, such as shown in FIG. 2. The x axis corresponds to one of the carrier signals (e.g., cosc~t) and the y axis 2i2193~

- corresponds tO the other carrier signal (sincot). The in-phase and quadrature samples delivered by element 110, in effect, specify a location in the signal space of FIG. 2.
Accordingly, the set of possible samples that element 110 can produce corresponds to a set of sample points (i.e., a constellation of points) in the signal space depicdon 5 of FIG. 2. A 4-point signal constellation is shown, by way of illustration, in FIG. 2.
It is well known, however, that one can create signal point constellations with a larger number of signal pOi21tS.
To receive signals that were modulated by the FIG. 1 apparatus in accordance with the specific constelladon depicted in FIG. 2, one must only idendfy ~ ~
10 whether the received signal is in the first, second, third or fourth quadrant of the ~- -signal space. That means that there exists great latitude in the signals that are received, and any received signal that is sdll in the correct quadrant is mapped to the correct constellation signal point in that quadrant. Extended to other (and perhaps larger) constellations, the signal space can be divided into regions and the receiver's 15 decision is made with respect to the region-in which the received signal is located.
We call these regions "neighborhood" regions.
Returning to FIG. 1 and addressing the modem's receiver section, the modulated signal is applied to demodulator 210. Demodulator 210 recovers the in- ~
phase and quadrature components and applies them to slicer 220. Slicer 220 ~ -20 converts the in-phase and quadrature components into symbols and applies the symbols to de-mapper 230. De-mapper 230 maps the symbols into bit streams to form the recovered digital data stream.
Absent any signal degradation (such as due to noise added in the channel) the signal received by demodulator 210 would be precisely the same as the 25 signal sent by adder 140, and a determination of neighborhood regions in which the signal is found (by slicer 220) would be relatively simple and error-free. However, noise that is added to the transmitted signal shifts the received signal in the signal space and modifies the input to slicer 220. Stated in other words, a noise signal that adds to the signal flowing through the communication channel corresponds to a 30 vector signal in the signal space of FIG. 2 that is added to a transmitted sample point.
That added vector is of unknown magnitude and unknown phase. Consequently, added noise converts a transmitted signal that corresponds to a point in the signal space into a re~ion in the signal space. This phenomenon is depicted in FIG. 2 by circle 11. Some refer to this circle as a signal space "noise cloud" surrounding the 35 transmitted signal.

, ~.
~; - 6-- From the above it is clear that in order to detect the transmitted signals ~ -~
without errors, the neighborhood regions must be large enough to encompass the -~
noise cloud. Since the average power of the sent signal is typically limited by other consideradons, the extent to which the signal constel1ation covers the infinite space 5 represented by the x and y axes is also limited. This is represented in FIG. 2 by circle 12. The restricdon imposed by circle 12, coupled with the restricdon on thc size of the neighborhood regions that is imposed by noise consideradons limits the number of transmitted signal points in the constelladon.
As indicated above, it has been observed that in typical modem designs 10 the allowable signal power and the expected fidelity of the channel combine to ~ -control the constelladon siæ. Less noisy channels allow for larger constelladons, and larger constelladons permit higher digital data throughputs. This leads to atotally revolutionary idea of udlizing all, or essentially all, of the available signal space for the transmission of irlformadon. A transmitter signal space in accordance vith this revoludonary approach is depicted in FIG. 3 vhere a plurality of signal ~ -points are depicted randomly within the signal space. These Points a~e illustradve of the various vectors that the transmitter is allowed to send out. There are no more "constellations of points", where a decision must be made between constelladon points; there is ody the endrety of the signal space. In other words, rather than 20 having digital signals that are mapped onto a fixed constelladon within a signal space, FIG. 3 depicts analog signals that are mapped onto a signal space. When the analog signals that form the in-phase component are independent of the analog signals that form the quadrature component, thc viable signal space of FIG. 3 may be rectangular.
Having recognized the advantages of sending analog signals in accordance with the signal space of FIG. 3, the next innovadon is to alternate bctween the signal spaces of FIG. 2 and FIG. 3. That is, the innovadon is to send customer analog signals _ customer digital signals as the need arises. This is depicted in FIG. 4.
Further, having recognized the advantages of sending either analog or digital signals in accordance with the signal spaces of FIG. 4, it was discovered that a totally different communication approach can be taken, that communicating bothanalog and digital signals, can be exPressed concurrently, in a combined signal space. This is illustrated in FIG. 5, where four neighborhoods are idendfied for35 illustradve purposes, with demarcadon borders idendfied by dashed lines 21 and 22.

2121~36 . , It may be noted that, for purposes of this disclosure, according to the FIG. S depiction, the analog signals that form "signa1 clouds" around each digital constellation point (e.g., point 31) should be restricted in their dynamic range to be totally contained within the neighborhood regions. Hence, here too there is a trade- ~-5 off between constellation size (which directly affects digital through-put) and dynamic range of the transmitted analog signal (which in some situations translates to"resolution").
FIG. 6 depicts an arrangement that very basically illustrates the principles of this invention. It includes a 1-to-2 dimensional mapper 60 responsive 10 to digital signals applied on line 61. Mapper 60 develops two output signals on lines 62 and 63, each of which possesses pulses with quandzed amplitudes that relate to , the digital signals arriving on line 61. FIG. 6 also includes a 1-to-2 mapper 50 that responds tO an applied analog signal on line 51, and it develops two output signals on lines 52 and 53, each of which possesses pulses with condnuous amplitudes that relate to the analog signal on line 5. Outputs 52 and 62 are combined in adder 70 - - ~ -and outputs 53 and 63 are combined in adder 80. The outputs of adders 70 and 80 form the components of the signals that are represented by the signal space of FIG.
5. As in FIG. 1, the outputs of adders 70 and 80 are applied via low pass f,ilters 150 -and 160 to modulators 120 and 130 and summed in adder 140 to form a modulated 20 signal as is typically known in the modem art.
In FIG. 6 element 60 is depicted as a 1-to-2 mapper. However, it should be understood that ele,ment 60 can be an M-to-N mapper. That is, element 60 can be ~ :
responsive to a p1urality (M) of digital signals and it can develop a different plural,ity (N) of output signals. Similarly, element 50 can be a J-to-K encoder that is 25 responsive to a plurality of analog signals. Likewise, the col1ection of elements that follow elements 50 and 60 (i.e., elements 70, 80, 120, 130, 140, 150 and 160), which :
form orthogonal modulator 90 can be constructed to be responsive to whatever ;
plurality of outputs of that elements 50 and 60 are designed to produce. More specifically, those elements must account for all of the applied input signals, and that -30 means that they must be able to handle K or N signals, whichever is larger. In such a circumstance, however, the user can assume that the 1arger of the two (K or N) is the dimensionality of the system, and some of the dimensions have either no digital data, or no analog data, whichever applies. Of course, if there are "dimensions" for which there is no digital or analog data, other information can be sent over those 35 dimensions, such as equalization "side" information.
.
' ~ ,' .

`~ 212193~

- In the context of a signal space, the N pluralities of output signals of elements 50 and 60 (assuming N is larger than K) correspond to the col1ecdon of components of vectors in multi-dimensional space; e.g., N-dimensional space. Thecoordinates of this multi-dimensional space correspond to the orthogonal modulation S signals within orthogonal modulator 90. In FIG. 6, the two orthogonal moduladon signals are cos~t and sin~t, but other modulation signals are also possible; for ! : -:
exarnple, code division multiplexing (CDMA) templates. For purposes of this invendon, orthogonal modulation signals are modulation signals that develop a transmitted signal comprising concurrent element signals and yet allow the receiver 10 to separate the received signal into its consdtuent element signals, those being the signals developed in response to each of the modulation signals. It may also be observed that, reladve to FIG. 5, orthogonal modulator 90 performs vector summation of the sym~ol vector represented by the components developed by element 60 with the analog ir~forrnation ~ector represented by the components 15 developed by element 50. This is depicted in FIG. 7.
In connection with FIG. 1, it may be noted in passing that the principles of this invention may be utilized even when the output signals of adders 70 and 80 are communicated (e.g., transmitted) direcdy, without the benefit of combining them in orthogonal modulator 90. Also, orthogonal modulator 90 can simply be a band-20 shifting means. To the extent that the output of adder 70 (for example) is band-limited, the output of adder 80 can be shifted beyond the band-limited output signat of adder 70 and combined with the output signal of adder 70. This is presented in FIG. 8. It may also be appreciated that the principles of this invendon may be exercised without the use of element 60 in those situations where no digital streams 25 are presented.
To this point in the instant disclosure the implicadon has been that the input signal applied to element 50 of FIG. 6 is analog. However, that does not have to be stricdy the case. In accordance with convendonal techniques, an analog signal that is bandilimited can be sampled (within the proper Nyquist bounds). Hence, it 30 should be understood that the input signal to element 50 can be a sequence of analog samples. Moreover, a sampled analog signal can be quantized and represented in digital form. Indeed, an analog signal that has been sampled and converted to digital form can then be converted to amplitude quantized pulse amplitude-modulated format. All of those rep esentadons are representations of an analog signal. For35 example, the collecdon of the amplitude-quandzed PAM pulses is idendcal to the original analog signal within the bounds of the quantization errors introduced by the 212193~

g :
- sampling and quantizing (A/D conversion followed by D/A conversion) processes.
The fact that sampling and amplitude quandzadon of the analog signal at the input oi element 50 is permitted offers a number of benefits. For one, it allows the signal to be presented to element S0 in digital format. For another, it permits S simple multiplexing of different informadon sources. Thus, for example, elements S0, 60 and 90 can be implemented in accordance with present day modem realizations; i.e., with one or more microprocessors operating under stored program control.
An example of input signal multiplexing is shown in FIG. 9, which -10 presents an embodiment that includes an A/D converter bank 30 followed by a multiplexer 40. Converter bank 30 converts a plurality of analog signals, such as on - :
lines 33 and 34, to digital forrnat and multiplexer 40 multiplexes its input signals and applies them to element S0. Elements 30 and 40 are conventdonal A/D and multiplexer elements, respectively.
lS The combinatdon of elements 30 and 40 allows applying a number of narrowband analog signals to orthogonal modulator 90. The primary limitations are the carrier frequency and the allowable transmission bandwidth of the channel. The -narrowband signal can, of course, come from any source. For example, a system ~ -installed in an ambulance may sacrifice some voice bandwidth in order to allow 20 narrowband telemetry data of blood pressure and heart pulse rate to be communicated concurrently with the voicc.
Additionally, a voice signal energy detector may be included, such as ~;
disclosed in U.S. Patent 5,081,647, which would detect periods of silence and send less urgent telemetry data during those silence periods. This is illustrated by 25 elements 31 and 32 in FIG. 9.
The fact that the input to element 50 is digital (in a digital implementation of elements 50, 60 and 90) and that the input to element 60 is also digital should not be confused. The digital input to element 60 is a stream of digits -that are each equallv important. Hence, those digits are converted into symbols and 30 the symbols into constellation points, and the constelladon points are withinneighborhoods which are identified by a slicer (e.g., slicer 220 in FIG. 1) within a ~
modem's receiver section. In contradistinction, the digital signals applied to element ~ -50 correspond to digital words that represent amplitude, and the specific interrelationship between adjacent bits of the digital words is maintained. As 35 indicated above, the signal cloud around a signal point within a constellation does not represent a plurality of signal points that must be distinguished, and that is a . Lr ~, , .~ - 10- ~ ~
- fundamental distinction.
FIG. 10 presents a basic block diagram of a modem's receiver secdon in conformance with the principles of this invention. The modulated input signal received from the channel is applied to demodulator 210 which develops the in-5 phase and quadrature components. Those are applied to slicer 220 which identifiesthe syrnbols, and the symbols are applied to de-mapper 230. All this is in accord with conventional modem approaches, as described in connection with FIG. 1. In addition, FIG. 10 includes a mapper 240 that is responsive to the symbols developed by slicer 220. The output of mapper 240 is an accurate estimate of the set of in-10 phase and quadrature components (that are applied in the FIG. I arrangement toelements 150 and 160). The outputs of mapper 240 are subtracted from the outputs of demodulator 210 in subtracters 250 and 260. The outputs of subtracters 250 and 260 are applied to 2-to-1 de-mapper 270 which rccombines the analog samples to form an estirnate of the original analog signal. De-mapper 270 performs the inverse 15 function of mapper 50.
It may be noted that slicer 220 can be designed to directly provide the output signals that mapper 240 develops; and moreover, de-mapper 230 can be maderesponsive to such signals. That would alter the FIG. 10 in the sense that slicer 220 and mapper 240 would combine to form a single element and de-mapper 230 as well 20 as adders 250 and 260 would be responsive to that combined element.
In analog rcalizations of this invention (e.g., FIG. 6), mapper 50 is responsive to analog signals. Various approaches can be taken to develop the plurality of outputs (two outputs, in the case of element 50 shown in the FIGS.). For examp1e, a single bandlimited analog signal can be divided into a plurality of 25 baseband signals by simply filtering and moduladng selected sub-bands.
Alternativdy, element 50 can accept a plurality of bandlimited analog signals and assign each one of the plurality of bandlimited analog signals to different outputs of element 50.
In dme sampled realizations of this invendon (whether the realization 30 continues with analog circuitry or digital circuitry), element 50 can simply route alternate samples of a single analog signal to different outputs of element 50, or muldplex a plurality of analog signals and distribute the samples of those signals in any convénient manner.
In order to allow for nonlinear techniques that may be employed to 35 enhance the communicadon qualides of this invendon, it is important to effectequalizadon of the channel in order to minimize intersymbol interference.

j - 1 1 - , - Convendonal modem technology can be brought to bear to this need.
FIG. 11 presents a block diagram of an arrangement that incorporates equalizadon. Specifically, FIG. 11 is depicted with a modulator that is followed by equalization hardware (which together can be thought of as a super-demodulator). - -5 The equalizadon hardware comprises an adaptive filter 280 that is interposed - -between demodulator 210 and slicer 220. The operadonal characteristdcs of filter280 are controlled by filter coefficients that are stored -- in modifiable form -- within tap update block 290. Tap update block 290 is responsive to the output signals of subtracters 250 and 260. The adaptation of filter 280 is carried out in accordance 10 with convendonal modem techniques. The outputs of subtracters 250 and 260 arealso applied to demuldplexer 275 and the outputs of demuldplexer 275 are applied to de-mapper 276. De-mapper 276 comprises a bank of de-mappers 270 of FIG. 10.
Ebments 275 and 276 are included to illustrate a receiver that is adapted for applications where a plurality of analog inputs are multiplexed. Of course, in ! ~
15 applicatdons where there is no multiplexing, de-mapper 270 can be substituted. ~ -In accordance with some adaptation approaches, it is easiest to ca~y out - ~
adaptation and the corresponding coefficient updates when the power in the analog ~ -signal is small. To limit the process to such intervals, FIG. 11 includes a power ~ -dbtector within control element 295 that is responsive to subtracters 250 and 260.
20 Block 295 is also convendonal. It includes a power detecdon circuit that evaluates the power contained in the signals of subtracters 250 and 260 and delivers a control signal to block 290 to enable (or disable) the coefficient updating process. Of course, block 295 may be more generic, in that the control signal can be derivedfrom other than the analog signal, such as from side informadon from the 25 transmitter.
FIG. 11 depicts one arrangement for effecting equalization of the transmission channel between a sending modem's transmitter sectdon and a receiving modem's receiver sectdon; to wit, at thc receiva's front end, following the demodulator. However, it is well known that equalizadon can be performed 30 anywhere along the channd, going back even to within a modem's transmitter sectdon.
FIG. 12 depicts the endre, full duplex, modem constructed in accordance with the depicdons of FIGS. 9 and 11. More specifically, a transmitter secdon (E;IG. 9) is coupled with a receiver sectdon (E;IG. 11) through hybrid 300 and 35 subtracter 310. Subtracter 310 cooperates with echo canceller 320 in the conventdonal way to subtract unwanted signals from the signal applied to r ,~
demodulator 210. For sake of simplicity, echo canceller 320 is shown to connected to the output of orthogonal modulator 90, and in analog embodiments of e1ement 320 this is perfectly satisfactory. However, in digital embodiments it is well known that efficiencies can be realized by having the echo canceller be responsive to the outputs 5 of mapper 60, where the signal rate is much lower. An improvement which incorporates the principles of this invendon is shown in FIG. 13. It may be noted that some of the elements in FIG. 13 are designated by different labels; such as'~ilbert passband filter", which corresponds to a modulator, etc. These are circuits that attain the desired results through somewhat different calculations and are well 10 known to persons skilled in the modem art.
The echo cancelling is performed, as in all modems, during a training period, when the far end signal source is silent and the echo canceller is adapted to minimize the output of subtracter 310.
In connection with FIG. 6 it has been disclosed that the input to element 15 50 can be a sampled analog signal, as well as an unsampled analog signal. It has also been disclosed above that when element 50 is a 1-to-2 mapper (as compared to l-to-N mapper) and the desired output of element 50 is pairs of a sampled analogsignal, the pairs of analog samples can be derived by simply delaying the incoming analog signal by l/B and sampling both thc delayed and the undelayed versions at20 rate B. This provides sample pairs that correspond to adjacent samples of theoriginal analog signal sampled at rate l/2B seconds. Actually, privacy of the communication is enhanced when the samples are not adjacent, and FIG. 14 presents one approach for deriving pairs from non-adjacent samples. It basically includes an input register 55 for storing K analog samples that arrive at rate 2B, a scrambling 25 network 56 that scrambles the outputs of register 55 and develops K outputs, and registers 57 and 58 that are responsive to the outputs of network 56. Registers 57 and 58 store K/2 analog samples every K/2B seconds and output the stored samplesat rate l/2B seconds. Scrambling network 56 may be simply a cross-connect field.Other configurations are possible and other elements can be included to 30 enhance operation of the configurations. For example, the "analog" input that enters orLhogonal modulator 90 can be filtered to pre-emphasize the high frequencies and, correspondingly, the "analog" output of subtracters 250 and 260 can be filtered to remove the pre-emphasis. The preemphasis can be effected, for example, within the A/D converter 30 or even prior thereto, such as in pre-emphasis filter 20 shown in 35 FIG. 12. The filtering can be done while the "analog" signal is truly analog, or it could be done when the "analog" signal is represented digitally -- such as when the ' ~, '~ ~

212~936 transmitter and receiver sections are effected with digital hardware. ~-Other configurations are possible and other elements can be included to enhance operadon of the configurations. For example, the "analog" input that enters orthogonal modulator 90 can be filtered to pre-emphasize the high frequencies and, 5 correspondingly, the "analog" output of subtracters 250 and 260 can be filtered to remove the pre-emphasis. The preemphasis can be effected, for example, within the AID converter 30 or even prior thereto, such as in pre-emphasis filter 20 shown in FIG.12. The filtering can be done while the "analog" signal is truly analog, or it - -could be done when the "analog" signal is represented digitally -- such as when the 10 transmitter and receiver sections are effected with digital hardware. ~ - - -A very comrnon symbol rate for modems is 2400 symbols/sec. As shown in FIG. 15, at this symbol rate, for a data rate of 7200 bits/sec, each symbol corresponds to 3 bits, for a data rate of 9600 bits/sec, each symbol corresponds to 4 bits, and so on. Furthermore, in a QAM modulation scheme, 8 signal points or -15 symbols are required for 7200 bits/sec, 16 signal points or symbols are required for 9600 bits/sec and so on. In general, the number of points required for a given data -~ -and symbol rate is given by m=2C, where c=bit rate/symbol rate (c also represents ~
the number of bits per symbol) and is generally an integer. ;
However, many channels can now be used for broader bandwidth data -transmission. For example, standard leased telephone cable can be used to transmit 3200 symbols/sec reliably. Submarine cables can be used to transmit 2800 ~ -symbols/sec. Therefore, fractional rate encoding techniques are needed to transmit data efficiendy at dhes~ higher baud rates. In fractional rate encoding the number of symbols or signal points m is the nearest integer larger than 2c where c is a fraction which approximates the ratdo of bit rate/symbol rate (or bits per symbol). As shall become apparent from the discussion below, the divisor of c is preferably small.FIG. 15 shows some rados selected for various bit and symbol rates, and the corresponding number of signal points m required for QAM data transmission. ¦
The improvement in the performance of fracdonal encoding over 30 standardencodingissignificant,anditmaybeexpressedasi=101Og(mlbl/m2b where i is an indicia for performance, m I is the number of symbols or constelladon points using standard QAM techniques at symbol rate, b I, and m 2 is the number of symbols or constellation points for fractional QAM encoding at symbol rate, b2. For example from the table in FIG. 15, for 24000 bits/sec at b 1 =2400 symbols/sec, the 35 number of bits per symbol is 10 and the number of signal points m I = 1024 (m 1 = 224000/2400). If the symbol rate is increased to b 2 = 2743, the number of bits - per symbol is approximately 8.75 (24000/2743), and the number of signal points required for the same bit rate is reduced to m2 =431 (m 2 = smallese integer 2 224000/2743). The improvement in the performance is then about 3.18 db.
S Inspection of the table in FIG. 15 indicates that for a given symbol rate, the divisor for c for each bit rate is either the same (for example 7 for a 2800 symbol rate) or have a common multiple. For example, for 3086 symbol rates the division is either 3 or 9. For 3200 symbol rates, the divisor is either 2 or 4. This divisor shows the number of symbols required to send the number of bits indicated by the dividend.
For example for a 3200 symbol rate, 24000 bits/s transmission ratio c = 15/2 indicadng that 2 symbols are required to send 15 bits, using a QAM scheme of 182signal points or symbols (182 = smallest integer 22l5/2).
In the present invention, the fractional rate (or fractional number of bits per symbol) encoding is accomplished as follows. First the incoming binary data .
15 bits a~e partitioned into words with a preselected number of words forming a frame.
The frame undergoes a modulus conversion with the number of signal points or symbols composing the constelladon being used as a modulus, and with the number of words composing the frame being equal to the number of fracdonally encoded words that represent the frame after the modulus conversion. Each of the 20 fracdonally encoded words are used to specify a symbol to be transmitted. More pardcularly, the number of bits per frame is equal to the numerator of the rado c as defined above. The number of words per frame is equal to the divisor of rado c.
Each word is made up of an integer number of bits and the number of bits per word may be different. Output data will be grouped into fracdonally encoded words or 25 remainders which may contain a fractional number of bits idendfied by log2m where m is the modulus or number of symbols in the symbol constellation that will be used to transmit information. All fractionally encoded words will have the same modulus for efficient transmission. Input data is in binary words. Output data is in fracdonally encoded words. Advantageously, for a given symbol rate, while the 30 number of bits per word may change, the same number of words is grouped to form -frames having the same number of bits. FIG. 16 shows how bits may be arranged into words and the words may be grouped into frames. For example, for a 3200 symbol rate the number of words per frame is selected to equal the least common muldplier for the divisors, i.e., four. Then for 24000 bits/sec at 3200 syrnbols/sec 35 each sequendal 30 binary bits are partidoned into four words, the first and third words containing 8 bits and second and fourth words containing 7 bits. Similarly, as 212193~

- shown in FIGs. 15 and 16 for 3200 symboUsec,7200 bitlsec transmission, c = 9/4.
Therefore, a frame is used to transmit four words. The first word contains or corresponds tc three bits, and the remaining words contain 2 bits each. A frame undergoes a modulus conversion with the number of signal points composing the `
5 constellation being used as a modulus, and thereby produces four fractionally ¦
encoded words as detailed below. The fractionally encoded words are then fed to I ~ -mapper 600 in FIG. 17.
Details of a circuit used for modulus conversion are shown in FIG. 17.
The circuit 710 includes a serial in-parallel out shift register 712 for receiving data 10 bits on line 714, under the control of clock pulses on line 716. A mode selector 718 is used to set up the circuit to convert the data bits in accordance with the bit rate received on line 714 and the symbol rate of the particular channel used. Based on -these parameters, the mode selector generated three control parameters for the modula, i.e., m, the number of signal points used by mapper 600 to transmit the data 15 signals; b, the number of bits per each word; and f, the number of words per frame, ~ -as def~ned in FlGs. 15 and 16. The parameters, m and f, are constant for a given pair " `-of symbol and bit rates. The parameter b changes as shown in FIG. 15. For example, for a 24000 bitlsec, 3200 symboVsec. transmission, m=182, f-4 and b=7 or -~ -8.
The clock pulses on line 716 are used by bit counter 722 and a word counter 724. For the example given above (i.e.,24000 bit/sec 3200 symboVsec) inidally, b=8 (see FIG. 16).
While the data bits are entered serially into register 712, counter 722 counts the bits contained therein. Word counter 724 keeps track of the number of25 bits received and when this number equals b, the word counter generates an enabling signal on line 726. Register 712 has an output port illustrated in FIG. 17 syrnbolically as a switch 728. Similarly, counter 722 has an output port symbolized by a switch 730. In response to the enabling signal on line 726, switch 728 transfers in parallel the b bits found in register 712 to a remainder cell 732. Similarly, in ~ `
response to the enabling pulse on line 726, switch 730 also transmits count b from counter 722 to a look-up table such as a ROM 736. In response, ROM 736 generatesa binary signal equal to 2b on line 738. This 2b is the modulus or base of the input data ward in register 712. Finally, the signal on line 726 is also used as a clock -signal to clock the various elements of the remainder cell 732, as well as the other 35 remainder cells described more fully below.

.

212~93~

- Remainder cell 732, as well as the other remainder cells such as cells 740 and 742 are used to calculate the remainder in modulus m for the f words in a frame. More particularly, each remainder cell calculates the remainder for one of the words, with the higher remainder cells also taking into account the integer portion of S the quodent generated by the previous cells. Thus, the number of remainder cells required for a conversion is equal to f. In FIG. 17, the first cell 732, second cell 740, and last or most significant digit cell 742 are shown. Since all the cells are idendcal, the cell between cells 740 and 742 (and more intermediate cells for converters with more words per frame) are not shown for the sake of simplicity.
For a first word X0, in remainder cell 732, the bits from register 712 for a first word X0 are first entered into an adder 744. Adder 744 receives a secondinput from a multiplier 746. Multiplier 746 multiplies the outputs of register 748 and ROM 736. Since at the end of each frame, the clear signal on line 727 clearsregister 748, for the first byte in register 712, the output of multiplier 746 is 0. The 15 output of adder 744 is entered on line 750 to a multiplier 752 and an adder 754. An inverter 75S is uscd to invert the parameter m from mode selector 718 thereby generadng a parameter 1/m describcd in more detail below. Muldplier 752 in effect divides the output of adder 744 by m and generates a quodent which has two components; an integer component Q and a fracdonal component Fr. Instead of this20 scheme, a true division may also be performed. However, multiplicadon by thc inverse because it is easier and cheaper to implement is preferable. Fracdonal component Fr is truncated to zero. The integer component Q is multiplied in multiplier 756 by m to scalc it back to the magnitude before the operation of multiplier 752. The output of multiplier 756 is fed to adder 754 which subtracts it 25 from the output of adder 744 on line 750. The output of adder 754 is the remainder of first word X0 from register 712 when divided by m. This remainder is stored in ~ ~ -register 748 as a remainder R0. The remainder is always less than m. The quodentQ passes through adders 844 and 854 of remainder cell 40 and is stored in register 848 as a remainder R1. -If a multiplication by the inverse l/m rather than a true division is performed, a quantizing error is introduced into the process. A check may be performed at the end of each iteration to insure that as a result of this quantizing error, the output of adder 754 is not too large. For example, the output of adder 754 may be compared to m. An output bigger than m is unacceptab1e. This error may be35 corrected by subtracting m from the output of adder 754 (several times if necessary until the adder 754 is reduced below m). For each correction, the integer component -`. 2~21~3~ ~:- 17- -~
Q on line Q must be increased by one.
For the next word X I, a similar iteration occurs with two exceptions: -since new word X ~ has only 7 b;ts, b now is changed to 7 in accordance with thearTangement of bits shown in E~IG. 16, and adder 744 adds R 0 2b to X l . The rest of S the remainder cells operate on this new sum as described above. The multiplier is important because it allows successive words of various bits in size to be successively converted. Conventional modulus or base conversion would require all bits in a frame to be held in a single large register with increased complexity. After four iterations, during which each of the cells is progressively brought into play, the ~-10 registers in the remainder cells contain the remainders required to uniquely define f bits from register 712 in modula m. The intermediate results of the iterations and the final contents of the registers 748, 848, 948 are shown in table I below~

TABLE I

SY~1BOL D~mlT Ro al R2 R~
PERIOD
- :
o XO Ro=reimXo Rl =mo~Xo Xl R'o=2~RolXI R'1=2~RI ~modR'o R2=modR' Ro=rcimR'o Rl =~mR' 2 X~ a~o~2~R~x~ R'l ~2~RI ~modR'o R'~.2~R~tmodR'I R~=modR'~
Ro = ~ a o Rl = rem R'l R2 = lem R 2 3 X~ R'o=2~Ro~X~ R'1 =2~RI I modR'o R'2=2~R~modR'1 R'~=mod2~R~ ~ modR'2 Ro = I~im R~o Rl = lan R'l R~ = rem R 2 R~ = rtm R'~ .

In this table the R'; indicates thc output of the initial adder of the i-th cell. Thus, when second word X I is rcad into the first remainder cell 732, 15 intermediate parametcr R'o is given by R'o = 2bRo + X 1.
After the remainders for all the bytes of a frame have becn generated, word counter 724 generates a pulse on line 727 which, as previously mentioned, clears the registers 748,848, 948 of each remainder cells. However, the information from these registers is transferred before clearing to respective storage registers 762, ~ -20 764 and 768.
':

l8 2 1 2 1 9 ~ ~
.

- In the next four symbol periods (a symbol provides l/symbol rate) (for f=4), the remainder cells convert the next four words as described above.
Meanwhile, muldplexer switch 770 samples each of the storage register 762, 764, . . . 768, starting with the most significant remainder found in storage register 5 768. The remainders or fracdonally encoded words stored therein are then sequendally transferred by switch 770 to mapper 600. The mapper also receives the modu1us m from mode selector 718. The switch 770 may be stepped from one storage register to another by the clock pulses on line 726. The same cloclc pulses may also be used by mapper 600 to generate the data signals that specify symbols or 10 signal points. The mapper generates a symbol or signal point constelladon of m points. All remainders are limited to values between O and m-l. As a result, the last remainder cell 742 has a zero integer component Q, and overflow or non-zero Q isprevented. The modulus m is chosen to be the smallest integer greater than 2c where c=bit rate/symbol rate. Since m4 22(b+bl +b2+b3), the modulus is chosen such that 15 overflow can not occur. The bit rate is achieved with the smallest possible signal constelladon or modulus. The output of mapper 600 is tleated in the same manner as the output of mapper 60 of FIG. 6.
At the receiver end, as shown in FIG. 18, signals from communication channel 774 are converted back into remainders or fracdonally encoded words by 20 receiver circuitry 776. Receiver 776 comprises the circuitry of FIG. 10, except that de-mapper 230 receives the modulus m from mode selector 780. De-mapper 230 decodes the received symbol or signal points using a constelladon of m points.
Mode selector 780 generates the parameters m and f in a manner identical to mode ~ -selector 718. Muldpliers bO, bl, b2, b3 and their inverses are stored in a register 25 781. Alternadvely, the inverses of these parameters are calculated as described more fully above. Again, the number of remainder circuits is equa1 to the number of words per frame f. The remainder circuits are used to convert thc fracdonally encoded words into standard binary words. In remainder circuit 790, the bits obtained from de-mapping the first received symbol, which encoded the first 30 fracdonally encoded word from a given frame, are fed to adder 800. The output of adder 800 is fed to multiplier 802 and another adder 804. Muldplier 802 divides its input by 2b to generate a truncated integer Q described above. The integer Q is fed into a second muldplier 806 which multiplies by 2b. The output is subtracted from the output of adder 800 by adder 804 to generate a flrst remainder. This first 35 remainder is stored in register 808. The quotient Q is processed by the next remainder circuit 792.

~12~9~6 ,~ , 19- .
In the next symbol period, multiplier 810 multiplies the output remainder in register 808 by m and the product is added by adder 800 to the bitsobtained from de-mapping the next symbol, which represented the next fracdonallyencoded word of the frame. The whole process is then repeated. At the end of the5 frame, the buffer registers of the remainder circuits 790, 792,794, 796 contain the remainders which are saved in buffer register 890, 892, 894, 896 and mu1tiplexed by a switch 812, starting with the output of the last remainder circuit 896. The binary signals from switch 812 are then fed to a register 814 for further processing.
Operation of the receiver remainder circuits is idendcal to the 10 transmitta except the multiplier coefficients are changed. These coefficients are -~ -generally pre-computed. The inverse, for example, depends on the register size used in the converter. For 16 bit registers the inverse is computed as 65536/m or (l/m) (2l6). The division is then accomplished by keeping only the most significant 15bits of the 31 bit product of two 16 bit 2's compliment numbers. This is effectively a 15 right shift of 16 bits or division by 65536. Note than 2- 16 = 1 /65536.
In the receiver, the remainder circuits are restoring the original binary words with integer numbers of bits as they were received in register 712 at the transmitter. Thus, the multipliers 2-bi and 2bi in the receiver can be accomplished ~ ;
by shift operations.
Table II illustrates typical coefficients for 3200 symbols/sec using 16 bit registers selected in accordance with the principles set forth above. ; -. -::, .: "
. .. :.~.
., ''~ ' ' ,~' 2~219~
,~
. 20 -i EXAMPLe OF PRE{:OMPUTED COEFPICIENTS FOR
ALL DATA RATES AT 3200 SYMBOLS/SEC USING 16 BIT REGlSTeRS
r~ ~R~c C m Ihn2~32-~32~2 2--2 2~1 2-~ 2N 2-~

24000 ISn 182 360 256 256 128 512 256 256 128 512 14400 9n 232840 322048164096322048 164096 120001514 14468~ 164096164096t64096 88192 9600 3 88192 88192 88192 88192 88192 .
7200 914 513107 88192 4163U 416384 4163U ;
~; ': - '-m m~ r22' ~:` .
I/m~21~/m It should be understood that the apparatus may be implemented by using i a microprocessor rather than using discrete components, for example by using a software program written in C.
Modu10s converting is one of many techniques available to accomplish simultaneous analog and digital communication using fracdonal rate encoding. Anyof the well known techniques to produce a fractionally encoded data signal may be ;
used to produce the data signal that is added to the analog signa1. For exarnple, it is also possible to perform fractional rate encoding by switching constellations. For o example, to achieve 4800 bits per second with 3000 symbols per second (1.6 bits per symbol), an 8 bit fran~e is partitioned into 3 words containing 2 bits each and 2 words containing 1 bit each. The 3 words with 2 bits are transmitted using a 4 symbol constellation, and the 2 words with 1 bit are transmitted using a 2 symbol constellation. This results in a total of 8 bits being transmitted using 5 symbols to 15 achieve 1.6 bits per symbol. A desired fractional encoding may be achieved usingconstellations of any size and/or combinations of two or more symbol constellations.
This technique offers the advantage of fractional rate encoding while using , : '. :.

212193~
:

~ -21- ' ~
- constellations that have square decision regions.
-Other techniques for fractional rate encoding may be used. These techniques are wel1 known in the art and include techniques such as the multidimensional signaling scheme disclosed in U. S. patent 5,115,453, and the S shell mapping scheme, the radix mapping scheme and the half bit signaling scheme i -disclosed in CCITT V.fast modem standard recommendations D196, D115 and D143, respectively.
. .
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1 ~ :
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! . .

;

Claims

1. A communication method CHARACTERIZED BY the steps of:
mapping data bits into a symbol constellation having a plurality of symbols to produce a data signal, each of said plurality of symbols representing a noninteger number of said data bits;
adding a second signal to said data signal to form a combined signal;
and transmitting said combined signal.

2. The method of claim 1, CHARACTERIZED IN THAT said step of transmitting comprises modulating said combined signal using QAM.

3. The method of claim 1, further CHARACTERIZED BY the step of encoding an input signal to produce said second signal, said second signal having two dimensions.

4. A communication method CHARACTERIZED BY the steps of:
encoding binary data having binary bits, to produce fractionally encoded words, mapping said fractionally encoded words into a symbol constellation to produce a data signal;
adding a second signal to said data signal to form a combined signal;
and transmitting said combined signal.

5. The method of claim 4 CHARACTERIZED IN THAT said step of encoding comprises using a modulus m converter to produce said fractionally encoded words, where m is the nearest integer larger than 2c and c is a noninteger,

6. The method of claim 5, CHARACTERIZED IN THAT said step of transmitting comprises modulating said combined signal using QAM.

7. The method of claim 5, further CHARACTERIZED BY the step of encoding an input signal to produce said second signal, said second signal having two dimensions.

8. The method of claim 5, CHARACTERIZED IN THAT said step of encoding binary data comprises partitioning said binary data into sequential frames, each frame having a predetermined number of said binary bits.

9. The method of claim 9, CHARACTERIZED IN THAT said step of encoding binary data comprises partitioning said frames into words, at least twowords within each of said frames having an unequal number of said binary bits.

10. The method of claim 9, CHARACTERIZED IN THAT said step of encoding binary data comprises dividing each of said words in sequence by a modulus to generate fractionally encoded words.