CA2124424A1 - Fast Connection Setup Interfaces Using Pre-Assigned Virtual Channel Identifiers - Google Patents

Fast Connection Setup Interfaces Using Pre-Assigned Virtual Channel Identifiers

Info

Publication number
CA2124424A1
CA2124424A1 CA2124424A CA2124424A CA2124424A1 CA 2124424 A1 CA2124424 A1 CA 2124424A1 CA 2124424 A CA2124424 A CA 2124424A CA 2124424 A CA2124424 A CA 2124424A CA 2124424 A1 CA2124424 A1 CA 2124424A1
Authority
CA
Canada
Prior art keywords
vcis
signaling
vci
outgoing
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2124424A
Other languages
French (fr)
Other versions
CA2124424C (en
Inventor
Hiroshi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ciena Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of CA2124424A1 publication Critical patent/CA2124424A1/en
Application granted granted Critical
Publication of CA2124424C publication Critical patent/CA2124424C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L45/00—Routing or path finding of packets in data switching networks
    • H04L45/02—Topology update or discovery
    • H04L45/10—Routing in connection-oriented networks, e.g. X.25 or ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5629—Admission control
    • H04L2012/563—Signalling, e.g. protocols, reference model
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5638—Services, e.g. multimedia, GOS, QOS
    • H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
    • H04L2012/5652—Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly

Abstract

In a packet-switched network in which a source station dissembles a packet into multiple cells and transmits them in sequence to a destination station, each switching system pre-assigns a unique set of VCI to each outgoing line. Corresponding respectively to incoming lines, each switching system includes line interface units for receiving normal signaling cells, a fast signaling cell and a data cell. Each interface unit includes a memory for storing the VCIs pre-assigned to the outgoing lines and a header translation table for defining relationships between a set of incoming VCIs and a corresponding set of outgoing VCIs. The interface unit assigns one of the stored VCIs to the fast signaling cell according to its destination, establishes a connection in the translation table between an incoming VCI and the assigned outgoing VC, and assigns an outgoing VCI
of the established connection to the data cell according to an incoming VCI contained in the data cell. A central controller is provided for assembling the normal signaling cells into a signaling packet and assigning one of the stored VCIs to each of the normal signaling cells comprising the signaling packet. A self-routing switch provides routing of any of the cells according to a VCI assigned thereto.
CA002124424A 1993-05-27 1994-05-26 Fast connection setup interfaces using pre-assigned virtual channel identifiers Expired - Lifetime CA2124424C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP12454993A JP2518515B2 (en) 1993-05-27 1993-05-27 High-speed connection setup packet switch
JP5-124549 1993-05-27

Publications (2)

Publication Number Publication Date
CA2124424A1 true CA2124424A1 (en) 1994-11-28
CA2124424C CA2124424C (en) 1999-09-28

Family

ID=14888232

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002124424A Expired - Lifetime CA2124424C (en) 1993-05-27 1994-05-26 Fast connection setup interfaces using pre-assigned virtual channel identifiers

Country Status (3)

Country Link
US (1) US5463621A (en)
JP (1) JP2518515B2 (en)
CA (1) CA2124424C (en)

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Also Published As

Publication number Publication date
JPH06338901A (en) 1994-12-06
CA2124424C (en) 1999-09-28
JP2518515B2 (en) 1996-07-24
US5463621A (en) 1995-10-31

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Effective date: 20140526