CA2124452A1 - Method and apparatus for processing data within stations of a communication network - Google Patents

Method and apparatus for processing data within stations of a communication network

Info

Publication number
CA2124452A1
CA2124452A1 CA002124452A CA2124452A CA2124452A1 CA 2124452 A1 CA2124452 A1 CA 2124452A1 CA 002124452 A CA002124452 A CA 002124452A CA 2124452 A CA2124452 A CA 2124452A CA 2124452 A1 CA2124452 A1 CA 2124452A1
Authority
CA
Canada
Prior art keywords
central processing
data communication
processing unit
communication controller
data path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002124452A
Other languages
French (fr)
Other versions
CA2124452C (en
Inventor
Min Paul Tan
Eric Fuh
Philip Tze-Tak Chan (Deceased)
John Ta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Standard Microsystems LLC
Original Assignee
Min Paul Tan
Eric Fuh
Philip Tze-Tak Chan (Deceased)
John Ta
Chan, Anna L.
Standard Microsystems Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Min Paul Tan, Eric Fuh, Philip Tze-Tak Chan (Deceased), John Ta, Chan, Anna L., Standard Microsystems Corporation filed Critical Min Paul Tan
Publication of CA2124452A1 publication Critical patent/CA2124452A1/en
Application granted granted Critical
Publication of CA2124452C publication Critical patent/CA2124452C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H04L49/9078—Intermediate storage in different physical parts of a node or terminal using an external memory or storage device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9031—Wraparound memory, e.g. overrun or underrun detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H04L49/9068—Intermediate storage in different physical parts of a node or terminal in the network interface card
    • H04L49/9073—Early interruption upon arrival of a fraction of a packet
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/12—Protocol engines

Abstract

A high speed data communication controller comprising two independent central processing units (50 and 54), each has its own program instruction fetch data path; and instruction execution data path.
The data communication controller includes a du-al-port serial communication subsystem (32) and a bus interface unit (40) operably associated with a four channel DMA controll-er (43). One central processing unit (29) is assigned the task of handling the medium access control (MAC) layer function of a multilayered local area network protocol, while the other central processing unit handles host commands (27) and buffer memory management functions associated with the transmission and reception of packets relating to the higher layer protocol. As a result of the present invention, efficient data communication processing is achieved within a single VLSI chip, thereby improving node and network data throughout.
CA002124452A 1992-09-28 1993-09-22 Method and apparatus for processing data within stations of a communication network Expired - Fee Related CA2124452C (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US95245092A 1992-09-28 1992-09-28
US952,450 1992-09-28
US965,145 1992-10-22
US07/965,145 US5434976A (en) 1992-09-28 1992-10-22 Communications controller utilizing an external buffer memory with plural channels between a host and network interface operating independently for transferring packets between protocol layers
PCT/US1993/008985 WO1994008308A1 (en) 1992-09-28 1993-09-22 Method and apparatus for processing data within stations of a communication network

Publications (2)

Publication Number Publication Date
CA2124452A1 true CA2124452A1 (en) 1994-04-14
CA2124452C CA2124452C (en) 2003-07-29

Family

ID=27130328

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002124452A Expired - Fee Related CA2124452C (en) 1992-09-28 1993-09-22 Method and apparatus for processing data within stations of a communication network

Country Status (5)

Country Link
US (1) US5434976A (en)
EP (1) EP0619036B1 (en)
CA (1) CA2124452C (en)
DE (1) DE69327044D1 (en)
WO (1) WO1994008308A1 (en)

Families Citing this family (66)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5799205A (en) * 1992-11-13 1998-08-25 Mannesmann Aktiengesellschaft Transfer system for data exchange using two active central processing units directly connected together parallel to serial system bus directly connecting CPUs to dispersed devices
US5668971A (en) * 1992-12-01 1997-09-16 Compaq Computer Corporation Posted disk read operations performed by signalling a disk read complete to the system prior to completion of data transfer
FR2699706B1 (en) * 1992-12-22 1995-02-24 Bull Sa Data transmission system between a computer bus and a network.
US5574862A (en) * 1993-04-14 1996-11-12 Radius Inc. Multiprocessing system with distributed input/output management
US5832310A (en) * 1993-12-30 1998-11-03 Unisys Corporation Serial I/O channel having dependent and synchronous sources of control data and user defined data
US5983275A (en) * 1994-05-04 1999-11-09 Cirrus Logic, Inc. Apparatus for and method of providing interrupts to a host processor in a frame receiving system
US5761422A (en) * 1995-03-22 1998-06-02 Telefonaktiebolaget Lm Ericsson Transferring address of data in buffer memory between processors using read-only register with respect to second processor
US5774745A (en) * 1995-03-31 1998-06-30 Cirrus Logic, Inc. Method and apparatus for writing and reading entries in an event status queue of a host memory
US5682553A (en) * 1995-04-14 1997-10-28 Mitsubishi Electric Information Technology Center America, Inc. Host computer and network interface using a two-dimensional per-application list of application level free buffers
US5799314A (en) * 1995-06-30 1998-08-25 Sun Microsystems, Inc. System and method of controlling mapping of data buffers for heterogenous programs in digital computer system
US5648965A (en) * 1995-07-07 1997-07-15 Sun Microsystems, Inc. Method and apparatus for dynamic distributed packet tracing and analysis
US5729705A (en) * 1995-07-24 1998-03-17 Symbios Logic Inc. Method and apparatus for enhancing throughput of disk array data transfers in a controller
FR2737592B1 (en) * 1995-08-03 1997-10-17 Sgs Thomson Microelectronics HDLC CIRCUIT WITH SHARED INTERNAL BUS
US6009527A (en) * 1995-11-13 1999-12-28 Intel Corporation Computer system security
KR0164546B1 (en) * 1996-01-09 1999-01-15 김광호 Partition use method of memory
US5841992A (en) * 1996-03-25 1998-11-24 Snap-On Tools Company Network-to-serial device intelligent converter
EP0804008B1 (en) * 1996-04-26 2006-11-15 Texas Instruments Incorporated Apparatus for data packet transfer control
US6006286A (en) * 1996-04-26 1999-12-21 Texas Instruments Incorporated System for controlling data packet transfers by associating plurality of data packet transfer control instructions in packet control list including plurality of related logical functions
SG77135A1 (en) * 1996-04-26 2000-12-19 Texas Instruments Inc Method and system for assigning a channel number to a received data packet
US5818844A (en) * 1996-06-06 1998-10-06 Advanced Micro Devices, Inc. Address generation and data path arbitration to and from SRAM to accommodate multiple transmitted packets
US5761428A (en) * 1996-07-05 1998-06-02 Ncr Corporation Method and aparatus for providing agent capability independent from a network node
US5933654A (en) * 1996-09-24 1999-08-03 Allen-Bradley Company, Llc Dynamic buffer fracturing by a DMA controller
US5930480A (en) * 1996-10-10 1999-07-27 Apple Computer, Inc. Software architecture for controlling data streams based on linked command blocks
US6072781A (en) 1996-10-22 2000-06-06 International Business Machines Corporation Multi-tasking adapter for parallel network applications
US6718375B1 (en) * 1997-01-31 2004-04-06 Hewlett-Packard Development Company, L.P. Using local storage to handle multiple outstanding requests in a SCI system
US6381657B2 (en) * 1997-01-31 2002-04-30 Hewlett-Packard Company Sharing list for multi-node DMA write operations
US6108713A (en) * 1997-02-11 2000-08-22 Xaqti Corporation Media access control architectures and network management systems
US6128674A (en) * 1997-08-08 2000-10-03 International Business Machines Corporation Method of minimizing host CPU utilization in driving an adapter by residing in system memory a command/status block a soft interrupt block and a status block queue
US6049845A (en) * 1997-11-05 2000-04-11 Unisys Corporation System and method for providing speculative arbitration for transferring data
GB2332335A (en) * 1997-12-10 1999-06-16 Northern Telecom Ltd Network management system
US6021430A (en) * 1998-04-15 2000-02-01 Unisys Corporation Output interface method and system for enhanced data transfers via cooperative service interface
US6009463A (en) * 1998-04-15 1999-12-28 Unisys Corporation Cooperative service interface with buffer and lock pool sharing, for enhancing message-dialog transfer between network provider and distributed system services
GB9809203D0 (en) * 1998-04-29 1998-07-01 Sgs Thomson Microelectronics Packet distribution in a microcomputer
US6067300A (en) * 1998-06-11 2000-05-23 Cabletron Systems, Inc. Method and apparatus for optimizing the transfer of data packets between local area networks
US6373841B1 (en) * 1998-06-22 2002-04-16 Agilent Technologies, Inc. Integrated LAN controller and web server chip
US6438133B1 (en) 1998-09-09 2002-08-20 Cisco Technology, Inc. Load balancing mechanism for a translational bridge environment
US7046625B1 (en) * 1998-09-30 2006-05-16 Stmicroelectronics, Inc. Method and system for routing network-based data using frame address notification
US6526451B2 (en) * 1998-09-30 2003-02-25 Stmicroelectronics, Inc. Method and network device for creating circular queue structures in shared memory
US6360259B1 (en) * 1998-10-09 2002-03-19 United Technologies Corporation Method for optimizing communication speed between processors
US7181548B2 (en) 1998-10-30 2007-02-20 Lsi Logic Corporation Command queueing engine
EP1171957A2 (en) * 1998-11-12 2002-01-16 I-Data International A/S Apparatus and method for performing and controlling encryption/decryption for data to be transmitted on local area network
US6487606B1 (en) * 1998-11-18 2002-11-26 Nortel Networks Limited System and method for delivering messages through a totem communications system
US6738821B1 (en) * 1999-01-26 2004-05-18 Adaptec, Inc. Ethernet storage protocol networks
US6665306B1 (en) * 1999-11-24 2003-12-16 Intel Corporation Immediate cut-off protocol and interface for a packet-based bus connecting processors
US6862630B1 (en) * 2000-08-23 2005-03-01 Advanced Micro Devices, Inc. Network transmitter with data frame priority management for data transmission
US7401126B2 (en) * 2001-03-23 2008-07-15 Neteffect, Inc. Transaction switch and network interface adapter incorporating same
US20020184381A1 (en) * 2001-05-30 2002-12-05 Celox Networks, Inc. Method and apparatus for dynamically controlling data flow on a bi-directional data bus
US6880077B2 (en) * 2001-09-28 2005-04-12 Intel Corporation Enabling communication between video BIOS and graphics drivers
US6865622B2 (en) 2002-05-13 2005-03-08 Intel Corporation System including real-time data communication features
JP4385247B2 (en) * 2003-08-04 2009-12-16 日本電気株式会社 Integrated circuit and information processing apparatus
US7536674B2 (en) * 2003-08-13 2009-05-19 Intel Corporation Method and system for configuring network processing software to exploit packet flow data locality
JP4401788B2 (en) * 2004-01-06 2010-01-20 株式会社日立製作所 Storage controller
US7774374B1 (en) * 2004-03-02 2010-08-10 Qlogic Corporation Switching systems and methods using wildcard searching
US20060004904A1 (en) * 2004-06-30 2006-01-05 Intel Corporation Method, system, and program for managing transmit throughput for a network controller
DE102004052612B4 (en) * 2004-10-29 2008-04-17 Qimonda Ag Semiconductor memory module, semiconductor memory module and method for transmitting write data to semiconductor memory devices
KR20070116893A (en) * 2005-03-30 2007-12-11 웰치알린인코포레이티드 Communication of information between a plurality of network elements
US8458280B2 (en) * 2005-04-08 2013-06-04 Intel-Ne, Inc. Apparatus and method for packet transmission over a high speed network supporting remote direct memory access operations
US7782905B2 (en) * 2006-01-19 2010-08-24 Intel-Ne, Inc. Apparatus and method for stateless CRC calculation
US7889762B2 (en) 2006-01-19 2011-02-15 Intel-Ne, Inc. Apparatus and method for in-line insertion and removal of markers
US7849232B2 (en) * 2006-02-17 2010-12-07 Intel-Ne, Inc. Method and apparatus for using a single multi-function adapter with different operating systems
US8078743B2 (en) * 2006-02-17 2011-12-13 Intel-Ne, Inc. Pipelined processing of RDMA-type network transactions
US8316156B2 (en) * 2006-02-17 2012-11-20 Intel-Ne, Inc. Method and apparatus for interfacing device drivers to single multi-function adapter
US7787375B2 (en) * 2007-08-06 2010-08-31 International Business Machines Corporation Performing a recovery action in response to a credit depletion notification
US7975027B2 (en) * 2007-08-06 2011-07-05 International Business Machines Corporation Credit depletion notification for transmitting frames between a port pair
CN103067240B (en) * 2013-01-04 2016-01-06 中国兵器工业集团第二一四研究所苏州研发中心 Four road universal serial bus and four tunnel CAN change-over circuits
US11281609B2 (en) * 2019-03-12 2022-03-22 Preferred Networks, Inc. Arithmetic processor and control method for arithmetic processor

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4667287A (en) * 1982-10-28 1987-05-19 Tandem Computers Incorporated Multiprocessor multisystem communications network
US4663706A (en) * 1982-10-28 1987-05-05 Tandem Computers Incorporated Multiprocessor multisystem communications network
US4789982A (en) * 1986-01-27 1988-12-06 Codenoll Technology Corporation Method for implementing a token passing ring network on a bus network
US4771391A (en) * 1986-07-21 1988-09-13 International Business Machines Corporation Adaptive packet length traffic control in a local area network
US4750114A (en) * 1986-07-28 1988-06-07 Honeywell Bull Inc. Local area network control block
GB8709771D0 (en) * 1987-04-24 1987-05-28 Madge Networks Ltd Token ring expander/hub
JPH0787461B2 (en) * 1987-06-19 1995-09-20 株式会社東芝 Local Area Network System
JPS6450152A (en) * 1987-08-20 1989-02-27 Fujitsu Ltd Communication controller
US4914652A (en) * 1988-08-01 1990-04-03 Advanced Micro Devices, Inc. Method for transfer of data between a media access controller and buffer memory in a token ring network
US4951280A (en) * 1988-12-09 1990-08-21 Advanced Micro Devices, Inc. Method and apparatus for configuring data paths within a supernet station
CA2011935A1 (en) * 1989-04-07 1990-10-07 Desiree A. Awiszio Dual-path computer interconnect system with four-ported packet memory control
US5247626A (en) * 1990-05-29 1993-09-21 Advanced Micro Devices, Inc. Fddi controller having flexible buffer management
JP2530060B2 (en) * 1991-01-17 1996-09-04 株式会社東芝 Communication control device
US5165021A (en) * 1991-01-18 1992-11-17 Racal-Datacom, Inc. Transmit queue with loadsheding
US5175732A (en) * 1991-02-15 1992-12-29 Standard Microsystems Corp. Method and apparatus for controlling data communication operations within stations of a local-area network

Also Published As

Publication number Publication date
CA2124452C (en) 2003-07-29
WO1994008308A1 (en) 1994-04-14
EP0619036B1 (en) 1999-11-17
DE69327044D1 (en) 1999-12-23
US5434976A (en) 1995-07-18
EP0619036A1 (en) 1994-10-12
EP0619036A4 (en) 1995-02-15

Similar Documents

Publication Publication Date Title
CA2124452A1 (en) Method and apparatus for processing data within stations of a communication network
US5247626A (en) Fddi controller having flexible buffer management
US5151895A (en) Terminal server architecture
US6839345B2 (en) MAC/PHY interface
US5764895A (en) Method and apparatus for directing data packets in a local area network device having a plurality of ports interconnected by a high-speed communication bus
WO1992006436A3 (en) Parallel computer system
CA2159459A1 (en) Method and System for Managing Memory in a High Speed Network
JP3684405B2 (en) Data structure to support multiple transmission packets with high performance
CA2105866A1 (en) Method and apparatus for buffering data within stations of a communication network
US5748634A (en) Method and apparatus for implementing a two-port ethernet bridge using a semaphoring technique
EP0119039A3 (en) Token access controller protocol and architecture
EP1014649A3 (en) Method and system of data transfer control
JPH0787461B2 (en) Local Area Network System
JPH05204835A (en) General purpose device for connecting bus of computer to controller of peripheral equipment
CA2194026A1 (en) Method and apparatus for moving data packets between networks while minimizing cpu interventions using a multi-bus architecture
CA2130064A1 (en) Method and Apparatus for Transferring Data Between a Host Processor and a Subsystem Processor in a Data Processing System
KR0177734B1 (en) Ihgh-speed data exchanging apparatus for ethernet system
JP2611388B2 (en) Data processing device
JPS58170155A (en) Packet communication system
KR970002360B1 (en) Method for protecting map-communication
JPH04282938A (en) Communication controller
JP2596098B2 (en) Communication line selection method
Frese et al. FPSS-A Fast Packet Switching System
CA2077750A1 (en) Apparatus for Networking Programmable Logic Controllers to Host Computers
JPS6121654A (en) Communication controller

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed