CA2129825A1 - Real Time Processing System - Google Patents

Real Time Processing System

Info

Publication number
CA2129825A1
CA2129825A1 CA 2129825 CA2129825A CA2129825A1 CA 2129825 A1 CA2129825 A1 CA 2129825A1 CA 2129825 CA2129825 CA 2129825 CA 2129825 A CA2129825 A CA 2129825A CA 2129825 A1 CA2129825 A1 CA 2129825A1
Authority
CA
Canada
Prior art keywords
bus
memory
port
real time
processing system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA 2129825
Other languages
French (fr)
Other versions
CA2129825C (en
Inventor
Anil Gupta
Walter Nixon
Hugh Humphreys
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems, Inc.
Anil Gupta
Walter Nixon
Hugh Humphreys
Encore Computer U.S., Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems, Inc., Anil Gupta, Walter Nixon, Hugh Humphreys, Encore Computer U.S., Inc. filed Critical Sun Microsystems, Inc.
Publication of CA2129825A1 publication Critical patent/CA2129825A1/en
Application granted granted Critical
Publication of CA2129825C publication Critical patent/CA2129825C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Abstract

A real time data processing system consisting of a plurality of processing nodes (NODE1, NODE2, NODE3) and a write only reflective data link (46) for transferring information containing writes only between the plurality of processing nodes (NODE1, NODE2, NODE3). All the nodes (NODE1, NODE2, NODE3) include a bus (22), a processor (20) coupled to the bus (22), a memory (40) having at least two ports with one port (42) connected to the bus (22) and the other port (48) connected to the data link (46) and a sensor (60) for sensing a write to the memory (40). At least one node has a VME bus (22) as the bus (22) and serves as an I/O connected to one port (42) of the memory (40). Further a local bus (24) is included for inputting and outputting from the memory (40). The local bus (24) is connected to a third port (44) of the memory (40).
CA002129825A 1992-03-25 1993-03-25 Real time processing system Expired - Fee Related CA2129825C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US85758092A 1992-03-25 1992-03-25
US07/857,580 1992-03-25
PCT/US1993/002838 WO1993019421A1 (en) 1992-03-25 1993-03-25 Real time processing system

Publications (2)

Publication Number Publication Date
CA2129825A1 true CA2129825A1 (en) 1993-09-30
CA2129825C CA2129825C (en) 2000-08-15

Family

ID=25326307

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002129825A Expired - Fee Related CA2129825C (en) 1992-03-25 1993-03-25 Real time processing system

Country Status (8)

Country Link
US (1) US5475858A (en)
EP (1) EP0632912B1 (en)
JP (1) JP2677454B2 (en)
AU (1) AU3936593A (en)
CA (1) CA2129825C (en)
DE (1) DE69329904T2 (en)
ES (1) ES2154269T3 (en)
WO (1) WO1993019421A1 (en)

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KR0154618B1 (en) * 1995-11-01 1998-11-16 양승택 Dual port ram interfacing circuit of vme bus
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US6078994A (en) * 1997-05-30 2000-06-20 Oracle Corporation System for maintaining a shared cache in a multi-threaded computer environment
US5946711A (en) * 1997-05-30 1999-08-31 Oracle Corporation System for locking data in a shared cache
US6324623B1 (en) * 1997-05-30 2001-11-27 Oracle Corporation Computing system for implementing a shared cache
US6574720B1 (en) 1997-05-30 2003-06-03 Oracle International Corporation System for maintaining a buffer pool
US6295584B1 (en) * 1997-08-29 2001-09-25 International Business Machines Corporation Multiprocessor computer system with memory map translation
US6230252B1 (en) 1997-11-17 2001-05-08 Silicon Graphics, Inc. Hybrid hypercube/torus architecture
US5970232A (en) * 1997-11-17 1999-10-19 Cray Research, Inc. Router table lookup mechanism
US6101181A (en) * 1997-11-17 2000-08-08 Cray Research Inc. Virtual channel assignment in large torus systems
US6085303A (en) * 1997-11-17 2000-07-04 Cray Research, Inc. Seralized race-free virtual barrier network
US6163829A (en) * 1998-04-17 2000-12-19 Intelect Systems Corporation DSP interrupt control for handling multiple interrupts
US6393530B1 (en) 1998-04-17 2002-05-21 Intelect Communications, Inc. Paging method for DSP
US6456628B1 (en) * 1998-04-17 2002-09-24 Intelect Communications, Inc. DSP intercommunication network
US6678801B1 (en) * 1998-04-17 2004-01-13 Terraforce Technologies Corp. DSP with distributed RAM structure
US6216174B1 (en) 1998-09-29 2001-04-10 Silicon Graphics, Inc. System and method for fast barrier synchronization
DE10081049D2 (en) * 1999-04-20 2001-08-09 Siemens Ag Scalable multi-processor system for real-time applications in telecommunications
US6311255B1 (en) * 1999-04-29 2001-10-30 International Business Machines Corporation System and method for selectively restricting access to memory for bus attached unit IDs
US6751698B1 (en) 1999-09-29 2004-06-15 Silicon Graphics, Inc. Multiprocessor node controller circuit and method
US6674720B1 (en) 1999-09-29 2004-01-06 Silicon Graphics, Inc. Age-based network arbitration system and method
US6542949B1 (en) 1999-11-08 2003-04-01 International Business Machines Corporation Method and apparatus for increased performance of a parked data bus in the non-parked direction
US6889278B1 (en) * 2001-04-04 2005-05-03 Cisco Technology, Inc. Method and apparatus for fast acknowledgement and efficient servicing of interrupt sources coupled to high latency paths
US7010740B1 (en) * 2001-05-17 2006-03-07 Emc Corporation Data storage system having no-operation command
US6999998B2 (en) * 2001-10-04 2006-02-14 Hewlett-Packard Development Company, L.P. Shared memory coupling of network infrastructure devices
US6920485B2 (en) * 2001-10-04 2005-07-19 Hewlett-Packard Development Company, L.P. Packet processing in shared memory multi-computer systems
US20030069949A1 (en) * 2001-10-04 2003-04-10 Chan Michele W. Managing distributed network infrastructure services
US7315551B2 (en) * 2002-03-15 2008-01-01 Lockheed Martin Corporation Synchronous low voltage differential I/O buss
US20030185177A1 (en) * 2002-03-26 2003-10-02 Interdigital Technology Corporation TDD-RLAN wireless telecommunication system with RAN IP gateway and methods
US20060083102A1 (en) * 2004-10-20 2006-04-20 Seagate Technology Llc Failover control of dual controllers in a redundant data storage system
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Also Published As

Publication number Publication date
US5475858A (en) 1995-12-12
ES2154269T3 (en) 2001-04-01
JPH07504774A (en) 1995-05-25
AU3936593A (en) 1993-10-21
EP0632912B1 (en) 2001-01-31
CA2129825C (en) 2000-08-15
DE69329904T2 (en) 2001-06-13
JP2677454B2 (en) 1997-11-17
EP0632912A1 (en) 1995-01-11
DE69329904D1 (en) 2001-03-08
WO1993019421A1 (en) 1993-09-30
EP0632912A4 (en) 1998-06-03

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Legal Events

Date Code Title Description
EEER Examination request
FZDC Discontinued application reinstated
MKLA Lapsed