CA2132756A1 - High Efficiency Learning Network - Google Patents

High Efficiency Learning Network

Info

Publication number
CA2132756A1
CA2132756A1 CA2132756A CA2132756A CA2132756A1 CA 2132756 A1 CA2132756 A1 CA 2132756A1 CA 2132756 A CA2132756 A CA 2132756A CA 2132756 A CA2132756 A CA 2132756A CA 2132756 A1 CA2132756 A1 CA 2132756A1
Authority
CA
Canada
Prior art keywords
integer
operations
equal
high efficiency
learning network
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2132756A
Other languages
French (fr)
Other versions
CA2132756C (en
Inventor
Patrice Yvon Simard
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of CA2132756A1 publication Critical patent/CA2132756A1/en
Application granted granted Critical
Publication of CA2132756C publication Critical patent/CA2132756C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

Nodal outputs are discretized to values of S2n where n is an integer and S is equal to +1 or -1. During forward propagation, this offers the advantage offorming a product of a nodal output and a weight using a simple shift operation rather than a multiply operation. Replacing multiply operations with shift operations through out a neural network improves response times and permits building largernetworks that have broader applicability. Training is also improved by increasing the efficiency of backward propagation. The multiplications involved in backwardpropagation are reduced to shift operations by discretizing the errors associated with each node so that they are represented as S2n where n is an integer and S is equal to +1 or -1.
CA002132756A 1993-11-09 1994-09-23 High efficiency learning network Expired - Fee Related CA2132756C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/150,677 US5473730A (en) 1993-11-09 1993-11-09 High efficiency learning network
US150,677 1993-11-09

Publications (2)

Publication Number Publication Date
CA2132756A1 true CA2132756A1 (en) 1995-05-10
CA2132756C CA2132756C (en) 1999-05-18

Family

ID=22535542

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002132756A Expired - Fee Related CA2132756C (en) 1993-11-09 1994-09-23 High efficiency learning network

Country Status (6)

Country Link
US (1) US5473730A (en)
EP (1) EP0652525B1 (en)
JP (1) JPH07191950A (en)
CA (1) CA2132756C (en)
DE (1) DE69424372T2 (en)
TW (1) TW270186B (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5630024A (en) * 1994-01-19 1997-05-13 Nippon Telegraph And Telephone Corporation Method and apparatus for processing using neural network with reduced calculation amount
US6141044A (en) * 1996-09-26 2000-10-31 Apple Computer, Inc. Method and system for coherent image group maintenance in memory
US5883716A (en) * 1997-07-15 1999-03-16 Litton Systems, Inc. Rate control loop for fiber optic gyroscope
US7362892B2 (en) 2003-07-02 2008-04-22 Lockheed Martin Corporation Self-optimizing classifier
US7814038B1 (en) 2007-12-06 2010-10-12 Dominic John Repici Feedback-tolerant method and device producing weight-adjustment factors for pre-synaptic neurons in artificial neural networks
US8583577B2 (en) * 2011-05-25 2013-11-12 Qualcomm Incorporated Method and apparatus for unsupervised training of input synapses of primary visual cortex simple cells and other neural circuits
JP6567381B2 (en) * 2015-09-30 2019-08-28 株式会社東芝 Arithmetic apparatus, method and program
EP3557484B1 (en) * 2016-12-14 2021-11-17 Shanghai Cambricon Information Technology Co., Ltd Neural network convolution operation device and method
JP7029321B2 (en) * 2017-04-20 2022-03-03 パナソニック インテレクチュアル プロパティ コーポレーション オブ アメリカ Information processing methods, information processing equipment and programs
US11256978B2 (en) * 2017-07-14 2022-02-22 Intel Corporation Hyperbolic functions for machine learning acceleration
JP6504331B1 (en) * 2017-09-29 2019-04-24 ソニー株式会社 INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD
WO2019168088A1 (en) 2018-03-02 2019-09-06 日本電気株式会社 Inference device, convolution operation execution method, and program
CN113554163B (en) * 2021-07-27 2024-03-29 深圳思谋信息科技有限公司 Convolutional neural network accelerator

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2625347B1 (en) * 1987-12-23 1990-05-04 Labo Electronique Physique NEURON NETWORK STRUCTURE AND CIRCUIT AND ARRANGEMENT OF NEURON NETWORKS
AU633812B2 (en) * 1988-08-31 1993-02-11 Fujitsu Limited Neurocomputer
US4972363A (en) * 1989-02-01 1990-11-20 The Boeing Company Neural network using stochastic processing
US5222195A (en) * 1989-05-17 1993-06-22 United States Of America Dynamically stable associative learning neural system with one fixed weight
US5138924A (en) * 1989-08-10 1992-08-18 Yamaha Corporation Electronic musical instrument utilizing a neural network
US5109351A (en) * 1989-08-21 1992-04-28 Texas Instruments Incorporated Learning device and method
GB2236608B (en) * 1989-10-06 1993-08-18 British Telecomm Digital neural networks
US5067164A (en) * 1989-11-30 1991-11-19 At&T Bell Laboratories Hierarchical constrained automatic learning neural network for character recognition
JPH0782481B2 (en) * 1989-12-26 1995-09-06 三菱電機株式会社 Semiconductor neural network
US5255346A (en) * 1989-12-28 1993-10-19 U S West Advanced Technologies, Inc. Method and apparatus for design of a vector quantizer
US5167006A (en) * 1989-12-29 1992-11-24 Ricoh Company, Ltd. Neuron unit, neural network and signal processing method
US5058179A (en) * 1990-01-31 1991-10-15 At&T Bell Laboratories Hierarchical constrained automatic learning network for character recognition
JP3110434B2 (en) * 1990-03-17 2000-11-20 科学技術振興事業団 Analog backpropagation learning circuit
US5337395A (en) * 1991-04-08 1994-08-09 International Business Machines Corporation SPIN: a sequential pipeline neurocomputer
EP0461902B1 (en) * 1990-06-14 1998-12-23 Canon Kabushiki Kaisha Neural network
US5097141A (en) * 1990-12-12 1992-03-17 Motorola, Inc. Simple distance neuron
US5228113A (en) * 1991-06-17 1993-07-13 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Accelerated training apparatus for back propagation networks

Also Published As

Publication number Publication date
EP0652525B1 (en) 2000-05-10
DE69424372D1 (en) 2000-06-15
DE69424372T2 (en) 2000-09-21
JPH07191950A (en) 1995-07-28
TW270186B (en) 1996-02-11
EP0652525A2 (en) 1995-05-10
CA2132756C (en) 1999-05-18
EP0652525A3 (en) 1995-12-27
US5473730A (en) 1995-12-05

Similar Documents

Publication Publication Date Title
CA2132756A1 (en) High Efficiency Learning Network
Robinson et al. Static and dynamic error propagation networks with application to speech coding
WO1990003464A3 (en) Composite elastic necked-bonded material
ITRM920634A1 (en) QUICK CLOSING BAGS AND THEIR TRAINING METHOD.
ES2073567T3 (en) PARALLEL DISTRIBUTED PROCESS NETWORK IN WHICH CONNECTION WEIGHTS ARE GENERATED THROUGH THE USE OF DIFFERENTIAL EQUATIONS WITH CONSTANT COEFFICIENTS.
DE69422097D1 (en) Training of combined chain models with minimal error rate
EP0103722A3 (en) Multiplying circuit
Stanton Analytic extension of the holomorphic discrete series
EP0248166A3 (en) Binary multibit multiplier
EP0862110A3 (en) Wallace-tree multipliers using half and full adders
CA2158801A1 (en) Pipeline Weight and Method of Installing the Same
KR900009200A (en) Inertial welding method, product manufactured by the method and repair method using the inertial welding method
EP0385637A3 (en) Learning machine with multi-input single output circuits connected in hierarchical structure
AU6831696A (en) Apparatus for use as an educational toy
EP0373737A3 (en) General network modeling and synthesis
EP0291963A3 (en) Fast c-mos adder
WO1993018168A3 (en) Transgenic wheat
CA2024362A1 (en) Transmitting power control circuit
EP0174397A3 (en) Dummy load controlled multi-level logic single clock logic circuit
Lesgold Going from intelligent tutors to tools for learning
Greek Exporting success by degrees
JPS5476048A (en) Noncyclic variable filter
Yoshinaga et al. VERY SIMPLE PROOFS OF GENERALIZED PHYTAGOREAN THEOREM
JPS566525A (en) 2-phase clock pulse generating circuit
AU7091494A (en) Object-oriented input/output framework

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed