CA2139746A1 - A digital frequency conversion and tuning scheme for microwave radio receivers and transmitters - Google Patents

Abstract

A digital frequency upconversion and downconversion scheme for receivers and transmitters enables high resolution downconversion and upconversion, respectively, with low phase noise. A digital signal processor (DSP) (230) receives temperature measurement information from a temperature transducer associated with a reference oscillator (240), and also receives channel tuning and other information. The DSP adjusts the signal samples accordingly, without adjusting the operation of the oscillator. Additionally, the inventive filtering scheme, preferably implemented in an application specific integrated circuit (ASIC), receives digital filtering coefficient information, digital symbol timing phase control signals, and, in some cases, other information from the DSP. As a result, the scheme enables operation at 1 Hz resolution, with phase noise which is at least 33.5 dB down at 10 Hz in the case of downconversion, and at least 42 dB down at 10 Hz in the case of upconversion.

Description

WO 94/27375 213 9 7 ~ 6 PCT/US94/04812 .

A DIGITAL ~REQUENCY CONVERSION AND TUNING SCHEME
FOR MICROWAVE RADIO RECEIVERS AND TRANS~

BACKGROUND OF THE INVENTION
The pre. _nt invention relates to a method of and an apparatus for effecting frequency translation at microwave frequencies, and in particular to a frequencytr~nCl~tion scheme which works at L-band, using an analog-to-digital sampling scheme which enables elimin~tion of multiple-step mixer/local oscillator circuitry at the front end. The invention conte-mrl~t~s applicability to both reception (downconversion) and tr~ncmiccion (upconversion) at frequencies of 2 GHz or less.
Figure 1 shows a block diagram of a typical frequency-tunable RF-to-b~ceb~nd downconverter, employing a triple analog conversion scheme with a quadrature third conversion stage. An L-band filter 102 filters an L-band RF
input from a low noise ~mplifier (LNA). A first amplifier 104 receives the filtered output of the filter 102 and provides an amplified output to a first mixer 106, which also receives an output of a fixed local oscillator (LO) 120. The output of mixer 106 is provided to a first interm~Ai~te frequency (IF) filter 108, whose output is provided to a second ~mplifi~r 110, which comprises a variable gain amplifier which is driven by an automatic gain control (AGC) signal derivedfrom demodulator 150.
The output of ~r"plifier 110 is provided to a second mixer 112, which also receives an output of a tunable LO 122. The output of mixer 112 is provided to a second IF filter 114, whose output in turn is provided to a third amplifier 116.
The out~ut of amplifier is provided to mixers 132, 134. Mixer 132 receives an output of fixed LO 124 which is 90 out of phase (via phase shifter 126) from the LO 124 output which is provided to mixer 134. A high-stability frequency reference osç~ tor 130 provides reference values to the respective LOs.
The l~sl,eclive outputs of mixers 132, 134 are filtered in b~eb~nd filters 136, 138, and converted in respective analog-to-digital (A/D) converters 140, 142. The outputs of A/D converters 140, 142, which are quadrature and in-wO 94/27375 PcT/uss4/04812 21397~

phase values, respectively, are provided to a digital signal processor (DSP) based demodulator 150, which provides a demodulated output.
Variations employing different numbers of conversion stages also are known. In any event, each such conversion stage requires a mixer, an LO, and a filter to remove the undesired mixer products. A variable gain amplifier, which is placed in one of the stages for gain control, is driven by an AGC signal derived from the demodulator.
As shown in Figure 1, the second conversion stage uses a tunable LO for ch~nnel selection. The third LO is split into its in-phase (I) and quadrature (Q) CO~pOI ents. As a result, the final downconversion to b~ceb~nd is complex, requiring two mixers and two lowpass filters. The I and Q b~cPb~nd signals each are then sampled by an A/D converter. The resl~lting complex digital signal is sent to a digital signal plocessor for ~-lbse luent m~tt~llPd filtering, denlodul~tion, carrier recovery, and bit dete~tiQn.
Typically, each LO is phase-locked to a high-stability crystal frequency erele.lce oscill~tor 130, as shown, in order to m~int~in a high degree of frequency tuning ~-cu~.y. TmplernPnt~ti~n of the tunable LO 122 is based on one of three methods:
i) Analog rl~uency synthesis, in which a signal at the desired rr~uency is obtained by controlling one or more analog phase locked loop (PLL) circuits. The exact number of loops required ~epen~c on the total tuning range, step size, and phase-noise performance.
ii) Direct digital synthesis (DDS), in which the sine (and cosine) waveform at the desired frequency is generated digitally and is converted to an analog signal with a digital-to-analog (D/A) converter.
iii) Hybrid analog PLL/DDS, in which the output of a DDS synthes-izer is mixed with the outputs of one or more analog phase locked loops to give some of the advantages of both techniques.
A primary disadvantage rçclllting from the scheme shown in Figure 1 is the large number of components required. The analog filters often are large, WO 94/27375 ~ t 3 ~ 7 4 6 PCT/US94/04812 require precise component m~tching, and are difficult to incorporate into an integrated circuit. Other disadvantages include the following:
i) The reference oscillator 130 often requires an oven to m~in~in precise temperature control to minimi7e frequency drift. For low bit-rate S phase shift keying (PSK) or q~dr~t~re amplitude modulation (QAM) systems, the total frequency error in the downconversion process must be much less than the tr~n~mi~cion symbol rate in order to minimi7P losses in the demodulator m~tchecl filter and for the carrier tracking loop to acquire successfully.
ii) Analog frequency synthç~i7~rs are difficult to design for low phase noise, especially if a fine step size is required. The PLL loop bandwidth is directly propollional to the synthP-~i7~r step size. As the loop bandwidth is decreased, the loop is less able to track the extremely low phase distortion of the crystal reference oscillator accurately. A 1 Hz step size, which is desired, requires a large number of components, increasing system cost.
iii) DDS synthe~i7~ors exhibit low phase noise çh~r~rteri~ti~s~ but suffer from relatively high levels of spurious emissions. Pe.~l,l,ance is limited by the resolution and dynamic characteAstics of the subsequent D/A converter. The maximum frequency available from a DDS synthes-izer currently is limited to below 100 MHz, and thus is nn~uit~kle for oper~tion at L-band.
iv) Hybrid analog/digital synthe~i7~rs can achieve very low phase noise and extremely high frequency resolution, but again a large number of co",pone,lts is required.
v) Qu~r~t--re sampling requires an LO splitter with a precise 90 phase difference between the two ch~nne-l~. The two mixers, b~eb~nd filters, and A/D converters also must have precise phase and gain m~t~hing .

WO 94/27375 21)3 9 7-4~ PCT/US94/04812 vi) The baseband filter must have a constant group delay versus frequency response and minim~l p~csb~nd gain ripple so as to minimi7e intersymbol intelrelence. Typically, an eqll~li7~tion network is required.
vii) The use of multiple conversion stages requires careful construction S techniques in order to avoid inlelrel~;nce between stages. The mixers must be laid out so as to maximize the isolation between ports.
viii) The use of several stages of mixing and amplification often creates large DC offsets to the A/D converter. Typically either an analog nulling circuit precel1ing the A/D converter or a digital nulling algorithm following the A/D converter is required.
Other known approaches include the following.
USP 4,737,728, USP 5,142,553, and USP 5,172,070 ~iic~lose fixed-frequency receive-only sci-emçs which have some of the disadvantageous, space-taking mixer-oscillator structure shown in Pigure 1. The '728 patent does not 15sample at RP frequencies. The '553 patent refers to an "HF" carrier signal, but is not cpe~ific as to the frequency of that signal. Sampling is carried out after two mixing stages which downconvert the signal to an IF frequency.
USP 4,884,265 rliccloses a receive-only scheme o~lating at frequencies well below L-band.
20None of the aforernentioned patents discloses an efficient le~ dture compçn~tiQn scheme - an ecc~nti~l elemPnt in order to minimi7e frequency drift.
Other convçnticl-~l techniques include those disclosed in the following U.S. p~tPntc- 4,117,541; 4,138,730; 4,241,443; 4,312,062; 4,316,282;
4,636,972; 4,859,960; 4,910,469; and 5,077,531.
25It would be desirable to implement a frequency conversion scheme which is tunable to different frequen~i~s, which colllyenc~tes effici~ntly for frequency drift without ~lt~ing the operation of the reference oscill~tor~ and which is applicable not only to reception but also to tr~ncmiccion~ particularly at microwave frequencies (2 GHz and below). Such a system should operate at 30high resolution (preferably 1 Hz), and at low phase noise.

wo 94/27375 ~ 13 ~ 7 ~ 6 PCT~uSs4/048 SVMMARY OF THE INVENTION
In view of the foregoing, it is one object of the present invention to provide a scheme for digitally sampling an analog RF b~ndp~cs signal directly at microwave frequencies (2 GHz and below) and downconverting it to b~ceb~nd.
S It is another object of the present invention to provide such a scheme for upconversion from b~ceb~nfl to microwave frequencies, for tr~nsmiccion.
It is yet another object of the present invention to provide a scheme for downconverting an analog RF b~ndp~c~ signal, digitally sampling at an IF
frequency, and then ~lrul,lling downconversion to b~ceb~nd.
The inventive scheme, which çlimin~tes the need for analog mixers, splitters, filters, local oscill~tors, and frequency synthesizers used in typical microwave receivers, is particularly well suited for implernent~tion in a customVLSI chip, as an application specific integrated circuit (ASIC). Frequency tuning for ch~nn~l sçl~tion, as well as real-time frequency tracking to C~m~ te for drift or Doppler shifts, are accomplished readily to a resolution on the order of 1 Hz across a 20 MHz RF bandwidth. A natural consequence of the digital downconversion process is that the digital output is complex, providing ~,Ç~clly phase and gain m~tched in-phase and quadrature samples typically required for phase shift keying (PSK) and qu~lr~t'-re amplitude modulation (QAM) demodul~tors.
The method is particularly well suited to low bit-rate FDMA (frequency division multirle access) systems employing PSK or QAM modul~tion where phase noise and frequency offsets are a major concem. The method can be used in many applications where ch~nn~li7~d tr~ncmiccions are employed, including digital cellular telephone, ~tFllitP comm--ni~tions, and digital microwave radioThe elimin~tion of all receiver local oscill~tors (and the frequency synth~ci7~r in particular) removes the most common phase noise sources. Another i~ t aspect of the invention relates to the digital co~ tion for the inherent frequency drift versus te",~ldture of the reference osçill~tor.

wo 94/2737~ PCT/uS94/04812 213974~ --The inventive technique is based on the ability to sample a b~ndp~cc signal at a rate of at least twice the bandwidth rather than the Nyquist criterion of at least twice the maximum signal frequency. In the present situation, bandwidth refers to the total frequency span of the receiver. For microwave receivers, this bandwidth is typically much less than the carrier frequency, permitting practical sampling rates to be used. After digital sampling, one of many narrow-band ch~nn~lc can be selected using a linear-phase, tunable digital b~n~cs filter.
Tuning of the digital filter for channel sele~tiol- is accomplished readily by pre-co,.l~uling the filter coefficients in an external control processor (DSP) and downlo~-ling them to the filter. After filtering, the sample rate can be decimated to a much lower rate, and downconversion and frequency tracking can be accomplished using a digital frequency rotation at the lower sampling rate.
The digital filter is implernentçd in multiple stages, res--ltin~ in an extremely efficient design. The majority of the downconversion with ch~nnçl tuning capability can be readily i~ le.. ~çnl~d in a single CMOS ASIC plus a sep~t~- static RAM memory. The final digital downconversion to b~cPb~nd, inC]~l~ing the frequency tracking m~h~nicm, is implem~nt~ in a programmable DSP. However, the algorithm is efficient enough that it could be implemented in the same DSP that typically would be used to ~lrOllll the digital demodnl~tion filncti~nc.
The same techniques are also directly applicable to a digital upconverter for a microwave tr~ncmittçr. In accordance with the present invention, the digital upconversion is to an IF frequency. The IF signal then is ~rocessed in asubsequent analog upconversion stage to RF.
In accoldance with yet another embodiment of the invention, an analog dowllcollversion stage is used to downconvert an L-band signal to ~F frequçncies, wh~eu~on the above-mentioned ASIC/DSP combination is used to downconvert the IF signal the rest of the way to b~ceb~nd. The filtering scheme in the ASIC
can be simpler than in the first-described inct~n~e because of the analog downconversion stage.

WO 94/27375 ~13 ~ 7 ~ ~ PCT/US94/04812 BRIEF DESCRIPIION OF THE DRAWINGS
The foregoing and other objects, features, and advantages of the invention will be appreciated from the following det~ile~ description, taken in conjunction with the accompanying drawings, in which:
Figure 1 is a block diagram of conventional L-band to b~eb~nd receiver archit~tnre;
Figure 2 is a block diagram of a first embodiment of the present invention;
Figure 3 is a block diagram of a DSP-based demodulator used in 10 accordance with the first embodiment of the invention;
Figures 4(a)-(h) are graphs of spectra of an L-band signal during various stages of downconversion in accor~ance with a first emb~im~nt of the invention;
Figures 5 and 6 show results in accordance with the first embodiment of the invention, using ~rF pling techniques of varying resolutions;
Figure 7 is a block ~ gr~m depicting a digital de~im~tion filter algorithm for downconversion in accordance with the first embodiment of the invention;
Figures 8 and 9 show filter composite response at different resolutions in accordance with the first embo-iiment of the invention;
Figure 10 is a block f~i~gr~m of the hardware employed in the digital de~im~tion filter used in the first embodiment of the invention, collGsl,onding to the algorithm shown in Figure 7;
Figure 11 is a diagram depicting tr~n~mitter arrhite~t~re with an ASIC-based digital upconverter, in accordance with a second embodimçnt of the presentinvention;
Figure 12 is a block diagram of a DSP-based modulator for ~.Ç~ ling upconversion in accGldance with the second embodiment of the invention;
Figures 13(a)-(f) are graphs of spectra of an L-band signal during various stages of upconversion in accordance with the second embo~iimto-nt of the invention;

wo 94/27375 PCT/US94/04812 Figure 14 is a block diagram depicting a digital ~iecim~tinn filter algorithm for upconversion in accordance with the second embodiment of the invention;
Figure 15 is a block diagram of a digital downconverter which converts S L-band signals to a low IF frequency in accordance with a third embo~lim~nt of the invention;
Figure 16 is a diagram of a digital decimation filter algorithm which operates in accordance with the third embodiment of the invention; and Figure 17 is a hardware block diagram of the digital decimation filter used in accordance with the third embodiment of the invention, corresponding to the algorithm shown in Figure 16.

DETAILED DESCRIPIION OF THE PREEERRED EMBODIMENTS
A block diagram of the inventive digital downconverter is shown in Figure 2. A det~iled explanation is provided below. The highly integr~t~
design should be noted. In accordance with this design, all analog components have been elimin~t~d except for the RF input filter 202 and AGC amplifier 204.
Sampling at RF is accomplished using an A/D converter 210 with a resolution of two or three bits. Tunable digital bandpass filter 220 is implement~d in a single custom ASIC, plus a bank of static RAM memory 250. Frequency control is included as part of the DSP-based demodulator 230.
Looking more closely now at the embodiment of the invention as shown in Figure 2, an L-band filter 202 receives an L-band input from an LNA. In the prt~ d embo~iment, the p~ccb~nd of the filter 202 is 1520-1550 MHz, but the invention is not so limit~d. AGC amplifier 204 receives the output of filter 202.
A/D converter 210, which in the ~lefell~d embodiment has a two or three bit resolution, receives the output of amplifier 204. The sampling rate of A/D
converter 210 is 80 MHz in the prefellc;d embodiment.
For an RF center frequency fc~ sample rate f" and two-sided signal bandwidth B, the following criteria must be met for ideal b~ndp~cs sampling:

WO 94/27375 ~ 1 3 9 7 ~ 6 PCT/US94/04812 f9 > 2B [1]

4f f5= ~n+Cl ~2]
where n = any non-negative integer Thus, the sample rate must be at least twice the bandwidth of the input signal, and must be one of several discrete frequencies determined by the parameter n in equation (2). If f, is chosen to meet the two criteria, the aliases of the input spectrum will be equally spaced from one another without overlap. As a result, the signal will be repr~sented perfectly by the digital c~mples. In the plefe.led embodiment an 80 MHz sample rate coll~s~onds to n = 38.
The output of A/D converter 210 is provided to a tunable multi-stage digital b~ndp~cc filter 220, which in the ~ .red embodiment is impleme~t~cl in an ASIC. The filte ing technique will be ~i~c~lcc~d in further detail below.
For now, it is sufficient to note that the filter 220 is a 2500: 1 digital decim~tiQn filter. A DSP-based demodulator 230 provides coeffici~nts used in the filter stages of filter 220. Static RAM banks 250 (2K x 16 x 4) receive table data which are downloaded from DSP 230, and are ~t~cesced by filter 220, two banks at a time, via parallel 16-bit lines, in accordance with ll-bit addresses whose derivation also will be described in further detail below.
The output of filter 220 comprises complex samples, at a sampling frequency of 32 kHz, in accordance with the 2500: 1 decim~tion. The DSP 230 receives these complex samples, and also (as shown in Figure 3) receives tel,l~,dlllre measurement information from reference oscill~tor 240, which in the preferred embo~iment is a medium-stability oscillator with an ~Csoci~t~A
le~lpel~tllre tr~n~ducçr. The oscill~tor 240 provides a sample clock to A/D
converter 210. The sample clock is not adjusted with ~ell~ldtU~e drift; incte~

wo 94/2737s PCT/US94/04812 213974~ ~

the DSP 230 contains a look-up table (Figure 3) which provides compensation values for le.,-pel~ture drift to the filter 220 outputs them~elves.
Looking more closely at Figure 3, reference oscillator 240 is comprised of oscill~tQr section 302 and tel-lpeldture tr~n~ducer 304. Unlike other approaches in which operation of the oscill~tor is controlled as a function of te..-peldture in order to co--l~ensate for lel--peldture drift, in accordance with the present invention te..l~ldture measurement information is provided to DSP 230.
DSP 230 cont~ins a reference frequency error versus te"l~.dtur~ look-up table 310 which provides lelllpeldture error collll,ensation information to a sl-mmingsection 315. Summing section 315 also receives ch~nn~l tuning frequency information and other error information (such as that relating to Doppler shift,shown in Figure 3 as automatic frequency control (AFC) frequency error), and provides a complex summçd output to mixing section 320. Mixing section 320 also receives the complex sampled outputs from ASIC 220. In this manner, the sampled outputs th~m~elves are adjusted for various types of errors, as will be r~icruc~.od below.
The output of mixing section 320 is provided to a 65-tap square-root Nyquist ch~nn~l filter 330, which provides a 4: 1 decim~tion to a 8 kHz sample frequency to a demodulation section 340 which removes the carrier signal, recovers the clock, and the like. Demodulated samples then are sent to a controller (not shown). The demodulation section 340 communir~t~s in a known fashion with a Viterbi d~oder 350. The demod~ tiQn section 340 also provides digital symbol timing (phase) control to ASIC 220, as will be ~ cu~ below.
Figure 3 also shows a block diagram of the frequency tracking scheme within the clemodul~tor DSP 230. For an O-QPSK modlll~ted 60% filtered signal, the one-sided 3 dB signal bandwidth is 2 kHz and the total bandwidth is 3.2 kHz. Frequency tracking must be much more precise than 2 kHz for coherent demod~ tinn. The tr~n~mitted signal can often have a frequency error of 1 kHz or more. In addition, if the demodulator is to be used inside an aircraft in flight, the Doppler frequency shift at L-band can be up to + 2 kHz. In WO 94/2737~ 213 9 7 ~ ~ PCT/US94/04812 addition, a relatively low-cost sample-clock oscillator with an accuracy of 5 parts-per-million can cause a downconversion frequency error of +7.7 kHz.
Consequently, the digital filter must have a total 3 dB one-sided bandwidth of ~11 kHz. The digital filter then can be fixed upon ch~nnel ~ gnmPnt and S real-time frequency tracking is accomplished in the demodulator DSP 230.
Tr~ncmitter and Doppler frequency errors can be obtained from either the demodulator carrier recovery loop or other external means. The reference oscill~tor freqllency error can be obtained easily because the prime source of drift in a crystal osc~ tor such as that used in reference oscill~t~r 302 is from temperature variations. The oscill~t-~r frequency versus telllpeldture behavior can be calibrated by the manufacturer and stored in permanent memory in the demodulator DSP 230, as described above. A tel.lpe.ature tr~nsducer such as tr~nsducer 302 (Figure 3) capable of supplying a digital output byte to the dernodnl~t~r DSP chip is mounted directly on the oscill~tor 302. The DSP 230 can perio~ic~lly (e.g. once per second) read the telll~ldlule value, pelfollll atable look-up, and make the neceS~ry frequency calc~ tion~
The DSP 230 then sums the frequency errors from all sources and makes the final downconversion precisely to b~Pb~n-l using a frequency rotation:
~27tnf, y (n) =x (n) * e f' where x = complex demodulator DSP input y = complex b~Pb~nd output fe = total frequency error f, = sample rate (32 kHz) The downconversion is quite simple because of the relatively slow sample rate. 16 bits of accuracy is more than adequate to meet the required phase noise WO 94/2737!!; r PCT/US94104812 ~1~397~6 ~

spe~ific~tion~. Phase noise is limited only by the reference osc~ t~r characteristics .
While for purposes of illustration the DSP operation has been described in block diagram, it will be appreciated by those of working skill in this field that S much of the operation of the DSP is implem~-nted in software.
For reasons of economy and ~implific~tion of the downconverter design, the tuning range is limited to 20 MHz in the middle of the total 34 MHz Inmarsat-M frequency range (1530-1550 MHz).
Solely for purposes of illustration, an L-band mobile ~ttollite receiver for the Inmarsat-M system has been chosen as a ~ iesçllt~tive design case.
However, it should be noted that the inventive design also is applicable to other L-band systems with little or no ~no~ific~tion. The Inmarsat-M spe~ific~tions are given in Table 1 below. Tables 2A and 2B show the limit spe~ifi~tionc for phase noise for reception and tr~nsmi~ion for operation in the Tnm~r.c~t-M
system.
Table 1 - Inmarcat-M Mobile Receiver Spe.~ e~tionc Operating F.~~ s 1525-1559 MHz Channel F-~u~ Spacing S kHz Acces~s Method SCPC FDMA
MoA~ tirm O-QPSK
T~ or~ Rate 8 kbit/s Symbol Rate 4 kbit/s Transmit, Receive Filters 60% Square-root raised cosine M~imllm ~ u~u~ UIK~ Y i966 Hz at L-Band Mobile Receiver Input C/No 4R0 dB-Hz ~ imllm Roceived Phase Noise See Table 2A
at L-Band M~imllm T,~ d Phase See Table 2B
Noise at L-Band , ~

Table 2A - Limit Mask for Inmarsat-M Received Phase Noise at ~band Offse~ from Actual SSB Phase Noise Tr~ncmit~ Carrier Limit (in 1 Hz F~ u_.lcy Bandwidth) 10 Hz -33.5 dBc 100 Hz -60.5 dBc 1,000 Hz -74.5 dBc 10,000 Hz -79.0 dBc Table 2B - Limit Mask for Inmarsat-M Received Phase Noise at L,band Offset from Actual SSB Phase Noise T..~ r~ Carrier Limit (in I Hz Fl~u_.~cy Bandwidth) 10 Hz -42.0 dBc 100 Hz -65.0 dBc 1,000 Hz -73.0 dBc 10,000 Hz -90.0 dBc In Tables 2A and 2B, SSB stands for single sideb~nd An i~ olL~nt aspect of the invention is the sampling technique used, including sampling rate, RF input frequency, and the resolution of the digital q~nti7er. The b~ndp~cs sampling technique is best understood by referring to Figure 4, which shows the spectra at each step of the downconversion ~locess shown in Figures 2 and 3.
Figure 4(a) shows the analog frequency spectrum after the RF input b~n~ip~cc filter 202. The p~c~b~d is from 1530-1550 MHz; Figure 4(a) shows both positive and negative frequency components. The shaded areas in the figure ~c~l~;sent the rolloff of the RF filter 202. After the bandpass signal is sampled with A/D converter 210, an aliased spectrum is observed, as shown in Figure 4(b) for an ideal sample-and-hold process.
After sampling, the digital signal is filtered with a digital b~ndp~cc filter 220 which is tuned to the desired channel frequency. The digital filter rejects all wo 94/27375 PCT/US94/04~'.12 213974~

negative frequenci~s; as a result, the filter coefficients are complex. Figure 4(c) shows a ch~nnel frequency of 1547 MHz. However, the digital filter actually has a center frequency of 27 MHz, an alias of 1547 MHz. Once the signal band-width has been reduced by the digital filter, the sample rate can be decimated to a lower rate. Figure 4(d) shows 50:1 decim~tion to f, = 1.6 MHz, co,le~.ponding to a first stage of the filter 220. The spectrum now repeats every 1.6 MHz and, although each alias subst~nti~lly overlaps its adjacent aliases dueto the broad digital filter rolloff, there is no spectral overlap into the desired c'~nnel. The alias of the desired channel closest to baseband is at -0.2 MHz.
Once the sampling rate has been reduced, an extremely sharp multi-stage digital filter can be implemented efficiently to perform the final ch~nnel selection, as shown in Figure 4(e), corresponding to the fourth stage of filter 220. Next, the sample rate is decimated to 32 kHz and the desired ch~nnel has an alias at -8.0 kHz, as seen in Figure 4(f), cGlle~ponding to an output stage of filter 220. Finally, the digital s~mples are multiplied by a complex exponentialwith frequency 8 kHz in the DSP chip, as shown in Figure 4(g). The r~sul~in~
b~ceb~nd I and Q ch~nnPl c~mples are filtered with a m~tl hed filter, as shown in Figure 4(h), and are then ready for demod~ tion.
Downconverter performance is highly dependent on the specific~tions of the A/D converter 210 that is chosen. Although the sampling rate is not prohibit-ively high, the A/D input circuitry must be capable of h~n~ling the highest RF
signal frequency (1550 MHz in the specific case being ~iccussed in connection with the ~-efc,red embodiment, though the invention is not so limited).
However, the resolution required is very low. Consequently, it is contemplated presently that a 3-bit A/D converter should give extremely good ~lro""ance.
Ideally, the A/D converter should have a b~ndpacs input amplifier with a 1540 MHz center frequency.
When sampling a 1550 MHz carrier frequency, the timing uncertainty (aperture jitter) of the sampler must be small enough that the amplitude error is WO 94/27375 ~13 ~ ~ ~ G PCT/US94/04812 less than one half of a least significant bit (LSB). This error is given by the following equation:

2 -m /~ t = [ 3 ]
~ fmax where m = the number of bits of resolution S f",.,, = the maximum signal frequency For m = 3 bits and f,,,x = 1550 MHz, ~t = 25 ps. This jitter specific~tion is readily achievable with current technology, in a known fashion.In terms of overall signal-to-noise (S/N) ratio, a l-bit A/D converter should be sufficient, because of the high sampling rate. An S/N ratio of greaterthan 30 dB is sufficient for O-QPSK demodulators. The digital filtering removes a substantial portion of the wide-band qu~nti7~tion noise, and in general S/N
improves by 3 dB for every octave increase in the oversampling ratio. For a 4 kHz symbol rate sampled at 80 MHz, S/N is improved by 43 dB (approximate-ly six bits of resolution). However, two to three bits of resolution are recommende~d to minimi7e discrete intermodulation distortion products within thedigital filter p~c~b~nd.
A spectral plot of three equal-amplitude sinusoidal tones at 1233.999 MHz, 1234.0003 MHz, and 1234.0012 MHz sampled by an ideal 2-bit A/D
converter and digitally filtered (with a filter that is described below) is shown in Figure 5. The results shown are taken from a computer simulation. However, finite integer filter coefficient qu~nti7~tion and arithmetic computations are include~. It should be noted that the three tones have aliased to 15.0, 16.3, and 17.2 kHz as a result of the sample rate decimation to 32 kHz. There are several distortion products between 25-30 dB down. Figure 6 shows a spectral plot of the same three tones sampled by an ideal 3-bit A/D converter and digitally WO 9~/27375 PCT/Us94/04812 2~ 397~6 filtered (again, with the filter to be described below). All distortion products are greater than 35 dB down.
The dynamic pe.rollllance of a 1-bit A/D converter may be improved using a b~nclp~cs sigma-delta modulator in a known fashion as described, for S example, in S. Jantzi et al., "R~ndp~cc Sigma-Delta Analog-to-DigitalConversion", IEEE Transactions on Circuits and Systems, Vol. 38, No. 11, November 1991.
Frequency ch~nnPl selection within the 20 MHz tuning range and sample rate decim~tion is accomplished with a digital bandpass filter shown in Figure 2.
The filter also decim~t~s the sample rate by 2500:1 down to 32 kHz. The filter is implem~ted as a c~cc~e of four linear-phase, bandpass decimation finite impulse response (FIR) filter stages for optimal efficiency, as shown in Figure 7. The b~ndp~cs filter coefficientc are all derived from equivalent lowpass filter designs of comb, half-band, and equi-ripple filters. Specifications of each filter stage are given in Table 3 for the equivalent lowpass deci~nc Table 3 - Four-Stage Digital Downconverter Filter Specif~lc~ c St ge/ Numbcr Input/OutputDecim. Passband Stopband Max. Min.
Filtcr of Taps Sample Ratc Ratio CutoffComcr Passband Stopband Typc Freq.~req.RipplcAttcn.
1 99, 80 MHz/ 50 Comb Complex 1.6 MHz 2 13, 1.6 MHzl S:l Comb Complcx 320 kHz 3 15, 320 IcHz/ 2:1 8 kHz88 kHz i-012 d8 81 dB
25Half- Complcx 160 kHz Band 4 34, 160 kHz/ 5:1 8 IcHz24 kHzi-02S dB70 dB
Equi- Complcx 32 ~:Hz npplc 30Total 2500:1 7.2 kHz St~g 5 2 i 3 9 7 4 G PCT~US94/04812 Stage 1 is a 99-tap comb filter with a decimation ratio of 50:1 and frequency response of [ sin (x) ] . The lowpass equivalent filter coefficients can be derived by convolving a sequence of 50 ones with itself to give a ramp function:
hl(n) = n/2500 n=l, 2, ..., 50 hl(n) = (100-n)/2500 n =5 1 , 52, . . ., 99 Stage 2 is a 13-tap comb filter with a decimation ratio of 5:1 and frequency response of [ sin (x) ] . The lowpass equivalent filter coefficientc can be derived by convolving three sequence of 5 ones with itself (see Table 4).Stages 3 and 4 can be decigned using the Parks-McClellan equiripple design 10 algorithm available in several commercial filter software design packages.
Half-band filters are discussed in detail in texts such as Crochiere and Rabiner, Multirate Digital Signal Processing, Chapter 5 (Prentice-Hall, 1983).

Table 4 - Stage 2 Lowpass Filter Coefficients n S~ge 2 n S~ge 2 h2(n) h2(n) 1 .008 8 .144 2 .024 9 .120 3 .048 10 .080 4 .080 11 .048 .120 12 .024 6 .144 13 .008 ~ .152 Table 5 shows the specific~tions of the composite 4-stage c~ d~d filter design. The composite frequency response is shown in Figures 8 and 9 for a 21`397~6 ~

channel frequency of 1221.234 MHz (the filter being tuned to 21.234 MHz - an 80 MHz alias of the channel frequency). The filter is flat within +.014 dB for frequencies within +7.2 kHz of the ch~nnel frequency. The filter is greater than70 dB down for frequencies farther than i450 kHz from the ch~nn~l frequency.
S Spe~ifi~tions include degradations of the finite arithmçtic word sizes of the digital hardware described below.

Table S - Composite ~Stage Lowpass Filter Specif;~t~ c NumberofTapsInput/Output D~u~1tiu~Passband Response Stopband Sample Ra~e Ratiû Response 21,478 equiv.80 MHz/3~kHz 2500:1 0-7.2 kHz ~.014 dB 24-450 kHz-60dB
10taps ~ 80 MHz 8.0 kHz -.08 dB >450 kHz -70 dB
12.9kHz 03 dB

The lowpass filter coeffiçientc of each stage are stored in the control processor; in the preferred embodiment, this would be the DSP demod~ tor.
The lowpass filters can be readily converted to b~ndp~cc designs using the following simple frequency translation formula:
~21~nfc hb (n) = hl (n) * e f' where hb = tr~n~l~ted bandpass filter coefficient h, = lowpass filter coefficient fc = ch~nnel frequency f, = sample rate The b~ndp~cc filter coefficients become complex and non-symmetric about the center tap as a result of the multiplication by the complex expon~onti~ Iowever,the transformation is quite simple, and controlling DSP 230 can use the same WO 94/27375 21319 7 ~ 6 PCT/US94/04~12 sine and cosine tables required for the frequency tr~ncl~ti~ n to baseband described previously. The filter coefficients only need to be computed and downloaded to the filter ASIC 220 once upon ch~nnel ~Csignment A block diagram of the major hardware functions to implement the - 5 4-stage filter is shown in Figure 10. The entire filter can be implemented in a single CMOS ASIC (either array or cell based) plus 2K x 64 bits of RAM 250 (Figure 2). Stage 1, a 50: 1 decim~ion filter 1010, is implemPnted using a tablelook-up approach because of the high spe~ed involved. Two 3-bit inputs are latched in latches 1012, 1014, 1016, and 1018 so that two filter taps can be looked up simultaneously. Logic circuitry, comprising a clock logic and state sequencer 1020, details of which are not eccPnti~l to an understanding of the invention, identifies which of 25 tap pairs within the first 50 taps is being ~rcesse~. In this manner, two l l-bit addresses are supplied to respeclive pairsof banks of the look-up RAM 250 (Figure 2).
The look-up RAM 250 is divided into 4 banks of 2K x 16-bit words each.
Banks 1 and 2 are used for looking up the re~ecli~e real and im~in~ry results for the first 50 taps. Banks 3 and 4 are used for looking up the respective realand im~in~ry results for the second 49 taps. All banks are ~- cecc~d in parallel, requiring a 64-bit memory bus with a 40 MHz bus speed. The two 3-bit latched data inputs are delayed by 50 taps using a 25 x 6-bit register file 1022. The RAM contents are loaded from an external control processor so that the filter can be readily tuned to any desired frequency.
The look-up results are output from each bank as 16-bit values. Pairs of values from respective pairs of RAM banks are added in 16-bit adders 1030, 1032. Outputs of adders 1030, 1032 are accllmlll~te~ in rejpecLi~re 20-bit accumulators 1040, 1042, which are cleared every 50 A/D clock cycles to yield a 50: 1 decimation ratio. The results, which are complex, are rounded to 16 bitsin respective scaler/rounder/limiters 1050, 1052 before being passed to stage 2.Stages 2, 3, and 4 are implemented with a pair of 16 x 16-bit multiplier açcum~ tors 1068, 1070, a bank of coefficient RAM 1066, and a bank of data wo 94l2737s PCT/US94/04812 2~397~6 RAM 1064, as shown. The multiplier accumulators are each clocked at a rate of 20 MHz and are time-shared between all three stages using control logic 1000.As shown in Figure 10, the output of stage 1 is provided to 144 x 16 data RAM
1064. 144 x 16 coefficient RAM 1066 receives coefficient information which is S downloaded from DSP 230 via bus 1055. RAM 1064 and 1066 also receive output of 6 x 6 bit address pointer/counters 1062, and provide respective outputs to the multiplier/accllmul~tors 1068, 1070. Shifter/limiter/rounders 1072, 1074 round the results from respective multiplier/accumul~tQrs 1068, 1070 in a known fashion, details of which are not e~enti~l to an understanding of the invention.As a result of the foregoing, the output of the fourth stage provides 16-bit in-phase and quadrature values to multiplexer 1080 at a sample rate of 32 kHz, which includes a serial output interface to DSP 230.
The ASIC 220 opcl~tes with a 40 MHz clock input, and has dedic~ed serial busses for coefficient input and data output, as described above. The serial busses can be readily interfaced to standard DSP processor chips.
One advantage of the digital downconversion process of the present inven-tion is that symbol timing correction, under control of the DSP dernoclul~tor's timing recovery loop, can be pclro~.,-ed digitally in the ASIC with virtually noadded complexity. In conventional digital demodulators, the A/D sample clock is steered by a timing correction circuit which is driven by the demodulator's timing recovery loop. The circuit shifts the sample timing phase so that sampling occurs at the maximum opening of the receiver eye pattern (i.e. sampling in the middle of a digital symbol) to minimi7e intersymbol interrclence. However, in the inventive digital downconverter, the A/D sample clock is free-running. The 2S output of the stage 1 ~lecim~tinn filter is at a sample rate of 1.6 MHz, which collc~ponds to 400 samples per symbol. Symbol timing phase can be adjusted quite easily merely by shifting the samples in time as they come into the secondstage FIR filter delay line. A shift of one sample corresponds to a shift in timing phase of 1/400 symbol, for a maximum timing adjustment error of +0.45. The WO 94/27375 ~ 13~ 7 4 ~ PCT/US94/04812 , .

resolution is sufficient that timing phase errors will cause negligible loss in bit error rate (BER) p~lro,."ance.
The DSP 230's timing recovery loop provides a control signal (Figure 3) which causes samples in the second stage FIR filter delay line data RAM 1064 5 to be either skipped or repe~ted as ne~e~c~ry until the proper timing phase isachieved. The timing control signal from the DSP 230 is fed to the control circuitry 1000 in the ASIC 220, as shown in Figure 10. The control circuitry 1000 then determines whether to perform a filterin~ operation on the same input data (i.e. reuse the current input sample) or wait for two input samples to be shifted into RAM before filtering (i.e. skip an input sample).
As described in detail in the foregoing, in addition to its compact size, the inventive downconverter has the following advantages:
i) Extremely good phase noise performance. Since there are no local oscillators, mixers, or PLL circuits, the downconverter phase noise output should track accurately the phase noise of the frequency reference oscill~tor which provides the sample clock.
ii) Wk~eb~nd digital filtering allows precise, flexible control of filter response. For eY~mple, filter coefflci~ntc can be derived (or trained using adaptive filtering techniques) to notch out known sources of intelr~ ce.
iii) The scheme includçs digital frequency compensation of reference frequency oscill~tor drift versus te-,-~ldture. No oven is required. This saves approximately 1-2 watts of power required for the oven, and also provides for nearly inct~nt~neous warm-up time, in contrast to the 30 minutes it takes for an oven to stabilize.
iv) Both wide tuning bandwidth and fine ~app-uximately 1 Hz) frequency resolution are obtained with no co~ uro-,-ise in other ~lrul"~ance specific~tions (espe~i~lly phase noise).
v) Digital filter is finite impulse response (FIR), linear phase. No group delay equ~li7~tit~n is neces~ry.

7~; PCT/US94/04812 vi) I and Q baseband samples have perfect phase and gain m~t~hing.
vii) Symbol timing phase adjustments are accomplished very easily without the need for any external hardware.
Although the invention has been di~cu~ed in detail thus far with reference S to an Inmarsat-M downconverter, the inventive technique also is applicable to digital upconversion. In fact, phase noise specifications typically are more stringent in the tr~ncmittp~r than in the receiver for TDMA ~tPllit~P transceivers.
Thus, the low phase noise of the digital frequency tuning technique of the present invention becomes even more advantageous in such applications.
A digital upconverter can be desi~nP~d using a scheme very similar to that for the receiver, except for reversal of the digital proce~ing steps. The tr~n~mitter also uses a digital ASIC in conjunction with a tr~n~mit DSP to upconvert the signal from b~eb~nd. However, for simplicity, digital tuning is accomplished within a 1 MHz range, and the digital upconversion is to an intermeAi~t~ frequency of 10 MHz. One or more analog IF stages are used to upconvert the signal to microwave frequencies (1640 MHz, for eY~mple).
An e~rempl~ry block rli~r~m of the inventive upconverter is shown in Figure 11. A DSP 1100 receives digital data at b~ceb~nd from a controller (not shown). The DSP also receives le..-peldtul~ measurement information from an crystal oscill~tor 1110 which includes an integral te~ el~ture tr~nsducer. The DSP 1100 downloads coefficient information to an ASIC 1120, which comprises a tunable digital four-stage interpolation filter providing 250:1 interpolation,shown schPm~ti~ y in Figure 14. The DSP 1100 also provides m~~ t~d samples at a sampling rate of 32 kHz to ASIC 1120.
The output of ASIC 1120, conctitut~ by ~mples at a sampling frequency of 16 MHz, is provided to a 10-bit D/A converter 1130, which provides an analog output to an analog bandpass filter 1140, whose output in turn is provided to an analog upconverter 1160, of known con~titlltion, for final conversion to L-band.

wo 94/2737~ 213 9 7 ~ 6 PCT/USg4/04812 As shown, a syntheci7er IC 1150 may be used to extend the tuning range of the upconverter by stepping the analog local oscillator 1110 in 1 MHz steps, and providing an LO output to analog upconverter 1160. However, phase noise ~lrol,-,ance is excellent because of the very large step size and simplicity of the - S analog syntheci7er. With this scheme, digital channel tuni~g to a resolution of 1 Hz with real-time frequency tracking is accomplished readily.
Referring now to Figures 12-13, Figure 12 is a block diagram of the DSP-based modulator 1100, and Figures 13(a)-(f) show the spectrum at each stage. First, baseband I and Q ch~nnel ~mples are filtered by a real 64-tap square-root Nyquist ch~nn~l filter 1240 at a rate of 8 samples per symbol, as shown in Figure 12. The filter is implemented as an interpolation filter, where the filter coefficients are divided into eight blocks of eight each. The filter outputs are obtained by first convolving eight data symbols by the first block of coefficientc, then the second block, and so on, until the eighth output is obtained with a convolution by the eighth coefficient block. The delay line is shifted, and the process is repe~tPd. The res-llting b~ceb~nd spectrum is shown in Figure 13(a). The filtered signal has a two-sided bandwidth of 6.4 kHz (for a 60%
rolloff filter), with aliases every 32 kHz.
The filtered signal then is frequency-tr~ncl~t~d in the DSP 1100 to the correct ch~nnel frequency, including AFC and osçill~tor temperature col"pen-sation. Temperature collll)ensation information is derived from look-up table 1210, bdsed on tel-~pe.dture mea~u-. .--cnt information from ~--peldture tr~ncducer 1204. The various co-upensation information is summed in s~lmming section 1220, and is mixed with an output of filter 1240 in mixing section 1250,as shown in Figure 13(b). The tr~ncl~tion is identic~l to the one ~lrolllled in the receiver using sine and cosine look-up tables, as described earlier. The sampling rate is 32 kHz. As in the previous embodiment, while for purposes of ~ lstr~tion the DSP operation has been described in block diagram, it will be appreciated by those of working skill in this field that much of the operation of the DSP is implemented in software.

wo g~/27375 213 9 7~ ~ PCT/US94/04812 Next, the signal is filtered by a 250:1 interpolating bandpass filter in the ASIC 1120, as shown in Figure 13(c). The filter increases the output sampling rate to 8 MHz, thus removing all alias components except those that occur at 8 MHz intervals. The filter also selects the correct alias component to tune to the proper frequency within the 1 MHz tuning range. This filter is very similar to the receive ~ecim~tinn filter, except that the ordering of each stage is reversed, as shown in Figure 14. In fact, stages 1, 2, and 3 have the same coefficients asstages 4, 3, and 2, respectively, in the receiver, as will be appreciated by co~l,pa~ing Figure 14 with Figure 7. Stage 4 is a 9-tap comb filter with a de~im~tiQn ratio of 5:1 and a frequency response of [ sin(x) ] . The lowpass coefficients are 0.2 * (1,2,3,4,5,4,3,2,1). The bandpass filter coefficiçntc are derived from the lowpass coefficients, as discussed above.
The b~n~p~cc filter coefficiçntc are downloaded to the ASIC 1120 from the modulator DSP 1100 upon ch~nnel re~ccignrnçnt Both the input data and the filter coefficientc are complex. The lowpass filter 3dB cut-off frequency is 11 kHz (22 kHz two-sided bandwidth) - wide enough to permit real-time APC
tuning without ch~ngin~ the filter characteristics.
The ASIC 1120 performs complex digital filtering in the first three stages.
However, only the real component is computed in the last stage, since the ASIC
1120 only drives a single D/A converter 1130, and the analog IF upconversion is real. Therefore, the resulting spectrum is symm~tric about 0 Hz, and mirror-image spectral co,l,yonents at -10, -2, and 6 MHz appear, as shown in Figure 13(d). It should be noted that, since the sampling rate has been chosen properly, all the ~ cing co"lponents are nearly equally spaced, and there is a co",ponent at the desired IF frequency of approximately 10 MHz (10 MHz plus the ch~nnel tuning frequency). Stage 4 of the digital filter computes results rounded to 10 bits of accuracy - enough to drive a suitable D/A converter.
There is one minor complication in the D/A conversion process which the present invention addresses, as now will be discussed. Typically, D/A convertersoperate with a track-and-hold function which holds each converted sample until wo 94/27375 213 9 7 ~ 6 PCT/USg4/04812 the next sample time, 1/f,. This causes the analog output spectrum to roll off as sin(~rf/f,)/(~f/f,) - a function of the frequency, f. At the desired IF frequency of f = 10 MHz and f, = 8 MHz, this collesponds to a loss of 15 d~ compared to the m~gnitude of the baseband spectrum. Thus, the signal-to-noise ratio at the S D/A converter would be degr~ and the higher-level low-frequency aliases must be removed with a higher order analog bandpass filter.
The solution is to increase the sampling rate going to the D/A converter.
This is accomplished easily with a digital multiplexer before the D/A converter.As shown in Figure 11, the D/A converter is clocked at a rate of 16 MHz. As shown in Figure 14, a multiplexer in the ASIC 1120 alternates between the filteroutput and the digital codeword corresponding to zero analog volts, and the output is sent to the D/A converter 1130. The zero-p~ 1ing operation does not alter the locations of each alias component, but it does shorten the D/A a~~ re sample time by a factor of two. The effect is to broaden the sin(~rf/fJ)/(~f/f,)rolloff of the analog spectrum, as shown in Figure 13(e). The spectrum attenua-tion is in the range of 5.8 to 7.4 dB across the full 1 MHz ch~nnçl tuning range.
Ch~nne] to ch~nn~ol gain variations can easily be comFen~ted by scaling the stage 4 filter coefficients by the approp,iate factor in the DSP 1100 before downlo~-lin~ them to the ASIC 1120. A look-up table can be stored in the DSP
1100 for this purpose.
Finally, the D/A converter output is filtered with a 10 MHz analog band-pass filter 1140 (the bandwidth being apl)luximately 1 MHz), and the signal is upconverted in analog upconverter 1160, as ~i~cu~sed previously. The above schçme results in extremely good phase noise char~cterictics because of the minimum of 84 dB stopband ~ttçnn~tion in the ASIC digital filter. Spurious res-ponse is primarily a function of the D/A converter; 10-12 bits are recommçndecl.Such parts, having a 16 MHz speed, are readily available from several m~nllf~-.tllrers.
Many variations of the invention also are possible. Figure 15 shows a receiver scheme with an analog downconversion to a lO MHz IF, followed by wo 94/2737s PCT/US94/04812 213g746 ~

the digital downconverter. An RF input signal from an LNA (not shown) is input to a b~n~p~cs filter 1510 which in this preferred embodiment has a center frequency of 1542 MHz and a bandwidth of 34 MHz. The output of filter 1510 is provided to analog downconverter 1520, which converts the filter output from L-band to an IF frequency of 10 MHz in known fashion. Analog downconverter 1520 is controlled in accordance with tuning provided by synthesizer IC 1530 whose output preferably is tuned in 1 MHz steps. Synthesizer IC 1530 obtains its frequency reference from crystal oscillator 1580.
The output of analog downconverter 1520 is provided to an IF b~n~p~s filter 1540 which in the described embo-lim~nt has a center frequency of 10 MHz and a bandwidth of 1 MHz. The output of filter 1540 is A/D converted in a six-bit A/D converter 1550; a higher resolution A/D converter than in the Figure 2 embodiment is neCcss~ry because of the lower sampling rate employed. The output of A/D converter 1550 is at a sampling frequency of 8 MHz.
The digital downconverter, comrri~ing ASIC 1560 and DSP 1570, ~ lS the rem~indPr of the tuning steps to 1 Hz resolution. Design of a low phase noise synthP~i7Pd analog local oscillator is relatively straightforward because of the large frequency step size.
The digital downconverter is virtually identi~l to that described previously with reference to Figure 2. For optimum b~n~r~ sampling, a sample rate of 8 MHz is chosen for the 10 MHz IF b~ndp~c center frequency.
The IF signal is sampled with 6-bit A/D converter 1550, as was mPntion~
above. The ASIC 1560 contains a four-stage tunable digital bandpass filter with a sample rate decimation ratio of 250: 1. The filter may be tuned to any ch~nn within the 1 MHz IF bandwidth.
Figure 16 shows a block diagram of the digital decim~fic)n filter, which is similar to that shown in Figure 7. In fact, stages 2, 3, and 4 in the Figure 16 filter are identir~l to those in Figure 7, but stage 1 now derim~tes by 5: 1 instead of 50:1, as in Figure 7. The filter is implemPnted as a conventional sum of products FIR filter using a multiplier accumulator. Coeffi~i~nts are complex, but WO 94/27375 213 9 7 4 ~ PcTlus94lo48lz input data from the A/D converter is real. The filter is a 9-t~p comb filter with a frequency response of L sinx(X) ] The lowpass coefficients are 0.2 *
(1,2,3,4,5,4,3,2,1).
The design of the ASIC 1560 is very similar to that of Figure 10, except that the stage 1 filter uses two 16 x 6 bit multiplier accumulators, as seen in Figure 17, instead of the external SRAM, adders, and accumulators of the Figure 10 stage 1 filter. Looking at Figure 17 in more detail, the 6-bit data input from the A/D converter is provided to the two l6 x 6 bit multiplier accumulators 1702, 1704. Data from respective coefficient RAMs 1712, 1714 are provided to these multiplier accumulators 1702, 1704, based on coefficients downloaded from DSP 1570. The outputs of accumulators 1702, 1704 are provided to respective shifter/limiter/rounders 1722, 1724, the outputs of which are provided to stage 2 of the filter. The constitution of filter stages 2-4 in Figure 17 is i-le~tir~l to that of Figure 10, and so need not be described in further detail here.
As in the Figure 10 embo~iment, the output of filter stage 4 comprises in-phase and qua~lr~tllre cGIl~ponents, which are provided via a multiplexer in serial fashion to the DSP 1570.
Operation of the DSP 1570 in the Figure 15 embodiment is identi~l to that of the DSP of Figure 3, except for what is downlo~-1e~ for the operation ofthe stage 1 filter. The DSP 1570 downloads filter coefficients to the ASIC 1560,Ol IIIS frequency correction based upon reference oscillator te",~.~ture measurement~, and performs precise frequency tuning with 1 Hz resolution.
Ideally, for a very compact hardware design capable of both reception and tr~ncmi~sion in accordance with the present invention, the ASIC preferably in~ des circuitry for both transmit and receive functions, and a single DSP
performs both modul~tion and demodul~tion. The tr~n~mitter DSP also includes ch~nnel tuning, automatic frequency control, and reference osc~ tor tel"~ldture col"pen~tion, While the invention has been described in detail with reference to a ~ fellt;d embodimPnt, various changes and mo-lific~tions within the scope and wo 94/27375 PcT/uss4/04812 ~1`3~74 ~ --spirit of the invention will be apparent to those of working skill in this technological field. Thus, the invention is to be considered as limited only by the scope of the appended claims.

Claims (19)

What is claimed is:

1. Apparatus for performing digital frequency conversion and real-time frequency tracking, comprising:
a bandpass filter for bandpass filtering an input signal at a predetermined bandwidth to provide a bandpass filtered signal;
an analog-to-digital (A/D) converter for sampling said bandpass filtered signal at a sampling rate related to a center frequency of said bandpass filtered signal to provide a digital sampled signal;
an uncompensated frequency reference oscillator having an integral temperature transducer;
a tunable multi-stage digital decimation filter for downconverting said digital sampled signal; and a digital signal processor (DSP), receiving temperature measurement values from said temperature transducer, and receiving channel tuning information from the tunable multi-stage digital decimation filter, for providing temperature-compensated tuning of said digital sampled signal from a desired channel frequency to baseband at a 1 Hz resolution, wherein phase noise as measured in a 1 Hz bandwidth is at least 33.5 dB down for a 10 Hz offset from baseband, and at least 60.5 dB down for a 100 Hz offset from baseband.

2. Apparatus as claimed in claim 1, wherein said tunable multi-stage digital decimation filter comprises an application specific integrated circuit (ASIC), said apparatus further comprising a random access memory (RAM) which is loaded with filter values from said DSP, and wherein a first stage of said filter is tuned in accordance with said filter values.

3. Apparatus as claimed in claim 1, wherein said tunable multi-stage digital decimation filter comprises an application specific integrated circuit (ASIC), said DSP providing coefficient values to second through fourth stages of said filter, wherein said second through fourth stages are tuned in accordance with said coefficient values.

4. Apparatus as claimed in claim 1, wherein a first stage of said tunable multi-stage decimation filter is a complex finite impulse response (FIR) filter comprising a look-up random access memory (RAM).

5. Apparatus as claimed in claim 4, wherein said RAM comprises a plurality of banks, said RAM being loaded with values from said DSP in accordance with said desired channel frequency, and wherein said first stage of said filter comprises:
a plurality of latches for simultaneously looking up values in more than one of said banks;
a first adder for adding a first pair of said values from a first pair of said banks;
a second adder for adding a second pair of said values from a second pair of said banks;
a first accumulator for accumulating outputs of said first adder; and a second accumulator for accumulating outputs of said second adder.

6. Apparatus as claimed in claim 5, wherein an output of said first accumulator is an in-phase value, and an output of said second accumulator is a quadrature value, said fourth stage of said filter providing further filtered in-phase and quadrature values to said DSP.

7. Apparatus as claimed in claim 1, wherein said tunable multi-stage digital decimation filter comprises an application specific integrated circuit (ASIC), said ASIC receiving digital symbol timing phase control signals from said DSP.

8. Apparatus as claimed in claim 1, wherein said A/D converter comprises a two-bit A/D converter, said sampling being performed at microwave frequencies.

9. Apparatus as claimed in claim 1, wherein said A/D converter comprises a three-bit A/D converter, said sampling being performed at microwave frequencies.

10. Apparatus as claimed in claim 1, wherein said A/D converter performs said sampling in accordance with the following:

fs > 2B

fs = where B is a two-sided signal bandwidth;
fs is said sampling rate;
fe is said center frequency; and n is a non-negative integer.

11. Apparatus for performing digital frequency conversion and real-time frequency tracking, comprising:
a RF bandpass filter for bandpass filtering an input signal at a first predetermined bandwidth to provide an RF bandpass filtered signal;
an analog downconverter for downconverting said RF bandpass filtered signal to an IF signal;
an IF bandpass filter for bandpass filtering said IF signal at a second predetermined bandwidth to provide an IF bandpass filtered signal;

an analog-to-digital (A/D) converter for sampling said IF bandpass filtered signal at a sampling rate related to a center frequency of said IF bandpass filtered signal to provide a digital sampled signal;
an uncompensated frequency reference oscillator having an integral temperature transducer;
a tunable multi-stage digital decimation filter for downconverting said digital sampled signal; and a digital signal processor (DSP), receiving temperature measurement values from said temperature transducer, and receiving channel tuning information from the tunable multi-stage digital decimation filter, for providing temperature-compensated tuning of said digital sampled signal from a desired channel frequency to baseband at a 1 Hz resolution, wherein phase noise as measured in a 1 Hz bandwidth is at least 33.5 dB down for a 10 Hz offset from baseband, and at least 60.5 dB down for a 100 Hz offset from baseband.

12. Apparatus as claimed in claim 11, wherein said A/D converter comprises a six-bit A/D converter.

13. Apparatus as claimed in claim 11, wherein said tunable multi-stage digital decimation filter comprises an application specific integrated circuit (ASIC), said DSP providing coefficient values to first through fourth stages of said filter, wherein said first through fourth stages are tuned in accordance with said coefficient values.

14. Apparatus as claimed in claim 11, wherein said tunable multi-stage digital decimation filter comprises an application specific integrated circuit (ASIC), said ASIC receiving digital symbol timing phase control signals from said DSP.

15. Apparatus for performing digital frequency conversion and real-time frequency tracking, comprising:

an uncompensated frequency reference oscillator having an integral temperature transducer;
a digital signal processor (DSP), receiving temperature measurement values from said temperature transducer, channel tuning information, and a baseband modulated digital signal having in-phase and quadrature components, for providing temperature-compensated tuning of said baseband modulated digital signal from baseband to a desired intermediate frequency to provide a first digital intermediate frequency signal, having in-phase and quadrature components, at a 1 Hz resolution, wherein phase noise as measured in a 1 Hz bandwidth is at least42 dB down for a 10 Hz offset from baseband, and at least 65 dB down for a 100 Hz offset from baseband;
a tunable multi-stage digital interpolation filter for upconverting said first digital intermediate frequency signal to provide a second digital intermediate frequency signal;
a digital-to-analog (D/A) converter for receiving said second digital intermediate frequency signal and outputting an analog intermediate frequency signal;
an analog bandpass filter for bandpass filtering said analog intermediate frequency signal to provide a bandpass filtered signal; and an analog upconverter, receiving said bandpass filtered signal and a local oscillator signal related to an output of said uncompensated reference oscillator, for upconverting said bandpass filtered signal to provide an RF signal.

16. Apparatus as claimed in claim 15, further comprising a synthesizer, tunable in 1 MHz frequency, and receiving said output of said uncompensated reference oscillator, for providing said local oscillator to said analog upconverter.

17. Apparatus as claimed in claim 15, wherein said D/A converter is a 10-bit D/A converter.

18. Apparatus as claimed in claim 15, wherein said tunable multi-stage digital interpolation filter comprises an application specific integrated circuit (ASIC), said DSP providing coefficient values to first through fourth stages of said filter, wherein said first through fourth stages are tuned in accordance with said coefficient values.

19. Apparatus as claimed in claim 18, further comprising a multiplexer receiving an output of said fourth stage of said filter, and zero padding information, said multiplexer outputting said second digital intermediate frequency signal.