CA2153383A1 - Method and apparatus for rendering images - Google Patents

Abstract

A rendering device for converting input information into a bit map including a Bezier subdivision processor responsive to Bezier curve information describing a Bezier curve of an image. The Bezier subdivision processor performs at least one subdivision on the Bezier curve if the Bezier curve is greater than a desired resolution of a bit map to produce subdivided Bezier curves until all subdivided Bezier curves are at about the resolution of the bit map. The Bezier subdivision processor produces cross information from each Bezier curve which makes one crossing of a grid having the resolution of the bit map. The rendering device also includes a digital processor responsive to the cross information and operative to produce a bit map of the image from the cross information. A method for producing cross positions of Bezier curves with a grid of the present invention includes receiving a Bezier curve, sequentially subdividing the Bezier curve into a plurality of subdivided Bezier curves until each Bezier curve crosses less than a plurality of times with cell boundaries of a grid of a desired resolution, and developing the Cartesian coordinates and direction of each of the crosses of a Bezier curve with a boundary.

Description

21~33 METHOD AND APPARATUS
FOR RENDERING IMAGES

s BY INVENTOR
Jeffrey H. Hoel BACKGROUND OF T~ T~v~ TIoN

The present ~ tion relates generally to the ~.n~ n of images with output devices such 10 as p~inle,~ and colllpul~ .... nilo~ and more particula!y to a method and a~dtUs for rçn~ering an image from an outline le~ f -~ o~ and a des(-~ ,pti~n of the char~t~ lics of the image.

A co.~ e~ system can be used to create and output images on a wide variety of output devices. Raster devices, such as video displays, laser l~ t~ , and color plotters, as well as other devices such as Iy~seth.~ and image setters, are popular for o~ linE 2~ n~ionAl imA.~es.

The process of ren~ering an image for display by an output device can be complex. A
raster pixel map, co...l.. ;.ci~-g a matrix of individual pixels, can l~rcsellt an image and a raster output device can use the pixel map to create a ~. ~ nf.l~t or semi-pe~ nf nt depiction of the image. For example, a laser printer can print dots on a piece of paper coll~,;,ponding to the information of the pixel map. ~ .Atively, a co..-l-!-t ~ n;lor can illl..ll;l-Ate pixels based upon 20 the infollllalion of the pixel map. The depicted image typically coll~ins a lwlllber of predefined shapes, such as cha~ , which can be ~escribed as bit maps. These bit maps can be used to create the pixel map of the image.

A problem with storing pl~derlned shapes as bit maps on co...l.ut~ r ~y~lt;llls is that they can CO~ .llf a great deal of memory space. For a cha,dcl~ of a font, for ex~mrle~ a dirre~l~t bit map 25 is required for each font size, orient~tion~ stem weight, etc., even though the bit maps all have the same general appe~lce. In order to conse~ limited memory space when printing characters, and to er-h~nce the flexibility of character displays, shape descriptions employing Bezier curves - 2 J 21 S33g3 and "hints" have been developed to desçri~e text ch~d~te.~ in less lllClllCSl~' space than would be l~Uil~d for storing a collection of bit maps of these çh~-~t- .~

For example, a popular ch~dcla outline format developed by Adobe Systems, Inc., ("Adobe") of Mountain View, California is the Type 1~9 font format, which is a subset of the s PostScript~9 language, also developed by Adobe. The Postecrirt Inte~ eta (a colll~ul.,l program that pfocesses programs written in the PostSairt language) ope.àtes to render bit maps from chalac~r outlin~s and other cha~ ta info..-.~t;- n Por eY~mple~ the PostSr-ript Inte.~let~r can gbn~ a bit m~pped chalact~,. having deci~ted size, o. ;~ A~ion, and other ch~us~cl~ ;xl;cs A bit map is gelle.aled which app.~ tes a specifi~ ch~tef outline, and the bit map is then used to o create an image on a raster output device. "Hints" are typically used to adjust the outlines to illl~lO~ the final ~l igllmPnt and a~ nce of the bit map image.

U.S. Patent 5,301,267 of ~sett et ~l teaches a control device for int~ ting shape definitions and for coll~e.~ g the o~ltlinPs and hints provided thelefiolll to l~te~ A bit maps of ch~t~ which can be stored or displayed on raster devices. The control device can ~ fullll a cl~ te.'s outline data from a ch~t~,r coordinate space to a device coor~illate space which allows the ch~a.;ler to be displayed. A chalac~a is first coll~,.led from its Type 1 format to a stream of hinted, scaled, and l fulllled Bezia control points. The Bezier control points are used to define the curves and lines in~hlded in the transformed ch~r. A Bezier stack m~t hin~ ;ul~ .ly subdivides the Bezier curves. Each curve is subdivided into two pieces unless it passes a fl~tness 20 test and can be appro~im~ted as a straight line segment. A digital dirrel~,.lLal analyzer ~,locesses line se~,llent~ to dete ...;.~e where they cross pixel mi-llin~.s, where the pixels define an output resolutio~ InÇu~ ;on about these crossings is used to fill spe~ ific pixels and create a bit map image of the original outline ch~ 0~ ~.

A problem ~csoci^~ed with plucescil~g Bezier curves involves the storage and retrieval of 2s the curves to and from ,lle,ll~l y. Memory structures for storing data are known in the art. For example, Donald E. Knutn, in Th~ Art of Colll~uler Proll~a.~ ~. Vol. 1, Addison Wesley, des~il~s a double-ended queue l~lOl~ structure. This memory structure can be used both as a Patent ADOBP002 21S338~
'~J 3 queue (first-in first-out) or as a stack (last-in first-out) to write and read data from either end of the C llOl~ structure.

A problem enru~ t~ d with prior art pnùCeSSeS, such as the method ~ rlosed by Hassett et al., is that the recursive subdivision process used on Bezier curves can result in somewhat s inaccurate cross specifications. This occurs bec~llce, in these processes, a Bezier curve is appluAilllated by a series of straight line se~ -nt~, which can cause inacculale cross p!~re~

Another problem with prior art prùcesses is that they typically use dirreçf nt m~thods for processing Bezier curves and straight line segmrnts~ and can thus prûve inrfficiç~t in terms of A Ulli~,. .al plublPm enr~ tf .ed with pdor art p~ccsses is how to effiriently dete .. ;I~e when to stop subdividing the Bezier curves. If the subdivision is stopped too soon, poor results may occur. If the subdivision is allowed to go too far, plùces~ g speed suffers.

Patent ADOBP002 2l~3383 -- ~ 4 -SuMMARy OF T~ Il~ TION

The present invention provides a method and app~lus for ~nelaliilg a multi~ llf ncional image from an image description. Bezier curves referenced by the image description are 5 subdivided until each curve crosses at most one boundary of a grid of a desired resolution. Curves that cross one boundary are used to specify crosses, from which a bit map can be produced and an image displayed. In a pl~,fell~,d embo~limpnt~ the present invention is used to provide cross spe~ifi~tions from stored ch~a~t~r o-~ es so that a bit map of a character can be produced for sub3~u~ nt display of an image of that chara~t~ l.

A system for ~ne.~ g a multi-.1;.~u~ n~1 image from an image de~,i~lion in~ludes a digital processor which l~ S an image de3ç~;p~ n The processor produces image rP~ering hlfc.lll~ion from the image des~ d;~n, where the image rPn~çring h~. ,..;~;ol- is ~csoci~tp~d with a shape description; for example, the image ren(3~pring infc.llllalion can reference ch~ct~,r shapes specified in a ch~a~ outline format. The shape descliL,~ion inrl~ldes Bezier curve information describing at least one Bezier curve of the image. A rP~ndPring device is coupled to the digital processor and develops image h~ ;on from the image lçn~1~P. ;i~g h~ n and the ~ccoci^~P,d Bezier curve h~follllation. The re~tlpring device pelrolllls a number of subdivisions on Bezier curves to produce subdivided Bezier curves until all subdivided Bezier curves are at about a desired resolution level and convclls this information into image inform~tion, such as a bit map. The 20 digital processor uses the image infollllation to com~ose a pixel map of the image to be displayed.
Finally, the system in~h1des an output device having the desired resolll~ion level which can display the multi--limPncional image from the pixel map. Suitable output devices include such 2-n~io~l output devices as a co.~ display, a printer, and a plotter.

The re~dçring device of the present invention in~llldes a Bezier subdivision pl~ccssor for 25 subdividing the Bezier curves and producing zero or more crosses, and a microcontroller for providing the Bezier curves to said Bezier subdivision pç~cessor and for prodllcing a bit map from the crosses. The Bezier subdivision processor p~rOlllls subdivisions on a Bezier curve if it is Patent ADOBP002 - - ~
21~33,~3 greater than a desired r~sollltio~ of the desired bit map. Subdivided Bezier cunes are produced until all subdivided Bezier cunes are at about the resolution of the bit map. The subdivision ploccssor produces cross info. .~tion from each of the Bezier cunes which makes one crossing of a grid having the bit map resolution. The microcontroller is r~SyOllSi~c to the cross information 5 and produces the bit map from the cross h~fc...., ~i..n The Bezier subdivision yr~ssor of the present invention pfef~ably in~ludes a number of ccilllyolle~ . A lllClllOl,~r unit is used to store at least one Bezier cune, and a boundary crossings detector is used to detect the number of crossings of Bezier cunes with the cell bound~ries of the grid. A Bezier subdivision unit is used to produce a number of subdivided Bezier cunes for each o Bezier cune in the memory unit that has more than one crossing of cell boundaries. The subdivision unit stores a portion of the subdivided Bezier cunes in the memory unit. A cross fc~ er is used to produce cross h~follll~tion for each Bezier curve having one crossing of the cell bound:~ril~s.

The memory unit pl~felably comrricec a last-in, first-out (L~O) stack. The Bezier 5 subdivision unit pushes the subdivided Bezier cunes onto the stack so that the crossings detector and the Bezier subdivision unit can f~cul~ivcly subdivide the Bezier cunes on the stack. The crossings det~;lor preferably incllldes combin~tori~l logic for d~t~ ini~ wLclll~r a Bezier cune makes a plurality of crossings of cell bolln~riçs. The crossings detector detects the number of boundaries crossed by the line segment connf~l;ng the endpoints of said Bezier cune and 20 COlllyd~S ho. ;~.ol~l~l and vertical coor~il.ates of endpoints of the curve to d~te ...;ne the llUnll~ of cros~ing.~. The Bezier sul~di~i~ion unit further in~ludes an X subdivision unit and a Y subdivision unit. The subdivision unit preferably uses averagers col-.-~led to produce X and Y coordinates of the control points of two subdivided Bezier cunes. The cross form~tter in~ludes a number of mllltiplexers combined to receive inf .. ~ n from the cl~Jssillgs detector and to ~ene.~le the X and 25 Y coordinates and direction of a cross. Finally, the Bezier subdivision processor plefeldbly includes a control unit, an input ~gi~l~r, and â register for storing a cull~llly-processed Bezier curve.

Patent ADOBP002 - .
21~3383 .
~ 6 A mPthod for producing cross positionc of Bezier curves with cell bo--n-l~ries of a grid includes the steps of receiving a Bezier curve, sequçnt~ y dividing the Bezier curve into subdivided Bezier curves until each Bezier curve crosses æro or one times with cell bol1nd~ri~.s of a grid of a desired resolution, and developing crosses including the Cartesian coordinates and 5 direction of each of the crosses of a Bezier curve with a boundary. The method plerelably includes le~iving a line se.gment Bezier curve and con-vt;l~ g the line Sf g~ nt Bezier curve to the Bezier curve type used in the present invention. The step of seque~ti~lly dividing is preferably a l~ul~ive subdivision step which includes subdividing a Bezier curve into two pieces, each of which comprices a Bezier curve. Curves which do not cross any of the bollntl~ries are pçtfel~.bly 10 ignored. The crosses can then be used to produce a bit map or to control an output device.

A llle.llol~/ conslluct of the present invention jncludes a stack which o~rales as a LIFO
elllol~ and a queue which O~aleS as a FIFO lllelllol~. The queue is ~csoci~led with the stack such that when the stack is empty, data is read from the queue. A lllelllol~ control writes data to the stack, reads data from the stack, and writes data to the queue. The llltlllOl,~/ control preferably 5 includ~s a stack up/down c~unttr to provide a stack pointer into the stack, a FlFO-out up counter to provide a FIFO-out pointer which points to the front of the queue, and a FIFO-in up counter to provide a FIFO-in pointer into the queue. The stack and the queue are plefe~ably contiguous, and the stack pointer points to the front of the queue when the stack is empty.

The r~n-lering device of the present invention provides an effi~ipnt method of detf ....;~ g 20 an optimal time to stop subdividing Bezier curves. This produces accurate images with good procescin~ speeds. Furth~-~ ...o~, since the r~ndering device of the present invention is o~ ed to subdivide cubic Bezier curves, straight line segm~nts, which are Bezier curves of degree one, are converted to cubic Bezier curves before proce-ssing This allows the subdivision logic to be highly oplin~ed for its task.

2s These and other advantages of the present invention will b~olll~ app~nt to those skilled in the art upon a reading of the following spec;fic~tion of the invention and a study of the several figures of the drawing.

Patent ADOBP002 21~3383 BRIEF DF^~cRTpIloN OF T~F I)I~VVINGS

Figure 1 is a block rli~m of a co~ t~,l system in accGl~lce with the present in~llLioll;

Figure 2 is a block diagram of the r~.n~lering device shown in Figure 1;

s Figure 3 is a block diagram of the Be_ier subdivision p~cessor shown in Figure 2;

Figure 4 is a block ~liagr~m of the lllclllol~ unit of Pigure 3;

Figure 4a is a dia~,.."".~1;r. illl~chPtion of the o~ 7~-~;on of the lll~ unit;

Figure S is a block ~ ~m of the subdivision unit of Figure 3;

Figure 6 is a schr ..~;c di~ of the y-coo~dinale carry-in circuit of Figure 5;

Figure 7 is a block diagram of the ~md~y crossings d~ tor of Figure 3;

Figure 7a is a block diagram of a logic block 136 of Figure 7;

Figure 7b is a table of logic block O~ J~;

Figure 7c is a table of five-bit codes le~ g logic block olltputc;

Figure 7d is a s~ ;c ~ -,. of a logic block 140 of Figure 7a;

IS Figure 7e is a schf .. ~;r .~ .. of logic block 142 of Figure 7a;

Figure 7f is a scl~ ic diagram of logic block 138 of Figure 7;

Figure 8 is a s~h ~ ;c diagram of the cross fn. ~ .r of Figure 3;

Figure 9 is a flow diagram illu~ldLillg the m~thod imple~ d by the Bezier subdivision plocessor to find the crosses of a Bezier curve;

Patent ADOBP002 Figure lOa is a diaglh.. ~ic illustration of an outline of a ch~acler that has been ll~sÇ~ ed to device coo,di~ale space;

Figure lOb is a diaglA ....~ ~ir illustration of a Bezier curve from Figure lOa, processed in device co~ te space, and ~soc~ ,os~s, Figure lOc is a diag,A~ r ~p~cse~ ;on of the cha,ael~r outline of Figure lOa having filled pixels; and Figure 11 is a flow diagram illustrating the mrthod of the present invention to develop crosses from Bezier curves.

Patent ADOBP~2 - ~ 9 2 1 ~3383 DETAILED DESCR~PTION OF T~ PREF~RR~n EMROD~l~ENT

The present invention is well suited for producing bit maps of a desired resolution which can be used to display an image on an output device such as a laser printer or display screen. The 5 pref~ d embodiment of the invention provides a 2-~im~.cional bit map for displaying 2-~iimlo.ncional imagec, such as text and graphics, on such devices as display screens and p~ e,s.
However, since the present invention provides a description of curved paths to a desired resolution, it can also be used for producin~ other image inrc.. ~ion which is useful in creating or displaying a multi rlim~cion~l desired image, such as a three~iim~ncion~l model.
0 A number of terms are used herein to ~esçribe images and related ~lluctules. "Pixel" refers to a single picture C1F~ of a raster image. Taken collectively, the pixels form the image. "Pixel map" refers to bits stored in digital lllSlll~ly in a data structure that l~,l,l~ell~ the pixels. The pixel map in~ dec information on the location of the displayed pixels and other inform~tion, such as color and brightness of the pixels. "Bit map" refers to a nulllbcr of bits stored in memory which can be used to select which pixels in a pixel map are to be displayed, modified, etc. "Resolution"
refers to the spacing of pixels in a pixel map. For eY~mple, a displayed pixel map of very small pixels, closely spaced, has a greater resolution, i.e., greater detail, than a displayed pixel map having large pixels widely spaced. "Render" refers to the creation of a bit map from image ren~-in~ infc~ ion and a lGr~,~,nced shape dcsc~iption. "Raster" refers to an output device that creates an image by displaying an array of pixels arranged in rows and coll~mnc. By "raster" it is meant herein any output device which can display a 2~ ncional image with a matrix of pixels arranged in rows and colllmnc~ regardless of how those pixels are activated. Raster output devices include laser pl;~.te~ c~ .ut~ displays, video displays, LCD displays, etc.

In Figure 1, a digital system 8 is co!~l,l~ to a rçn~lç-ing system 10. Digital system 8 can 25 be, ~or example, a personal colll~u~ system or any other type of digital device or tr~-.cic~ion m~ lm Digital system 8 can display or print images on the rendering system 10. To display such an image, digital system 8 sends an image descliplion via co~ ;r~tion bus 12 to rçnrlçrin~
Patent ADOBP002 21 ~3~83 , J 10 ~~

system 10. This image description can include lercrcllces to shapes of which the image is colll~osed, and each such lGfe~ence can include the identity, loc~tio~ size, ol ;c~ tion~ etc. of the e of the lerelGnced shape. If the shape is a character, then the identity of the shape in~h-des the font of the character. If, for example, the digital system requests that the r~ndering system 10 5 pAnt out a text file on a laser printer, then an image de~ tinn of the ch&~;t~,r shapes of the text is sent to the re~lering system 10. Such an image description can be in a standard, widely-used language, such as PostScript~9 by Adobe Systems, Inc. of Mountain View, California. The PostScApt language allows shapes, such as characters, to be descAbed by lefc.lillg to shape desç. ;l)tions~ which include outlines of the shapes and other inforrnation and determine how the o shapes appear in the displayed image. A page of text in the PostScript language can be stored in a relatively small lllelllol.~ space yet include all of the i~ l~tion l~e-ss~ y to produce a high-quality image of the text.

Renderirlg system 10 preferably inrludes a digital ploc~ssor 14, dynamic random access melll~l~/ (DRAM) 16, read-only lllellloly (ROM) 18, a l~"df~ g device 20, optional static random 15 access lllel~ (SRAM) 22, and an output device 24.

Digital ~ cessor 14 is a microprocessor which controls the general operation and filn~tion.c of rendering system 10. Processor 14 r~ceiv~;s an image desclip~ion from digital system 8 and d~t~ )es what il~foll~lalion to send to other co~onellt~ in ren-1ering system 10 so that an image can be displayed on output device 24. The image descliption recei~.,d by digital ~rocessor 14 20 describes what shapes are inf~llld~l in the image, where each shape is located within the image, and display ch~et. . ;~lics such as size and o. ;~, ~t~ion. For ex~rnple., an image de~liption of a page of text in the PostScript language can be input to digital processor 14. Digital plocessor 14 can control other devices in ren~lerin~ system 10 to produce a pixel map, based on the original PostScript image descri~lion, that can be displayed by output device 24 . Digital pr~xessor 14 2s co------~ ; t~ to other CO--~ f ~ in re~d~rir.g system 10 through system bus 15.

Once digital ~locessor 14 lecei~cs an image d~ ;p!iQI~ from digital system 8, plvcessor 14 creates a pixel map of the des-~ribe~l image that can be displayed on output device 24. Bit map image information coll~,sponding to a shape, such as a character, referenced by the image Patent ADOBP002 lj, t~ 2IS33~

d~s~ ;pl;o.. may already exist and be stored in IllGlll~ /, such as DRAM 16. In this case, pl~essor 14 can imme~i~tely use this bit map image inform~fion to update the output pixel map. However, if no such bit map image infc....~tion is available, digital processor 14 produces image re~-lering information from the image description. This image rçndçring information is then used by s relldçring device 20 to produce the required bit map image information, which processor 14 can then use to update an output pixel map. Typically, this bit map image information is also saved (cached) in lllelllGly for possible further use. When the output pixel map is completed, processor 14 sends it to output device 24, where it is displayed.

The image rendering info,.~.~lio~ is an information packet which provides information in o the correct format for rend~oring device 20 to create rendered bit map image information. In a preferred embo~im~nf, the image re.ndçring information includes a pointer to the location in lllelllol~ (such as ROM 18) for rendçring device 20 to find a shape desc~ ;plion of the shape to be rendered, where to output lel1dercd image information (e.g., a location in memory), and how rendering device 20 is to co~ ir~te with digital pl~cessor 14 to in-iir~te it has fini.chPd its 5 rendering task, needs ~C~ict~nce~ etc. Both the image rçndçring information and the shape descli~tions referred to by the image 1~ nd~ ;ng il~O....~;l n can be collectively referred to as "input information" to rendering device 20. Rçndçring device 20 COIl~ this input information into image infc.l~ lion, such as a rendered bit map.

In a plcftllcd embotlimtont, the shape des.;li~lion required by rçn~l~ring device 20 inellldes 20 an outline of the shape, desc-ribed as a series of Bezier curves of degree one or three, and may also include hints. Rendering device 20 transforms this outline from a shape definition coordinate space to a device coo~ e space according to image renderin~ infollllation, such as size and orient~tion. Rende-ring device 20 further l~a,l~rolllls the outline to a "hinted" device coordinate - space accolding to "hints" s~il;e~l in the shape descli~tion. R~ndto.ring device 20 then renders the 25 outline, coll~ ing it into bit map image inrcllllalion. The shape dcscfil)tion can be specified in a standard format, such as the Type 1~9 font format by Adobe Systems, Inc. The shapes described in Type 1 format are typically ch=-~ - t....~ of a font.

Patent AWBP002 2l 53383 ~ i 12 ~' Rçn~lPr ng device 20 p~feldbly stores the rendered bit map in a cache within lllelll~ such as DRAM 16. If the image descliplion should reference this shape again (at the same size, orientation, etc.), digital pr~cessor 14 can use this bit map to update the pixel map, rather than having to col~ n~1 rentlP.rin~ device 20 to render the bit map again. These methods are well-5 known to those skilled in the art.

DRAM 16 is used to store various data used by co...l on~ of rçn-lçring system 10. It can be used to store bit map data from ~.-de.;l~ device 20. ROM 18 stores infol...~tion of a read-only nature, such as instructions esecllted by digital pl~cessor 14 and shape descliptions used by Ç- ;llg device 20.

Rçndçring device 20 uses the image rel lering infGlllldtion to create bit map image il~.lllatiol1 from a portion of the image des~-~ ;p1ion In one embo-limPnt rçn~lPring device 20 uses image l~ lç ;ng h~... 'ion from processor 14 to convert shape descrirti~n~ to bit maps which can be used by p~cGssor 14 to update a pixel map which is eventually dis~!a~ed on output device 24. ~lt~prn~tively~ ren~Pring device 20 can output a bit map that is treated as a pixel map and 15 displayed directly by output device 24. p~Pn~iPring device 20 can access lllellloly such as ROM 18 or DRAM 16 via system bus 15 to retrieve shape des~ ;on~.

In the desçribed embotlimPnt, digital processor 14 leCei~,S a Post-~çript language page-level image description from the digital system 8. This descli~ion includes the character identity, font attributes, size, oriPnt~tion, etc., of the chalacte,~ which are desired to be displayed. The 20 image descliption refers to shape desc~ tion~ of the ch~dct~ in, for es~mrle7 the Type 1 font format. Digital processor 14 int~let~ the image dPs~ .irtion and sends packets of image rPndPring information to ren~Pring device 20, one packet at a time. A single packet of image rendering information describes a single character which ren~çring device 20 is to col.~ into bit map infol.~lation. The packet includes, among other things, inf~ ation about where in memory 2s 1~iu3f,. ;,-~. device 20 should look to retrieve the shape desc.i~tion pc~ori~tp~ with that ch~d~;t~,r. In this described embo~limpnt~ it is ~sumPd that shape descliptions for all standard characters are stored in ROM 18 or DRAM 16.

Patent ADOBP002 -2I ~33~3 J 13 ~, Ren-l~Pring device 20 writes bit map i~folulaLion to DRAM 16 via bus 15. ~çncl~P.ring device 20 and its operation are cles~-ribed in greater detail with lGf~,ncG to Figure 2.

SRAM 22 is an optional com~ollenl in 1~ ~de ;,~ system 10. If present, SRAM 22 can be used to store information used by renrlpring device 20. If SRAM 22 is not present, the information s can be stored in DRAM 16. SRAM 22 can be used to store crosses and intPrn~l bit maps genelaled by rendPrin~ device 20, as well as microcode used by rend~Pring device 20. SRAM 22 can also serve for other general pulpose, scratch-pad-type functions. In general, the operation of relul~prin~
system 10 is much faster when SRAM 22 is used, because rendçring device 20 and digital plocessor 14 do not have to coul~Gte for the use of bus 15 and b~a~lse SRAM 22 is typically faster 10 than DRAM 16.

Output device 24 is used to display a desired image from a pixel map developed by processor 14. The pixel map was derived by processor 14 from the bit map image information developed by rend~Pring device 20. In the described embo-limP-nt output device 24 is a raster device such as a display screen, laser printer, plotter, etc., which can display the pixel map directly 15 on a pixel-by-pixel basis to produce the desired image on a display screen, sheet of paper, etc.

In other embo l;...~.t~, output device 24 can be used to display other types of images from the image information received from rPndPring device 20. For eY~rnrle, output device 24 can be a three-tlimPn~ional modçling device which lecei~es Bezier cross information (described below) from rend~Pring device 20 to control its mo~ n~ in forming a three~limPn~ional shape or image.
20 For P~mpl~o., Bezier cross inform~tion can control a nnmPric~lly controlled mill to produce 3-d models of objects.

Figure 2 is a block diagram of a ~l..l~ ~;,.g device 20 shown in Figure 1. In the descAbed embodimPnt, re~dçring device 20 in~ des a microcontroller 30, ROM 32, SRAM 34 and 35, a front channel intPrf.~e 36, a Bezier subdivision processor 38, and a back channel int~rf -~e 40. In 25 the preferred embo-limPnt, ren~l~pring device 20 is i~ e~ t~Pd as a single integrated circuit chip.
~Pn-lçring device 20 is descAbed as a synchr~nous digital system, but may also be imple-mPntP,d as an asynchronous system.
Patent ADOBP002 - ` 14 ~ 21~3383 Micnxc,ntl- ller 30 is a digital pr~cessor and controller of ~ d~F~ p device 20 and l~cFives the image rend~ring information from digital processor 14 over system bus 15. The image rendering information is sent through front ch~nnPI interf~çe 36 and on front ch~nnçl bus 31.
Micl(~contloller 30 reads the image rend~Pring inform~tion which, for e~rnrle, describes where to 5 retrieve a shape descfipLion from lllelllOl~/ such as ROM 18 or DRAM 16. The processor 30 then hlt~ ~ts the lGtliGvGd shape des-;fi~ion and sends Bezier control points to the Bezier subdivision prûcessor 38.

In the described embo~limPnt, the image rendP-rin_ information includes a packet of infollllalion describing which character is to be rendered and the location in memory of the shape 10 descfiption for that cha~iter. The shape de~;ption can be in a format such as Type 1 and can include many dirfe,~.ll types of illfolllldtion des~-~ ;bil~p the de~ig~ed Ch~dCt~l. Such info~ io~-includ~Ps an outline of the shape, hinting infolllldtion7 and spacing inform~tio~ The outline of the shape includes Bezier curve infolllld~ion, i.e., the outline is preferably desl-ribed as a sequence of Bezier curves of degree one (i.e., line segments) or three (i.e., cubic Bezier curves), and each 5 curve is des~ribed by its control points.

Microcontroller 30 converts the outline of a shape descli~tion from a shape definition coordin~le space to a device coonlilldte space that is suitable for rendPring the shape as a bit map.
Microcontroller 30 thus must inlGlpl~t the outline and ~ Çullll the outline to a desired resolution.
Microcontroller 30 also pGlrullns "hinting" on the outline accoldillg to hinting i,~ollll~ion retlie~Gd 20 from lllemul~ with the outline. Hintin~, as described above, is the adj..~...Fnt of the outlines of ch~ t,l~ to ilU~lo~G the ~lignm~nt and appear~ce of the resulting cha.a~t~l bit map. ~inting is generally desçribed in the book Adobe Tyye 1 Font Form~t Adobe Systems, Inc., 1990. Some details of hinting are described in U.S. Patent 5,301,267, by Hassett et al., ~si~ned to the same ~c~ e as the present invention, and hlcol~olatGd by lcÇc.~"lce herein.

2s Microcontroller 30 tlallsÇolllls the outline to a scaled, hinted dFs~;plion of the character having a number of Bezier control points which describe Bezier curves. Each Bezier curve is defined by a number of control points and a number of Bezier curves can be used to describe a shape quite accurately. A commonly-used Bezier curve referred to herein is a cubic Bezier curve, Patent ADOBP002 21~3383 ~

which has four control points. A straight line seg~ is a Bezier curve of degree 1, i.e., a Bezier curve having two control points. Bezier curves are well known to those skilled in the art and are desçrihed in greater detail with l~fc~ence to Figure 10b. The Bezier control points are specified in the shape d~sc~ ion format which is read by micloconllùller 30. Micfuconlloller 30 provides the s coordinates of the Bezier control points to the Bezier subdivision processor 38 (described below).

ROM 32 is used to store ~luc~ùcode used by micf~co~ oller 30. SRAM 34 and 35 are used to store data for mic,o~lucessor 30. In the described embo-limPnt, SRAM 34 is used to store micl.~code overlays, which are groups of insL~u-;lions eYP,cuted by miclucont.~oller 30. SRAM 35 is used to store certain data used by micrùcon~oller 30, including hinting and scratchpad 0 h~folll~tion. In an ~ltrrn~te embo~imP-nt, a single SRAM can be used instead of SRAM 34 and 35.

Bezier suWvision plocessor 38 pe.r,l l s suWvision on Bezier curves which are specified by coor~ ales of control points input to suWvision processor 38 from llliclocont oller 30 via bus 58. Subdivision processor 38 of the present invention does not ~rulm a flatness test on a curve, but instead checks if the curve crosses multiple piYel milllinr. ("cell") bo~ln~l~ries. Curves are 5 subdivided only until the lengths of the suWvided curves are about the resolution of the desired pixel grid, which illlpfO~,s cross ac-;ulacy over the prior art cross specification methods. The ~llu~:lul~ and functionality of subdivision pl~cessol 38 is (lesçribed in greater detail with reference to Figure 3.

Back cl.~ .nFI int~ ce 40 is used to provide input and output access to SRAM 22 via back 20 cl ~nl~rl bus 41. Bezier subdivision processor 38 stores "crosses," produced from Bezier curves, in SRAM 22. In embo l;."~ where SRAM 22 is not available, the back ch~nnrl bus 41 and back rh~nnel il~t~.. ri.ce 40 are not used, and DRAM 16 is used instead of SRAM æ.

Bezier subdivision processor 38 outputs "crosses," which are blocks of h~fo,lllalion that describe where Bezier curves cross cell bo..,~ ;cs of a pixel grid. Each cell boundary falls on a 25 pixel millline, i.e., a line passing through the centers of a row or column of pixels, so that each cell col.l;.inc a quadrant each of four different pixels. These elem~ntc are described in greater detail with reference to Figures 10a-c. In the described embo-limrrlt, a cross includes the x and y Patent ADOBP002 coordinates of the cell below or to the left of the crossed boundary and a direction, i.e., north, south, east, or west. Bezier subdivision proce$sor 38 stores these crosses in SRAM 22, where ,llic~conl,~ ller 30 can later retrieve them.

Subdivision processor 38 is reset to an initial state each time mici~contr~ller 30 begins s proce.ssing a new shape descliplion. Once subdivision processor 38 has found all the boundary crossings for all of the Bezier curves of an input outline and has stored the crosses in SRAM 22, processor 38 im1irates to microcontroller 30 that it has comrloted its task. If another outline needs to be analyzed, microcontroller 30 can send a signal to reset subdivision processor 38 to the initial state for the next outline.

Once all the crosses of the outline of a shape, such as a character, have been found and stored in memory, micloconlloller 30 can use the cross infollnalion, employing one or more of several different methods to create a bit map. That is, specific bits of a bit map are turned on acco~ g to certain rules and acco,ding to the location and direction of the crosses (see Figure lOc). Methods to g~,ne~ale a bit map from crosses are well known to those skilled in the art; see, 15 for e~mpl~7 U.S. patent 5,301,267, supra, and U.S. Patent 5,200,740, by Paxton et al.

When a bit map has been generated by rnic,ocol.l,oller 30, the bit map is output by micr~colltroller 30 onto system bus 15, where it is preferably stored in memory ncces.cible to digital processor 14. The image rendçring hlfo....~ion ori~in~lly sent by digital processor 14 to re-n-lering device 20 inrhldes information about where the microcontroller 30 should send the 20 oul~ulled bit map.

Figure 3 is a block diagram of Bezier subdivision processor 38 shown in Figure 2.
Subdivision processor 38 includes an input register 44, a memory unit 46, a register 50, a ~7uWivision unit 48, a boundary crossings detector 52, a cross form~tter 54, and a control unit 56.

Input register 44 is a standard storage register which receives and stores coordinates for 25 control points of Bezier curves on bus 58 from micnxolllroller 30. In the ~lesc~i-be~ embodiment, input register 44 includes eight 15-bit registers (X0, Y0, Xl, Yl, X2, Y2, X3, and Y3), each Patent ADOBP002 2l~3383 ~~ 17 capable of storing one of the eight coo r~linat~s that specify the four control points of a cubic Bezier cune.

Mic.ucollll~ ller 30 in~ t~s to control unit 56 via line 59 v~Lctllcr the coordinate on bus 58 is valid, wrll~ r it is part of the specifi~tion of a cubic Bezier cune or a 1st degree Bezier curve s (a line segment), whether it is an x coordinate or a y coordinate, which control point is being specified (i.e., first, secon-l etc.), and whether the coordinate is the last coordillate needed to complete the specification of the Bezier cune. Control unit 56 COnV`e1I~ this infollllation into signarls for enabling individual 15-bit registers within register 44, which it sends to register 44 via bus 62.

Input register 44 l~,cei~r~,s one 15-bit coordinate via bus 58. The coordinate is stored in ~gi~t~r 44 if micr~r~)cessor 30 in~iir~tes (on line 59) that the coordinate is valid, and if control unit 56 in~ic~tes via line 60 that subdivision processor 38 can accept the coordinate. Register 44 ~ccllm~ t~s coolrlinales as they are l~ceived until a cc mp~ete Bezier curve is received. In ~ltPrn~te embo-li...r.~ , the coordinates of Bezier curves can be specified in a nulllbel of bits other than 15;
5 register 44 and other colllponf;llts of subdivision processor 38 would then be çh~nged accol.lil~gly.

If a l~i~r~d coordinate is part of a cubic Bezier cune specifir~tion, then it is loaded into the 15-bit register that cOllr.,spollds to the intlic~te l control point and axis (x or y). If the ç~ceived coordinate is part of a line seglll~nt specifit~ation (inrlu-ling four coordinates xO, yO, xl and yl), then it is loaded into two 15-bit registers as follows: input cool.li~ldle xO is loaded into IYgi~ X0 20 and Xl, input coor~inate yO is loaded into registers Y0 and Yl, input coonlinate xl is loaded into e~ X2 and X3, and input coordinate yl is loaded into registers Y2 and Y3. rhe line segrnPnt specification (Bezier curve with two control points) is thus con~.led into a cubic Bezier curve specification having four control points. By con-elling line se~..f ~ to cubic Bezier cunes, only one subdivision unit is required to process one type of input Bezier curve. In alternate 25 elllbo~ f l~ts~ a sep~ate suWvision unit is inchlde~l for each type of input Bezier curve, and the conversion of line se~lt;lll~ to cubic Bezier curves is not be le~luilcd. In other embofiim~r~t~ a previously-stored coordinate value is used to leplesent an input coordinate. Using a previously-stored value for some coordinates can save time if re~tili~e coordinates are being input to Patent ADOBP002 - . , 21~383 18 ~

subdivision processor 38. In other embo~ .F~ , Bezier curves having more or fewer than four control points can be processe-l The curve stored in input lcgi~l~r 44 is æGces~ihle on bus 64 to a first-in first-out (FIFO) lloly structure in l~C~l~ly unit 46 (det~ilP~d below).

s Memory unit 46 stores Bezier curves which are to be processed by Bezier subdivision plocessor 38. In the described embodiment, memory unit 46 is logically partition~qd into a queue (first-in first-out, i.e., ~l~O) for storing Bezier curves lccei~ed from input register 44, and as a stack (last-in first~ut, i.e., LIFO) for storing Bezier curves l~ceiv~d from subdivision unit 48 via bus 70.

The FIFO within luelllol~ unit 46 is used to buffer Bezier curves and thus allows lllicluco,ll oller 30 to input Bezier curves and Bezier subdivision processor 38 to process Bezier curves at their scpa~te rates. This .~ .;,.,s the possibility that llliclocontloller 30 might have to stall, waiting for Bezier subdivision processor 38 to accept the next Bezier curve, or the pos.~ibility that Bezier subdivision l)locessor 38 might have to stall, waiting for micl xontloller 30 to provide the next Bezier curve.

The FIFO within lllC.llOl~' unit 46 can be co.. ~ ~ by control unit 56 via control bus 66 to retain its current state, to becolll~ empty, to write a Bezier curve from input register 44 via bus 64 to the end of the queue, or to read a Bezier curve from input register 44 via bus 64 from the front of the queue to register 50 via bus 68. Memory unit 46 in~ie~tes to control unit 56 via status 20 bus 67 whe~ or not the FIFO is full. When a con~rlet~ Bezier curve has been ~ccum~ ted in input register 44, the curve is loaded into the FIFO if the FIFO is not full. Input register 44 is then allowed by control unit 56 to load the next Bezier curve. If the ~O is full, input register 44 is not allowed to load another Bezier curve until the FIFO becomes not full and the current curve in register 44 can be written to the FI~O.

2s The stack of memory unit 46 is used to store subdivided Bezier curves created by subdivision unit 48. When a Bezier curve is subdivided by subdivision unit 48 into two Bezier curves, the first curve is ex~minçd next, and the second curve is pushed onto the stack to be Patent ADOBP002 19 ~ ` 21 S33~3 eY~nined after the first curve has been co...l,letely subdivided. This process is desç ibed in more detail with reference to Figure 9. When subdivision processor 38 has popped all subdivided curves from the stack so that the stack is empty, p.ocessor 38 then ,el-ieves the next Bezier curve from the front of the FIFO.

The stack can be co~ nrled by control unit 56 via control bus 66 to retain its current state, to becon~ empty, to push a Bezier curve onto the stack from subdivision unit 48 via bus 70, or to pop a Bezier curve from the stack to register 50 on bus 68. Memory unit 46 in-lic~tes to control unit 56 via status bus 67 whether or not the FIFO and the stack are empty.

The structure and operation of memory unit 46 is desc-ribed in greater detail with lefc.~.nce to Figure 4.

Register 50 is used to store the Bezier curve c~ ,.llly being processed by Bezier suWvision plocessor 38. The curve stored in register 50 is made available to subdivision unit 48, boundary crossings det~;lor 52, and cross fc ~ ,r 54 via bus 72.

Register 50 can be controlled by control unit 56 via control bus 76 to retain its current state, to load a curve either popped from the stack or read from the ~O of ~.lIOI y unit 46 via bus 68, or to load a curve re~;ved from subdivision unit 48 via bus 74.

Subdivision unit 48 subdivides the current Bezier curve, supplied by register 50 via bus 72, into two Bezier curves. The first of the subdivided Bezier curves, which has the same first control point P0 as the current Bezier curve, is sent to .~gi~l~r 50 via bus 74 so that it can beco"lc the next current Bezier curve. The second of the subdivided curves, which has the same last control point P3 as the current Bezier curve, is sent to lll~lllOl ~ unit 46 via bus 70 so that it can be pushed onto the stack. Subdivision unit 48 subdivides the current Bezier curve whether or not it is needed (as d~le~ rd by boundary crossings det~tor 52, desç~ ;~d below). If the subdivision of the current Bezier curve is not needed. then the outputs of subdivision unit 48 are ignored by 2s register 50 and llle,~GI~ unit 46 under the control of control unit 56. Subdivision unit is desçrihed in greater detail with Icfc.~l~ce to Figure 5.
.

Patent ADOBP002 .
~ 20 - `~ 21~3383 Boundary crossings detector 52 is used to dete~...ine whether the current Bezier curve crosses zero boun-l~ri~s, one boundary, or more than one boundary belweell cells of a pixel grid.
The number of crossings detelmilles if a curve should be subdivided further, discarded, or fc,~ ed into a cross by cross forrn~tter 54. If the current curve crosses more than one boundary, s it is subdivided. If it crosses no bo~lnd~ries, it is discarded. If it crosses one boundary, it is used by cross fo~ ,r 54 to gel~-dle a cross, and then it is discarded. Boundary crossings detector 52 thus allows the subdivision of a Bezier curve to conLillue until the curve has been subdivided to the resolution of the pixel grid. Boundary crossings detector 52 also dete. mil~fs the direction of a ~e.lc.aled cross.

Boundary crossings detector 52 ~;~.s the current Bezier curve from register 50 via bus 72. Detector 52 sends infollllation about the nulllber of bo~ln~l~ries crossed by the current Bezier curve to control unit 56 via bus 78. From this infollllation, control unit 56 decides whether to subdivide the current Bezier curve and ~I,~tllcr to output a cross. Bound~ ~ crossings detçctor 52 sends information about the direction of the cross to cross form~tter 54 via bus 80. Boundary 15 crossings deteclol 52 is described in greater detail with respect to Figure 7.

Cross fo.l..h~l- r 54 ~i~/es the çn-lpoint~ of the current Bezier curve from r~gisl~,r 50 via bus 72 and the direction of the detectecl boundary crossing from boundary crossings det~-ctor 52 via bus 80. From this hlf .~ n, cross fo.... ~ ,r 54 creates a cross spec-ifi~ation~ which in~hldes an x coordinate, a y coordinate, and a direction. The x coordinate of the cross is preferably the 20 lesser of the x coor~il.ales of the endpoints of the Bezier curve. Similarly, the y coordinate of the cross is preferably the lesser of the y-coordinates of the endpoints of the Bezier curve. Cross formatter 54 provides the cross specification on output bus 82, which is coupled to memory ;..1~ . r;~ce 55. Cross fo....;~l~r 54 is described in greater detail with ler~. ,nce to Figure 8.

Memory ;~ . r~ce 55 ~cei~es crosses from cross fo....~ ,r 54 on bus 82 and preferably 2s writes them to SRAM 22 via back ch~nn~-l bus 41 and back ch~nnlol ;--t~- r~ce 40 (if SRAM 22 is used), or otherwise to DRAM 16 via front ch~nnel bus 31 and front ch~nn~ lf.. r~. e 36. Crosses thus stored in lll~lllol~r are then ~ssed by micl~,conlloller 30 to create a bit map.

Patent ADOBP002 21 21~338~

Memory intçrfr^,e 55 inputs a cross from cross fo~ ~r 54 wllenc~cr control unit 56 in~lic~tçs via line 84 that a valid cross is available and lllClllOl,y intP.~ce 55 iS able to input a cross, which it intlic~t~c to control unit 56 via line 85.

Control unit 56 provides the control signals n~.cess~ to operate the Bezier subdivision 5 pl~cessor 38. In the desr.ribed embo-lim~.nt, control unit 56 is imrl~ n~ed using a state "~r.l~
which provides the logic ~escri~ed above and with l~,fc.cnce to Figure 9. Such state m~rhin~.s are well known by those skilled in the art.

In an ~ltrrn~te emboflim~nt~ llle.ll~l~ unit 46 is used entirely as a stack and does not include a FIFO. Input Bezier curves are t~src.led directly from input register 44 to register 50 using an 0 additional input, namely bus 64. However, such an embodim~ont does not provide the advantage of l rr~ing the input as in the above-desclil,cd clllbo~ nl In another ~ltprn~te embo~limp-nt~ input register 44 is not used to ~c~;u~ te input Bezier curves. Tn.ctr~d, lllicloplocessor 30 provides an entire Bezier cune in parallel via bus 58, which is input directly to the FIFO within lllelllol~/ unit 46. In such an embo-lim~nt, lcsponsibility for 15 ~çcllm~ ting the input Bezier curve is shifted to lllicloconl,oller 30.

The various co~onents of the Bezier subdivision processor are plcfc.~bly imr,k.. -t~3 using hal.lw~c colll~ollel ts and logic gates. Various functions desc-ribecl above can, of course, also be implçm~nted in s~rlw~c. The h~.lw~u~c imrlem~.nt~tion, ho~.~,vcr, provides a more efficient cross specification process than if some or all of the functions were implemented in 20 sonw~

In the plcfc.l~,d embo~lim~t~ subdivision unit 48, boundary crossings detector 52, and cross form~tter 54 are combinAIo. ;~1, mP.~ning that they com~ule their outputs in the same clock cycie that they receive their inputs. This provides a fast, effiçient process for collll)ulhlg cross spe~ifir~tions.

25Figure 4 is a block diagram of mc.l~ unit 46 as shown in Figure 3. In the desçribe~
embo~lim~-nt, a single SRAM unit is used to imrlen ~.nt a memory construct including both the Patent ADOBP002 21~3383 ~ . 22 ~

FIFO and the stack of the present invention, where the access of either l,lcl,lol~ structure can be selecte~l by control unit 56. Other types of RAM or similarly-filnctinning lllclll~l~ devices can also be used. Memory unit 46 pl~,felably in~ludes FIFO-in up counter 90, FIFO-out up counter 92, stack up/down coullt~l 94, m-lltirleYPr 96, tri-state mllltirl.oY~er 111, SRAM 98, and logic 100.
5 Control bus 66 of Figure 3 include5 bus 91, bus 93, bus 95, line 108, and bus 109 of Figure 4.
Control unit 56, FIFO-in up counter 90, FIFO-out up counter 92, stack up/down coulll~ r 94, logic 100, and multiplexers 96 and 111 are col~c;~lered a "memory control" for the lllcl,lul y Slrul;~u~,S of SRAM 98. Alternatively, a general purpose microprocessor can, under software contrûl, p~ t the process of the lllGlllUl,~ control.

FIFO-in up counter 90 is used to specify the address of the memory location within SRAM
98 into which the next input Bezier curve will be written (at the back of the ~O). Counter 90 is controlled by control unit 56 via bus 91 to hlcnGlllcnt its count when a curve is written to the FIFO.
FIFO-in up countcl 90 provides its count as an address on bus 102 to multiplexer 96 and logic 100.

FIFO-out up counter 92 is used to specify the address of the lll.,mol~ location within SRAM 98 that stores the Bezier curve at the front of the FIFO (unless the ~O is empty).
Counter 92 is controlled by control unit 56 via bus 93 to incl~,l,l~nl its count when a curve is read from the front of the FIFO and loaded in register 50. Counter 92 provides its count to logic 100 on bus 104.

Stack up/down COUiltC- 94 is used to specify the address of the lll~,lllol~ location within SRAM 98 that stores the Bezier curve at the top of the stack (unless the stack is empty). Stack up/down counter 94 is controlled by control unit 56 on bus 95 to hlclelll~ nt its count when a curve is popped from the stack and to decl.,lllcnt its count when a curve is pushed onto the stack. Stack counter 94 provides its count as an address on bus 106 to mllltipl~Y~r 96 and logic 100.

2s Ml~ltirle~Yer 96 is used to switch ~t~n the addresses output by the FIFO-in coullter 90 on bus 102 and the stack counter 94 on bus 106. A control signal on line 108 from control unit 56 ~ete~ .s which address is sent to SRAM 98 on bus 110 so that Bezier curves can either be Patent ADOBP002 2l~3383 ~ 23 ~j stored to or ~ ie~,d from the ~O or the stack. The control signal on line 108 also controls ml~ltirleY~r 111 to select either data bus 64 with a Bezier curve from input register 44 or bus 70 with a subdivided Bezier curve from subdivision unit 48.

SRAM 98 is addressed from the values output by collnters 90 and 94. SRAM 98 is further s det~ilPA with respect to Figure 4a.

When an input Bezier curve is to be inserted into the FIFO, control unit 56 indicates to multiplexer 96 via line 108 to select the address on bus 102 to present to SRAM 98 via bus 110.
Conkol unit 56 also controls mllltiplexer 111 via bus 109 to enable its output and via line 108 to select the data on bus 64 to provide to SRAM 98 via bus 68. Control unit 56 also controls FIFO-in 10 up counter 90 via bus 91 to h~clelllellt its count so that the count is the address of the next location within SRAM 98. Finally, control unit 56 co.. ~n-ls SRAM 98 via bus 109 to write the data provided on bus 68.

When a Bezier curve is to be pushed onto the stack, control unit 56 in~ teS to stack up/down cou~ter 94 via bus 95 to decl~ nt its count so that the count is the address of the new 15 top of the stack. Then control unit 56 inl1icAt~ to mllltirleYer 96 via line 108 to select the address on bus 106 to present to SRAM 98 on bus 110. Control unit 56 also indicates to mllltirleYPr 111 via bus 109 to enable its output and via line 108 to select the data on bus 70 to present to SRAM 98 via bus 68. Finally, control unit 56 co...~..An~l~ SRAM 98 via bus 109 to write the data provided on bus 68.

When a Bezier curve is to be popped from the stack, control unit 56 ~ ic; ~s to multiplexer 96 via line 108 to select the address on bus 106 to present to SRAM 98 via bus 110. Control unit 56 also in~ tes to mulLipl~xer 111 via bus 109 to disable its output so that SRAM 98 can drive bus 68. Control unit 56 also co.. ~n-ls SRAM 98 via bus 109 to read the data at the address on bus 106. Control unit 56 further in-lir~tes to stack up/down counter 94 via bus 95 to h~ lcnlent its 2s count so that its count is the address of the new top of the stack.

When a Bezier curve is to be read from the FIFO, control unit 56 controls FIFO-out up counter 92 via bus 93 to incl~,.ll~nt its count so that the count is the address of the front of the Patent ADOBP002 ~ ~ 2~3383 ~ 24 FIFO. In ~d~litit~n control unit 56 does e~ lg that it does when it pops a curve from the stack, as ,desçribed above.

When r~n~erin~ device 20 is initi~li7ed control unit 56 in~ ates~ via busses 91, 93, and 95, that FIFO-in up coullt~l 90, FIFO-out up counter 92, and stack up/down coun~r 94 must be 5 init;~li7P,d to the same address, at which point the FIFO and stack are empty.
Logic 100 is used to provide status signals to control unit 56 on status bus 67 as described below. Logic 100 l~CGiVGS the address of FIFO-in up coullter 90 via bus 102, the address of FIFO-out up cou~ ,r 92 via bus 104, and the address of stack up/down counter 94 via bus 106. If the address on bus 102 is equal to the address on bus 104, logic 100 in~ tes to control unit 56 via 0 status bus 67 that the FIFO is empty. If the address on bus 102 is equal to the address on bus 104 plus the maximum nllmher of curves pf ...;l~ed in the FIFO, modulo the number of locations in SRAM 98, then logic 100 indicates to control unit 56 via status bus 67 that the ~O is full.
(Logic 100 can thus be considered a "~O full detector.") If the address on bus 106 is equal to the address on bus 104, then logic 100 in-lir~t~e to control unit 56 via status bus 67 that the stack is 15 empty. Logic CO111I?O1IGIIlS required to output the desçribed signals are well known to those skilled in the art.

In ~lt~rn~te embo~im~nte, digital pr~cessors other than control unit 56 can be used to control the access to the FIFO and stack memory structures. For example, a micr~processor or other controller ;...ple-..r~ g an appl~pl;ate process can be col~led to SRAM 98.

Figure 4a is a dia~A~.. ~tic illustration of the structure of memory unit 46 as shown in Figure 4 for the described embo~ nt The increment operations pe~rolllled by FIFO-in up counter 90, FIFO-out up counter 92, and stack coullter 94, and the decre,l,ent operations pc.r~lllled by stack counter 94, are pelroll~ed modulo the number of locations in SRAM 98.
Incl~ l.t;.~g the largest address value provides the sm~llest address value, and decrem.onting the 25 .cm~llest address value provides the largest address value. Thus, SRAM 98 can be represented by a circular ring of loc ~ionC as shown in Figure 4a Patent ADOBP002 ~ 25 ~ 21 ~3383 SRAM 98 inr,ludes a nu~llber of locations 112, each of which can store one Bezier curve.
FIFO-out pointer 116 points to the memory location 120 specified by FIFO-out counter 92 and FIFO-in pointer 114 points to the lllelllol~ location 122 specified by ~O-in counter 90. When FIFO-in pointer 114 or FlFO-out pointer 116 are inc~ nteA~ they are moved counte.clockwise as shown by the dotted arrows 124. FIFO-out pointer 116 is inc~ ed when a Bezier curve has been read from the ~O, and FIFO-in pointer 114 is incr~,.f ~led when a Bezier curve has been written into the ~O. FIFO-in pointer 114 and FIFO-out pointer 116 initially point at the same memory location when the FIFO is empty. As the FIFO fills with curves, the ~O-in pointer moves co~u..ler~lockwise. As curves are read from the FIFO, the ~O-out pointer moves 10 coul.t~-;lockwise.

Stack pointer 118 points to a lll~,~Gl~' location 123. If stack couut~r 94 is incl~ nt~, pointer 118 is moved to the position of dotted arrow 126, intlic~ting a curve has been popped off the stack. If stack counter 94 is dec~."lonted, pointer 118 is moved to the position of dotted arrow 128, int1ir~ting a curve has been pushed onto the stack.

As shown in Figure 4a, the locations in ~lllol~ used for the FIFO are conti~llol~s with the locations in memory used for the stack. When the stack is empty, stack pointer 118 and FIFO-out pointer 116 point to the same ~ llol y loc^~ir~ Thus, reading a curve from the FIFO is equivalent to popping the stack even though the stack is empty. The llulll~r of ~le,~Gl ~ locations in SRAM
98 is chosen to be no fewer than the sum of the ",-~;"~ " llUlll~r of curves ~ .";~ in the FIFO
and the m~xi,.~ . possible number of curves on the stack. In ~ltprn~te embo-li.l~f-~ , the FIFO
and stack lll~lllOl~ structures can be impl~ ed in s~p~- ~^ SRAMs.

Figure 5 is a block diagram of suWivision unit 48 as shown in Figure 3, which subdivides a Bezier curve into two curves. Subdivision unit 48 int1ll~1es twelve a~ aging circuits 128a-1, a y carry-in circuit 130, and an x carry-in circuit 132. Averaging circuits 128a-1 are subdivided into 2s two sections, where circuits 128a-f are used to subdivide the x coordinates as an "X subdivision unit", and circuits 128g-1 are used to subdivide the y coordinates as a "Y subdivision unit." Each bus 127a-127d carries, in the described embodiment, the 15-bit x coordinate for a Bezier control point. Likewise, each bus 129a-129d carries the 15-bit y cool~ ate for a Bezier control point.
Patent ADOBP002 26 `~ 2I~33~3 .

Subdivision unit 48 is able to pe.ro~ the subdivision of a curve into two curves co~--bi~-Ato. j~lly, i.e., within one dock cycle.

Each of the averaging circuits 128a-1 adds two 15-bit cool~inales and a 1-bit carry-in signal and divides the result by two, thereby gGneldlillg another 15-bit coordinate. The addition is 5 pelrolmed by a co~ ;"~tori~l adder circuit and the division by two is pelfolllled by a bus rewiring.
These imple..~f nt~inn details are well known to those skilled in the art. The origin~l four control points of the input cubic Bezier curve are thus con~elted into seven coordinates describing two cubic Bezier curves as shown in Figure 5. Seven x coordinates from the X subdivision unit and seven y coordinates from the Y subdivision unit provide seven coordinate pairs. Thus, control 0 points (X0, Y0) (X01, Y01), (X02, Y02), (X03, Y03), (X13, Y13), (X23, Y23) and (X3, Y3) are produced from coordinate pairs (X0, Y0), (X1, Y1), (X2, Y2), and (X3, Y3). The seven produced coor~inate pairs lepl~s~nt two Bezier curves: a curve defined by control points (X0, Y0), (X01, Y01), (X02, Y02), (X03, Y03); and a curve defined by control points (X03, Y03), (X13, Y13), (X23, Y23) and (X3, Y3). Subdivision unit 48 sends the former of these curves to f~gi~tl,r 50 via bus 74 and the latter of these curves to the stack of lllGlll~ unit 46 via bus 70.

For each n-bit coordinate, the m most .ci~nifir~t bits preferably repr~sellt an uncig~ed integer and the n-m least sig~ifir^-~t bits pfef~dbly l~ple~l,l a fraction. For each cooldinate pair, the integer parts of the coordinates desigll~te a unit cell within the coordinate space, and the fractional parts of the cool~linales ~1Ccip~ t~ a location within that unit cell. The fractional part of a cool~ a~e is ~l~feldbly l~Uiled to be at least three bits.

As shown in Figure 5, a carry-in signal is input to each of the averaging circuits 128a-1.
For example, the carry-in signal for circuits 128a and 128d is bit 2 of the X3 bus, denoted X3[2]
(X[O] denotes the least .cigrlifir~nt bit of X). For others of averaging circuits 128a-1, a dirrGf~llt carry-in signal is provided. The carry-in signal for circuits 128b and 128h are grounded, i.e., 2s always zero. The y carry-in signal for circuit 1281 is dGl. . ~ nfd by carry-in circuit 130, which is dr,sc-ribGd with ~felGnce to Figure 6. The x carry-in signal for circuit 128f is genelatGd by XNOR
circuit 132, whose output (line 133) is true whenever its inputs (lines X3[0] and X0[0]) are equal.

Patent ADOBP002 The carry-in signals for the twelve averaging circuits 128a-1 are chosen to address the following re(~ .k~ . First, they help to ~!;n;~.~;7~ s~ e~ ic round-off error. Second, they assure that the path of a curve specifled by control points P3, P2, Pl, and P0 will exactly retrace the path of a curve spec-ifpd by control points P0, P1, P2, P3. Third, the carry-in signals depend s only on the coor~inale values of control points input from bus 72 (Figure 3). That is, the path (set of crosses) generated for a curve depends only on the curve and not on extraneous information.
The~Gfole, carry-in values will not vary if two id~-ntit ~I curves are subdivided, allowing ~ ble results with sepd~ate idçntiç~l curves. Fourth, the carry-in signals are simple enough that they do not slow down the co~..pul~ion Finally, the carry-in signals assure that a de~nelate subdivision lo is ill,?os~ible. Degenerate subdivision would occur if the output curve on eidher bus 70 or bus 74 were exacdy equal to the input curve on bus 72 and boundary crossings detector 52 in~ atetl that subdivision was n~ess~ry. In this case, Bezier subdivision processor 38 would subdivide dhe same curve l~dtedly, without limit, and would lLc,~,fol~ fail to C~ G its task.

In ~ltprn~t~ elllbo~ c~.;uill~ similar to that descril~ above can be used to subdivide 15 Bezier curves of degree other dhan dlree. For eY~mple~ ci~uill~ capable of subdividing quadratic Bezier curves (i.e., Bezier curves of degree two) l~uiles dlree averaging circuits 128 per axis, rather dhan six, and inputs dlree control points, rather dlan four. Similarly, cil~;uill~ capable of subdividing Bezier curves of degree four re~luil.,s ten ~ agillg circuits 128 per axis, and inputs five control points. Circuitry sirnilar to subdivision 48 as described above can be desi~ned to 20 subdivide Bezier curves of dirf~,lGl~t degrees, under dhe control of eYt~rn~l control signals.

Figure 6 is a sçhf ~ ~tn showillg the logic imple..~l.ti~ti--~ of y carry-in circuit 130 of Figure 5. The carry-in signal ~neldted by y carry-in circuit 130 is generat~d wll~ never bit 0 of bus 129a (Y0) and bit 0 of dle bus 129d (Y3) are equal; or wll~nG~,r bits 2, 1, and 0 of both bus 127a (X0) and dhe Y0 bus are zero and bits 2, 1, and 0 of both bus 127d (X3) and the Y3 bus are 25 one; or wllGn~ ~r bits 2, 1, and 0 of both the X0 bus and the Y0 bus are one and bits 2, 1, and 0 of both the X3 bus and the Y3 bus are zero. Subcil.;uil portion 134 of carry-in circuit 130 is used to cilcul~ lt the possibility of degeneldtG subdivision, which could otllelwisG occur if a Bezier curve crossed both a hs. ;~n..~l boundary and a vertical ~ulldal~ at or near their inlGlsG;lion point.

Patent ADOBP002 ~i 28 ~ 21S3~8~

Figure 7 is a block diagram ill~ .ting the boundary crossings detector 52 as shown in Figure 3, which detects whether a Bezier curve crosses 0, 1, or more than 1 cell bol~nd~riP~s of the pixel grid. In the described embo-limPnt, boundary crossings detector 52 detects the crossings of cell bo~m~l~ries of the line se~mP-nt col nP~ g the two en.l~int~ of the current Bezier curve. For a s Bezier curve defined by control points P0, P1, P2 and P3, this would be the straight line segment col-ne~;ling points P0 and P3. Boundary crossings detector 52 detects the crossings of vertical (x-cooldinate) and h~ nnt~l (y-coo dinate) bo~ln-lAriPs sep~udt~ly and then co...hinf s the results.

Boundary crossings ~etector 52 pl~,fe,dbly incllldes an x-axis crossings ~etP~tor 136a, a y-axis crossings detector 136b, and combining logic block 138. Bus 72 provides the following 10 inputs: Ax and Bx, the integer portions of x coo~inates X0 and X3, respectively, to x-axis crossings detector 136a; and Ay and By~ the integer portions of y coo~illales Y0 and Y3, e.~ ely, to y-axis crossings det~lol 136b. Crossings dete~lol~ 136a and 136b are desçri~
in greater detail with reference to Figure 7a. Colllbh~ g logic block 138 leceives the inputs from the two crossings d~,t~lo.s 136a and 136b on busses 141a and 141b, res~ iv-ely, and coll~
15 the inputs to an output sent to control unit 56 via bus 78 desçribing how many crossings were made by the line segmP.nt cQl~n~ g the end~oillt~ of the current Bezier curve. The direction of the cross (if any) is output on bus 80 to cross form~tter 54. Colllbining logic block 138 is dc~ in greater detail with l.,f.,.~ce to Figure 7f.

Other mPtholl~ to detect crossings of cell bo~ lr-- ;f,S can also be used. For example, in an 20 AlbPrnAtp embo~limpnt) bound&y cç~ssings detector 52 detects the ll~ull~r of bound~rip~s crossed by the ~.ecc~vise linear path conn~~ g the control points of the Bezier curve, in an order from P0 to P1 to P2 to P3. This ~lt~PrnAte embo~limpnt can be implPmP-nted by detecting the number of bo~n~l~ries crossed by the line se~,lllelll from P0 to P3, as before, and also ~iryi~g that at least two out of three of the line seg....-nl~i from P0 to Pl, from P1 to P2, and from P2 to P3 cross no 25 bound~riP,s. If the line seg...~ ~.t from P0 to P3 crosses mllltiple bo~ln~lAries or if more than one of the line segments from P0 to P1, P1 to P2, and P2 to P3 cross at least one boundary, then boundary crossings detector 52 in~lir~s to control unit 56 that the Bezier curve crosses multiple boundaries, so further subdivision is nece~s~y. Otherwise, boundary crossings detector 52 Patent ADOBP002 ~: 29 `~ 21~3383 detects the number of bolln~ries crossed by the Bezier cune as before, i.e., by detecting the number of bonn~ies crossed by the line seg,.--~nt conl~f~l;ng the endpoints of the Bezier cune.
This emho lim~nt is more eA~nsi~., to i~.ple-~f-nt than the embo~1im~nt shown in Figure 7, but it is gu~ultced to find all of a cune's boundary crossings (at the Ç~ ~ of so,..~t;,nrs subdividing a 5 cune which has only one crossing).

Figure 7a is a block diagram ill~ ting a generic single-axis crossings detector 136.
Single-axis crossings det~,clor 136 is used to ;--.l,le..-f.nt both x-axis crossings detector 136a and y-axis crossings ~et~;l~r 136b as shown in Figure 7. Single-axis crossings ~Ptector 136 includes a ,l,ber of input logic Uocks 140a-1 and a llwllb~,r of co.~hi~in~ logic blocks 142a-k.

o Input A 146 is the m-bit integer portion of a coordinate, for example, the X0 coordinate, and input B 148 is the m-bit integer portion of another coordinate, for eY~mrl~., the X3 cooldinate.
In the described emh~lim~nt the integer portion of a coordinate is twelve bits, so buses 146 and 148 are twelve-bit buses, and there are twelve input blocks 140a-1.

To detect boundary crossings in one axis, for ç~ ,le, the x axis, a bitwise co...pz ;.con of 5 input A 146 and input B 148 is ~lÇolllled by input logic blocks 140a-1. For each bit position, the logic block 140 for that bit position outputs a symbol describing the result of the COIl~iSOl for that bit position. "E" in~ic~tes that A is equal to B for that bit position; "H" in~ic~tes that A is greater than B for that bit position; and "M" indicates that A is less than B fo r that bit position. A
logic desclil)lion of logic blocks 140a-1 is d~çribed gfi~ ally with respect to Figure 7d.

The outputs of logic blocks 140a-1 are then co.. hi~-r,d by logic blocks 142a-k. Each of the logic blocks 142a-k receives two symbols, on a most ci~nifi~ nt input and a least .cig~ifil~nt input.
Each of the logic blocks 142a-k outputs a symbol according to Table 156 of Figure 7b. In Table 156, the possibilities for the most significant input are listed in the leftmost column and the possibilities for the least ci~ifi--qrlt input are listed in the top row. The symbol output by a logic 2s block 142 is shown at the i~ e~ m of the specific row and spe~ific column of the inputs to logic block 142. A generic logic de~li~tion of logic blocks 142a-k is described with respect to Figure 7e.

Patent ADOBP002 21S3~83 The output of each of the logic blocks 142a-k desçribes a span of contiguous bit positions.
For example, the output of logic block 142b describes bit positions 11 to 9, and the output of logic block 142j describes bit positions 5 to 0. A symbol "E" in(3ic~tes that, within the span, A and B
are equal; "G" in-lir~tes that, within the span, A is one unit greater than B; "L" in~lic~tes that, 5 within the span, A is one unit less than B; "g" in~ic~s that, within the span, each bit of A is zero and each bit of B is one; "l" intlir~tes that, within the span, each bit of A is one and each bit of B is zero; and "N" inrlir~t~s that none of the above con~itir~ is applir~b~

In the describe~ embo l;..~r-~l, the symbols of Table 156 are lep~ 1 by five-bit codes, as shown in Table 157 of Figure 7c. For each symbol shown in the leftmost column of Table 157, lO the five binary digits to the right of the symbol show the five-bit code for that symbol. The five symbols shown in the top row of Table 157 identify the five wires used to carry the five-bit code, as des~rihed in greater detail with respect to Figures 7d and 7e.

In an ~ltern~te embo~limpnt~ logic blocks 142a-k can couubine the outputs of logic blocks 140a-l using any tree sllu-;lul~ (i.e., any tree of logic blocks, of which the ~;ull~ ly disclosed tree 15 of logic blocks is one example), provided that each of logic blocks 142a-k covers a span of contiguous bit positions. Further, gates 158 and 159 can be o~ ed from any of logic blocks 142a-k whose span inrlu~les the most si~lifir~nt bit pOSi~ll (bit 11).

In an ~ltern~te embo~im~nt~ any of logic blocks 142aj can be merged with the logic block which ~cci~s its output, to form a three-input block, and the logic within this three-input logic 20 block can be o~tuu~cd using mrthorls well-known to one skilled in the art. Similarly, a two-input logic block and a three-input logic block can be merged to form a four-input logic block, and so on.

In an ~lt~rn~te c~ubo~ r ~ the logic shown in Figure 7 can be repl^^ed by a sul,tl~;lor, which COlu~ulcS the dirreçcl~ce A - B, and ~ ition~l logic to detect whether the output of the 25 subtl~ctor is zero, one, minus one, or so...~-~l.;ng else. This embo limP.nt is conceptually simpler than the embo~lim~nt shown in Figure 7 but l~uil~s more logic to implement.

Patent ADOBP002 "! 31 ~' 2 1 5 3 3 8 3 Figure 7d is a sch~ ;c diagram showing the logic imrle."F n~ n of one of logic blocks 140a-1 shown in Figure 7a, intlir~^ted generally by 140. A logic block 140 inr,ludes three NAND
gates 150 and three in~.le.~ 152. The l-bit inputs A and B are received by logic block 140 and are co~ d to produce a five-bit code on the wires G, l, E, g, and L which form bus 137 (see 5 Figure 7c).

Figure 7e is a srh~ ic diagram showing the logic impl~ tion of one of logic blocks 142a-k shown in Figure 7a, in~ic~ted generally by 142. Most igi^ific. nt bus 149 and least ~ig~lifir~nt bus 151 each carry a 5-bit code l~ese ~ g a symbol as shown in Figures 7b and 7c.
Each of logic blocks 142 comhinPs two five-bit code inputs into a single 5-bit code output. For o logic blocks 142a, 142b, 142i, and 142k, the "g" and "1" wires of the output codes are ignored.
Thus, in an ~~ d embo limPnt, gates 158 and 159 can be omittP"~

~ Pf~Prring to the output of logic block 142k, if the "E" bit of the five-bit code is asserted, then A = B; if the "G" bit is ~selted, then A = B + l; if the "L" bit is asserted, then A + 1 = B; and otherwise, none of these conditions is true (the "N" symbol).

Figure 7f is a sçh-Pm^-tir diagram showing the logic impl~P.~ t~l;on of combining logic block 138. Coll-bi~ g logic block 138 combines the symbols received from x-axis crossings detector 136a via bus 141a and y-axis crossings d~lr~tor 136b via bus 141b to produce a two-bit signal on output bus 78 desc~ibing how many crosses were made by the line segment colm~ct;l~g the en~oillts of the Bezier curve. Line 153 is asserted if the line se~ c~nnf~ the endpoints 20 of the Bezier curve crosses one boundary. Line 155 is asserted if this line segn~nt crosses zero bo~n(:l~ries. If neither line 153 nor line 155 are asserted, then this line se} ...F ~-t crosses multiple boundaries. XG line 166, YG line 170, and XE line 175 fonn bus 80 which is coupled to the cross form ~tPr 54 (desAri~ with le,f~,nce to Figure 8).

Figure 8 is a sçhf ~ ic diagra-m-- illu~lrdling cross fo.... ~t~" 54 âs shown in Figure 3, which 2s provides a cross spec--ifir^~tion inr,lurlinp an X cooldil,ate, a Y coordinate, and a direction. Cross f~ lf~,~ s4 inrl~ldes X-coordinate mllltipl^Y~Pr 160, Y-coordinate r.^lllti~lPYer 162, and direction multiplexer 164. Bus 80 of Figure 3 inr.lude~ line 166 (XG), line 170 (YG), and line 175 (XE) of Patent ADOBP002 21~33,~3 - ~- 32 Figure 8. Bus 82 of Figure 3 co..~r~ ;~ x cool~ a~ bus 168, y coGnlinat~ bus 172, and direction bus 174. Direction bus 174 CG...p. ;~es lines 175 and 176. Bus 72 incllldes coo~inates X0, Y0, Xl, Yl, X2, Y2, X3, and Y3 of the current Bezier curve. Cross fo. ..~z~ r 54 uses only Ax, the integer portion of X0; Bx, the integer portion of X3; Ay, the integer portion of Y0; and By, the s integer portion of Y3.

X-coordinate multiplexer 160 has two data inputs, Ax and Bx, which are the integer portions of endpoint coordinates X0 and X3 of the Bezier curve. X-coo,.]inale multiplexer 160 selects the lesser of co~.lill~t~,s Ax and Bx as controlled by XG line 166, which is the "G" output of logic block 142k of the x-axis crossings detector 136a as shown in Figure 7a. The lesser lo coordinate is output as the X cOOl&,dt~ of the cross on bus 168.

Y-coordinate mllltipl~YIo,r 162 has two data inputs, Ay and By, which are the integer portions of endpo,L.t coordinates Y0 and Y3 of the Bezier curve. Y-coordinate multiplexer 160 selects the lesser of coordinates Ay and By as controlled by YG line 170, which is the "G" output of logic block 142k of the y-axis cl~ossillgs ~etector 136b. The lesser coor~ al~ is output as the Y
5 coo~dh~le of the cross on bus 172.

Direction mltltirleYer 164 has two data inputs, which are XG line 166 and YG line 170.
Directional multiplexer 164 selects XG for horizontal crosses and YG for vertical crosses as controlled by XE signal on line 175, which is the "E" output of logic block 142k of the x-axis crossing detector 136a. Bus 174, which inrllldes line 175 as the most .cigJtifi-~nt bit and line 176 20 as the least ~igt~ifi~z~nt bit, sperifies a &~lion: north (10), south (11), east (00), or west (01).

Figure 9 is a flow diagra_ 200 illu~lating the method imI~le....~.n~ed by Bezier subdivision processor 38 to find the crosses of a Bezier curve. The process starts at 202, and, in a step 204, the stack and the FIFO are cleared v~l~n~ ~. the pl~essor 38 is reset.

Two p.ocesses are then inifi~ed ~im~ neuusly. The first of these plucesses is desc-ribed in steps 206 and 210, and the second process is described in steps 212, 214, 216, 222, and 226.
The two ~lucesses reflect the operation of the Bezier processor 38, which accepts and stores input Bezier curves while subdividing curves and fo....~ crosses.
Patent ADOBP002 33 J 21~3383 In the first process, processor 38 ~ete ...;.les in step 206 if an input Bezier curve is available and the FIFO is not full. If so, processor 38 stores the input Bezier curve in the FIFO in step 210 and then returns to step 206. If no input curve is available, or if the FIFO is full, then step 206 is repeated until both an input curve is available and the FIFO is not full.

In the second (concurrent or parallel) process, Bezier subdivision processor 38 ~ .s if the stack and the ~O are both empty in step 212. If so, a new Bezier curve needs to be input in the first procoss, and step 212 is lGpeæted until the stack and FIFO are not both empty. In step 214, processor 38 ~llie~es a Bezier curve from memory unit 46 and makes it the current curve. If the stack is not empty in step 214, the curve is ~tlieved from the top of the stack; if the stack is empty, then the curve is retrieved from the front of the FIFO. In next step 216, plocessor 38 d~ te. ..~ s how many bound~ri~os are crossed by the current curve. If there are zero croscings~ the current curve is discar~ed, and the process returns back to step 212 to retrieve another curve. If there is one crossing, step 226 is executed. If there is more than one crossing, step 224 is ex~cut~

In step 2æ, the current curve is subdivided into two curves. The first of these curves becomes the current curve, and the second curve is pushed onto the stack. The process then returns back to step 216, where it is dete ...i~.Pd how many crossings are made by the new current curve.

In step 226, processor 38 gen~tes a cross coll.,sl>onding to the current curve. Th 20 cDnt curve is then disc~ led, and control returns to step 212 to ~tl.ic~, another curve.

In the desc-~ibed eml~o l;,.~l.t. a cross inc~ es only the x and y coor~inates of the cell below or to the left of the crossed boundary and a direction (north, south, east, or west), i.e., the cross is speçified in the resolution of the pixel grid. Further subdivision of a curve after the curve crosses only one boundary is therefore not advantageous. However, in ~lte~n~te embodi...~
25 subdivision of a curve beyond the general resolution of the pixel grid might be desired. This could be useful, for example, to identify with greater precision where the current curve crossed a boundary. If such further sulJdivision were desired, a step can be impl~.. ~.-ted after one crossing Patent ADOBP002 . ~
- ~ 34 ~ 21S3383 is found in step 216, wLc~n the plùcessor 38 d~,te~ P,s if lmlls~lql suWivision is neede~ If so, the process can co~ ue to step 222 and subdivide the current curve. If not, then the process can continlle to step 226 and output a cross.

As ~ cllssed with ,-,fe.e.lce to Figure 5, the imple~f nt~l;o~ of subdivision unit 48 within 5 processor 38 assures that degel~.ate subdivision of Bezier curves can never occur. However, other embc~ pnt~ may not use the particular imrlp~".~ tion clesçribed for ple~e~ g degen~.~te suWvision. In such a case, steps can be implemPnte~ after step 216 if more than one crossillg is found. Processor 38 can dete ...i~-e if ~lmlsuLq-l terminqtion of the subdivision process is needecl, i.e., the current curve is a deeel~ e curve. If so, the subdivision procedure is terminq-tPd, and 0 crosses ccllespollding to the current curve are geneldted by any e~cpe~liPnt mPthod The curve is then discarded and the process returns to step 212 to retrieve another curve. If llnll~uql ~e. ~ qtion is not needed the process can continue to step 222 to subdivide the curve.

Figure 10a is a diagl;~ tic illustr~qtiol~ 230 of the outline of a ch~a~ler that has been lld,l~ru,l"cd to device coordinate space, i.e., the originql outline des~ liplion of the chz.aclel has 15 been scaled to the output pixel resolution and hinted. Grid 233 defines the resolution of the device space. Character outline 232 inrhldes a set of Bezier curves, each s~ec;r.ed by its control points.
In the example of Figure 10a, Bezier curve 234 in one of the set of curves cG...l.. ;.cing the outline of a ch~t~r.

Figure 10b is a diag,~ ;c illustration of Bezier curve 234 p,ucæcced by processor 38.
20 Grid 233 in~ les hc.. ;~ol-tql and vertical lines which are spaced from each other to form a desired resolution. This resolution typically ccll~,sponds to the resolution of pixels to be displayed by output device 24. The grid lines in the desçri~l embo~lim~ont coll~ olld to pixel mitllin~s, i.e., the grid lines pass through the centers of pixels. Cells 238 are formed by the horizontal and vertical grid lines. Each cell has bonn~l~ries 240 which are portions of the ho. ;~.onl~l and vertical 2s lines of the grid 233.

Bezier curve 234, a cubic Bezier curve, is ~;rP-d by four control points P0, Pl, P2, and P3 . Other types of Bezier curves can be specifiP,d by more or fewer than four control points.

Patent ADOBP002 21~3383 Each control point has a holi~ontal (X) coordinate and a vertical (Y) coordinate. If curve 234 crosses more than one boundary 240, it is subdivided accordillg to the method of the present invention. A method used in the present invention for dete~ ing how many boundaries are crossed by curve 234;nC1UdeSdete..-;n;n~ how many boun~l~rip~s are crossed by the straight line 5 segmPnt col-n~cl;..g the endpoints of the curve. The endpoints of curve 234 are points P0 and P3;
straight line segment 242 connects these points. Line segment 242 crosses more than one boundary, so curve 234iS subdivided, creating the following points. Point P01 is the average of P0 and Pl; P12iS the average of Pl and P2;P23iS the average of P2 and P3;PO2iS the average of P01 and P12; P13 iS the average of P12 and P23; and P03 iS the average of P02 and P13.
10 Subdivided curve 246, having control points P03,P13,P23, and P3~iS pushed onto the stack, and subdivided curve 244, having control points P0, P01,P02, and P03, is e~rninPd next.

Line Sf.~,lllf-nt 248 connects the endpoints P0 and P03 of curve 244. Line Se~llle-lt248 crosses more than one boundary, so curve 244iS subdivided .$;m;1~r1Y to the subdivision of curve 234. This produces curve 252, which is pushed onto the stack, and curve 2S0, which is PY~rnined 5 next. (The points c~lcul~te~ by this subdivision are not ill~sl.,~t~l in Figure 10b, except for point 256, which is the endl)oint shared by curves 250 and 252.) Line se~;Jll~nt 254 connects the endpoints P0 and 256 of curve 250 and crosses exactly one bo~ dal~ (h~ .on~l boundary 255).
A cross is ~neraled for this curve, having the integer portion of the x coGldindte of point P0 as it x coordinate, the integer portion of the y coordinate of P0 as its y coordillat~, and a direction of "north," since curve 250 crosses the hc.. ;~on~l boundary 255 in the direction from point P0 to point 256. The res~lting cross is illustrated sçhf!~llA~ lly as cross 260.

Once cross 260 has been output, the top curve on the stack, i.e., curve 252,iS popped from the stack. Curve 252iS de~ ;n~d to cross exactly one bound~, so cross 262iSgene1.~ted.
The 1GIII~ g portions of Bezier curve 234 are analyzed and subdivided in a similar lll~n~er to 2sproduce the rern~ining crosses 264 shown in Figure 10b. The directions of crosses 260,262, and 264 are int~ sÇhf-~ lly by arrows 251.

Figure 10c is a diagl, ------~ic l~ ~S~ on265 of the ch&acl~r outline 232 on grid 233 having filled pixels. A set of crosses 267 has been utilized by miclucollll~ller30 to fill in specific Patent ADOBP002 J 36 ~ 21~33~3 pixels 266 which are col~t~ined within the area bounded by the crosses. Several methods are well-known for filling in pixels according to crosses, some of which are described in U.S. Patent 5,301,267 and U.S. Patent 5,200,740. Figure 10c illusl,ates a "center fill" method, which fills in pixels whose centers fall within the area bounded by crosses 267. The result is a bit map 268 of a s character in the resolution of the output device 24.

Figure 11 is a flow diagram illu~llating the generalized process 280 of the present invention. The process begins at 282. In step 283, a Bezier curve is .ece;vGd. Process 276 is then e-YPcute~l, in which the Bezier curve is subdivided to a desired resolution level and a set of crosses is developed. Process 276 includes steps 284, 286, 288, 290, 292, 294, 296, 298, 300, 10 and 302, which are desc~ l below.

In step 284, a variable L is initi~li7~d to zero. In step 286, the process checks if the Bezier curve crosses multiple bc~n-1~ies of the cells of a grid. If there are mllltirl.o. croscingc, then step 288 is çY~-cuted, in which the Bezier curve is subdivided. The curve is subdivided into two pieces:
a first level L piece and a second level L piece. One way to subdivide a Bezier curve is desçribed above with respect to Figure 5. Once the curve has been subdivided, step 290 is eX~cl1tç(l. where the first level L piece is picked. That is, the first level L piece of the curve will be ex~mined while the second level L piece is tenlpof~ily put aside. For eY~mrle~ the second level L piece can be stored on a stack as described with lefelellce to melllGl~ unit 46 in Figure 3. The process then continues to step 292, where the variable L is illc.~ ted The process then returns to step 286, 20 where the picked L piece is e~mined to d~ ~ ;nr, if it crosses mnltirlP bo~lnd~ s.

Once it is d~,te....;n~d that an ey~min~ Bezier curve does not cross mllltirlç boun~l~ries in step 286, step 294 is executed, in which it is det~ ...ined whether the curve crosses zero bollnd~ries. If the curve crosses zero bollnd~ries, the process continues to step 298 (described below). If the curve does not cross zero bollnd~ries> it must cross one boundary. Step 296 is 2s e~ecuted if one boundary is crossed, whel~ the cooldinates of the cross for the one crossing are stored, for exarnple, in IllGlllOl~ such as RAM. In next step 298, the value of L is ch~ d If L is not equal to zero, step 300 is executed, in which the second level L piece put aside previously is Patent ADOBP002 37 ~ 2153383 retrieved. In next step 302, the variable L is dec~ ted and the process returns to step 286 to eY~minf, the second level L piece for mllltipl~f boundary croccing~c~

If L is equal to zero in step 298, then step 304 is e ~ecute I in which the process d~,t~ .ni1.f~c if all available curves have been processe~l If not, the process returns to step 283 and l~,cei~,s the 5 next Bezier curve. If all curves have been processed in step 304, step 306 is executed, in which the set of stored crosses is utilized to control an output device. In an ~ltern ~tf~ embo-limPIlt, each cross created in step 296 can be utilized when it is created to control an output device in real time, without having to be stored; step 306 can then be omittf,d The process is then c~nlrlete at 308.

The crosses can be used to control an output device in a nm~bel of ways. One way is to 0 use the crosses to generate a bit map, which is then used to create a pixel map which is then displayed on a raster device such as a laser printer. This is described in greater detail with reference to Figures 10a-c. The crosses can also be used to specify a path in n .li".f ncions for a variety of applir~ti- n.c While this invention has been described in terms of several pl~f~ d embo-limf-llt.c, it is 15 c~..t "pl ~ that alterations, lll~l;rlr~lionc and pf .",.~ln~ n~ thereof will become appa~ent to those skilled in the art upon a reading of the specifi~tion and study of the drawings. Furthr~mQre~
certain te~ inology has been used for the pul~oses of descl;ptive clarity, and not to limit the present invention. It is theltfole intrn~ed that the following appended claims include all such alterations, mo-lifirations and pe ..l~tions as fall within the true spirit and scope of the present invention.

Patent ADOBP002

Claims (59)

1. A system for generating a multi-dimensional image from an image description comprising:

a digital processor which receives an image description describing a multi-dimensional image and produces image rendering information from said image description, said image rendering information being associated with Bezier curve information describing at least one Bezier curve of said image;

a rendering device coupled to said digital processor to develop image information, said rendering device being capable of performing at least one subdivision on said Bezier curve of said image to produce a plurality of subdivided Bezier curves until all subdivided Bezier curves are at about a desired resolution level, said rendering device developing said image information from said image rendering information, said associated Bezier curve information and said subdivided Bezier curves; and an output device having said desired resolution level, said output device being coupled to said rendering g device to create said multi-dimensional image derived from said image information.

2. A system as recited in claim 1 wherein said multi-dimensional image is 2-dimensional.

3. A system as recited in claim 2 wherein said image rendering information includes a reference to information specified in an outline format.

4. A system as recited in claim 3 wherein said multi-dimensional image is an image including at least one character, and wherein said output device is one of a 2-dimensional display, a printer, and a plotter.

5. A system as recited in claim 1 wherein said rendering device includes a Bezier subdivision processor for subdividing said Bezier curves and producing zero or more crosses for each of said Bezier curves, said crosses being used to develop said image information.

6. A system as recited in claim 5 wherein said rendering device includes a microcontroller for providing said Bezier curves to said Bezier subdivision processor.

7. A system as recited in claim 1 wherein said digital processor creates a pixel map using said image information and inputs said pixel map to said output device, said output device creating said desired image from said pixel map.

8. A rendering device for converting input information to a bit map comprising:

a Bezier subdivision processor which receives Bezier curve information describing a Bezier curve of an image, said Bezier subdivision processor performing at least one subdivision on said Bezier curve if said Bezier curve is greater than a desired resolution of a bit map to produce subdivided Bezier curves until all subdivided Bezier curves are at about the resolution of said bit map, said Bezier subdivision processor producing cross information from each of said Bezier curves which makes one crossing of a grid having said resolution; and a digital processor which receives said cross information and produces a bit map of said image from said cross information.

9. A rendering device as recited in claim 8 wherein said Bezier subdivision processor includes a memory unit for storing subdivided Bezier curves.

10. A rendering device as recited in claim 9 wherein said memory unit includes a stack memory structure for storing said subdivided Bezier curves.

11. A rendering device as recited in claim 10 wherein said memory unit includes a FIFO
memory structure for storing received Bezier curves.

12. A rendering device as recited in claim 9 wherein said Bezier subdivision processor includes a boundary crossings detector for determining the number of crossings of said grid made by said Bezier curve.

13. A rendering device as recited in claim 12 wherein said Bezier subdivision processor includes a cross formatter for providing a cross specification when a Bezier curve is found to cross said grid only once.

14. A rendering device as recited in claim 8 wherein said Bezier subdivision processor includes a control unit operative to control the operation of said Bezier subdivision processor to receive said Bezier curve information, perform said subdivision, and provide said cross information.

15. A rendering device as recited in claim 8 wherein said Bezier subdivision processor includes an input register operative to store said Bezier curve information until sufficient Bezier curve information to describe said Bezier curve has been received.

16. A Bezier subdivision processor comprising:
a memory unit for storing at least one Bezier curve;

a boundary crossings detector deriving said at least one Bezier curve from said memory unit to detect crossings of said Bezier curve with a grid having cells of a desired resolution, said grid defining the boundaries of said cells; and a Bezier subdivision unit producing a plurality of subdivided Bezier curves for each Bezier curve in said memory unit that has a plurality of crossings of cell boundaries and storing at least some of said plurality of subdivided Bezier curves in said memory unit.

17. A Bezier subdivision processor as recited in claim 16 further comprising:

a cross formatter for producing cross information for each Bezier curve having a single crossing of a cell boundary; and a register having inputs coupled to said Bezier subdivision unit and said memory unit, and having outputs coupled to said Bezier subdivision unit, said boundary crossings detector, and said cross formatter.

18. A Bezier subdivision processor as recited in claim 17 wherein said memory unit comprises a stack, and wherein said subdivided Bezier curves are pushed onto said stack and popped from said stack such that said Bezier subdivision unit recursively subdivides said Bezier curves on said stack until said stack is empty.

19. A Bezier subdivision processor as recited in claim 18 further comprising a control unit coupled to said input register, said memory unit, and said register.

20. A Bezier subdivision processor as recited in claim 18 wherein said memory unit further includes a FIFO for storing received Bezier curves.

21. A Bezier subdivision processor as recited in claim 20 wherein said FIFO and said stack are contiguous in said memory unit such that when said stack is empty and a curve is popped from said stack, a curve is read from said FIFO.

22. A Bezier subdivision processor as recited in claim 20 wherein said memory unit includes:
read/write memory;
a FIFO-in up counter coupled to said read/write memory; and a stack up/down counter coupled to said read/write memory.

23. A Bezier subdivision processor as recited in claim 22 wherein said memory unit further comprises a FIFO full output.

24. A Bezier subdivision processor as recited in claim 23 wherein said memory unit further comprises:
a FIFO-out up counter; and logic having inputs coupled to said FIFO-in up counter, said FIFO-out up counter, and said stack up/down counter, said logic having said FIFO full output, a FIFO empty output, and a stack empty output.

25. A Bezier subdivision processor as recited in claim 18 wherein said crossingsdetector includes combinatorial logic for determining whether a Bezier curve makes at least one crossing of cell boundaries.

26. A Bezier subdivision processor as recited in claim 18 wherein said crossingsdetector detects whether zero, one, or a plurality of said boundaries are crossed by a line segment connecting the endpoints of said Bezier curve.

27. A Bezier subdivision processor as recited in claim 18 wherein said Bezier curve includes a plurality of control points, and wherein said crossings detector detects whether zero, one, or a plurality of said boundaries are crossed by line segments connecting said control points.

28. A Bezier subdivision processor as recited in claim 27 wherein said control points have an order, and wherein said crossings detector detects whether zero, one, or a plurality of said boundaries are crossed by the piecewise linear path connecting said plurality of control points in said order.

29. A Bezier subdivision processor as recited in claim 26 wherein said crossingsdetector includes a horizontal comparing portion for comparing horizontal coordinates of said endpoints of said Bezier curve and a vertical comparing portion for comparing the vertical coordinates of said endpoints to determine whether said Bezier curve crosses zero, one, or a plurality of said boundaries.

30. A Bezier subdivision processor as recited in claim 26 wherein said crossingsdetector includes a tree of logic blocks which processes the coordinates of a first endpoint of said Bezier curve and corresponding coordinates of a second endpoint of said Bezier curve to determine whether said line segment crosses zero, one, or a plurality of said boundaries.

31. A Bezier subdivision processor as recited in claim 18 wherein said Bezier subdivision unit includes a single-axis subdivision unit for each coordinate axis.

32. A Bezier subdivision processor as recited in claim 31 wherein each of said single-axis subdivision units includes a plurality of averagers combinatorially connected to produce coordinates of the control points of a subdivided Bezier curve in said coordinate axis.

33. A Bezier subdivision processor as recited in claim 32 wherein said Bezier subdivision unit further includes means for generating carry-in functions for said averagers to preclude the possibility of degenerate subdivision.

34. A Bezier subdivision processor as recited in claim 18 wherein said cross formatter includes a plurality of multiplexers combined to receive information from said crossings detector and to generate coordinates included in said cross information.

35. A method for determining crossings of Bezier curves with a grid, the method comprising:

receiving a Bezier curve;

sequentially subdividing said Bezier curve into a plurality of subdivided Bezier curves, if required, until each received or subdivided Bezier curve crosses less than a plurality of times with cell boundaries of a grid of a desired resolution; and developing a cross associated with each of said received or subdivided Bezier curves which crosses one of said boundaries, said cross including Cartesian coordinates and direction.

36. A method as recited in claim 35 wherein said step of sequentially subdividing is a recursive subdivision step.

37. A method as recited in claim 35 wherein said step of sequentially subdividing said Bezier curve includes subdividing an examined Bezier curve into two pieces and picking the first of said two pieces as a next Bezier curve to examine.

38. A method as recited in claim 37 wherein said step of sequentially subdividing said Bezier curve includes picking said second piece of said two pieces to examine after said picked first piece has been subdivided and developed into said crosses.

39. A method as recited in claim 37 wherein said step of sequentially subdividing said Bezier curve includes ignoring curves which do not cross any of said boundaries.

40. A method as recited in claim 37 wherein said step of sequentially subdividing said Bezier curve until each Bezier curve crosses less than a plurality of times includes detecting whether zero, one, or a plurality of said boundaries are crossed by a line segment connecting the endpoints of said Bezier curve.

41. A method as recited in claim 37 wherein said Bezier curves include control points described by a number of bits, and wherein said step of sequentially subdividing said Bezier curve until each Bezier curve crosses less than a plurality of times includes comparing corresponding bits of two of said control points to produce a resulting string of bits, wherein adjacent bits of said resulting string of bits are compared to determine if said Bezier curve crosses less than a plurality of times.

42. A method as recited in claim 36 further comprising a step of utilizing said crosses to control an output device.

43. A method as recited in claim 36 wherein said step of receiving a Bezier curve includes receiving a Bezier curve of degree one and converting said Bezier curve of degree one to a Bezier curve of higher degree.

44. A method as recited in claim 36 wherein said step of receiving a Bezier curve includes storing said received Bezier curve in a FIFO memory structure until it is subdivided in said subdividing step.

45. A method as recited in claim 36 wherein said step of sequentially subdividing includes storing some of said subdivided curves on said stack to be retrieved and subdivided at a later time.

46. A method as recited in claim 36 wherein said step of developing the Cartesian coordinates and direction of said cross includes taking minimum coordinate values of endpoints in each coordinate axis of said Bezier curve associated with said cross.

47. A crossings detector for detecting whether a first coordinate differs from a second coordinate by zero, one, or more than one, comprising:
a first coordinate ate input represented by a first m-bit binary integer;
a second coordinate input represented by a second m-bit binary integer;

first logic having, as inputs, said first integer and said second integer, and operative to make a bitwise comparison on of corresponding bit positions of said first integer and said second integer to produce a sequence of m symbols describing the result of said comparison for each bit position; and second logic having, as inputs, said sequence of m symbols, and operative to output a single output symbol representing whether said first coordinate differs from said second coordinate by zero, one, or more than one.

48. A crossings detector as recited in claim 47 further comprising output logic having, as an input, said single output symbol, and operative to output crossing information.

49. A crossings detector as recited in claim 47 wherein said second logic comprises a tree of combining logic blocks wherein each of said combining logic blocks combines at least two input symbols, representing adjacent spans of said bit positions, into an output symbol, representing a single span of said bit positions.

50. A crossings detector as recited in claim 49 wherein said output symbol of each of said logic blocks represents a span of contiguous bit positions, and wherein an output of said logic block is: a symbol "E" when said span of said first coordinate is equal to said span of said second coordinate; a symbol "G" when said span of said first coordinate is one greater than said span of said second coordinate; a symbol "L" when said span of said first coordinate is one less than said span of said second coordinate; a symbol "g" when each bit of said span of said first coordinate is zero and each bit of said span of said second coordinate is one; a symbol "l" when each bit of said span of said first coordinate is one and each bit of said span of said second coordinate is one; and "N" when none of the above conditions is applicable.

51. A crossings detector as recited in claim 50 wherein at least one of said combining logic blocks combines a more significant input symbol and a less significant input symbol as indicated in the following table, wherein the possible values of said more significant input symbol are listed in the leftmost column of said table and the possible values of said less significant input symbol are listed in the top row of said table, and wherein a symbol "H" indicates that a bit of said first coordinate is greater than a bit of said second coordinate for one of said bit positions, and a symbol "M" indicates that a bit of said first coordinate is less than a bit of said second coordinate for one of said bit positions.

52. A crossings detector as recited in claim 51 wherein said combining logic block is a three-input logic block which combines two input symbols as indicated in said table into an intermediate symbol, and combines said intermediate symbol with a third input symbol as indicated in said table, wherein said three-input logic block includes logic optimized for combining said three symbols.

53. A memory construct comprising:
a stack which operates as a LIFO memory; and a queue which operates as a FIFO memory and which is associated with said stack such that when said stack is empty, data is read from said queue.

54. A memory construct as recited in claim 53 further comprising:

memory control to write data to said stack and to read data from said stack, and to write data to said queue, where data is read from said queue only when said stack is empty of data.

55. A memory construct as recited in claim 54 wherein said memory control includes:

a stack up/down counter to provide a stack pointer into said stack; and a FIFO-in up counter to provide a FIFO-in pointer into said queue.

56. A memory construct as recited in claim 55 wherein said stack and said queue are contiguous, and wherein said stack pointer points to the front of said queue when said stack is empty.

57. A memory construct as recited in claim 56 wherein said memory control further includes a FIFO full detector which prevents further writes to said queue when said queue is full.

58. A memory construct as recited in claim 57 wherein said FIFO full detector includes a FIFO-out up counter to provide a FIFO-out pointer which points to said front of said queue, such that said FIFO full detector can determine said queue is full when said FIFO-in pointer is separated from said FIFO-out pointer by a predetermined amount, and wherein said memory control determines that said stack is empty when said stack pointer is equal to said FIFO-out pointer.

59. A memory construct as recited in claim 54 wherein said stack and said queue comprise a plurality of data storage locations in read/write memory, wherein said memory control includes a digital processor which implements a process which operates said read/write memory to provide said stack and said queue.