CA2158324A1 - Atm queuing and scheduling apparatus - Google Patents
Atm queuing and scheduling apparatusInfo
- Publication number
- CA2158324A1 CA2158324A1 CA002158324A CA2158324A CA2158324A1 CA 2158324 A1 CA2158324 A1 CA 2158324A1 CA 002158324 A CA002158324 A CA 002158324A CA 2158324 A CA2158324 A CA 2158324A CA 2158324 A1 CA2158324 A1 CA 2158324A1
- Authority
- CA
- Canada
- Prior art keywords
- calendar
- cell
- atm
- cells
- cell rate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3081—ATM peripheral units, e.g. policing, insertion or extraction
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L12/5602—Bandwidth control in ATM Networks, e.g. leaky bucket
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/50—Overload detection or protection within a single switching element
- H04L49/501—Overload detection
- H04L49/503—Policing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5629—Admission control
- H04L2012/5631—Resource management and allocation
- H04L2012/5636—Monitoring or policing, e.g. compliance with allocated rate, corrective actions
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5649—Cell delay or jitter
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5638—Services, e.g. multimedia, GOS, QOS
- H04L2012/5646—Cell characteristics, e.g. loss, delay, jitter, sequence integrity
- H04L2012/5651—Priority, marking, classes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5672—Multiplexing, e.g. coding, scrambling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5678—Traffic aspects, e.g. arbitration, load balancing, smoothing, buffer management
- H04L2012/5679—Arbitration or scheduling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/20—Support for services
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
Abstract
The apparatus is used for queuing and scheduling ATM cells across an ATM switch. A sustainable cell rate calendar is connected in series with a peak cell rate calendar and cells are scheduled independently in each. The sustainable cell rate calendar guarantees the maximum ATM cell delay is not exceeded.
The ATM cells are not placed on the peak cell rate calendar unless the peak cell rate threshold might be exceeded. In this case the cell is scheduled on the peak cell rate calendar and it is this that determines when the cell is sent. In this way, it is possible to guarantee absolute minimum and maximum cell rates of a connection.
The ATM cells are not placed on the peak cell rate calendar unless the peak cell rate threshold might be exceeded. In this case the cell is scheduled on the peak cell rate calendar and it is this that determines when the cell is sent. In this way, it is possible to guarantee absolute minimum and maximum cell rates of a connection.
Description
.~e'~
21S8~2~
_ I
ATM QUEUING AND SCHEDULING APPARATUS
The present invention relates to apparatus for queuing and scheduling ATM cells in an ATM switch.
ATM networks and switches support a mixture of traffic including bursty traffic. By its nature, bursty traffic requires high bit rates for part of the time and little or no bit rate for the rest of the time. ln order to use efficiently the bit rate available in a network, it is necessary to allocate a connection at a lower bit rate than the peak bit rate, such that the total peak bit rate of all the connections may be greater than the bit rate of the network links.
In a German Patent Application No 93120828.4, there is detailed and method of providing an output of ATM cells whereby the sustainable cell rate as defined in the ATM Forum User Network Interface (UNI) specification, version 3.0, is guaranteed.
By using a leaky bucket method, as described in the ATM Forum UNI specification, version 3.0, each ATM cell has the time of transmission from the system calculated by identification of its virtual channel identifier/virtual path identifier (VCI/VPI) field, or other similar method which uniquely identifies ATM cells belonging to the same communication connection. This transmission time is provided as a delay value and is used to schedule the ATM cell on a calendar, which is effectively a time schedu ler.
The problem with the method as mentioned in this German patent application. is that it does not limit the minimum delay, ATM cells can be transmitted at up to the maximum bit rate of the - 2158~4 network link. This means that the cells can exceed the peak cell rate (PCR) of the connection as defined in the ATM Forum UNI
specification, version 3Ø
In GB Patent Application No 9405788.2, another method is disclosed which uses two calendars. The first calendar, as with the above mentioned German patent application, guarantees the sustainable cell rate, by scheduling ATM cells according to the sustainable cell rate leaky bucket delay value. This calendar is called the sustainable cell rate (SCR) calendar. A second calendar is used which limits the peak cell rate. The second calendar is called the peak cell rate (PCR) calendar and schedules the cells according to their PCR delay value. Although there are two calendars, each ATM cell is stored only once. Each ATM cell is pointed to from both calendars. The second calendar has some distinct differences in the way it operates as follows:
The SCR calendar has two time pointers, a real time read pointer (T) and a read pointer (RP).
The PCR calendar has only one pointer, a real time read pointer (T).
The SCR calendar read pointer will move from one filled time slot to the next filled time slot. For both SCR and PCR
calendars the real time read pointer will only move by one time slot each ATM cell transmission period.
Once the real time read pointer of the PCR calendar has passed a tlme slot, it will remove the pointer from the ATM cell, returning it to a null value. This is the key for the SCR calendar to transmit the cell from the system when it arrives.
~3- 21~8324 The system is intended to limit the ATM cell rate for a specific connection to within its specified threshold for the sustainable cell rate and the peak cell rate, that is the maximum and minimum ATM cell rate.
There is a problem with the above mentioned prior art system, in that, in a specific situation it is possible that the peak cell rate may exceed the PCR value set. This occurs if there is sudden change in the usage of the system from high to low usage.
In a high load situation, the real time read pointer moves from cell slot to cell slot removing the PCR pointer from cells.
However, the cells are actually transmitted from the system based on the read pointer, which in a high load situation will operate as a slow rate. It is possible that the real time read pointer on the PCR calendar may remove the PCR pointer from several ATM cells all belonging to the same connection before the read pointer of the SCR calendar sends them. If the system enters a low load period, the read pointer will run faster and send any ATM cells with a null PCR pointer. There is therefore the opportunity to send ATM
cells from the same connection at a greater ATM cell rate than the PCR value.
An aim of the present invention is to provide ATM queuing and scheduling apparatus which does not suffer from the above mentioned problem.
According to the present invention there is provided apparatus for queuing and scheduling ATM cells connected to an output side of an ATM switch, comprising first and second calendars connected in series, said first calendar being used to 21~8324 schedule cells for transmission in accordance with a maximum delay value, said second calendar being used to schedule cells for transmission in accordance with a minimum delay value, and comparator means for determining when a cell is to be scheduled on said second calendar.
An embodiment of the present invention will now be described with reference to the accompanying drawings, in which, FIGURE 1 shows a block diagram of a typical ATM switch, and, FIGURE 2 shows a sustainable bit rate calendar and a peak bit rate calendar connected in series, together with a table which is used to identify the VCI/VPI, the PCR intercell time and the last cell time.
Referring to Figure 1, on the ingress side are shown line cards 8, the output of which are connected to an input of an ATM
multiplexer 12. The output of the multiplexer 12 is connected to an input of a statistical multiplexing unit 16, the output of which is fed to the ATM switching network 20. The output of the switching network 20 is connected to an input of a further statistical multiplexing unit 18, the output of which is connected to an input of an ATM multiplexer 14. The outputs of the ATM
multiplexer 14 are connected to the input of a number of line cards 10 which are on the egress side of the switching network.
The links between the various components designated M
represent multiplexed internal links. Each statistical multiplexing unit has a flow control controller 22. The combination, for example, of the line cards 8, multiplexer 12 and statistical s multiplexing unit 16 comprises a peripheral switch group. In practice there will be a number of peripheral switch groups connected to the ATM switching network. Within each statistical multiplexing unit 16 there is one input queue for each of the peripheral switch groups attached to the ATM switching network.
Cells may be sent independently between any of the peripheral switch groups. There are limiting factors which control the cell rate, and they are the output link bit rate from the ATM switching network to a peripheral switch group, and the output link bit rate from a peripheral switch group to the ATM switching network.
Flow control procedures operate to manage these limited bit rates fairly for all connections, both internally to the switch and between the peripheral switch groups, and to limit bit rate to peak reservation across the ATM switching network.
The present invention is conveniently located in the statistical multiplexing unit 18 and will now be described.
Referring to Figure 2, there is shown a sustainable bit rate calendar 30 serially connected to a peak bit rate calendar 32.
ATM cells 34 are received over a line 36 from the ATM switch of Figure 1, and are processed by a leaky bucket manager circuit 38, which is used to generate the required maximum delay Dmax.
The ATM cells 40 which are fed out from the sustainable bit rate calendar 30, are processed by a leaky bucket manager circuit 42, to provide the required minimum delay Dmin.
In Figure 2, the following abbreviations are used, FLT is the Free List Tail, FLH is the Free List Head, CET is the Calendar Entry Tail, CEH is the Calendar Entry Head, RP is the Read Pointer, T is ~lS8324 the Real Time Pointer, OLT is the Output List Tail, OLH is the Output List Head, MCA is the Size of Calendar, VPI is the Virtual Path Indicator, VCI is the Virtual Channel Indicator.
In Figure 2 there is also shown a table 46, in which would be listed the VCI/VPI data which identifies the ATM cell address, the PCR intercell time, which represents the peak cell rate intercell time, and a further column identified as last cell time.
By placing the two calendars 30, 32 in series, cells A to D for example, may be scheduled independently in each calendar in their respective cell memory 48, 50 in accordance with the read pointer of RP and the real time pointer T.
In operation, cells leaving the sustainable cell rate calendar 30 are checked against the table values for the peak cell rate intercell time and the last time a cell was transmitted. If the intercell time will be less with this particular cell being transmitted immediately, the cell must be scheduled on the peak cell rate calendar 32 at an intercell time. The sustainable cell rate therefore guarantees the maximum ATM cell delay is not exceeded. The ATM cells are not placed on the peak cell rate calendar 32 unless the above mentioned PCR threshold might be exceeded. It is the scheduling on the peak cell rate calendar which determines when the cell is sent. In this manner it is possible to guarantee absolutely the minimum and maximum cell rate of a connection is observed.
It will be readily appreciated that there are various ways of implementing the control of the sustainable cell rate calendar and 21~8324 the peak cell rate calendar which fall within the scope of the present invention.
21S8~2~
_ I
ATM QUEUING AND SCHEDULING APPARATUS
The present invention relates to apparatus for queuing and scheduling ATM cells in an ATM switch.
ATM networks and switches support a mixture of traffic including bursty traffic. By its nature, bursty traffic requires high bit rates for part of the time and little or no bit rate for the rest of the time. ln order to use efficiently the bit rate available in a network, it is necessary to allocate a connection at a lower bit rate than the peak bit rate, such that the total peak bit rate of all the connections may be greater than the bit rate of the network links.
In a German Patent Application No 93120828.4, there is detailed and method of providing an output of ATM cells whereby the sustainable cell rate as defined in the ATM Forum User Network Interface (UNI) specification, version 3.0, is guaranteed.
By using a leaky bucket method, as described in the ATM Forum UNI specification, version 3.0, each ATM cell has the time of transmission from the system calculated by identification of its virtual channel identifier/virtual path identifier (VCI/VPI) field, or other similar method which uniquely identifies ATM cells belonging to the same communication connection. This transmission time is provided as a delay value and is used to schedule the ATM cell on a calendar, which is effectively a time schedu ler.
The problem with the method as mentioned in this German patent application. is that it does not limit the minimum delay, ATM cells can be transmitted at up to the maximum bit rate of the - 2158~4 network link. This means that the cells can exceed the peak cell rate (PCR) of the connection as defined in the ATM Forum UNI
specification, version 3Ø
In GB Patent Application No 9405788.2, another method is disclosed which uses two calendars. The first calendar, as with the above mentioned German patent application, guarantees the sustainable cell rate, by scheduling ATM cells according to the sustainable cell rate leaky bucket delay value. This calendar is called the sustainable cell rate (SCR) calendar. A second calendar is used which limits the peak cell rate. The second calendar is called the peak cell rate (PCR) calendar and schedules the cells according to their PCR delay value. Although there are two calendars, each ATM cell is stored only once. Each ATM cell is pointed to from both calendars. The second calendar has some distinct differences in the way it operates as follows:
The SCR calendar has two time pointers, a real time read pointer (T) and a read pointer (RP).
The PCR calendar has only one pointer, a real time read pointer (T).
The SCR calendar read pointer will move from one filled time slot to the next filled time slot. For both SCR and PCR
calendars the real time read pointer will only move by one time slot each ATM cell transmission period.
Once the real time read pointer of the PCR calendar has passed a tlme slot, it will remove the pointer from the ATM cell, returning it to a null value. This is the key for the SCR calendar to transmit the cell from the system when it arrives.
~3- 21~8324 The system is intended to limit the ATM cell rate for a specific connection to within its specified threshold for the sustainable cell rate and the peak cell rate, that is the maximum and minimum ATM cell rate.
There is a problem with the above mentioned prior art system, in that, in a specific situation it is possible that the peak cell rate may exceed the PCR value set. This occurs if there is sudden change in the usage of the system from high to low usage.
In a high load situation, the real time read pointer moves from cell slot to cell slot removing the PCR pointer from cells.
However, the cells are actually transmitted from the system based on the read pointer, which in a high load situation will operate as a slow rate. It is possible that the real time read pointer on the PCR calendar may remove the PCR pointer from several ATM cells all belonging to the same connection before the read pointer of the SCR calendar sends them. If the system enters a low load period, the read pointer will run faster and send any ATM cells with a null PCR pointer. There is therefore the opportunity to send ATM
cells from the same connection at a greater ATM cell rate than the PCR value.
An aim of the present invention is to provide ATM queuing and scheduling apparatus which does not suffer from the above mentioned problem.
According to the present invention there is provided apparatus for queuing and scheduling ATM cells connected to an output side of an ATM switch, comprising first and second calendars connected in series, said first calendar being used to 21~8324 schedule cells for transmission in accordance with a maximum delay value, said second calendar being used to schedule cells for transmission in accordance with a minimum delay value, and comparator means for determining when a cell is to be scheduled on said second calendar.
An embodiment of the present invention will now be described with reference to the accompanying drawings, in which, FIGURE 1 shows a block diagram of a typical ATM switch, and, FIGURE 2 shows a sustainable bit rate calendar and a peak bit rate calendar connected in series, together with a table which is used to identify the VCI/VPI, the PCR intercell time and the last cell time.
Referring to Figure 1, on the ingress side are shown line cards 8, the output of which are connected to an input of an ATM
multiplexer 12. The output of the multiplexer 12 is connected to an input of a statistical multiplexing unit 16, the output of which is fed to the ATM switching network 20. The output of the switching network 20 is connected to an input of a further statistical multiplexing unit 18, the output of which is connected to an input of an ATM multiplexer 14. The outputs of the ATM
multiplexer 14 are connected to the input of a number of line cards 10 which are on the egress side of the switching network.
The links between the various components designated M
represent multiplexed internal links. Each statistical multiplexing unit has a flow control controller 22. The combination, for example, of the line cards 8, multiplexer 12 and statistical s multiplexing unit 16 comprises a peripheral switch group. In practice there will be a number of peripheral switch groups connected to the ATM switching network. Within each statistical multiplexing unit 16 there is one input queue for each of the peripheral switch groups attached to the ATM switching network.
Cells may be sent independently between any of the peripheral switch groups. There are limiting factors which control the cell rate, and they are the output link bit rate from the ATM switching network to a peripheral switch group, and the output link bit rate from a peripheral switch group to the ATM switching network.
Flow control procedures operate to manage these limited bit rates fairly for all connections, both internally to the switch and between the peripheral switch groups, and to limit bit rate to peak reservation across the ATM switching network.
The present invention is conveniently located in the statistical multiplexing unit 18 and will now be described.
Referring to Figure 2, there is shown a sustainable bit rate calendar 30 serially connected to a peak bit rate calendar 32.
ATM cells 34 are received over a line 36 from the ATM switch of Figure 1, and are processed by a leaky bucket manager circuit 38, which is used to generate the required maximum delay Dmax.
The ATM cells 40 which are fed out from the sustainable bit rate calendar 30, are processed by a leaky bucket manager circuit 42, to provide the required minimum delay Dmin.
In Figure 2, the following abbreviations are used, FLT is the Free List Tail, FLH is the Free List Head, CET is the Calendar Entry Tail, CEH is the Calendar Entry Head, RP is the Read Pointer, T is ~lS8324 the Real Time Pointer, OLT is the Output List Tail, OLH is the Output List Head, MCA is the Size of Calendar, VPI is the Virtual Path Indicator, VCI is the Virtual Channel Indicator.
In Figure 2 there is also shown a table 46, in which would be listed the VCI/VPI data which identifies the ATM cell address, the PCR intercell time, which represents the peak cell rate intercell time, and a further column identified as last cell time.
By placing the two calendars 30, 32 in series, cells A to D for example, may be scheduled independently in each calendar in their respective cell memory 48, 50 in accordance with the read pointer of RP and the real time pointer T.
In operation, cells leaving the sustainable cell rate calendar 30 are checked against the table values for the peak cell rate intercell time and the last time a cell was transmitted. If the intercell time will be less with this particular cell being transmitted immediately, the cell must be scheduled on the peak cell rate calendar 32 at an intercell time. The sustainable cell rate therefore guarantees the maximum ATM cell delay is not exceeded. The ATM cells are not placed on the peak cell rate calendar 32 unless the above mentioned PCR threshold might be exceeded. It is the scheduling on the peak cell rate calendar which determines when the cell is sent. In this manner it is possible to guarantee absolutely the minimum and maximum cell rate of a connection is observed.
It will be readily appreciated that there are various ways of implementing the control of the sustainable cell rate calendar and 21~8324 the peak cell rate calendar which fall within the scope of the present invention.
Claims (2)
1. Apparatus for queuing and scheduling ATM cells connected to an output side of an ATM switch, comprising first and second calendars connected in series, said first calendar being used to schedule cells for transmission in accordance with a maximum delay value, said second calendar being used to schedule cells for transmission in accordance with a minimum delay value, and comparator means for determining when a cell is to be scheduled on said second calendar.
2. Apparatus as claimed in Claim 1, wherein said apparatus comprises buffer means connected to an input line upon which ATM cells are received, first control means for receiving for each cell a channel identifier and a path identifier from which a first signal is generated indicative of said maximum delay value, said first calendar in which said cell is scheduled for transmission in accordance with the maximum delay value being used to control a sustainable cell rate, an output line from said first calendar which is connected to an input of said second calendar, second buffer means for receiving ATM cells from said first calendar, and second control means for receiving a channel identifier and a path identifier in respect of the received cell for generating a second signal indicative of said minimum delay value, which is used to schedule the particular cell for transmission on said second calendar for controlling a peak cell rate, wherein, cells are dispatched from said first calendar and are compared by said comparator means against a table of values for a peak cell rate intercell time and a last time the particular cell was transmitted and if said intercell time will be less when said cell is transmitted immediately, said cell is scheduled on said second calendar at said intercell time.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9419802A GB9419802D0 (en) | 1994-09-30 | 1994-09-30 | Serial egress shaping for atm switch |
| GB9510138.2 | 1995-05-19 | ||
| GB9510138A GB2293720B (en) | 1994-09-30 | 1995-05-19 | ATM Queuing and scheduling apparatus |
| GB9419802.5 | 1995-05-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2158324A1 true CA2158324A1 (en) | 1996-03-31 |
Family
ID=26305718
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002158324A Abandoned CA2158324A1 (en) | 1994-09-30 | 1995-09-14 | Atm queuing and scheduling apparatus |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5734650A (en) |
| EP (1) | EP0705007A3 (en) |
| JP (1) | JPH08125669A (en) |
| CA (1) | CA2158324A1 (en) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE9504231L (en) | 1995-11-27 | 1997-05-28 | Ericsson Telefon Ab L M | Queue system for transmitting information packets |
| US6128303A (en) * | 1996-05-09 | 2000-10-03 | Maker Communications, Inc. | Asynchronous transfer mode cell processing system with scoreboard scheduling |
| DE19620428A1 (en) * | 1996-05-21 | 1997-11-27 | Siemens Ag | Methods for optimizing the utilization of connection sections in systems in which information is transmitted in data packets |
| US5889763A (en) * | 1996-06-04 | 1999-03-30 | Motorola, Inc. | Transfer rate controller and method of operation |
| EP0817434B1 (en) * | 1996-06-27 | 2013-03-13 | Xerox Corporation | A packet switched communication system and traffic shaping process |
| DE69737249T2 (en) * | 1996-06-27 | 2007-08-09 | Xerox Corp. | Packet-switched communication system |
| DE19630919A1 (en) | 1996-07-31 | 1998-02-05 | Siemens Ag | Methods for optimizing the utilization of connection sections in systems in which information is transmitted in data packets |
| DE19634492B4 (en) * | 1996-08-26 | 2004-10-14 | Siemens Ag | Method for the optimized transmission of ATM cells over connection sections |
| US5818839A (en) * | 1997-06-27 | 1998-10-06 | Newbridge Networks Corporation | Timing reference for scheduling data traffic on multiple ports |
| US6408005B1 (en) * | 1997-09-05 | 2002-06-18 | Nec Usa, Inc. | Dynamic rate control scheduler for ATM networks |
| AU1123799A (en) * | 1997-10-28 | 1999-05-17 | Abrizio, Inc. | Stream-line data network |
| US6167059A (en) * | 1998-01-26 | 2000-12-26 | Motorola Inc. | Apparatus and method for transmitting data |
| JP3063726B2 (en) | 1998-03-06 | 2000-07-12 | 日本電気株式会社 | Traffic shaper |
| JPH11275107A (en) * | 1998-03-24 | 1999-10-08 | Nec Corp | Scheduling device, scheduling method and communication controller |
| US6198723B1 (en) * | 1998-04-14 | 2001-03-06 | Paxonet Communications, Inc. | Asynchronous transfer mode traffic shapers |
| GB2337406B (en) | 1998-05-11 | 2003-05-14 | Fujitsu Ltd | Scheduling circuitry and methods |
| FR2779302B1 (en) * | 1998-05-28 | 2000-06-23 | Alsthom Cge Alcatel | CONGESTION CONTROL IN AN ATM NODE |
| JP3711752B2 (en) * | 1998-07-09 | 2005-11-02 | 株式会社日立製作所 | Packet communication device |
| JP2000031997A (en) * | 1998-07-15 | 2000-01-28 | Fujitsu Ltd | Band management system and its method |
| CA2245367A1 (en) * | 1998-08-19 | 2000-02-19 | Newbridge Networks Corporation | Two-component bandwidth scheduler having application in multi-class digital communication systems |
| US6728253B1 (en) | 1999-09-24 | 2004-04-27 | International Business Machines Corporation | Mixed queue scheduler |
| US6952424B1 (en) * | 2000-04-13 | 2005-10-04 | International Business Machines Corporation | Method and system for network processor scheduling outputs using queueing |
| US7123622B2 (en) * | 2000-04-13 | 2006-10-17 | International Business Machines Corporation | Method and system for network processor scheduling based on service levels |
| US6862292B1 (en) * | 2000-04-13 | 2005-03-01 | International Business Machines Corporation | Method and system for network processor scheduling outputs based on multiple calendars |
| US6977946B1 (en) * | 2001-03-12 | 2005-12-20 | Cisco Technology, Inc. | Virtual connection service cache for filling available bandwidth |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2686205B1 (en) * | 1992-01-14 | 1994-03-25 | Pierre Boyer | METHOD FOR MONITORING CELL FLOW. |
| US5497375A (en) * | 1994-01-05 | 1996-03-05 | Motorola, Inc. | Device and method for ATM end system cell flow regulation |
| GB2288097B (en) * | 1994-03-23 | 1998-09-23 | Roke Manor Research | ATM queuing and scheduling apparatus |
| EP0702473A1 (en) * | 1994-09-19 | 1996-03-20 | International Business Machines Corporation | A method and an apparatus for shaping the output traffic in a fixed length cell switching network node |
| US5570360A (en) * | 1995-03-20 | 1996-10-29 | Stratacom, Inc. | Method and apparatus for implementing communication service contract using cell arrival information |
-
1995
- 1995-09-04 EP EP95113837A patent/EP0705007A3/en not_active Withdrawn
- 1995-09-14 CA CA002158324A patent/CA2158324A1/en not_active Abandoned
- 1995-09-29 US US08/536,952 patent/US5734650A/en not_active Expired - Fee Related
- 1995-10-02 JP JP25532495A patent/JPH08125669A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US5734650A (en) | 1998-03-31 |
| EP0705007A2 (en) | 1996-04-03 |
| JPH08125669A (en) | 1996-05-17 |
| EP0705007A3 (en) | 2003-01-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5734650A (en) | ATM queuing and scheduling apparatus | |
| US5629937A (en) | Apparatus and method for ATM queuing and scheduling | |
| US5339332A (en) | Arrangement for monitoring the bit rate in ATM networks | |
| US6067298A (en) | ATM switching system which separates services classes and uses a code switching section and back pressure signals | |
| US5704047A (en) | ATM communication system wherein upstream switching element stops the transmission of message for a predetermined period of time upon backpressure signal | |
| US5295135A (en) | Arrangement for monitoring the bit rate in ATM networks | |
| EP0853441B1 (en) | Switch control circuit and switch control method of ATM switchboard | |
| CA2239852C (en) | Timing reference for scheduling data traffic on multiple ports | |
| EP0763915A2 (en) | Packet transfer device and method adaptive to a large number of input ports | |
| EP0508378B1 (en) | Method and system for monitoring the packet rate in a packet network | |
| JP3115546B2 (en) | Method for optimally transmitting ATM cells | |
| EP1686742B1 (en) | Communiction control device and method for an ATM system applicable to an ABR mode | |
| GB2293720A (en) | ATM queuing and scheduling apparatus | |
| US20020159120A1 (en) | Optical line terminal, APON system and cell delay variation control method | |
| CA2263400C (en) | Process for optimising load distribution between connection sections of data package transmission systems | |
| KR960014421B1 (en) | Priority control method of atm switch | |
| CA2256341C (en) | Process for optimizing the utilization of connecting links in systems which transmit data in data packets | |
| CA2296688C (en) | Method for optimizing the load level on connecting sections for vbr traffic | |
| KR100294002B1 (en) | Real-time ADL Traffic Management in Asynchronous Transmission Mode Network | |
| JPH04178044A (en) | Traffic control system in atm exchange | |
| KR0150077B1 (en) | Multiplexing apparatus for controlling cell delay variation of cbr traffic in atm network and method thereof | |
| KR100238437B1 (en) | Traffic scheduler and scheduling method in an atm element | |
| KR100277718B1 (en) | Input control device and method of asynchronous transfer mode switch network | |
| MIN et al. | Performance of an ATM multiplexer with selective cell discarding for on-off bursty traffics | |
| JP3074918B2 (en) | Cell traffic monitoring device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Dead |