CA2161982A1 - Clock cleaner - Google Patents
Clock cleanerInfo
- Publication number
- CA2161982A1 CA2161982A1 CA002161982A CA2161982A CA2161982A1 CA 2161982 A1 CA2161982 A1 CA 2161982A1 CA 002161982 A CA002161982 A CA 002161982A CA 2161982 A CA2161982 A CA 2161982A CA 2161982 A1 CA2161982 A1 CA 2161982A1
- Authority
- CA
- Canada
- Prior art keywords
- frequency
- clock signal
- signal
- clock
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/0066—Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
Abstract
A device which reduces jitter and narrows the frequency spectrum of a jitter-ridden clock signal. A front end of the device locates missing clock pulses and ensures regular clock pulses are relayed to the remainder of the device. The succeeding sections hone the signal such that jitter elements are removed. By this time duty cycles are uneven so a positive edge triggerred flip-flop is used to obtain 50%
duty cycles at the expense of halving the clock signal's frequency. Optionally a frequency doubler can be employed to regain the clock signal's original frequency.
duty cycles at the expense of halving the clock signal's frequency. Optionally a frequency doubler can be employed to regain the clock signal's original frequency.
Description
Background of the Invention 1. Field of the In~ention This invention relates to jitter removing circuits, clock averagers and other clock signal correction devices.
2. Description of Relatod Art At present jitter is controlled by prevention rather than cure. By the use of good design technique the effects of factors such as current surges, temperature, EM intqrference ~ . - ; ' :
.
~_ 1 2161982 etc, are m; ~;m; sed. However there are many instances where despite such measures jitter is introduced into the system via transmission, mechanical devices and the like. Clock recovery systems, which recover clock signals distorted by transmission usually incorporate a high quality crystal which is used as a reference and as a source if a clock pulse is missing.
Summary of the Invention Presented is a device which removes jitter from a clock signal. The device is based upon a basic unit which is repeated throughout the device. The behaviour of this basic unit determines its jitter removal capabilities.
In its present embodiment the invention can be considered passive, however it is possible to include feedback loops connected to the oscillator to compensate for environmental conditions including aging.
The basic unit consists of a number of delay elements connected in series. The output of each delay is connected to the input of a multi-input AND gate. The output from the basic unit exhibits a narrower spectrum than the original spectrum. This statement must be qualified in that the actual signal emerges with an uneven duty cycle. By feeding 1~
the output from any of the basic units to a flip-flop a clock signal of half the original frequency is created with a 50~ duty cycle because the times between postive to negative transitions is constant. After being passed through a frequency doubler the resulting spectrum of this signal is narrower than the orignal.
The 'front end' of the device consists of a circuit which compensates for missing pulses. Any number of basic units are connected in series. Each of their outputs are fed into a corresponding flip-flop and to a corresponding AND gate.
There are one less AND gates connected such that the output from only one basic unit is let through to an EXOR gate. The output from there is presented to various basic units of different size, all connected in series.
The output from there is fed to a flip-flop which corrects the uneven duty cycle but produces a signal whose frequency is half that input. Either this signal can be used, or the signal can be applied to a frequency doubler to create a clock signal at the original frequency.
8rief De~cription of the Drawings Figure 1 shows a schematic diagram of the 'basic unit' which the present invention is comprised of, in particular it 2l6lg82 shows a basic unit with 8 buffers/delay elements and an input AND/NAND gate.
Figure 2 shows a block representation of Figure 1.
Figure 3 shows the 'front end' of the invention. Its function is to recognise the absense of a clock pulse and supply one to the remaining sections of the invention, by routing the signal from later or earlier parts of the signal contained within the delay line.
Figure 4 shows a possible configuration for the section following the 'front end'. It consists of basic units of increasing size connected in series.
Figure 5 shows the 'back end' of the invention. When the signal reaches this stage its duty cycle is rarely 50-50.
Its function is to create a 50-50 duty cycle.
Description of an Embodiment The present invention aims to eliminate jitter and compensate for the occassional missing pulse from clock signals. The key element of the invention is a simple circuit shown in figure 1. It is passive in the sense that no feedback loops are employed. This does not mean that none ~ 2161g82 can be; for example if there is no output it implies that the clock signal's frequency is outside the circuit's range and a feedback loop can be employed to control the crystal oscillator or clock source to bring the input frequency back within its range.
It is to be understood that the present invention is not limited to work within the confines of electricity, indeed the topologies described work equally well, theoretically if the medium is light or sound as well as electrons. The practicalities of implementing the deisgn fall within those of good design practice. For example delay lines of considerable length might be employed. In this circumstance stable voltage and current sources must be used to reduce jitter caused by the simultaneous switching of all these gates. In fact delay elements can be formed from complementary pairs to eliminate current surges.
This basic unit 14 consists of a number of delay elements 1-8 in series each having its output fed into a multi-input NAND/AND gate 9. The number of delay elements is arbitrary however the greater the number the narrower the range of frequencies from which the unit can accept an input. In general given a imperfect signal as input the basic unit will give out a signal whose duty cycle is uneven. This is corrected later.
Input 10 receives a signal direct from a crystal oscillator, other clock source or the output of another basic element.
The signal propagates through the delay elements 1-8, the output at each element controls the output of the NAND/AND
gate 9which forms part of the basic unit. The output 11 outputs the signal as it enters from the input 10. The output(changed)12 gives the basic unit's output and output(changedJ13 gives the inverse of 12.
A positive level from output(changed) 12 is only possible if all the levels presented at the inputs of the multi-input NAND/AND gate 9 are positive.
The delay of each element 1-8 must be identical and determines the 'ideal' frequency of the basic unit 14. Given a delay of x seconds then the 'ideal' or central frequency is 2~.x Hz. In other words the delay introduced by each element must equal the period of the input frequency.
It is difficult to analyse the circuit in the time domain, it is instructive to see its behaviour in the frequency domain by studying its effect on certain types of signals presented to it.
When presented with a jitter-free, stable clock signal whose frequency is off from the ideal the basic unit 14 has no effect on the signal. The range of clock signal periods which are allowed through unaffected is given approximately by 2~
x + x Hz, 2.nt where nt is the number of delay elements 1-8 in the basic unit 14 and x is the delay introduced by each delay element 1~ .
When presented with a signal containing a range of frequencies (introduced by jitter or other factors) the basic unit 14 narrows the range significantly. An interesting feature is that irrespective of whether or not the signal's frequencies are centred around the 'ideal' frequency the basic unit 14 narrows the frequency range and moves the spectrum's peak towards the ideal frequency.
However the closer the original signal's central frequency is to the basic unit's 14 the narrower the output spectrum.
The front end of the present invention is concerned with recognising the absence of clock pulses and compensating for them. If a clock pulse is missed then the logic is arranged so that the output from the basic unit 1~-19 containing the absence is blocked (e.g. 19) and the signal from the basic unit preceeding it (e.g. 18) takes over and is routed through to the following sections.
The flip-flops 20-23 ensure that the output from only one basic unit 1~-19 reaches the EXOR gate 37. The delay elements 44, 25, 27, 29, 31 provide a delay equal to that of the flip-flops the signal paths to the AND gate have the same propagation delay. The delay elements 24, 26, 28, 30 at the enable/disable input of the flip-flops 20, 21, 22, 23 are adjusted so that the flip-flop can identify an absent clock pulse and an actual clock pulse. It also serves to reset the device.
The signal then goes to a section containing four basic units 38-41 each containing an increasing number of delay elements. The actual topology of this section can be anything that works; experimentation will reveal the best ways of connecting basic elements 38-41 of any size and number. By using increasingly larger numbers of delay elements the resluting signal will have a much narrower frequency spectrum.
The signal is then presented to flip-flop 42 and optionally a frequency doubler 43. By the time the signal reaches this stage it may generally consist of a very short positive cycle and a very long negative half-cycle. The times between ~ ~ 2~61g82 negative to positive transitions are constant. Small deviations may occur periodically which are caused by the signal going out of phase with the delay elements 1-8.
:' Thus by using a positive edge triggered flip-flop 42 a signal with a 50% duty cycle, at the expense of halving the signal's frequency, is produced. If desired a frequency doubler 43 can be employed to regain the signal's original frequency. I
_
.
~_ 1 2161982 etc, are m; ~;m; sed. However there are many instances where despite such measures jitter is introduced into the system via transmission, mechanical devices and the like. Clock recovery systems, which recover clock signals distorted by transmission usually incorporate a high quality crystal which is used as a reference and as a source if a clock pulse is missing.
Summary of the Invention Presented is a device which removes jitter from a clock signal. The device is based upon a basic unit which is repeated throughout the device. The behaviour of this basic unit determines its jitter removal capabilities.
In its present embodiment the invention can be considered passive, however it is possible to include feedback loops connected to the oscillator to compensate for environmental conditions including aging.
The basic unit consists of a number of delay elements connected in series. The output of each delay is connected to the input of a multi-input AND gate. The output from the basic unit exhibits a narrower spectrum than the original spectrum. This statement must be qualified in that the actual signal emerges with an uneven duty cycle. By feeding 1~
the output from any of the basic units to a flip-flop a clock signal of half the original frequency is created with a 50~ duty cycle because the times between postive to negative transitions is constant. After being passed through a frequency doubler the resulting spectrum of this signal is narrower than the orignal.
The 'front end' of the device consists of a circuit which compensates for missing pulses. Any number of basic units are connected in series. Each of their outputs are fed into a corresponding flip-flop and to a corresponding AND gate.
There are one less AND gates connected such that the output from only one basic unit is let through to an EXOR gate. The output from there is presented to various basic units of different size, all connected in series.
The output from there is fed to a flip-flop which corrects the uneven duty cycle but produces a signal whose frequency is half that input. Either this signal can be used, or the signal can be applied to a frequency doubler to create a clock signal at the original frequency.
8rief De~cription of the Drawings Figure 1 shows a schematic diagram of the 'basic unit' which the present invention is comprised of, in particular it 2l6lg82 shows a basic unit with 8 buffers/delay elements and an input AND/NAND gate.
Figure 2 shows a block representation of Figure 1.
Figure 3 shows the 'front end' of the invention. Its function is to recognise the absense of a clock pulse and supply one to the remaining sections of the invention, by routing the signal from later or earlier parts of the signal contained within the delay line.
Figure 4 shows a possible configuration for the section following the 'front end'. It consists of basic units of increasing size connected in series.
Figure 5 shows the 'back end' of the invention. When the signal reaches this stage its duty cycle is rarely 50-50.
Its function is to create a 50-50 duty cycle.
Description of an Embodiment The present invention aims to eliminate jitter and compensate for the occassional missing pulse from clock signals. The key element of the invention is a simple circuit shown in figure 1. It is passive in the sense that no feedback loops are employed. This does not mean that none ~ 2161g82 can be; for example if there is no output it implies that the clock signal's frequency is outside the circuit's range and a feedback loop can be employed to control the crystal oscillator or clock source to bring the input frequency back within its range.
It is to be understood that the present invention is not limited to work within the confines of electricity, indeed the topologies described work equally well, theoretically if the medium is light or sound as well as electrons. The practicalities of implementing the deisgn fall within those of good design practice. For example delay lines of considerable length might be employed. In this circumstance stable voltage and current sources must be used to reduce jitter caused by the simultaneous switching of all these gates. In fact delay elements can be formed from complementary pairs to eliminate current surges.
This basic unit 14 consists of a number of delay elements 1-8 in series each having its output fed into a multi-input NAND/AND gate 9. The number of delay elements is arbitrary however the greater the number the narrower the range of frequencies from which the unit can accept an input. In general given a imperfect signal as input the basic unit will give out a signal whose duty cycle is uneven. This is corrected later.
Input 10 receives a signal direct from a crystal oscillator, other clock source or the output of another basic element.
The signal propagates through the delay elements 1-8, the output at each element controls the output of the NAND/AND
gate 9which forms part of the basic unit. The output 11 outputs the signal as it enters from the input 10. The output(changed)12 gives the basic unit's output and output(changedJ13 gives the inverse of 12.
A positive level from output(changed) 12 is only possible if all the levels presented at the inputs of the multi-input NAND/AND gate 9 are positive.
The delay of each element 1-8 must be identical and determines the 'ideal' frequency of the basic unit 14. Given a delay of x seconds then the 'ideal' or central frequency is 2~.x Hz. In other words the delay introduced by each element must equal the period of the input frequency.
It is difficult to analyse the circuit in the time domain, it is instructive to see its behaviour in the frequency domain by studying its effect on certain types of signals presented to it.
When presented with a jitter-free, stable clock signal whose frequency is off from the ideal the basic unit 14 has no effect on the signal. The range of clock signal periods which are allowed through unaffected is given approximately by 2~
x + x Hz, 2.nt where nt is the number of delay elements 1-8 in the basic unit 14 and x is the delay introduced by each delay element 1~ .
When presented with a signal containing a range of frequencies (introduced by jitter or other factors) the basic unit 14 narrows the range significantly. An interesting feature is that irrespective of whether or not the signal's frequencies are centred around the 'ideal' frequency the basic unit 14 narrows the frequency range and moves the spectrum's peak towards the ideal frequency.
However the closer the original signal's central frequency is to the basic unit's 14 the narrower the output spectrum.
The front end of the present invention is concerned with recognising the absence of clock pulses and compensating for them. If a clock pulse is missed then the logic is arranged so that the output from the basic unit 1~-19 containing the absence is blocked (e.g. 19) and the signal from the basic unit preceeding it (e.g. 18) takes over and is routed through to the following sections.
The flip-flops 20-23 ensure that the output from only one basic unit 1~-19 reaches the EXOR gate 37. The delay elements 44, 25, 27, 29, 31 provide a delay equal to that of the flip-flops the signal paths to the AND gate have the same propagation delay. The delay elements 24, 26, 28, 30 at the enable/disable input of the flip-flops 20, 21, 22, 23 are adjusted so that the flip-flop can identify an absent clock pulse and an actual clock pulse. It also serves to reset the device.
The signal then goes to a section containing four basic units 38-41 each containing an increasing number of delay elements. The actual topology of this section can be anything that works; experimentation will reveal the best ways of connecting basic elements 38-41 of any size and number. By using increasingly larger numbers of delay elements the resluting signal will have a much narrower frequency spectrum.
The signal is then presented to flip-flop 42 and optionally a frequency doubler 43. By the time the signal reaches this stage it may generally consist of a very short positive cycle and a very long negative half-cycle. The times between ~ ~ 2~61g82 negative to positive transitions are constant. Small deviations may occur periodically which are caused by the signal going out of phase with the delay elements 1-8.
:' Thus by using a positive edge triggered flip-flop 42 a signal with a 50% duty cycle, at the expense of halving the signal's frequency, is produced. If desired a frequency doubler 43 can be employed to regain the signal's original frequency. I
_
Claims (3)
1) A method for removing jitter and other small frequency fluctuations from a clock signal containing them using a basic circuit described in claim 2 which has the property of changing the spectrum of the clock signal entering it making it narrower, the maxima depending on the actual incoming spectrum and frequency which this circuit is 'tuned' to.
2) The basic circuit referred to in claim 1 comprises the following:
a) an input:
b) a number of identical delay elements connected in series, the delay of each element equal to the period, or multiple, of the 'ideal' frequency;
c) a multi-input AND/NAND gate, the number of inputs equal to the number of delay elements. Each input connected to the output of a corresponding delay element;
d) a bypass output where the signal emerges unaffected and outputs corresponding to the outputs of the AND/NAND gate.
a) an input:
b) a number of identical delay elements connected in series, the delay of each element equal to the period, or multiple, of the 'ideal' frequency;
c) a multi-input AND/NAND gate, the number of inputs equal to the number of delay elements. Each input connected to the output of a corresponding delay element;
d) a bypass output where the signal emerges unaffected and outputs corresponding to the outputs of the AND/NAND gate.
3) A method for removing jitter and replace missing clock pulses from a clock signal comprising:
a) a front end compensating for missing clock pulses by providing a good clock signal by routing through a later part of the clock signal where missing clock pulses are absent;
b) a middle section comprising a number of the basic circuits described in claim 2 containing differing numbers of delay elements arranged in any manner which delivers the best result;
c) a tail end comprising a flip-flop and a frequency doubler. The flip-flop restores a 50% duty cycle but halves the frequency.
a) a front end compensating for missing clock pulses by providing a good clock signal by routing through a later part of the clock signal where missing clock pulses are absent;
b) a middle section comprising a number of the basic circuits described in claim 2 containing differing numbers of delay elements arranged in any manner which delivers the best result;
c) a tail end comprising a flip-flop and a frequency doubler. The flip-flop restores a 50% duty cycle but halves the frequency.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002161982A CA2161982A1 (en) | 1995-11-02 | 1995-11-02 | Clock cleaner |
| EP96934256A EP0858699B1 (en) | 1995-11-02 | 1996-10-24 | Clock signal cleaning circuit |
| US09/066,423 US6246276B1 (en) | 1995-11-02 | 1996-10-24 | Clock signal cleaning circuit |
| ES96934256T ES2249787T3 (en) | 1995-11-02 | 1996-10-24 | WATCH SIGNAL CLEANING CIRCUIT. |
| CA002236423A CA2236423C (en) | 1995-11-02 | 1996-10-24 | Clock signal cleaning circuit |
| PCT/CA1996/000706 WO1997016901A1 (en) | 1995-11-02 | 1996-10-24 | Clock signal cleaning circuit |
| DE69635187T DE69635187T2 (en) | 1995-11-02 | 1996-10-24 | CIRCUIT ARRANGEMENT FOR CLOCK SIGNAL CLEANING |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002161982A CA2161982A1 (en) | 1995-11-02 | 1995-11-02 | Clock cleaner |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2161982A1 true CA2161982A1 (en) | 1997-05-03 |
Family
ID=4156897
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002161982A Abandoned CA2161982A1 (en) | 1995-11-02 | 1995-11-02 | Clock cleaner |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6246276B1 (en) |
| EP (1) | EP0858699B1 (en) |
| CA (1) | CA2161982A1 (en) |
| DE (1) | DE69635187T2 (en) |
| ES (1) | ES2249787T3 (en) |
| WO (1) | WO1997016901A1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3703997B2 (en) * | 1999-07-06 | 2005-10-05 | 沖電気工業株式会社 | Video signal control circuit |
| US6566939B1 (en) * | 2001-08-06 | 2003-05-20 | Lsi Logic Corporation | Programmable glitch filter |
| US7375569B2 (en) * | 2005-09-21 | 2008-05-20 | Leco Corporation | Last stage synchronizer system |
| US7420399B2 (en) * | 2005-11-10 | 2008-09-02 | Jonghee Han | Duty cycle corrector |
| US8294502B2 (en) * | 2011-03-04 | 2012-10-23 | Altera Corporation | Delay circuitry |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR1550432A (en) * | 1967-11-08 | 1968-12-20 | ||
| JPH0624315B2 (en) * | 1983-11-04 | 1994-03-30 | 日本ビクター株式会社 | Phase shifter |
| US4805197A (en) | 1986-12-18 | 1989-02-14 | Lecroy Corporation | Method and apparatus for recovering clock information from a received digital signal and for synchronizing that signal |
| EP0476968A3 (en) | 1990-09-21 | 1992-11-25 | Ncr Corporation | Clock recovery circuit |
| US5349612A (en) | 1992-06-19 | 1994-09-20 | Advanced Micro Devices, Inc. | Digital serializer and time delay regulator |
-
1995
- 1995-11-02 CA CA002161982A patent/CA2161982A1/en not_active Abandoned
-
1996
- 1996-10-24 WO PCT/CA1996/000706 patent/WO1997016901A1/en active IP Right Grant
- 1996-10-24 ES ES96934256T patent/ES2249787T3/en not_active Expired - Lifetime
- 1996-10-24 EP EP96934256A patent/EP0858699B1/en not_active Expired - Lifetime
- 1996-10-24 DE DE69635187T patent/DE69635187T2/en not_active Expired - Fee Related
- 1996-10-24 US US09/066,423 patent/US6246276B1/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE69635187D1 (en) | 2005-10-20 |
| EP0858699B1 (en) | 2005-09-14 |
| WO1997016901A1 (en) | 1997-05-09 |
| US6246276B1 (en) | 2001-06-12 |
| DE69635187T2 (en) | 2006-07-06 |
| ES2249787T3 (en) | 2006-04-01 |
| EP0858699A1 (en) | 1998-08-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FZDE | Discontinued |
Effective date: 19991102 |