CA2165831A1 - Method for configuring multiple adapter cards on a bus - Google Patents
Method for configuring multiple adapter cards on a busInfo
- Publication number
- CA2165831A1 CA2165831A1 CA002165831A CA2165831A CA2165831A1 CA 2165831 A1 CA2165831 A1 CA 2165831A1 CA 002165831 A CA002165831 A CA 002165831A CA 2165831 A CA2165831 A CA 2165831A CA 2165831 A1 CA2165831 A1 CA 2165831A1
- Authority
- CA
- Canada
- Prior art keywords
- adapter
- adapter unit
- host
- units
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/177—Initialisation or configuration control
Abstract
In a computer system having a cen-tral processing unit (12) which employs software drivers (14) as part of a host (12) for controlling peripheral units and including a bus (20) for connecting with adapters (10) for the peripheral units, wherein each adapter (10) has distributed intelligence means (210) for interpreting simple command information and a non-volatile storage element (124) for storing default configuration information, includ-ing a default port address for communica-tion, a method is provided for configuring such intelligent adapters connected to the bus. The method (fig. 3) includes ini-tializing the intelligent adapters (10) by applying power to the bus or by issuing a global reset signal (A) and causing a driver to be loaded by the central process-ing unit (B) so that the host (12) broadcast a start key via a sequence of write com-mands (C) via the bus (20) to any adapters (10) on the bus and to elicit responses from the intelligent adapters (10) in an interactive manner to narrow communica-tion between the intelligent adapters (10) and the host (12) to a single intelligent adapter (10) without first specifying a unique port address. The narrow process involves causing the intelligent adapter to first rank themselves for communication with the host by referring to unique ordered value in-formation, e.g., an identification serial number, stored in the nonvolatile storage element (122), such as an EEPROM element (220), placed on the adapter (10).
Description
2 1 6 5 8 3 I PCT~S94/07867 ' METHOD FOR CONFIGURING MULTIPLE ADAPTER CARDS
ON A BUS
BACKGROUND OF THE INVENTION
This invention relates to the field of adapter connectivity and configuration setup techniques in computers which accept plug-in adapters, and more particularly to a computer with a true parallel connection bus where the l?ositioning of an adapter device at a connector on the bus is independent of intended operation.
A peripheral or interface apparatus for a computer system, commonly known as an adapter, performs tasks between a central processing unit (CPU) with its related circuitry (.e.g., random access memory) and peripheral devices, such as a video display, a printer, a mass storage device, a telecommunications device or a network. These tasks include of reception, buffering processing and transmission of data. Each adapter must be configured to operate properly within its environment.
In the past, adapters have been rendered distinguishable by the placement position on a quasi-parallel bus structure (a bus which has position-sensitive or numbered connectors), such as found in the Extended ISA (EISA) environment or the MicroChannel environment, and/or by use of manual switches whereby the access or base address of the adapter in the memory space or Input/Output space of the processor is physically preset manually. In a true bus environment, such as is the case for the ISA bus, selective adapter placement is not possible and the manual setting of switches is not convenient or practical in some instances.
It is desirable to eliminate physical switches altogether and to enable "soft" configuration of an adapter. What would be highly useful is a mechanism whereby any a~apter type equipped with appropriate automating elements can be electronically configured WO95/03581 2 1 6 5 8 3 1 PCT~Sg4/07867 and automatically identified so that physical switch setting can be eliminated and/or so the adapter can be rendered insensitive to slot positioning.
S SUMMARY OF THE INVENTION
According to the invention, in a computer system having a central processing unit which employs software drivers as part of a host for controlling peripheral units and including a parallel signal bus for connecting with adapters for the peripheral units, wherein each adapter has distributed intelligence means for interpreting simple command information and a nonvolatile storage element for storing default configuration information, including a default port address for communication, a method is provided for configuring such intelligent adapters connected to the bus. The method includes initializing the intelligent adapters by applying power to the bus or by issuing a global reset signal and causing a driver to be loaded by the central processing unit so that the host broadcasts an initiation key which consists of a sequence of write commands via the bus to any adapters on the bus to elicit responses from the intelligent adapters in an interactive manner to narrow communication between the intelligent adapters and the host to a single intelligent adapter without first specifying a unique port address. The narrowing process involves prompting the intelligent adapters to first rank themselves for communication with the host by referring to unique ordered value information, e.g., an identification serial number, stored in the nonvolatile storage element, such as an EEPROM element, placed on the adapter, and then having identified itself in the hierarchy, defer attempts at communication to other adapters having a higher rank. The adapter having the highest rank is then free to interactively communicate over the bus and to accept and report information without interference from other adapters.
Specifically, each intelligent adapter does not automatically invoke the default configuration upon initialization other than the default port address, but rather starts with an WO9S/03581 2 1 6 5 8 3 1 PCT~S94/07867 arbitration procedure. Each driver, which is loaded by the host and is to be used for enabling communication between the central processing unit and the adapter, causes a broadcast on the bus of an identification request sequence (Write ID Sequence) to prompt all initialized intelligent adapters into a command state and to return contents of a specific word add~ess in the nonvolatile storage element. Thereafter, the host and all of the intelligent adapters interact using a primitive distributed intelligence means, i.e., a state machine, in a Read and Contend protocol which references the adapter's identification serial number value, each of which is unique to each adapter, to cause each adapter in turn to decide for itself whether it is the highest serial numbered adapter. Once an adapter has been noted as being the highest ranking active adapter, the host tags the ranking adapter with a tag and dismisses the ranking adapter, the tag assigning the adapter a unique identity. Adapters which have been tagged do not participate in the subsequent contention schemes which rank the remaining adapters. The host can select the tagged adapters by tags. The host can then command the selected adapter to activate some or all of the default configuration based on information stored in the nonvolatile storage unit. The command can also cause the host and the tagged adapter to lock onto a port address other than the default port address.
In subsequent interaction with the remaining adapters, substantially identical drivers are installed, and a similar protocol is followed until all of the adapters have been configured and enabled with unique port addresses. The tags may be used by the adapters themselves to streamline the read and contend protocol.
The invention eliminates jumpers and switches, relying merely on an EEPROM element, which is a nonvolatile programmable element, for all configuration information. Use of multiple, initially identical adapters are allowed in a true bus environment without danger of port contention.
A key feature of the setup procedure is control and WO95/03581 2 1 6 5 8 3 l PCT~S94/07867 attention to contention. The adapter is not rendered visible to other adapters on the bus until after automatic configuration logic has completed its reading of the EEPROM element and its loading of the configuration registers. A further understanding of the nature S and advantage of this invention may be realized by reference to the remaining portions of the specification and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram of pertinent portions of a host computer, host bus and an adapter unit according to the present nventlon.
Fig. 2 is a block diagram of a portion of a memory space of a host computer.
Fig. 3 is a process diagram of the automatic configuration sequence according to the invention.
DESCRIPTION OF SPECIFIC EMBODIMENTS
Referring to Fig. 1, a block diagram is shown of a portion of an interconnection of an exemplary adapter 10 which could be used according to the present invention with a client host central processing unit 12 connected via a true parallel bus, herein a host bus 20, such as an ISA bus, and intended to communicate with the adapter 10 through a software driver 14. The adapter 10 illustrated is merely an example showing part of the functional units and is not intended to be limiting as to the type of adapter which could be used in accordance with the invention.
Adapter 10 comprises a number of elements coupled to the host bus 20. The adapter 10 components enclosed by a dotted line indicate that this circuitry may all be contained within a single Application Specific Integrated Circuit (ASIC) 210. Adapter 10 may also employ an EEPROM 220, a nonvolatile digital storage device, coupled to the ASIC 210 to provide, in response to commands, certain data, such as i) an adapter identification term, which is unique for each adapter 10, which is also called a serial number stored in a specific memory location (Serial No. 222), ii) a ~ wo 95tO3~81 2 1 6 5 ~ 3 1 PCT~S94/07867 default adapter I/O base address, stored in a location called the I/O base configuration 224, and additional default adapter configuration descriptions, stored in locations such as herein called resource configuration 226. Also contained within and employed throughout the ASIC 210 are other circuit components which may be specific to a particular adapter function but which are not pertinent to the present invention.
The ASIC 210 includes host interface state machines 240, namely, simple logic elements to respond to commands received through the host bus. Among the state machines 240 is an ID
sequence state machine 242, which is coupled to a selected bit line 22 of the host bus 20 through a wired-OR-type driver circuit 250 for driving the selected bit line 22 and through a conventional receiver circuit 252 for reading signals on that selected bit line 22. (The key element is an open collector driver, an open drain driver or any circuit whose signal can be read and compared with local source data and which is subject to override by action by other drivers applying logic signals to a common node.) Also in the ASIC 210 are volatile storage registers, including an I/O base register 124 for receiving and storing the I/O base 224 from the EEPROM 220, othe] resource configuration registers 126 for receiving and storing the resource configurations 226 from the EEPROM 220 and a serial number register 122 for receiving and storing the serial number 222 for the adapter 10.
These registers are accessible within the ASIC 210 during applied power periods. In the absence of applied power, the registers store nothing, since the EEPROM 220 stores all such information without power, as it is nonvolatile.
The ASIC 210 also contains a tag register 128, as hereinafter explained, and it may also include an ID-port address register 130 (which could be a hardwired element specifying a common default port address used for the ID sequence state machine for contention).
The problem of having multiple adapters initially addressable at the same default port local:ion of host computer I/O
WO95/03581 2 1 6 5 ~ 3 1 PCT~Sg4/07867 ~
space is illustrated in Fig. 2. The host computer memory space 110 has in it an area set aside for a software driver 14. More importantly host I/O space 113 has a default base address 117 associated therewith. The I/O base address 117 is accessible to any adapter monitoring the port addresses 115 through the host bus 20 (Fig. 1). Thus, any instruction directed by the host 12 to the I/O base address 117 through the software driver 14 will elicit a response from all units, devices or adapters monitoring or sharing that address, thereby causing intolerable communication interference on the host bus 20.
According to the invention, after power up or a global reset or a specific command, the adapter 10 is not visible to the host 12 until after the automatic configuration logic in the form of the host i~nterface state machine 240 has completed an5 identification sequence and after the adapter address has been set.
Fig. 3 is a flow chart of a method according to the invention. An adapter 10 powers up or a global reset is invoked.
At the outset, the adapter 10 is prevented from using the default resources and is isolated from the host bus 20 (Step A). The adapter 10, not yet under- control of the software driver 14, thereupon retrieves the contents of the EEPROM 220 for the serial number (location 222) and stores the serial number in the serial number register 122 of the host (Step B). (At this point, the contents of EEPROM may also be loaded to the I/O base address register 124 and other resource configuration registers 126.) Since the contents of each EEPROM are being transferred to a physical location on each associated adapter and not to the bus 20, and since there is no information returned to the host 10, there is at this poi~t no concern about interference among adapters. In connection with this initialization, all adapters 10 monitor all of the I/O address space 113 or a selected subset. When the ID
sequence as hereinafter explained is written to a particular I/O
address, that address is stored by the adapter 10 in the ID port address register 130 as the ID port 114, and then the ID sequence state machine 242 enters the command state. Specifically, the host ~ WO9~/03581 2 1 6 5 ~ 3 ~ PCT~S94/07867 writes a complete ID sequence, one byte at a time to the address which is to become the ID port 114 while the adapter 10 watches for the exact ID sequence of bytes in the I/O address space (Step C).
Thereafter, the host 12 initiates a contention protocol by reading from the ID port 114 on the host bus 20 (Step D). The contention protocol is a "mask for ID" se~Iuence wherein one bit at a time is read by the host 12, read and compared by the adapter 10 with its own serial number, namely the value in the serial number register 122. The host 12 issues a read command to the host bus 20, each read returning one bit of a serial number from the serial number register 122. Each time a read is done, the adapter 10 reads bit line 22 through the wired-OR logic element 250 and compares the bit with its own corresponding bit from the serial number register 122 through receiver 257. Contention logic is invoked to determine if it is the lowest serial number. The ID
sequence state machine 242 returns the serial number one bit at a time. If it has issued a zero (0 or voltage low on an open collector driver, which is considered by this convention to be of highest ranking) through the driver 250, it expects to see a zero 20 (0) at the receiver 252. The ID sequence state machine 242 compares the corresponding bit in the serial number register 122 with the data from receiver 252 to determine if there is a match.
If there is a match, the process continues with issuance of the next bit.
If there are multiple adapters in the system and one of them drives out a one (1) while the adapter of interest drives out a zero (0) on the bit line 22 of the host data bus 20, then, due to the wired-OR logic, both adapters will read a zero (o) on the bit line 22. The contention test continues with each bit. If the data does not compare (Step E) with the data driven out, then the ID
sequence state machine 242 has a contention failure (Step F). This is a signal to cause the adapter 10 to go into an inactive state (Step F). It will wait for a next ID sequence.
Specifically, the adapter 10 tests itself to determine if it is the highest ranking adapter (lowest serial number 0 not 1) WO95/03581 2 1 6 5 8 3 1 PCT~S94/07867 still on the bus and if so, the host 12 configures the adapter 10 (Step G), tags the adapter 10 for future referënce with a value placed in the tag register 128, and dismisses the adapter 10 (Step H). The content of the tag register 128 can be read by the software driver 14 and used to identify the adapter 10 and possibly select the adapter 10 for later access. The writing of the ID
sequence continues (Step I) for the remaining adapters which had contention failure.
Since serial numbers are by definition unique, only the single adapter with the highest ranking serial number (closest to zero) will be active at the end of the contention sequence. This adapter 10 can then communicate uniquely, i.e., without interference from the other adapters, with the software driver 14 of the host 12 (Step J).
Multiple software drivers and multiple adapters can be loaded and set up in a similar automatic manner. Once the first software driver 14 has been loaded and has established communication uniquely with an adapter, additional drivers can be activated and the content of the Tag register can be used to uniquely identify each adapter on the bus without repeating the entire ID sequence.
The invention has now been explained with reference to specific embodiments. Other embodiments will be apparent to those of ordinary skill in the art. It is therefore not intended that this invention be limited, except as indicated by the appended claims.
ON A BUS
BACKGROUND OF THE INVENTION
This invention relates to the field of adapter connectivity and configuration setup techniques in computers which accept plug-in adapters, and more particularly to a computer with a true parallel connection bus where the l?ositioning of an adapter device at a connector on the bus is independent of intended operation.
A peripheral or interface apparatus for a computer system, commonly known as an adapter, performs tasks between a central processing unit (CPU) with its related circuitry (.e.g., random access memory) and peripheral devices, such as a video display, a printer, a mass storage device, a telecommunications device or a network. These tasks include of reception, buffering processing and transmission of data. Each adapter must be configured to operate properly within its environment.
In the past, adapters have been rendered distinguishable by the placement position on a quasi-parallel bus structure (a bus which has position-sensitive or numbered connectors), such as found in the Extended ISA (EISA) environment or the MicroChannel environment, and/or by use of manual switches whereby the access or base address of the adapter in the memory space or Input/Output space of the processor is physically preset manually. In a true bus environment, such as is the case for the ISA bus, selective adapter placement is not possible and the manual setting of switches is not convenient or practical in some instances.
It is desirable to eliminate physical switches altogether and to enable "soft" configuration of an adapter. What would be highly useful is a mechanism whereby any a~apter type equipped with appropriate automating elements can be electronically configured WO95/03581 2 1 6 5 8 3 1 PCT~Sg4/07867 and automatically identified so that physical switch setting can be eliminated and/or so the adapter can be rendered insensitive to slot positioning.
S SUMMARY OF THE INVENTION
According to the invention, in a computer system having a central processing unit which employs software drivers as part of a host for controlling peripheral units and including a parallel signal bus for connecting with adapters for the peripheral units, wherein each adapter has distributed intelligence means for interpreting simple command information and a nonvolatile storage element for storing default configuration information, including a default port address for communication, a method is provided for configuring such intelligent adapters connected to the bus. The method includes initializing the intelligent adapters by applying power to the bus or by issuing a global reset signal and causing a driver to be loaded by the central processing unit so that the host broadcasts an initiation key which consists of a sequence of write commands via the bus to any adapters on the bus to elicit responses from the intelligent adapters in an interactive manner to narrow communication between the intelligent adapters and the host to a single intelligent adapter without first specifying a unique port address. The narrowing process involves prompting the intelligent adapters to first rank themselves for communication with the host by referring to unique ordered value information, e.g., an identification serial number, stored in the nonvolatile storage element, such as an EEPROM element, placed on the adapter, and then having identified itself in the hierarchy, defer attempts at communication to other adapters having a higher rank. The adapter having the highest rank is then free to interactively communicate over the bus and to accept and report information without interference from other adapters.
Specifically, each intelligent adapter does not automatically invoke the default configuration upon initialization other than the default port address, but rather starts with an WO9S/03581 2 1 6 5 8 3 1 PCT~S94/07867 arbitration procedure. Each driver, which is loaded by the host and is to be used for enabling communication between the central processing unit and the adapter, causes a broadcast on the bus of an identification request sequence (Write ID Sequence) to prompt all initialized intelligent adapters into a command state and to return contents of a specific word add~ess in the nonvolatile storage element. Thereafter, the host and all of the intelligent adapters interact using a primitive distributed intelligence means, i.e., a state machine, in a Read and Contend protocol which references the adapter's identification serial number value, each of which is unique to each adapter, to cause each adapter in turn to decide for itself whether it is the highest serial numbered adapter. Once an adapter has been noted as being the highest ranking active adapter, the host tags the ranking adapter with a tag and dismisses the ranking adapter, the tag assigning the adapter a unique identity. Adapters which have been tagged do not participate in the subsequent contention schemes which rank the remaining adapters. The host can select the tagged adapters by tags. The host can then command the selected adapter to activate some or all of the default configuration based on information stored in the nonvolatile storage unit. The command can also cause the host and the tagged adapter to lock onto a port address other than the default port address.
In subsequent interaction with the remaining adapters, substantially identical drivers are installed, and a similar protocol is followed until all of the adapters have been configured and enabled with unique port addresses. The tags may be used by the adapters themselves to streamline the read and contend protocol.
The invention eliminates jumpers and switches, relying merely on an EEPROM element, which is a nonvolatile programmable element, for all configuration information. Use of multiple, initially identical adapters are allowed in a true bus environment without danger of port contention.
A key feature of the setup procedure is control and WO95/03581 2 1 6 5 8 3 l PCT~S94/07867 attention to contention. The adapter is not rendered visible to other adapters on the bus until after automatic configuration logic has completed its reading of the EEPROM element and its loading of the configuration registers. A further understanding of the nature S and advantage of this invention may be realized by reference to the remaining portions of the specification and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram of pertinent portions of a host computer, host bus and an adapter unit according to the present nventlon.
Fig. 2 is a block diagram of a portion of a memory space of a host computer.
Fig. 3 is a process diagram of the automatic configuration sequence according to the invention.
DESCRIPTION OF SPECIFIC EMBODIMENTS
Referring to Fig. 1, a block diagram is shown of a portion of an interconnection of an exemplary adapter 10 which could be used according to the present invention with a client host central processing unit 12 connected via a true parallel bus, herein a host bus 20, such as an ISA bus, and intended to communicate with the adapter 10 through a software driver 14. The adapter 10 illustrated is merely an example showing part of the functional units and is not intended to be limiting as to the type of adapter which could be used in accordance with the invention.
Adapter 10 comprises a number of elements coupled to the host bus 20. The adapter 10 components enclosed by a dotted line indicate that this circuitry may all be contained within a single Application Specific Integrated Circuit (ASIC) 210. Adapter 10 may also employ an EEPROM 220, a nonvolatile digital storage device, coupled to the ASIC 210 to provide, in response to commands, certain data, such as i) an adapter identification term, which is unique for each adapter 10, which is also called a serial number stored in a specific memory location (Serial No. 222), ii) a ~ wo 95tO3~81 2 1 6 5 ~ 3 1 PCT~S94/07867 default adapter I/O base address, stored in a location called the I/O base configuration 224, and additional default adapter configuration descriptions, stored in locations such as herein called resource configuration 226. Also contained within and employed throughout the ASIC 210 are other circuit components which may be specific to a particular adapter function but which are not pertinent to the present invention.
The ASIC 210 includes host interface state machines 240, namely, simple logic elements to respond to commands received through the host bus. Among the state machines 240 is an ID
sequence state machine 242, which is coupled to a selected bit line 22 of the host bus 20 through a wired-OR-type driver circuit 250 for driving the selected bit line 22 and through a conventional receiver circuit 252 for reading signals on that selected bit line 22. (The key element is an open collector driver, an open drain driver or any circuit whose signal can be read and compared with local source data and which is subject to override by action by other drivers applying logic signals to a common node.) Also in the ASIC 210 are volatile storage registers, including an I/O base register 124 for receiving and storing the I/O base 224 from the EEPROM 220, othe] resource configuration registers 126 for receiving and storing the resource configurations 226 from the EEPROM 220 and a serial number register 122 for receiving and storing the serial number 222 for the adapter 10.
These registers are accessible within the ASIC 210 during applied power periods. In the absence of applied power, the registers store nothing, since the EEPROM 220 stores all such information without power, as it is nonvolatile.
The ASIC 210 also contains a tag register 128, as hereinafter explained, and it may also include an ID-port address register 130 (which could be a hardwired element specifying a common default port address used for the ID sequence state machine for contention).
The problem of having multiple adapters initially addressable at the same default port local:ion of host computer I/O
WO95/03581 2 1 6 5 ~ 3 1 PCT~Sg4/07867 ~
space is illustrated in Fig. 2. The host computer memory space 110 has in it an area set aside for a software driver 14. More importantly host I/O space 113 has a default base address 117 associated therewith. The I/O base address 117 is accessible to any adapter monitoring the port addresses 115 through the host bus 20 (Fig. 1). Thus, any instruction directed by the host 12 to the I/O base address 117 through the software driver 14 will elicit a response from all units, devices or adapters monitoring or sharing that address, thereby causing intolerable communication interference on the host bus 20.
According to the invention, after power up or a global reset or a specific command, the adapter 10 is not visible to the host 12 until after the automatic configuration logic in the form of the host i~nterface state machine 240 has completed an5 identification sequence and after the adapter address has been set.
Fig. 3 is a flow chart of a method according to the invention. An adapter 10 powers up or a global reset is invoked.
At the outset, the adapter 10 is prevented from using the default resources and is isolated from the host bus 20 (Step A). The adapter 10, not yet under- control of the software driver 14, thereupon retrieves the contents of the EEPROM 220 for the serial number (location 222) and stores the serial number in the serial number register 122 of the host (Step B). (At this point, the contents of EEPROM may also be loaded to the I/O base address register 124 and other resource configuration registers 126.) Since the contents of each EEPROM are being transferred to a physical location on each associated adapter and not to the bus 20, and since there is no information returned to the host 10, there is at this poi~t no concern about interference among adapters. In connection with this initialization, all adapters 10 monitor all of the I/O address space 113 or a selected subset. When the ID
sequence as hereinafter explained is written to a particular I/O
address, that address is stored by the adapter 10 in the ID port address register 130 as the ID port 114, and then the ID sequence state machine 242 enters the command state. Specifically, the host ~ WO9~/03581 2 1 6 5 ~ 3 ~ PCT~S94/07867 writes a complete ID sequence, one byte at a time to the address which is to become the ID port 114 while the adapter 10 watches for the exact ID sequence of bytes in the I/O address space (Step C).
Thereafter, the host 12 initiates a contention protocol by reading from the ID port 114 on the host bus 20 (Step D). The contention protocol is a "mask for ID" se~Iuence wherein one bit at a time is read by the host 12, read and compared by the adapter 10 with its own serial number, namely the value in the serial number register 122. The host 12 issues a read command to the host bus 20, each read returning one bit of a serial number from the serial number register 122. Each time a read is done, the adapter 10 reads bit line 22 through the wired-OR logic element 250 and compares the bit with its own corresponding bit from the serial number register 122 through receiver 257. Contention logic is invoked to determine if it is the lowest serial number. The ID
sequence state machine 242 returns the serial number one bit at a time. If it has issued a zero (0 or voltage low on an open collector driver, which is considered by this convention to be of highest ranking) through the driver 250, it expects to see a zero 20 (0) at the receiver 252. The ID sequence state machine 242 compares the corresponding bit in the serial number register 122 with the data from receiver 252 to determine if there is a match.
If there is a match, the process continues with issuance of the next bit.
If there are multiple adapters in the system and one of them drives out a one (1) while the adapter of interest drives out a zero (0) on the bit line 22 of the host data bus 20, then, due to the wired-OR logic, both adapters will read a zero (o) on the bit line 22. The contention test continues with each bit. If the data does not compare (Step E) with the data driven out, then the ID
sequence state machine 242 has a contention failure (Step F). This is a signal to cause the adapter 10 to go into an inactive state (Step F). It will wait for a next ID sequence.
Specifically, the adapter 10 tests itself to determine if it is the highest ranking adapter (lowest serial number 0 not 1) WO95/03581 2 1 6 5 8 3 1 PCT~S94/07867 still on the bus and if so, the host 12 configures the adapter 10 (Step G), tags the adapter 10 for future referënce with a value placed in the tag register 128, and dismisses the adapter 10 (Step H). The content of the tag register 128 can be read by the software driver 14 and used to identify the adapter 10 and possibly select the adapter 10 for later access. The writing of the ID
sequence continues (Step I) for the remaining adapters which had contention failure.
Since serial numbers are by definition unique, only the single adapter with the highest ranking serial number (closest to zero) will be active at the end of the contention sequence. This adapter 10 can then communicate uniquely, i.e., without interference from the other adapters, with the software driver 14 of the host 12 (Step J).
Multiple software drivers and multiple adapters can be loaded and set up in a similar automatic manner. Once the first software driver 14 has been loaded and has established communication uniquely with an adapter, additional drivers can be activated and the content of the Tag register can be used to uniquely identify each adapter on the bus without repeating the entire ID sequence.
The invention has now been explained with reference to specific embodiments. Other embodiments will be apparent to those of ordinary skill in the art. It is therefore not intended that this invention be limited, except as indicated by the appended claims.
Claims (7)
1. A method for configuring a selected adapter unit on a host bus of a host computer in the presence of multiple adapter units, said selected adapter unit and each said multiple adapter units capable of having an initially identical port address in address space of the host computer, the method comprising the steps of:
initializing said selected adapter unit and said multiple adapter units to prevent said selected adapter unit and said multiple adapter units from responding to read commands from the host computer via the host bus and to initially load a volatile adapter identification register means of said selected adapter unit and said multiple adapter units with at least said adapter serial number, which is unique; thereafter broadcasting, by means of a driver of said host computer, a start sequence via the host bus to enable said selected adapter unit and said multiple adapter units to command logic means of said selected adapter unit and said multiple adapter units to be prepared to respond to a contention protocol causing said selected adapter unit and said multiple adapter units to contend for a right of access to the host computer via the host bus, wherein each read command from the host returns a single bit of the serial number such that as each bit of the serial number is driven from said adapter to the host bus at a selected bit position through a wired-OR-type driver circuit; said adapter monitors the selected bit position of the bus to verify a match with its data; thereafter recognizing, by means of logic means in said selected adapter unit and said multiple adapter units, that said multiple adapter units do not meet criteria for being granted access to the base address and allowing said selected adapter unit having the highest ranking unique serial number to respond without interference; and enabling, by means of the logic means in said selected adapter unit, the selected adapter unit to communicate with the host computer via the driver means.
initializing said selected adapter unit and said multiple adapter units to prevent said selected adapter unit and said multiple adapter units from responding to read commands from the host computer via the host bus and to initially load a volatile adapter identification register means of said selected adapter unit and said multiple adapter units with at least said adapter serial number, which is unique; thereafter broadcasting, by means of a driver of said host computer, a start sequence via the host bus to enable said selected adapter unit and said multiple adapter units to command logic means of said selected adapter unit and said multiple adapter units to be prepared to respond to a contention protocol causing said selected adapter unit and said multiple adapter units to contend for a right of access to the host computer via the host bus, wherein each read command from the host returns a single bit of the serial number such that as each bit of the serial number is driven from said adapter to the host bus at a selected bit position through a wired-OR-type driver circuit; said adapter monitors the selected bit position of the bus to verify a match with its data; thereafter recognizing, by means of logic means in said selected adapter unit and said multiple adapter units, that said multiple adapter units do not meet criteria for being granted access to the base address and allowing said selected adapter unit having the highest ranking unique serial number to respond without interference; and enabling, by means of the logic means in said selected adapter unit, the selected adapter unit to communicate with the host computer via the driver means.
2. The method according to claim 1 wherein said enabling step includes configuring the adapter.
3. The method according to claim 1 wherein said enabling step includes:
accepting instructions from the host computer to establish an adapter configuration description other than a default adapter configuration description such that each adapter is assigned unique resources.
accepting instructions from the host computer to establish an adapter configuration description other than a default adapter configuration description such that each adapter is assigned unique resources.
4. A method for configuring a selected adapter unit on a host bus of a host computer in the presence of multiple adapter units, said selected adapter unit and each said multiple adapter units having an initially unknown port address in address space of the host computer, the method comprising the steps of:
providing in said selected adapter unit and said multiple adapter units nonvolatile storage means with records of serial number, which is unique for said selected adapter unit and said multiple adapter units, a default adapter I/O base address, and a default adapter configuration description;
providing volatile register means in said selected adapter unit and said multiple adapter units for active storage of said adapter serial number, said adapter I/O base address and said adapter configuration description;
providing an identification sequence state machine means in said adapter unit and said multiple adapter units for controlling access via the host bus to said select adapter unit and multiplier;
providing in said selected adapter unit and in said multiple adapter units at a selected bit position of the host bus an open-drain-type driver circuit for use in a wired-OR logic function when coupled to the host bus;
providing driver logic means at the host computer for broadcasting commands and for reading and writing information on the host bus; thereafter initializing said selected adapter unit and said multiple adapter units to prevent said selected adapter unit and said multiple adapter units from responding to accesses to resources from the host computer via the host bus other than a default I/O
port, and to initially load said volatile register means with at least said adapter serial number; thereafter broadcasting by means of the driver logic means a command via the host bus to cause said selected adapter unit and said multiple adapter units to respond to a contention protocol;
thereafter causing said selected adapter unit and said multiple adapter units to contend for right to access to the host bus, by:
i) writing in response to a host-issued read access command by means of said identification sequence state machine a write bit value of said adapter serial number in sequence to said selected bit position through said open drain-type-driver circuit; thereupon at the end of the writing step ii) reading by means of said identification sequence state machine said selected bit position for a read bit value;
thereafter iii) comparing the write bit value and the read bit value for a match; and iv) if there is a match, repeating with steps i), ii) and iii) for a next bit value, until a complete sequence has been read; and v) if there is not a match, noting a contention failure and terminating the contending steps for said multiple adapter unit;
such that said selected adapter unit, which has the highest adapter serial number, is alone active at the default port address on the host bus; and enabling by means of the identification sequence state machine the selected adapter unit to communicate with the host computer via the driver means.
providing in said selected adapter unit and said multiple adapter units nonvolatile storage means with records of serial number, which is unique for said selected adapter unit and said multiple adapter units, a default adapter I/O base address, and a default adapter configuration description;
providing volatile register means in said selected adapter unit and said multiple adapter units for active storage of said adapter serial number, said adapter I/O base address and said adapter configuration description;
providing an identification sequence state machine means in said adapter unit and said multiple adapter units for controlling access via the host bus to said select adapter unit and multiplier;
providing in said selected adapter unit and in said multiple adapter units at a selected bit position of the host bus an open-drain-type driver circuit for use in a wired-OR logic function when coupled to the host bus;
providing driver logic means at the host computer for broadcasting commands and for reading and writing information on the host bus; thereafter initializing said selected adapter unit and said multiple adapter units to prevent said selected adapter unit and said multiple adapter units from responding to accesses to resources from the host computer via the host bus other than a default I/O
port, and to initially load said volatile register means with at least said adapter serial number; thereafter broadcasting by means of the driver logic means a command via the host bus to cause said selected adapter unit and said multiple adapter units to respond to a contention protocol;
thereafter causing said selected adapter unit and said multiple adapter units to contend for right to access to the host bus, by:
i) writing in response to a host-issued read access command by means of said identification sequence state machine a write bit value of said adapter serial number in sequence to said selected bit position through said open drain-type-driver circuit; thereupon at the end of the writing step ii) reading by means of said identification sequence state machine said selected bit position for a read bit value;
thereafter iii) comparing the write bit value and the read bit value for a match; and iv) if there is a match, repeating with steps i), ii) and iii) for a next bit value, until a complete sequence has been read; and v) if there is not a match, noting a contention failure and terminating the contending steps for said multiple adapter unit;
such that said selected adapter unit, which has the highest adapter serial number, is alone active at the default port address on the host bus; and enabling by means of the identification sequence state machine the selected adapter unit to communicate with the host computer via the driver means.
5. The method according to claim 4 wherein said selected adapter unit is isolated and provided with a tag for reference against participation, including said selected adapter unit, in further contention.
6. The method according to claim 4 wherein said enabling step includes:
accepting instructions from the host computer to establish an adapter configuration description to other than the default adapter configuration description.
accepting instructions from the host computer to establish an adapter configuration description to other than the default adapter configuration description.
7. An apparatus for use in a host computer and a selected adapter unit to configure the adapter unit in the presence of multiple adapter units, said apparatus comprising:
a nonvolatile storage means in the selected adapter unit with records of an adapter serial number, a default adapter base address, and a default adapter configuration description for the adapter unit;
a volatile register means in the selected adapter unit for active storage of said adapter serial number, an adapter base address and an adapter configuration description;
an identification sequence state machine means in said adapter unit for controlling access via the host bus to said volatile register means;
a wired-OR-type driver circuit in the adapter unit at a selected bit position of the host bus for use in a wired-OR logic function;
driver logic means at the host computer for broadcasting commands and for reading and writing information on the host bus;
said identification sequence state machine including contention logic for allowing said selected adapter unit to select for itself a base address in address space of the host computer, said contention logic including:
i) means for writing a write bit value of said adapter serial number in sequence to said selected bit position; thereupon at the end of the writing step ii) means for reading said selected bit position for a read bit value; thereafter iii) means for comparing the write bit value and the read bit value for match; and iv) means, if there is a match, for repeatedly writing, reading and comparing until a complete sequence has been read; and v) if there is not a match, means for noting failure of contention in the adapter unit and terminating the contention;
such that the selected adapter, if it has a highest adapter sequence is set uniquely at a selected address of the host bus; and means for enabling the selected adapter unit to communicate with the host computer via the driver means.
a nonvolatile storage means in the selected adapter unit with records of an adapter serial number, a default adapter base address, and a default adapter configuration description for the adapter unit;
a volatile register means in the selected adapter unit for active storage of said adapter serial number, an adapter base address and an adapter configuration description;
an identification sequence state machine means in said adapter unit for controlling access via the host bus to said volatile register means;
a wired-OR-type driver circuit in the adapter unit at a selected bit position of the host bus for use in a wired-OR logic function;
driver logic means at the host computer for broadcasting commands and for reading and writing information on the host bus;
said identification sequence state machine including contention logic for allowing said selected adapter unit to select for itself a base address in address space of the host computer, said contention logic including:
i) means for writing a write bit value of said adapter serial number in sequence to said selected bit position; thereupon at the end of the writing step ii) means for reading said selected bit position for a read bit value; thereafter iii) means for comparing the write bit value and the read bit value for match; and iv) means, if there is a match, for repeatedly writing, reading and comparing until a complete sequence has been read; and v) if there is not a match, means for noting failure of contention in the adapter unit and terminating the contention;
such that the selected adapter, if it has a highest adapter sequence is set uniquely at a selected address of the host bus; and means for enabling the selected adapter unit to communicate with the host computer via the driver means.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/093,380 US5420987A (en) | 1993-07-19 | 1993-07-19 | Method and apparatus for configuring a selected adapter unit on a common bus in the presence of other adapter units |
| US08/093,380 | 1993-07-19 | ||
| PCT/US1994/007867 WO1995003581A1 (en) | 1993-07-19 | 1994-07-13 | Method for configuring multiple adapter cards on a bus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2165831A1 true CA2165831A1 (en) | 1995-02-02 |
Family
ID=22238608
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002165831A Abandoned CA2165831A1 (en) | 1993-07-19 | 1994-07-13 | Method for configuring multiple adapter cards on a bus |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US5420987A (en) |
| EP (1) | EP0710376B1 (en) |
| JP (1) | JPH09500467A (en) |
| AU (1) | AU7361494A (en) |
| CA (1) | CA2165831A1 (en) |
| DE (1) | DE69428538T2 (en) |
| WO (1) | WO1995003581A1 (en) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW276312B (en) * | 1992-10-20 | 1996-05-21 | Cirrlis Logic Inc | |
| US5594874A (en) * | 1993-09-30 | 1997-01-14 | Cirrus Logic, Inc. | Automatic bus setting, sensing and switching interface unit |
| US5522086A (en) * | 1993-10-29 | 1996-05-28 | Sierra Semiconductor Canada, Inc. | Software configurable ISA bus card interface with security access read and write sequence to upper data bits at addresses used by a game device |
| US5787246A (en) * | 1994-05-27 | 1998-07-28 | Microsoft Corporation | System for configuring devices for a computer system |
| US5748980A (en) * | 1994-05-27 | 1998-05-05 | Microsoft Corporation | System for configuring a computer system |
| US6763454B2 (en) | 1994-05-27 | 2004-07-13 | Microsoft Corp. | System for allocating resources in a computer system |
| US5655148A (en) * | 1994-05-27 | 1997-08-05 | Microsoft Corporation | Method for automatically configuring devices including a network adapter without manual intervention and without prior configuration information |
| US5701515A (en) * | 1994-06-16 | 1997-12-23 | Apple Computer, Inc. | Interface for switching plurality of pin contacts to transmit data line and plurality of pin contacts to receive data line to interface with serial controller |
| US5666557A (en) * | 1994-06-16 | 1997-09-09 | Cassidy; Bruce Michael | Method and apparatus for automatically assigning device identifiers on a parallel data bus |
| US5727184A (en) * | 1994-06-27 | 1998-03-10 | Cirrus Logic, Inc. | Method and apparatus for interfacing between peripherals of multiple formats and a single system bus |
| US5794014A (en) * | 1994-06-27 | 1998-08-11 | Cirrus Logic, Inc. | Method and apparatus for interfacing between peripherals of multiple formats and a single system bus |
| US5892972A (en) * | 1995-06-07 | 1999-04-06 | Cirrus Logic, Inc. | Method of constructing a plug and play compatible bus card which allows for mass production of the bus card |
| US5732220A (en) * | 1995-08-04 | 1998-03-24 | International Business Machines Corporation | Method and apparatus for testing device bus resource resolution |
| US5768618A (en) * | 1995-12-21 | 1998-06-16 | Ncr Corporation | Method for performing sequence of actions in device connected to computer in response to specified values being written into snooped sub portions of address space |
| WO1998038044A2 (en) | 1997-02-28 | 1998-09-03 | Roberto Olvera Camacho | Method for obtaining a tabulation to display a range of colours which can be reproduced with accuracy |
| US6181030B1 (en) * | 1999-03-30 | 2001-01-30 | International Business Machines Corporation | Computer power supply system having switched remote voltage sensing and sense voltage averaging for hot pluggable adapter cards |
| DE10147757C2 (en) * | 2001-09-27 | 2003-07-31 | Siemens Ag | Method for configuring a system with several peripheral modules as well as system and connectors for implementing the method |
| US6718284B2 (en) | 2002-01-30 | 2004-04-06 | Cirris Systems Corporation | Smart module and adapter apparatus |
| US6886051B2 (en) * | 2002-03-28 | 2005-04-26 | Seagate Technology Llc | Device discovery method and apparatus |
| US7218730B2 (en) * | 2003-08-13 | 2007-05-15 | International Business Machines Corporation | System and method for analysis and filtering of signals in a telecommunications network |
| US20050050187A1 (en) * | 2003-09-03 | 2005-03-03 | International Business Machines Corporation | Method and apparatus for support of bottleneck avoidance in an intelligent adapter |
| US20060284876A1 (en) * | 2005-06-15 | 2006-12-21 | Low Yun S | Method and apparatus for programming an input/output device over a serial bus |
| US7904872B2 (en) * | 2008-05-22 | 2011-03-08 | International Business Machines Corporation | System-on-chip (SOC), design structure and method |
| US7962661B2 (en) * | 2008-06-30 | 2011-06-14 | Lg Chem, Ltd. | System and method for determining a bus address for a controller within a network |
| US8904049B2 (en) | 2012-08-23 | 2014-12-02 | Lg Chem, Ltd. | Battery pack monitoring system and method for assigning a binary ID to a microprocessor in the battery pack monitoring system |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4387425A (en) * | 1980-05-19 | 1983-06-07 | Data General Corporation | Masterless and contentionless computer network |
| US4660141A (en) * | 1983-12-06 | 1987-04-21 | Tri Sigma Corporation | Self configuring computer network with automatic bus exchange of module identification numbers and processor assigned module numbers |
| US4766536A (en) * | 1984-04-19 | 1988-08-23 | Rational | Computer bus apparatus with distributed arbitration |
| US4775931A (en) * | 1984-05-11 | 1988-10-04 | Hewlett-Packard Company | Dynamically configured computing device |
| US4727475A (en) * | 1984-05-18 | 1988-02-23 | Frederick Kiremidjian | Self-configuring modular computer system with automatic address initialization |
| US4773005A (en) * | 1984-09-07 | 1988-09-20 | Tektronix, Inc. | Dynamic address assignment system |
| EP0606102A1 (en) * | 1986-09-19 | 1994-07-13 | International Business Machines Corporation | An input output interface controller connecting a synchronous bus to an asynchronous bus and methods for performing operations on the buses |
| DE3685114D1 (en) * | 1986-10-30 | 1992-06-04 | Ibm | "DAISY-CHAIN" CONFIGURATION FOR BUS ACCESS. |
| US4980850A (en) * | 1987-05-14 | 1990-12-25 | Digital Equipment Corporation | Automatic sizing memory system with multiplexed configuration signals at memory modules |
| US5111423A (en) * | 1988-07-21 | 1992-05-05 | Altera Corporation | Programmable interface for computer system peripheral circuit card |
| US5175822A (en) * | 1989-06-19 | 1992-12-29 | International Business Machines Corporation | Apparatus and method for assigning addresses to scsi supported peripheral devices |
| EP0419750B1 (en) * | 1989-09-26 | 1994-11-30 | International Business Machines Corporation | Distribution mechanism for establishing communications between user interfaces of a communication system |
| US5204951A (en) * | 1989-10-02 | 1993-04-20 | International Business Machines Corporation | Apparatus and method for improving the communication efficiency between a host processor and peripheral devices connected by an scsi bus |
| IL96808A (en) * | 1990-04-18 | 1996-03-31 | Rambus Inc | Integrated circuit i/o using a high performance bus interface |
| US5237690A (en) * | 1990-07-06 | 1993-08-17 | International Business Machines Corporation | System for testing adaptor card upon power up and having disablement, enablement, and reconfiguration options |
| US5343478A (en) * | 1991-11-27 | 1994-08-30 | Ncr Corporation | Computer system configuration via test bus |
-
1993
- 1993-07-19 US US08/093,380 patent/US5420987A/en not_active Expired - Lifetime
-
1994
- 1994-07-13 EP EP94922545A patent/EP0710376B1/en not_active Expired - Lifetime
- 1994-07-13 AU AU73614/94A patent/AU7361494A/en not_active Abandoned
- 1994-07-13 WO PCT/US1994/007867 patent/WO1995003581A1/en active IP Right Grant
- 1994-07-13 DE DE69428538T patent/DE69428538T2/en not_active Expired - Fee Related
- 1994-07-13 JP JP7505203A patent/JPH09500467A/en active Pending
- 1994-07-13 CA CA002165831A patent/CA2165831A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| EP0710376B1 (en) | 2001-10-04 |
| AU7361494A (en) | 1995-02-20 |
| US5420987A (en) | 1995-05-30 |
| JPH09500467A (en) | 1997-01-14 |
| EP0710376A4 (en) | 1996-12-04 |
| DE69428538D1 (en) | 2001-11-08 |
| WO1995003581A1 (en) | 1995-02-02 |
| EP0710376A1 (en) | 1996-05-08 |
| DE69428538T2 (en) | 2002-05-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0710376B1 (en) | Method for configuring multiple adapter cards on a bus | |
| US5491804A (en) | Method and apparatus for automatic initialization of pluggable option cards | |
| US5787306A (en) | Automatic assignment of I/O addresses in a computer system | |
| CA1335843C (en) | Programmable option select | |
| US6012103A (en) | Bus interface system and method | |
| US4964038A (en) | Data processing system having automatic address allocation arrangements for addressing interface cards | |
| US5978862A (en) | PCMCIA card dynamically configured in first mode to program FPGA controlling application specific circuit and in second mode to operate as an I/O device | |
| US5974475A (en) | Method for flexible multiple access on a serial bus by a plurality of boards | |
| US5628027A (en) | Method of determining the configuration of devices installed on a computer bus | |
| US5263168A (en) | Circuitry for automatically entering and terminating an initialization mode in a data processing system in response to a control signal | |
| JPH0775014B2 (en) | Device and method for loading BIOS on computer | |
| EP0595960A1 (en) | Computer workstation expansion chassis | |
| US20060206286A1 (en) | Method to reduce IPMB traffic and improve performance for accessing sensor data | |
| JPH08278927A (en) | Reprogrammable network communication apparatus and reprogramming method of network communication apparatus | |
| JPH0812651B2 (en) | Data processing system and method of operating data processing system | |
| US6601165B2 (en) | Apparatus and method for implementing fault resilient booting in a multi-processor system by using a flush command to control resetting of the processors and isolating failed processors | |
| US4899274A (en) | Dynamic terminal address allocation by the terminal itself in a data processing system | |
| JP3310990B2 (en) | Electronics | |
| JPH08255118A (en) | Network communication equipment | |
| US5537663A (en) | System for determining configuration of devices installed on a computer bus by comparing response time of data lines to read from I/O address when undriven | |
| US7386711B1 (en) | Method and apparatus for redirecting the boot operations of one or more systems | |
| US5329634A (en) | Computer system with automatic adapter card setup | |
| US4729091A (en) | Directing storage requests prior to address comparator initialization with a reference address range | |
| US5922055A (en) | Method for determining a type of a serial EEPROM and plug and play controller | |
| JPS63116258A (en) | Data processing system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Discontinued |