CA2172233A1 - Slant-Surface Silicon Wafer Having a Reconstructed Atomic-Level Stepped Surface Structure - Google Patents

Slant-Surface Silicon Wafer Having a Reconstructed Atomic-Level Stepped Surface Structure

Info

Publication number
CA2172233A1
CA2172233A1 CA2172233A CA2172233A CA2172233A1 CA 2172233 A1 CA2172233 A1 CA 2172233A1 CA 2172233 A CA2172233 A CA 2172233A CA 2172233 A CA2172233 A CA 2172233A CA 2172233 A1 CA2172233 A1 CA 2172233A1
Authority
CA
Canada
Prior art keywords
silicon wafer
slant
surface structure
level stepped
stepped surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA2172233A
Other languages
French (fr)
Other versions
CA2172233C (en
Inventor
Lei Zhong
Norihiro Shimoi
Yoshio Kirino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Coorstek KK
Original Assignee
Toshiba Ceramics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP7087595A external-priority patent/JPH08264780A/en
Priority claimed from JP08759395A external-priority patent/JP3827166B2/en
Priority claimed from JP08759495A external-priority patent/JP3827167B2/en
Application filed by Toshiba Ceramics Co Ltd filed Critical Toshiba Ceramics Co Ltd
Publication of CA2172233A1 publication Critical patent/CA2172233A1/en
Application granted granted Critical
Publication of CA2172233C publication Critical patent/CA2172233C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Abstract

A single crystal silicon wafer is sliced off so as to have a slant surface that is inclined from plane (001) such that the normal of the slant surface is inclined by 0.01° to 0.2° from direction [001] toward direction [110]. After being cleaned, the silicon wafer is heat-treated at 600-1, 300°C for not less than 1 minute in an ultrapure argon or hydrogen atmosphere containing nitrogen at not more than 0.1 ppm, to thereby cause the slant surface to have a stepped crystal surface structure. The stepped crystal surface structure is constituted of step walls Sa and Sb when it has been formed by a heat treatment in an argon atmosphere, and substantially all of its step walls are of a type Sb when it has been formed by a heat treatment in a hydrogen atmosphere.
CA002172233A 1995-03-20 1996-03-20 Slant-surface silicon wafer having a reconstructed atomic-level stepped surface structure Expired - Fee Related CA2172233C (en)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
JP7087595A JPH08264780A (en) 1995-03-20 1995-03-20 Semiconductor element
JP08759395A JP3827166B2 (en) 1995-03-20 1995-03-20 Method for forming surface structure of inclined surface silicon wafer
JP08759495A JP3827167B2 (en) 1995-03-20 1995-03-20 Method for forming surface structure of inclined surface silicon wafer
JP7-87595 1995-03-20
JP7-87594 1995-03-20
JP7-87593 1995-03-20

Publications (2)

Publication Number Publication Date
CA2172233A1 true CA2172233A1 (en) 1996-09-21
CA2172233C CA2172233C (en) 2001-01-02

Family

ID=27305551

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002172233A Expired - Fee Related CA2172233C (en) 1995-03-20 1996-03-20 Slant-surface silicon wafer having a reconstructed atomic-level stepped surface structure

Country Status (5)

Country Link
US (1) US5966625A (en)
KR (1) KR100200973B1 (en)
CA (1) CA2172233C (en)
DE (1) DE19611043B4 (en)
TW (1) TW323382B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6645834B2 (en) 2000-11-09 2003-11-11 Shin-Etsu Handotai Co., Ltd. Method for manufacturing annealed wafer and annealed wafer

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DE19712561C1 (en) * 1997-03-25 1998-04-30 Siemens Ag Silicon carbide semiconductor device e.g. lateral or vertical MOSFET
US20070122997A1 (en) 1998-02-19 2007-05-31 Silicon Genesis Corporation Controlled process and resulting device
US5994207A (en) 1997-05-12 1999-11-30 Silicon Genesis Corporation Controlled cleavage process using pressurized fluid
JP3346249B2 (en) * 1997-10-30 2002-11-18 信越半導体株式会社 Heat treatment method for silicon wafer and silicon wafer
US6881644B2 (en) * 1999-04-21 2005-04-19 Silicon Genesis Corporation Smoothing method for cleaved films made using a release layer
US6204151B1 (en) 1999-04-21 2001-03-20 Silicon Genesis Corporation Smoothing method for cleaved films made using thermal treatment
US6171965B1 (en) 1999-04-21 2001-01-09 Silicon Genesis Corporation Treatment method of cleaved film for the manufacture of substrates
US6287941B1 (en) 1999-04-21 2001-09-11 Silicon Genesis Corporation Surface finishing of SOI substrates using an EPI process
JP2001048694A (en) * 1999-08-02 2001-02-20 Sumitomo Electric Ind Ltd Gallium.arsenic single crystal wafer and gallium.arsenic liquid phase epitaxial wafer
JP3910004B2 (en) * 2000-07-10 2007-04-25 忠弘 大見 Semiconductor silicon single crystal wafer
US6569741B2 (en) * 2000-09-25 2003-05-27 Texas Instruments Incorporated Hydrogen anneal before gate oxidation
US7749910B2 (en) * 2001-07-04 2010-07-06 S.O.I.Tec Silicon On Insulator Technologies Method of reducing the surface roughness of a semiconductor wafer
FR2827078B1 (en) * 2001-07-04 2005-02-04 Soitec Silicon On Insulator METHOD FOR REDUCING SURFACE ROUGHNESS
US7883628B2 (en) * 2001-07-04 2011-02-08 S.O.I.Tec Silicon On Insulator Technologies Method of reducing the surface roughness of a semiconductor wafer
JP4190906B2 (en) * 2003-02-07 2008-12-03 信越半導体株式会社 Silicon semiconductor substrate and manufacturing method thereof
JP2004296496A (en) * 2003-03-25 2004-10-21 Fujitsu Ltd Method of manufacturing semiconductor device
US7542197B2 (en) * 2003-11-01 2009-06-02 Silicon Quest Kabushiki-Kaisha Spatial light modulator featured with an anti-reflective structure
JP2008060355A (en) * 2006-08-31 2008-03-13 Sumco Corp Laminated wafer, and manufacturing method therefor
US8993410B2 (en) 2006-09-08 2015-03-31 Silicon Genesis Corporation Substrate cleaving under controlled stress conditions
US7811900B2 (en) 2006-09-08 2010-10-12 Silicon Genesis Corporation Method and structure for fabricating solar cells using a thick layer transfer process
US8293619B2 (en) 2008-08-28 2012-10-23 Silicon Genesis Corporation Layer transfer of films utilizing controlled propagation
US9362439B2 (en) 2008-05-07 2016-06-07 Silicon Genesis Corporation Layer transfer of films utilizing controlled shear region
JP2009094156A (en) * 2007-10-04 2009-04-30 Tohoku Univ Semiconductor substrate and semiconductor device
US8330126B2 (en) 2008-08-25 2012-12-11 Silicon Genesis Corporation Race track configuration and method for wafering silicon solar substrates
US8329557B2 (en) 2009-05-13 2012-12-11 Silicon Genesis Corporation Techniques for forming thin films by implantation with reduced channeling
DE102011122749A1 (en) * 2011-12-30 2013-07-25 Helmholtz-Zentrum Berlin Für Materialien Und Energie Gmbh Process for surface preparation of Si (100) substrates.

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Publication number Priority date Publication date Assignee Title
JPS5617011A (en) * 1979-07-23 1981-02-18 Toshiba Corp Semiconductor device and manufacture thereof
JPS61274313A (en) * 1985-05-29 1986-12-04 Mitsubishi Electric Corp Semiconductor device
US4803173A (en) * 1987-06-29 1989-02-07 North American Philips Corporation, Signetics Division Method of fabrication of semiconductor device having a planar configuration
US4931132A (en) * 1988-10-07 1990-06-05 Bell Communications Research, Inc. Optical control of deposition of crystal monolayers
US5141893A (en) * 1988-12-22 1992-08-25 Ford Microelectronics Growth of P type Group III-V compound semiconductor on Group IV semiconductor substrate
US4987094A (en) * 1989-06-02 1991-01-22 Bell Communications Research, Inc. Method of making a macroscopic stepped structure on a vicinally cut crystal
US5230768A (en) * 1990-03-26 1993-07-27 Sharp Kabushiki Kaisha Method for the production of SiC single crystals by using a specific substrate crystal orientation
JPH03290975A (en) * 1990-04-09 1991-12-20 Fujitsu Ltd Vertical type semiconductor device
JP2892170B2 (en) * 1990-07-20 1999-05-17 株式会社東芝 Heat treatment film formation method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6645834B2 (en) 2000-11-09 2003-11-11 Shin-Etsu Handotai Co., Ltd. Method for manufacturing annealed wafer and annealed wafer

Also Published As

Publication number Publication date
KR970067547A (en) 1997-10-13
DE19611043B4 (en) 2006-02-16
CA2172233C (en) 2001-01-02
KR100200973B1 (en) 1999-06-15
TW323382B (en) 1997-12-21
US5966625A (en) 1999-10-12
DE19611043A1 (en) 1996-10-02

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