CA2177728A1 - Procede de verrouillage de phase et boucle appliquant ce procede - Google Patents
Procede de verrouillage de phase et boucle appliquant ce procedeInfo
- Publication number
- CA2177728A1 CA2177728A1 CA2177728A CA2177728A CA2177728A1 CA 2177728 A1 CA2177728 A1 CA 2177728A1 CA 2177728 A CA2177728 A CA 2177728A CA 2177728 A CA2177728 A CA 2177728A CA 2177728 A1 CA2177728 A1 CA 2177728A1
- Authority
- CA
- Canada
- Prior art keywords
- signal
- phase
- frequency correction
- frequency
- loop
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010354 integration Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
Abstract
L'invention concerne le verrouillage de la phase d'un signal de sortie (Ys) par rapport à un signal d'entrée (Ye). Un premier signal de correction de fréquence (Yr1) est obtenu par intégration d'un signal représentatif d'un écart de ladite phase par rapport à une référence définie par le signal d'entrée . Puis il coopère avec un deuxième signal de correction de fréquence (Yr2) pour corriger la fréquence d'un oscillateur (VC0) fournissant le signal de sortie. Ce deuxième signal de correction de fréquence est obtenu avec l'aide d'un signal de réglage (Yg) par intégration d'un écart du premier signal de correction de fréquence (Yr1) par rapport à ce signal de réglage. Ce dernier peut lui-même être obtenu par intégration d'un écart de fréquence .
L'invention s'applique notamment aux systèmes de télécommunications.
L'invention s'applique notamment aux systèmes de télécommunications.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9506458 | 1995-05-31 | ||
FR9506458A FR2734967B1 (fr) | 1995-05-31 | 1995-05-31 | Procede de verrouillage de phase et boucle appliquant ce procede |
Publications (2)
Publication Number | Publication Date |
---|---|
CA2177728A1 true CA2177728A1 (fr) | 1996-12-01 |
CA2177728C CA2177728C (fr) | 1999-06-15 |
Family
ID=9479541
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA002177728A Expired - Fee Related CA2177728C (fr) | 1995-05-31 | 1996-05-29 | Procede de verrouillage de phase et boucle appliquant ce procede |
Country Status (6)
Country | Link |
---|---|
US (1) | US5684844A (fr) |
EP (1) | EP0746110B1 (fr) |
CA (1) | CA2177728C (fr) |
DE (1) | DE69617528T2 (fr) |
ES (1) | ES2168450T3 (fr) |
FR (1) | FR2734967B1 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5804831A (en) * | 1997-05-15 | 1998-09-08 | Casco Products Corporation | Liquid level sensor for use in a hot, pressurized liquid |
US6172571B1 (en) | 1998-07-28 | 2001-01-09 | Cypress Semiconductor Corp. | Method for reducing static phase offset in a PLL |
JP5243042B2 (ja) * | 2005-12-09 | 2013-07-24 | ソニー株式会社 | 音楽編集装置及び音楽編集方法 |
US7777541B1 (en) | 2006-02-01 | 2010-08-17 | Cypress Semiconductor Corporation | Charge pump circuit and method for phase locked loop |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4297728A (en) * | 1979-04-06 | 1981-10-27 | Lowe Virgil L | Charged coupled device time base corrector system |
US4404530A (en) * | 1980-10-22 | 1983-09-13 | Data General Corporation | Phase locked loop with compensation for loop phase errors |
DE3407582A1 (de) * | 1984-03-01 | 1985-09-05 | Dornier System Gmbh, 7990 Friedrichshafen | Schaltungsanordnung fuer einen regelkreis |
US4745371A (en) * | 1985-08-02 | 1988-05-17 | Libera Developments Limited | Phase-locked digital synthesizer |
US4686689A (en) * | 1986-07-24 | 1987-08-11 | Graham-Patten Systems, Inc. | Phase-locked loop circuit |
US5319680A (en) * | 1991-09-03 | 1994-06-07 | The Whitaker Corporation | Phase locked loop synchronization system for use in data communications |
US5570398A (en) * | 1994-05-02 | 1996-10-29 | Seagate Technology, Inc. | Method and apparatus for dynamic pole-zero reconfiguration for use with hard disc drive servos, electronic filters and other circuits |
-
1995
- 1995-05-31 FR FR9506458A patent/FR2734967B1/fr not_active Expired - Fee Related
-
1996
- 1996-05-24 EP EP96401134A patent/EP0746110B1/fr not_active Expired - Lifetime
- 1996-05-24 ES ES96401134T patent/ES2168450T3/es not_active Expired - Lifetime
- 1996-05-24 DE DE69617528T patent/DE69617528T2/de not_active Expired - Fee Related
- 1996-05-29 CA CA002177728A patent/CA2177728C/fr not_active Expired - Fee Related
- 1996-05-30 US US08/655,143 patent/US5684844A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
ES2168450T3 (es) | 2002-06-16 |
US5684844A (en) | 1997-11-04 |
EP0746110A1 (fr) | 1996-12-04 |
FR2734967B1 (fr) | 1997-07-04 |
CA2177728C (fr) | 1999-06-15 |
FR2734967A1 (fr) | 1996-12-06 |
DE69617528T2 (de) | 2002-08-01 |
DE69617528D1 (de) | 2002-01-17 |
EP0746110B1 (fr) | 2001-12-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EEER | Examination request | ||
MKLA | Lapsed |