CA2185901A1 - Improvements in an apparatus and method of use of radiofrequency identification tags - Google Patents

Abstract

A radiofrequency identification tag integrated circuit is provided with an antifuse circuit (10) for field programmability at high speed and low power using transient radiofrequency pulses, a self-calibration circuit (38, 40, 44, 46, 48, 50) for calibrating a receiver oscillator (34) with an external calibration reference signal, a communications bit and frame synchronization circuit (72, 74) for recognizing a received unique pattern violating an error detection code check, a carrier signal modulation (80, 82, 84) scheme for remotely supplying data and power to the tag, and a power supply rectifier including Schottky diodes (96, 98, 100, 102) fabricated on sapphire (106) or a passivated surface (122) for inter-diode isolation and isolation from other circuits.

Description

wo 96n3308 2 1 8 5 9 ~ 1 PCTIUSg6lon853 IMPROVEMENTS IN AN APPARATUS AND METHOD OF USE OF
RADIOFREQUENCY IDENTIFICATION TAGS

Background of the Invention 1. ~ield of the Invention The invention relates to radiofrequency identifir~tiQn devices used to tag or identify objects, and in particular to radiofrequency idPntific~sion devices that may be transiently programmed, remotely self-calibrated for synchlol~ion, remotely powered during data commnnication, and imrlemPntPd using a high frequency isolated monolithic rectifier.

2. Description of the Prior Art Low Power Antifuse RFID Memory A radiofrequency idPntific~tion device or tag (hereinafter referred to throughout this specific~tiQ~ as an "RFID tag") is a device which can be ~tt~hPd or ~cco~i~ted with another object, which the R~ID tag is then used to identify when queried remotely by an interrogating circuit. The RF~ tag is thus preprogl~l,med, or progr~mm~hle afterassociation with the object to return a signal to the interrogating circuit to provide sPIected i~fulllla~ion concerning the att~chPd object which is within the zone of the interrogating 2 5 circuit. More simply, a small electronic tag is ~tt~çhçd to an object and the tag is read by a reader. New data can be added to the tag by a progl ~,nlll~l, and the data received from the tag can either be read from a display screen, stored or later down-loaded to a personal comrutPr~ or linked directly to a col~lpLIler system.
RF~ tags have an advantage over bar codes and bar code readers which pe.rulm 3 0 similar filnctiorlc in that the RFID tag may be imhedded within the object and still be read as long as the interlying material bet~e.l the RFID tag and the reader is not conductive.
Thtlc;fol~, line of sight is not required for an RFID tag, which is required in any type of bar code reader. This allows the RF~ tag to function in very difficult en~h on~ s. Further, the RFID tag has the capacity for having digital data being added after it is ~ rltPd to the object, has a greater data capacity and can be read at dict~nres far greater than those achievable through optical bar code readers.

SUBSTITUTE SHEET (RULE 26) To date the cost of RFID tags, however has limited the market penetration of thedevice because of the high cost acQoçistted with such RF~ tags.
Ishihara et al., "Antifuse Memory Device with Switched C~ritQr Semng Me~hod," U.S. Patent 5,299152 (1994) describes a capacitively charged pump circuit in 5 which signals are applied to gates to charge pump a capacitive element for the purposes of subjecting an antifuse coupled to the cztrz~citor to dielectric breakdown for progl~lu~ung purposes. The charge pump is certainly not transient and required cortsi~Prable power, making both the circuitry and methodology impractical for most RFID tags.
Thel~;~re what is needed is an RFID tag which can be mzlmlfztcttlred at low cost, 10 pro~;,~,~",cd and run at low energies prog.a.~uned in the field and still retain each of the advantages of RFID tags over the bar codes as dicc~lQQed above.

Self-Calibration of Timingfor an RFID Tag A persistent problem with low power R~ tags is the remote calibration of the 15 circuit to allow u~ll,~Lion sent to the RFID tag to be decoded accurately. If the clock signals or disc,;...;n~l;on levels are not propc~ly calibrated on the RFID tag properly, or if such calibration is not ll-A;-l~h;llPd as en~,~o~ l circn ,~ n~ps of the tag çhztnges~ then transfer of il~lllla~ion to and from the tag becQt--es unreliable. First conQ;~Pr some prior art self-calibration sch~ e5 used in other applic~z~tions 2 0 Gof~m, ~, "Met~wd and A~u,u~s for a Cali~rated Electronic Timing Circuit, "
U.S. Patent 5 117 756 (1992) adjusts an internal osçillator by co..")&h-g its output to a control signal. A precision calibration pulse is applied to the timing circuit which counts the output cycles of a variable frequency oscillator during the period of the pulse. This count is stored and co",pared to the lê~r~nce count to produce an error count. The error 25 count is cnmhined with a previously stored control signal to produce a new control signal that drives the output of the os~illz~tor to a new frequency.
Goffin's calibration circuit is used for a calibrated time delay circuit for delayed ignition of explosive products. The appliGz~tion is to 111;~ 11;7P, the effects of rock blasting on nearby structures by reducing peak-to-peak zlmplihlde of frequency of ground vibration 3 0 produced by the blast by timing the ignition of the plurality of explosive charges. Gof~ln achieves this with an onboard calibration pulse derived from a time ~ert;rence and then calibrates the detonation timing circuitry to it in order to collll~enc~le for flllctllzltion SUBSTITUTE SHEET (RULE 26) wo 96/23308 2 1 8 5 9 0 1 PCTtUS9~ 853 ambient te~ re, hurnidity and pressure that may cause a variation in the local osrill~tor rate. Goffin is not concelllr d with a remote comml~n~ tion circuit, but rather with calibration of a plurality of deton-.tor circuits with each other, all connr~cted by hard w~ng.
Weaver, "Electronic Frequency Control for Radio Receivers," U.S. Patent 2,S01,883 (1950), also generally describes a circuit which adjusts an intemal oscillator by colll~.ali.~g its output to a control signal. Weaver's object is to provide a local beat frequency and proper frequency relationship to a carrier. In particular, Weaver seeks to keep a local oscillator ~ cted to generate a wave having substantially the same frequency 10 rel~tionchip to the received carrier as existed before a carrier fade co.l~ ced. Weaver achieves this by colllbil~lg a wave derived from the received carrier with a locally generated r~ nce wave to produce a controlling voltage whose m~gnihl~e and polarity are de~ ed by the vector sum or di~ ,..ce ofthe co...billed waves. A re~ct~n~e tube is connPcted to control the frequency generated by the osçill~tsr. The grid of the rear,~ e 15 tube is collpled to two biasing circuits, which are in tum driven by the controlling voltage.
IIlÇu~ ion ll;~ ed to an RF~ tag is decoded either by deter ting the variation in the ~mplihlde (AM) or frequency or equivalently the phase shift or tirne delay (FM) of the carrier signal, dr~ nrl;..g upon the commlmic~tign protocol which has been chosen as the standard. Changes in the ~-nplinlde of the carrier signal are econornically deter,ted by 20 convention~l RFID tag receivers, but are suscrplible to noise hl~t;lrele.lce. In the L~ ;c~iorl of digital i- Çulll~Lion, the loss of just a single bit of data can, if ina~.plùpliate, cause catastrophic co~eeq~1enr,es Detectio~ of a change of frequency is less suscepLiblc to noise i.ll~-rt;re. ce but requiles that the RFID tag receiver be capable of detertin~ changes in the carrier signal as 2 5 against a calibrated sLandard. R~ilD tag receivers typically rely on some type of internally tuned circuit to cOlll~ the incoming signal to the standard in order to detect the frequency variation. However, if the RFm tag receiver is depended upon the ;.~co~ p.
carrier signal as a reference itself, as is almost always the case with RFID tags, it is inhel~.lLly impossible to detect ~.h~nges in the inCorninP signal using sL~Id 3 0 techniques.
Theleru,t;, what is needed is a method whereby a remote RI~ID tag circuit can calibrate itself with respect to an input signal allowing for i-ll;~ll..aLion to be decoded after SUBSTITUTE SHEET (RULE 26) - 218590~
WO 96/23308 PCI'/US~6~ 5~

the comrletion of the calibration, which decoding would not have been possible before calibration.

Bit and Frame S~"-ch, u~ u~ion It is further well known that in every comml-nic~tion protocol some means is required to determine which bit is the first data bit in a digital data tr~ncmiccion This d~L~ ;on process becomes more difficult in wireless devices. Since the ~;.ric,~ g device may be at the extreme end of an opel~Ling range, noise and signal dropout make reliable detection of digital data ~iffir,lllt, as well as validation of s~,lcl~o~ t;on at both the bit and data frame levels.
Wireless devices typically move into and out of range quickly. Therefore, it is an advantage if the bit s~l,cl~ol-;,;.l;on is achieved in a minimllm of time so that the wireless device can start looking for the frame s~llch~o.-;,~l;on as soon as possible. Typically, the ability of the wireless device to do this makes a critical ~ ele.lce in whether the comm~lni ~tion is succeccfiJl or not.
In some RF~ tags a violation of the "normal" data protocol is used to identify the be~"";"~ of a data frame. Milheiser, U.S. Patent 4,730,188 teaches that using l~S~-rllP,l~Pr encotling defines a protocol that has a change of state every bit time. The data frame inch~d~ps a frame marker which cG~ ;.,c a p,.,~.l"ble with a specific bit pattem 2 0 followed by a violation of the ~nchpster bit timing protocol in which the rate of change of state is decreased to 1 1/2 bit times for 3 bit intervals, followed by the identification of the data in which the bit rate is restored. This type of bit sy~c}uo~u~lion is usable in Milheiser's application where the tag ~ "uls to a reader, but the RF~ tag does not receive coded data.
Even in ~ilhr:-e~s application, some disadvantages exist. Since Milheiser must first achieve bit s~,lch,o~ ;on the use of phase lock loop is nFc~Pcc~.y, which uses feedba~ of a received frequency tr~ncitiorl to adjust a rate to become syncl-rolfized. If the protocol violation occurs at that momPnt in time, the phase lock loop will attempt to ~y-lcl~oi~e to a rate 1/3 lower. The result is that the bit syncluo~ l;on is delayed in a 3 0 frame which could have been read but is not.
The prior art has also devised an alternative approach which is not subject to the disadvantages of the Milheiser protocol. According to this alternative approach, a unique SUBSTITUTE SHEET (RULE 26) wo 96n3308 2 1 8 5 9 0 1 Pcrlusg6mn8s3 data value is ~cci nPd as a frame marker, which unique value is then prohihited from being used as a data pattern. This approach allows for all or any part of the data frame to be used for a bit syncl-.un;~ ;o~ The unique data pattern must not be a pattern which the user would ever want to use in the data since it is prohihited to prevent ~mhi~lity If the unique 5 data pattern is required, an alias is created which is then tr~ncl~ted back to the prohibited value at a later time. This alias creation and retr~nclAtiûn is an awkward solution in most applic~Ation.c This approach also leads the user to choose a value such as all l's or all O's for the unique pattern. Such a pattern is not a practical choice since the memory in most 10 app~ tion devices is normally initi~li7Pd to either all 1's or O~s in any case.
Lee, "Faul~ and Error Detection Ar~ ",cnt," U.S. Patent 4,429,391 (1984), desc.ibes a fault and error detection rJ~ p.~ l for detectine ll,..,c,~ g and routing errors made in a central data l~ çr and receiver commllnic~tin~ with pt iph.,.~lcircuits in which parity bits of certain data words are ~ Pd by the central data 15 ~ er after being intpntionAlly inverted by central parity inverter in a known sequpn~e The pu~ose of the inversion every predetermined number of frame is used for a~llchro.l;~Al;on In particular, the central parity inverter inverts the parity bit every ninth data word in response to parity control signals IlA,.c...;lled by the seqnpn~e gen~ tor.
Thus, Lee looks for repetitive parity violation on a periodic basis in order to 20 es~blich timing. The dl~w~ , however, is in cases where there is signal fade which is common with RFID tag devices, an incllffirient number of sy.,cl;,lol~lion parity violations may have been received in order to reliably establish the pattern, or that the pattern may be unreliably ~l~.,c,..;lled thereby leading to subst~nti~l errors in s~ .hlon;~;onTerrab et al., "Method and Apparatus for Ensuring CRC Error Generation by a 2 5 Data C~,r,..,.,l"icalion Station Experiencing Tr ~ ".iller E~cceptions, " U.S. Patent 5,195,093 (1993), shows a unique code genelaLion scheme using parity change. Each byte of serial bit stream is seq~lçnti~lly ll~ e~ If a ll~..c...;ller exception occurs, the byte before the exception is ~ led normally. However, only the first seven bits of the last byte are ~ ed. The parity bit is sent as an eighth bit of the last byte c,~lalllhlg odd 30 parity fûr the previous bit stream. Therea~er, a byte even parity is sent to ensure the overall mpcc~e has odd parity. A receiving station interprets two concec~ltive bytes having SUBSTITUTE SHEET (RULE 26) 2 1 85~0 1 wo 96/23308 PCr/USg-lC~53 the predetemlined data pattem as the CRC, thus assuring that the receiving station will reject the frame.
The,~rore, what is needed is some type of method for achieving bit and frame syllclllu~ Al;on in digital signals ~ lclll;lled between radiofrequency i~entifir~tion tags and 5 readers or writers in a way which is very simple and yet efficient to ;Illpl~ llrll in an integrated circuit.

Data Communication and Power Typically R~ID systems l~ slllil a carrier signal and then divide down the carrier 10 frequency on the tag to use the signal as an intemal clock. The h~llllalion stored on the tag is then sequPnti~lly ~ le.l from the tag. A tag which opel~tes in this manner is a read-only tag. The h~llll_Lion in the tag must be entered during the m7mlf~çtllring of the tag by making direct electrical contact to external col~n~lUl~, or by having a battery or charged c~paçitQr physically connected to the tag.
There is a reco~i7pd need to be able to add hlrullllaLion into the R~ID tag remotely in the field rather than having inrolll,dlion loaded into the tag only during its m~mlf~etllre. Remote prog~ "";,l~ or wireless prog~ -e without any physical contact to the tag being made can only be ~ccomplichPd if power and h~llllalion are both ~upplied cirnlllt~nPollSIy to the tag. Progli.""";l-g the tag requires subst~nti~lly more power than 20 simply reading the tag. Prior art mPthotlc for remote pro~llllling rely on AM mndlll~tin~
the signal or FM ms)d~ ting the frequency to commllnir~tç with the tag. Again AM is susceptible to intelrtl~.lce through noise and FM requires ,cignifir~nt sensing or detectior circuitry to be built within the tag.
Consider first how the prior art has ll~"~ ed data and power on carrier sigIlals.
25 Kobayashi et al., "DigitallyRemote Control T~U,L~"~S~;rlnA~ IUS~"U.S. Patent4,914,428 (1990), describes the use of a time duration alteration between syll~lllo~ l;on signals. The lli1llclll;~ted coded digital instruction is composed of a sequenre of synch,ol~lion pulses having a predetermined period and data pulses which are inserted between the successive syllclll~ ;on pulses at predetermined positions dependent upon 30 whether data pulses rep~ese.ll a 0 or 1 bit. The receiving circuit dictin~lichp~s between the 0 and 1 bits by detecSing the length of the interval between the leading edge of a s-yllcl~ro,.;".l;o~ pulse and the leading edge of an ~ G~Pnt data pulse and d~Le~ lles the SUBSTITUTE SHEET (RULE 26) WO 96/23308 PCI/US~'C:~53 rYictpnce of noise if more than one data pulse is detected between succpccive syll~luu.~ t;rJn pulses. The length of each data word which is sent is concl~ regardless of the numbers of l's and O's in the word so that the detection of more than one data pulse b~;lween succeccive syllclllol~lion pulses of a co~ period is inte~ e~ed as being 5 noise. Kobayashi thus uses pulse delay in order to dictin~lich between binary O's and l's from a periodic timing pulse.
Stobbe et al. "Portable Field-Pro~ ".".able Detection Microchip, " U.S. Patent 5 218 343 (1993), shows a system for ~ c.ll;~ both power and i lro.lllation to a remote circuit using external charging cApacitQrs7 an internal oscillator an AM signal from the 10 chip, and a period variation to dictin~lich between binary O's and l's. The R~ID tag chip in Stobbe is provided with a cllar~ing c~pacitQr capable of storing electrical energy from the RF signal so that the microchip in the tag can be powered during pulse pauses of the RF
signal. The microchip incl~dçs a memory circuit for storing the idçntifi~tion code of the microchip in a code generator that is collpled to the memory circuit for gencl~ g an RF
15 signal that is modlll~t~d with the identific~tion data. A switching element detunes a ~sonan~ circuit in the llucloclu~ when the idPntific?~tion data is ~I; .c...;(led back to the read/write device. The reson&l~ circuit serves to field program the memory circuit of the microchip and the tag by receiving pulse/pause modlllAtiQn signals (PPM) of the RF carrier signal to allow the id~ntific~tiQn code of the tag to be altered. Stobbe describes a mixing 2 0 of cG.. .Ands and data by AM modlllAtion Kriofsky et al. "~nductively Coupled Tru~.~".il~er-Responder A~,"~,e~,.ent, " U.S.
Patent 3 859 624 (1975) describes a conventional low frequency RF~ tag which is powered through inductive coupling so that the tag generates uniquely coded h~,l,la~,on sent back to a reader. The coded info,l"alion is not however ~;.n~ ed as part of or 2 5 mot~ Atit~n of the inductive power signal.
Thelêîole what is needed is a method for delivering energy remotely to an RFID
tag while at the same time ~ llC.Il;~ infu""a~ion to the tag. Some means must be found whereby the carrier signal bro~dr~ctc to the tag can both deliver data which is sensed and power at the same time.

SUBSTITUTE SHEET (RULE 26) 218590~
WO 96/23308 PCIIUS96/On853 Rectifiersfor ~FID Tags In current designs for RFID tags, the carrier signals are rectified through the use of on-chip transistors which are typically slow, there being no need for fast response times. A
conventional full wave bridge rectifier using 4 diodes as depicted in Figure 9 is typically not 5 used in an RFID tag because the parasitic junctions formed in a conventional monolithic integrated circuit, by which such a diode bridge would be made, cause the structure to be inoperable in the application of an RFID tag.
Figure 10 is a cross section of a typical integrated circuit layout for a rectifier bridge as shown in Figure 9. Junctions 86 in the circuitry of Figure 10 become forward biased 10 when applying an AC signal on contactc 88 and 90 Co~ oltdl~lg to the same jllnGtione rerel..,ced in the sr~m~tic of Figure 9.
Trying to r'-mrns a transistor structure in a high frequency range such as 915 Megahertz or 2.5 Gigahertz in an R~ tag leads to even further difficllltips First, MOS
transistors must be scaled in order to operate at such speeds or a high speed bipolar device such as using a biCMOS process. Both types of transistor technology require a much higher cost to mqnllf~r*lre and the parasitic c~r~ n~e in such devices have a svl,~ lly greater effect as the frequency of operation is illcleased.
Ther~le, what is needed is a method of re~;Liryi~g a carrier signal ~ ed to an REID tag for the purposes of powering the tag which is not subject to the defects of the 2 0 prior art.

Brief Summary of the Invention The invention is a method of pro~""";ng a radiofrequency id~ ;r.calil)n device 2 5 comprising providing an antifuse in a memory cell coupled to a bit line in the radiofrequency idpntific~qtion device. A stray ç~pa~it~nr,e on the bit line is charged. The stray c~parit~nre is selectively dischhl~ed through the antifuse tO draw a high peak current from the charged stray c~par.it~nce to program the ~nfifil~e. As a result, the antifuse is programmed at high speed and low power.
Charging the stray c~pacit~n~e comprises charging the c~racit~nce to a voltage t ~ee~ g the antifuse prog,i-.. ;ng voltage. Typically chau~ng the stray c~pacitance on SUBSTITUTE SHEET (RULE 26) the bit line charges the c~pacit~nce with appro~lllalely 60 to 100 microwatts of power or less.
The selective discharging of the antifuse is performed in one embodiment by co~lpli..o the antifuse through a gated transistor to ground. The gated transistor has a 5 m~yimnm saturation current capacity. The antifuse has a pro~ l;llE time defined for a predetermined time duration. The stray c~p~cit~nce on the bit line is charged to a power level such that the saturation current is achieved through the antifuse and transistor during the progl~ g time of the ~ntifi~se p~pct~ted in another way the invention is a method of prog,~.lll.lng an antifusehaving a ,.. il.; .. pro~i.. i~.;ng time at high speed and low power COIIIyliSillg cl~ging a bit line col~pled to the antifuse to a predetermined voltage and thus stored predetermined power level. The bit line has a ~iha,geable c~r~c;~nce The bit line is dischalged through the ~ntifi)se at high speed s.. l.s~ lly equal to the .. ;.. ;... pro~;~ ;nE time r~4uil~,d by the antifuse to generate a voltage and current spike through the antifuse sllfficiPnt to 15 program the antifuse while utili7in~ low average power.
The invention is also a method for self-calibrating remote RFID tag circuitry coulpli~ulg receiving an eYtPrn~l signal having a chara~lel~ng p,..~..~Ler and receiving an internal signal having the chara~;lc.~ng p~.,ll~.ter. The characterizing pa~ of the extemal and internal signals are cGlll~,ared. An error signal indicative of the di~.w ce in 2 0 the characterizing p~ e.:, in the col.ll)ar~d extemal and intemal signals is gc~ aled. A
correction signal is generated which when applied to the remote circuit cG~p~c~tp~s the internal signal to allow for calibration to the extemal signal. As a result, the remote RF~D
tag circuit is calibrated with respect to the extemal signal for reliable and low cost comm~lnic~tinrl therewith.
2 5 Generating the correction signal cOI~ l ises gc.l~ illg an oscillator correction signal to adjust the intemal signal to within a predetermined tolerance of the external signal.
In an altemative embodiment gen~"a~illg the cn~ -e~ ;on signal cOIll~liscs g~"le~a~ g a correction factor for use in operation of the remote RFID tag circuit where the error in the characteristic parameter b~Lw~:en the extemal and internal signals remains 3 0 s~lbst~nti~lly cor.5l ~1 ~I during tirnes of operational interest of the remote RFID tag circuit.
The invention includes a method wl.c.eh~ operational characteristics of the remote RFID tag circuit change over tirne periods greater than those time periods of Op~aLiona SUBSTITUTE SHEET (RULE 26) WO 96/23308 PCI~/US9~ YS3 interest of the remote RFID tag circuit. The method further co~ ises repeating the steps of receiving the externalJinternal signals, col~ ing the characteristic pa.~lltlers gcn."~Lillg an error signal and generating a correction signal to update the cor.,~ AI;~
signal as the error signal ch~nges slowly over time.
In one particular embodiment gentlalh.g the correction signal comprises genF;-~ g a signal to select a co.npen~A.~ g RC time co~ to be coupled to the oscillator.
The invention is also defined as an apparatus for self-calibrating a remote RFID tag circuit co.n~.lisillg a colllp~lor coupled to an external signal and an internal signal which is to be calibrated with respect to the external signal. The colll~alor generates an error signal indicative of the di~ele,lce in a characteristic par~ll~,.er of the external and internal signals. A processing circuit is conpled to the col~ or and is re~polls;~e to the error signal to generate a co..~pe~-cAI;Qn signal which when applied to the remote RFID tag circuit allows for calibration of the internal signal from the remote RFID tag circuit to be calibrated to the extemal signal received by the remote circuit. As a result, the remote 15 RF~ tag circuit is provided with reliable ecQ~-o ..ic calibration for co"~ n:^~tion Thus it is understood that in one embodiment the a~p~a~lls further colll,cl;sFs a ~ ,.llGIy conFle~ to the processing circuit for storing the co,,,l.FI~c,,l;on signal to ...~;..1; ;~.
calibration of the remote RF~ tag circuit.
The a~pa~ s further co"""ises a oscill~tor in the remote circuit for ge"c~ali"g the 20 internal signal and an RC network having a plurality of sFIect~hle RC values. The collllJF ..c,ll ;on signal from the proceccing circuit selects one of the RC values for courlir~
to the osrill~tor in order to r..~;-.l~;.. a characteristic pa~ er of the internal signal calibrated within a predelellllil~ed tolerance to the external signal.
In another embodiment the CQ~ Cnc~l;on signal ge.lF.a~ed by the proce;,sil~g circuit 2 5 is a correction factor indicative of the error between the intemal and external signals. The correction factor is applied by the proceccing circuit to operations ~,vithin the remote RF~
tag circuit for ~ ;--l;3;n;--f~ reliable calibration to the external signal. In particular the correction signal is proportional to the ratio between the characteristic pdl~ullt~el for the external signal and the internal signal.
The invention is further defined as a method for providing data commllnic~tioll s~n~,hlu..i,,~l;Qn COIIIplisillg cl~çcLil~p a cQmmnniC~tion data stream having a predetermined error coll~ ;on protocol for an unique data bit pattern, and de~ fing whelher the SUBSTITUTE SHEET (RULE 26) 2 1 85~0 ~

unique data pattern also violates the error chPcL ;i~g protocol. The timing of the unique data pattern is used as a s~ h~oi-;7AI;on signal if the error chPrL ing protocol is violated.
As a result, bit and frame syllchlo~ AI;o~ is achieved anywhere within the data bit stream.
The unique pattern is a unique pattern which is typical of data normally received. In the 5 illustrated embodiment determining whether an error correction violation has occurred is a dele. l . .; ~ ;on of whether a parity error violation has occurred.
More specifir~lly the data stream is ol~.Lced into words and the unique data pattem collll~l.ses at least one word subject to the error correction protocol. The word has a bit length at least equal to a predetermined minimllm so that the probability of Clealing in 10 a normal data stream the unique pattern with error correction violation is less than a predeltll,~i,.ed acc~p~able ...;..;...~
The invention is an âp~alllS for providing a sy"ch~ ;on marker comprising an error correction circuit for receiving a data signal stream. A decoder checks the data signal stream for a unique pattem and cim~lh~nPollc parity error viol~tiorl The decoder is coupled 15 to the error correction circuit and ~ic~hles the error correction output in the event of Cimlllt~npious detectinn ofthe unique data pattern and error correction violation to gen~-ale a ~l.cluo~ .n signal. The error correction circuit is a parity checker.
The invention is a method of cimnlt~npoucly povv~;.ing and commllnir~ting data to a ~"~less remote RFID tag circuit comprising l.i...~.,.;ll;.~g a carrier signal to the circuit for providing power to the circuit. The carrier signal is modlll~ted to reduced levels using pulse widths equal to or less than a predel~;l.l"ned ~ The predeter-minpd m~timllm is del~.l.lined by the longest duration for which the carrier signal may be turned offbefore the remote R~ID tag circuit loses stored power to a degree suffiripnt to make operation of the remote RFID tag circuit ~ eliable.
The carrier signal is modl-l~ted by pulses having at least two tiictin~-ich~ble pulse widths. The pulse widths are correlated with ll~ ed h~l...alion to the remote RF~
tag circuit. In another embodiment the carrier signal is m~ ted by at least three pulses of di~ele.ll pulse widths to commnnir-~te binary data and control signals. The modlll~tion is at a frequency subst~nti~lly less than the carrier signal so that the remote circuit is 30 operated at the reduced frequency at lower power. For eY~mplYP7 the carrier signal is mod--l~ted with a duty cycle at or less than a predel~..lluned m~Yimllm as dclc:llluned by the minimllm duty cycle by which the remote RFID tag circuit will still reliably operate.

SUBSTITUTE SHEET (RULE 26) wos6/23308 Pcr/us~noss3 The invention is further an improvement in a diode rectifier having a plurality of diodes in an RF~D tag co~ ,lising an inc~ ting material disposed beneath and between each the diode in the rectifier to electrically isolate each diode from each other diode within the rectifier to prevent forward biasing of any of the diode junctions at high frequencies.
In one embo-limPnt the inc~ ting layer comprises an incnl~ting substrate upon which the diode is formed. For ~'A~ c, the substrate is sapphire and the diode is formed by a silicon-on-sal~phil~ process. In another embodiment the incnl~ting layer is a silicon substrate surface of an integrated circuit having an overlying oxide layer, and the diode is a stacked diode disposed on the oxide layer. The stacked diode is ~t;re~ably a Schottky diode operable at high frequency carrier sigflals at which the RFID tag is operated.
The invention may be better vis~1~1i7Pd by now turning to the following drawingswherein like çl..."~"lc are lert;rtnces by like numerals.

Brief Description of the Dl d~
Figure 1 is an ide~li7Pd sçl~ Al;c of a memory cell in which an antifuse is used and programmed in an R~ID tag.
Figure 2 is a timing diagram of the pro~l,.. ;n~ method of the invention used inthe memory cell of Figure l .
2 0 Figure 3 is a srhPrn~tic of a power of a self-calil.l ~l,llg circuit for an RFID tag.
Figure 4 is a flow diagram illustrating the operation of another embodiment of the invention where the circuit self-calibrates to a carrier signal.
Figure ~ is a block diagram of a circuit wherein the method of Figure 4 is used.Figure 6 is a block diagram of a circuit where a bit and frame s!~l,cl~oni~alion of the 2 5 invention is used.
Figure 7 is a wave diagram showing data ll~nc...;~i~;on on a power carrier signal.
Figure 8 is a wave diagram of an alternative embo~impnt showing data and controlsignal lli.nc...;cc jon on a power carrier signal.
Figure 9 is a sçhpm~tic of a convention~l full wave bridge rectifier.
Figure lO is a cross-section~l view of a conventional integrated circuit wherein the bfidge circuit of Figure 9 is implPmPnted SUBSTITUTE SHEET (RULE 26) 2'~ 859Q ~
WO 96/23308 PCrlUS96/00853 Figure 11 is a cross-section~l view of a integrated circuit SOS diode for use in the bridge circuit of Figure 9 in an RFID tag.
Figure 12 is a cross-section~l view of a integrated circuit stacked diode for use in the bridge circuit of Figure 9 in an RFID tag.
5The invention may now be better understood by turning to the following detaileddescription.

Detailed Description of the Preferred Embodiments 10Low Power Antifuse 12FID Memory First con~idPr a method of prog,~,.. ;.. g or writing to an RFID tag with a transient pulse at both high and low frequ~Pn~i~s i.e. in the GHz and KHz ranges. As will become clear below, pro~,i.. ino an RIilD tag using Ll~rls;c.ll pulses rather than a long duration re~ ted signal aUows for less control circuitry, less prog~i .. ;np time less energy, less 1 5 cost and power requ,lc",e.,ls for the R~ID tag.
In the prior art, pro~i.. ;np. of RFID tags was typically jmpl~Pmented through optically (ultraviolet) and electrically erasable p.og~ hle technologies that require a voltage or current pulse of a certain value for a spe~ifip~d period to be applied to the RFID
tag. For ~ Iplf., an optically erasable device must have a .. ;~.;.. , of 10 volts applied to 2 0 the device while supplying a current of the order of 0.5 milli~mps for at least 1 milli~econtl In electrically e~asablc memories the voltage requi,~;"l~nl is typically a minimnm of 15 volts for at least I milli~ecQn~l although current req.~"t;"l~.lLs may reach as low as 100 mlcl ~ S.
The advantages of the invention are realized by utili7in~ an electrically 2 5 prog~ "able element which requires very little energy to program. Such an element is an antifuse such as described in U.S. Patents 4 442,507; 4 796 074; and 5 095 362 which are hlcOllJolated herein by lefe,ence. The voltage on the stray nodal discl~ge c~ Git~nre in the ~ntifilce device is exploited to provide s-ffi~ip~nt energy to program the antifuse structure.
3 0 Consider the i-lP~Ii7~Pd s~ -n~l ;C diagram of Figure 1, showing an antifuse memory elemPnt generally denoted by refer,;l~ce numeral 10. FlemPnt 10 is comprised of a current source 12 of some type opel~Ll",g at a voltage of Vcc. Current source 12 is then coupled SUBSTITUTE SHEET (RULE 26) w096/23308 2 ~ 85 qO 1 Pcr/Usgf~

through a bit line 14 to an antifuse 16. A semiconductor transistor 18 is coupled to antifuse 16 and can be selectively activated to read whether antifuse 16 is in a high or low edAnce state, thereby representing a 1 or 0 bit. The nodal caracitAnce of circuit 10 with bit line 14 is re~.csel.~ed in the diagram of Figure 1 by an effective stray ç~racitAnce 20. In 5 normal operation, memory cell 10 is accecced by turning control transistor 18 on by increasing its gate voltage and ~etecting if current is flowing through bit line 14. If antifuse 16 has not been programmed, and is ther~;Çore open circuited or at high impedance, alrnost no current will flow. If antifuse 16 has been pro~l~u."..ed or short circuited or set at very low impedance, a predetermined amount of current will flow through bit line 14.
To program the bit in cell 10, bit line 14 is raised to an elevated voltage above the critical voltage required to program antifuse element 16. A finite amount of time is required to fully elevate bit line 14 because of the requ"e...~.lL to charge stray cArAcitAn~e 20. This charging time is a function of the amount of current being supplied to bit line 14 and amount of stray c~pacit~nce 20 Accoci~ted with bit line 14. By allowing bit line 14 to 15 reach its stable DC level of operation before tuming on control transistor 18, control transistor 18 can set the upper limit of current through antifuse 16, as opposed to being restricted or set by the capacity of current source 12.
For example, assume for the sake of illustration, that antifuse 16 has a pro~l~lll.~ng level of 4 volts. Assurne further that Vcc, the voltage supply, is set to 6 volts. Assume that 20 the m~Yimllm current level through control transistor 18 is 1 milli~mp, stray cApa~it~nre 20 is 3 picofarads and that current source 12 is capable of supplying up to 10 microa,..ps. By Ohrn's law in diJIele..Lial fomm when current source 12 is tumed on, bit line 14 will require 1.8 microseconds to reach the 6 volt level under these assumptions. At any time after this 1.8 microsecQrl-i time period, control l~ns.sLor 18 can be tumed on and antifuse 16 will try 25 to support the 6 volts applied to it through the voltage supply. However, the voltage across antifuse 16 will, in fact, only reach 4 volts before it coll~rses. The time required to program antifuse 16 iS, therefore, practically ;,,~ A,.rous, or at least much less than 10 n~noseconds.
Under the assumptions of this eYAmrle, a potential current level of 1.2 milliAmrs 30 could be reached within antifuse 16. However, control ~ s;slor 18 in the p.oposed mple is ~ccllm~d to limit the current to 1.0 milliAmp. Even more illlpol~ is the time averaged power require.llenL~ as is better illustrated in the tim~ng diagram of Figure 2.

SUBSTITUTE SHEET (RULE 26) 2 1 859~ 1 WO 96t23308 PCI'tUS9~ 3 Lines 24 and 26 represent the current and voltage on bit line 14 characteristic of a classic cha gil1g node. The voltage on control transistor 18 is depicted by curve 28 and goes active at time 30. The voltage and current on antifuse 16 are denoted by lines 32 and 22.
Note that the peak current through antifuse 16, as shown on line 22, is quite high, but of 5 very short duration. The average energy or current supplied through bit line 14 is, the,e~olt:, quite small.
Normally, the electrical behavior as shown in Figure ~ would not be considered abenefit. However, in the cit~ ti~n of RFID tags, the amount of energy available to the integrated circuit within the RFID tag is very limited. Typically, the power supplied to an 10 RF~ tag is supplied remotely through radiofrequency tr~ncmiccion~ The amount of power required to read an RFID tag is typically 20 microwatts, usually opelaL;ng at the level 2 volts and 10 microamps. On the basis of the h~,lllla~ion described above conce.llillg the power needed to prograrn a bit, the power supply to an RFID tag would have to bein.,l~ed to 60 llllcluwall~, namely 6 volts at 10 llllc~O~llps. If the memory device were 15 based upon W or electrically erasable memories, the power levels would need to be i".,reased to ~,000 to 1,500 microwatts l~s~,ec~ ely. Even these higher numbers for other technologies are miQ'~-~in~ since neither W nor electrically erasable devices can be pr~,l~lllned with transient pulses, but require well defined sl~ct~ined voltage pulses.

2 0 Self~alibration of Timingfor an RFID Tag Accoldi,lg to the invention, a reference signal is gene,a~ed initially in the remote RFID tag receiver by capturing an inComin~ and~rd signal and placing it in temporary o pe~ e~l~ storage in the R~ID tag circuit. Signals arriving later in time are then colllp&ed to the captured standard. Variations from the captured standard are then detected to allow 2 5 for decoding of the data by either AM or FM terhniques Figure 3 is a ~imrlified block diagram illustrating one means of imrle",~ g the invention. An osrill~tor 34 on the RFID tag chip operates applo~c;",Al~ly at the carrier frequency of the input signal or some mllltirle thereof. As shown in Figure 3, an input signal is provided on line 36 and an appr~lia~e characteristic thereof, such as frequency, 3 0 phase shi~, time delay, or the like, is cGl"~ared in a cGlllp~a~or circuit 38, which has as its other input, the output of osrill~tor 34. The ~ ;,.",ce in the characteristic pa,~"eler between the two is provided on output 40 of con~palator 38 and a~plupl;ately converted if SUBSTITUTE SHEET (RULE 26) 2t8~901 wo 96/23308 Pcr/uss6l008s3 n~ceqCA~ y to digital format by an analog-to-digital converter. A correction cGllllllAn~ signal is ultimAtely provided by means of a microprocessor 42 to a memory 44. Typically, because of the design of osrillAtor 34 it cannot pelr~ l accurately enough because of large variation components or processing of the integrated circuits or other envilu~",...,l~l 5 factors.
The correction signal corresponding to the dirre, ence signal is stored within memory 44 and then coupled through a decoder 46 to a plurality of switching devices 48, or a rçcict~nre ladder coupled to a single cAraçis~nre (not shown), each of which swilches 48 are coupled to n RC circuits 50. Any device or network capable of selectively providing 1 0 circuit options to oscillator 34 through which oscillator frequency may be varied can be equivalently s~bstitl~tr~l Each RC circuit 50 co~ .o~.'c to a dilTe~ RC delay, wnich when coupled through one of the devices 48 to oscillAtor 34, serves to adjust the output of osçill~tor 34. The app.ul,.iale one or ones of RC delay circuits 50 are thus chosen by microprocessor 42 until the output of colll~a~or 38 jn~iratrc that the applu~l;ale 1 5 di~tl ~,nce signal between input signal on line 36 and that output by oscillator 34 falls within an acceptable range. When this achieved, tne correction signal is stored within memory 48 for use during all subsequent opela~ion of the R~ID tag or at least until it is urd~te~
Memory 44 may be provided as a nonvolatile memory to allow the calibration ;"rO~.,. .l;on to be stored pel".~nr.,lly so that reconfi~lration of the internal osrill~tor is not required 2 0 each time the tag is powered up.
The operation can be clarified by conQidrnn~ an t-;.."plc. An initia,ly s~lectedresistor of lO0 kiloohms and a c~paçitor of 50 picofarads results in a time con~ of 5 microsecorldc for oscillator 34. Due to process variations, the final leci~l~nre might actually be instead 130 kiloohms resulting in an actual time corlcl;1llr of 6.5 microsecon~c 2 5 thereby putting oscillator 34 off frequency.
If an input signal had a periodicity of 4 microsecon~c the time conalallL of theinternal signal must be reduced in order to match the i~-co...;np; signal in a one-to-one fashion. Thererore, the resistor co~lpled to the internal osr~ tor 34 must be trimmed back to 80 kiloohms in order for the RC time cor~ for the osrill~tor to equal 4 microseco~tlc 3 0 Conventional resistor ladder networks allow such a transition within the accuracy required.
An alternative methodology is s~l""~uized by the flow diagram of Figure 4. The internal clock pulses from the RFID tag clock are counted at step 52 during a SUBSTITUTE SHEET (RULE 26) predetermined number of external clock pulses or at least during some arbitrary time period. The number internal clock pulses which were counted are then stored in step 54.
The ratio of the number of internal-to-external clock pulses is determined at step 56. This ratio beco,l,es a calibration ~ldard. Thereafter deviations from this ratio can be 5 reco~i7Pd as me~ningfill data with no attempt made to actually calibrate the R~ID tag clock to the external comml~nir~tion standard, but simply to measure and store what is in effect a recalibration ratio.
For eY~nnple assume data is ~ c.~ ed through frequency shift keying between 915 Megahertz and 920 Megahertz. Assume the clock on the RFID tag chip is Opc~aling 10 not at the 915 Megahertz standard but at 914 Megahertz. The calibration ratio e~Lablisl.ed by the mPth~dQlogy dia~ ""cd in Figure 4 of the internal clock frequency versus the input signal clock frequency is thus 0.9989. When a 920 Megahertz input signal is then received the ratio r~ ges to 0.9935. Th~ re~u,e high frequency ch~ngçs in the ratio can be reliably itirntified as a data change of state. Slower variations for device drift device 15 aging and en~i,ol.."~ l drift can be ~eteçted and used to readjust the calibration ratio ay~ropl iately.
Figure 5 illustrates a block diag,ram of one circuit which may be used to implement the metho~ology of Figure 4. The internal Rl~ID tag clock is provided to a first counter 58, while the external input signal or external clock signal is provided to a second counter 20 60. Both counters ~8 and 60 count the clock signals received during some predetermined time after which the acc~ml~l~ted count is provided to an address and data bus 62 to which a ~f~wù~rocessor 64 and memory 66 are collpl~ The ç~lclll~ted and stored ratio is then used as a calibration device for the operation of the RFID tag circuitry syrnbolically denoted in Figure S by reference numeral 68.
Bit and Frame S~"-ch, .",i ~lion The present invention ove,co",es the disadvantages of bit and frame ~"ch~ aLion described in the prior art section above, and lends itself to being le "rnted in an integrated circuit in a manner which does not contain a phase lock loop 30 or neces~lily even a ~iclu~ucessor. In the invention a unique bit pattern is provided which is a typical data pattern rather than being a prohibited or even an atypical data pattern. Bit and frarne ~y~chro~ ;on is achieved by violation of an error m~nagem~nt SUBSTITUTE SHEET (RULE 26) 218590i wo 96/23308 Pcr/uss6/nn8s3 scheme such as an error c and cû,.e~;Lillg (ECC) scheme which utilizes parity or polynornial bits to achieve frame syncluu~ ion At the same time, the use of a typical data pattem provides some assurance that the real data will be co-.~;clly recognized.
An eY~mrle will make this clearer. In an even parity scheme, the unique pattem is 5 an irregular pattern of 1's and O's with an odd parity bit identifying it as the frame marker followed by data with even parity. Bit synchroni7~tion can, thus, be achieved anywhere in the bit strearn. The unique frame marker pattern is effi~i~pntly m~tchçd to a stored pattem and validated by odd parity with the marking word and even parity with the following data words.
In other words, the broadcast digital illru~ aLion has Pmhe~dPd within it a collll)h~ation of bits co...~,.is...g a unique bit pattem. The unique bit pattem, may be a data pattem in which a particular error management scheme for the parity bit is chosen contrary to the a~s..med error convention. Whenever this unique pattem with a parity error is received, it is recogni7ed as a syl~.,luùn;~AI;on frame for all the following data and is not 15 treated as an error. The chance that the unique pattern with a parity error will occur is so small that incoll~cl idçntifi~tion in the unique sy...,h.u.~ ;oll frame is tAIle.llely un~,lobable.
An ~ ie makes the approach clear. Assume that 32 bit words are being generated in which the last bit is a parity bit. Assume further that the error detection and 20 correction scheme acs~nnPs even parity, that is the number of 1 bits in the 32 bit word are always Lli~-s~ ed so that an even number of bits are inr;l~1ded in the word, the parity bit being 1 or 0 as a~lupliale to make this so. Now assume that 31 of the bits are data bits and that a unique pattem of these 31 bits are chosen as the frame syncl~o~ I ;on pattern.
Assume that this pattern has an even number of 1's in it. The parity bit would be 0, if the 25 error correction scheme were not violated. In this case, the parity error is intPntion~lly violated and the parity bit is set at 1. The cQmm..ni~tion system in the RFID tag will then reco~i7P the word as having a parity error, but as also having the unique frame ~.yllcl~ulfi~lion data pattern. Therefore, the parity- error will be ignored. The time of receipt ofthis word is then taken as a sy.lch~o..;~;.)n or frame marker.
3 0 For an 8-bit word the chance of a data pattern ~Csuming the unique data bit pattern and hav ng a parity error is 1 out of 28, or 256 to 1 ~CS~ming as a worse case that there is a 50% chance of a data error. In fact the data error rate in most systems is much lower, SUBSTITUTE SHEET (RULE 26) wo 96/23308 2 1 8 5 9 0 t PCI/US~6/O~S3 typicaUy one out of 232 after noting mllltiple replicate ~ ,..;ci;onS in most R~ID tag applif~ti~nc. For an 8 bit word, this probability is probably not high enough for reliable ayllchr~ ;o~ However, in a 32 bit word, the probability of this parity error and bit pattern occurring becoll,es 232 in the very worst case, or beco~.les more than 4 billion to 1 5 against it. Comm~nication error rates at this level are more than acceptable and are eYceedecl by other error factors which normally arise in an RFID tag application.
The scheme can be easily imphPmPnted in an R~ID tag device simply by using a special decoder in co,.,bil,alion with a conventional parity checker to detect the unique data frame synclu ol~lion to disable the parity checker output for that word and to provide an 10 internal syncluu~ control signal for use within the RFID tag circuit in l~ap~l~se.
Figure 6 is a cimrlified block diagram of one circuit in which the synl,lu~l~aLion protocol can be inlpl~ ...le~ The input data stream is co-lp'~ on line 70 to a conventional parity checker 72 and to decoder 74 which checks the data strearn for the unique bit pattern toEeth.or with the parity violation. When this occurs, decoder 74 disables the output of parity checker 72 by means of gate 78 so that no parity error signal is ~ Pd to the RFID tag circuits (not sho~,vn), and gene~a~eS a s~,lcl ro~ n pulse on its output 76.

Sim7~1t~eous Pawer and Data Tru,.~"~;Qn By op~ ;ng at high frequençies the carrier frequency can be reduced in ~mplih~de2 0 or turned off comrletPIy for short periods of tirne as dia~ ly depicted in Figure 7 without causing the RFID tag to lose power. Since the reduction in carrier signal s~,eh~lh is for such a short period of time, the DC power in the ul~eglated circuit within the tag after rectification does not undergo a si~ifi~nt red~ Qn An eY~Tnple should make this clear. Consider a sample c~lcul~tion in which the longest pulse duration that the carrier would be turned offis 0.5 microsecQnflc Assume that the DC current requu~;ll,e.l~ is 20 ll,.~,roa,l",s and the s~racit~n~e of the voltage supply line, Vdd, on the RFID tag is 200 picor~ds. For this tirne period, it can be shown that the decrease in voltage on the Vdd line is apprc~ u,la~ely 0.05 volts. A 50 millivolt decrease in the power supply is typically not so drastic as to cause the chip to become inoperable.
3 0 The periodicity of mo~ tir~n allows for simple cl~c~ing In ~rli~ion~ varying the duration of the signal can be used to l~anallul data as l's and O's. Figure 7 is a wave diagram of a carrier envelope, showing typical data which might be ~ ed at a 33 SUBSTITUTE SHEET (RULE 26) Wo 96/23308 2 1 8 5 q O 1 PCrruS96/00853 kilohertz baud rate. The circuitry within the REID tag only has to be able to tlictin~lich between a 0.1 and a 0.5 microsecond pulse to be able to reliably identify whether a 1 or 0 is being ~ nc~ ed For example, the 0.1 microsecond pulse 80 may be used to el)les~O's, while the 0.5 miclosecQI ~ pulse 82 used to Icpleselll binary l's. Error red~lction can 5 be accomrlishçd through re~nnd~n~y or pulse repetition.
The RF~ tag remains fully powered because even though the carrier envelope is essenti~lly turned offby the data ll;...c,~ ;onc the pulse width is not so great as to cause the chip to power down at the baud rates that RFID tags normally operate. For ~ .'e, as shown in Figure 7, at 33 kilohertz baud rate, a pulse is ~ nc...;ll~Pd only once each 7.5 10 n~ osecollds. This leaves ap~,lù~i..,~tPly a 98 percent duty cycle which allows the power circuitry within the RF~D tag to easily recover the small voltage loss during the longest pulse duration 82 which it sees.
An alternative scheme is illustrated in Figure 8. Here, three di~cre..~ durationpulses are used to Icpresenl a marker, a binary 0 and a binary 1. Again, the 0.115 microsecond pulse 80 le~ s~ a binary 0, the 0.5 ~l~iclusecQntl pulse 82 a binary 1, and the 0.3 mi~.losecon~ pulse 84 a s~llcl~on~lion, control signal or other identifying marker.
All that is required of the RFID tag circuitry is that it is capable of detPcting pulse widths have a 0.2 micl~,secol.~ di~cl~nce.
A concequ~Pnce of this technique is that the clocking of the chip on the RF~ tag2 0 can be detcllll,ned from the m-~dlll~tion of the carrier at a much lower rate than the actual carrier itself. This, in turn, saves ci~ifil~nt energy concllmption on the RFID tag because circuitry ope~a~ing at high speeds concllmP s~bsl;...l;~lly greater energy than those Opl. al;ng at lower speeds.

2 5 An RFID Tag Diode for Use in Power ~tectification A diode rectifier is forrned accordillg to the invention by isolating the diodes from the integrated circuit substrate to insure that a charge is not inadvertently applied to the diode or other circuitry. One means of impl~---P--I;-~ this is to fabricate the diodes in an integrated circuit process with an inter ell.,-ll~,-lL iCol~tiorl such as silicon on sapphire (SOS) 30 such as shown in cross secti~n~l view in Figure 11, or more generally by fabrication by silicon on incl~l~tQr. In either case, the active device such as diode 104 is comrletPIy surrounded by an inc~ tor~ namely the substrate inclll~tor 106 and the Pnc~rslll~ting SUBSTITUTE SHEET (RULE 26) WO 96/23308 PCI`/US96/00853 passivating incul~tor 108. Metallic contacts 110 and 112 are provided to the N-doped region 114 and P-doped region 116, respectively.
Another means of achieving the same result is to fabricate the diode within the rectifier bridge on top of an integrated circuit surface as depicted in Figure 12. Fabrication 5 on integrated circuit surfaces is shown in Roesner, "Mass Pr~ ,.able Read-OnlyMemory S~nrk~ Above a Semiconductor Substrate, " U.S. Patent 4,424,579 (1984), in which is stacked diode is used as a memory cell. In Figure 2 the integrated circuit silicon substrate is provided beneath an oxide enc~rs~ ted N+ region 120. An oxide layer 122 lies between doped region 120 and substrate region 118. An N type silicon layer 124 is 10 then nested within N+ region 120 and applop.iately exposed to a metallic contact 26 to form a Schottky diode layer at the interface 128 therebetween. The heavily doped contact region 120 is similarly opened and provided with an electrical contact 130. The Schottky diode of Figure 12 could equivalently be s~-bstitllted with a P-N junction diode if desired.
The Schottky diode is pl~fell~d because it is a majority carrier device and does not require 1 5 as high a quality single crystal silicon as that required by a P-N jun~ion ~ition~lly, the Schottky diode is much faster and can easily respond to a high frequency carrier signal which is atypical for the conventional ...~eg,~ed circuit diode bridge diccl~cced above in con.-F~l;on with Figures 9 and 10.
Many alterations and mndifi~fionc may be made by those having ordinary skill in 2 0 the art without de~ Li~lg from the spirit and scope of the invention. Ther~fore, it must be .de.~ood that the illustrated embodiment has been set forth only for the purposes of Py~mple and that it should not be taken as limiting the invention as defined by the following claims.
The words used in this spe~ific~tion to describe the invention and its various 25 embo.limPntc are to be understood not only in the sense of their commonly defined me~nirtgC but to include by special dPfinition in this specification structure, material or acts beyond the scope of the co..l...only defined mP~ningc Thus if an element can be understood in the context of this speçifirafion as inclll~ling more than one mP~ning, then its use in a claim must be understood as being generic to all possible me~nin~;.c supported by 3 0 the spe~ific~tion and by the word itself.
The dPfinitionc of the words or e~ nlc of the following claims are, the~c;fole, defined in this speçific~tion to include not only the co.nbi.la~ion of elP~mPntc which are SUBSTITUTE SHEET (RULE 26) -2 1 8590 t Wo 96/23308 PCI/US96/00853 literally set forth, but all equivalent structure, material or acts for pe~ ~ g s~bs~ ly the same fi~netion in s~lbst~nfi~lly the same way to obtain s ,b~L~ ;ally the same result.
In ad~ition to the equivalents of the claimed elements, obvious subsfihltionc now or later known to one with ordinary skill in the art are defined to be within the scope of the 5 defined ~leml~nt~
The claims are thus to be understood to include what is specific~lly illustrated and desclil,ed above, what is concepLionally equivalent, what can be obviously s~lbsfinlted and also what ecs.onti~lly inco~o.~les the ecsenti~l idea ofthe invention.

SUBSTITUTE SHEET (RULE 26)

Claims (38)

We claim:

1. A method of programming a radiofrequency identification device comprising:
providing an antifuse in a memory cell coupled to a bit line in said radiofrequency identification device;
charging a stray capacitance on said bit line; and selectively discharging said antifuse to draw a high peak current through said antifuse from said charged stray capacitance to program said antifuse, whereby said antifuse is programmed at high speed and low power.

2. The method of Claim 1 where charging said stray capacitance comprises charging said capacitance to a voltage exceeding the antifuse programming voltage.

3. The method of Claim 1 where charging said stray capacitance on said bit line charges said capacitance with approximately 60 microwatts of power or less.

4. The method of Claim 1 where charging said stray capacitance on said bit line charges said capacitance with approximately less than 100 microwatts of power.

5. The method of Claim 1 where selectively discharging said antifuse couples said antifuse through a gated transistor to ground, said gated transistor having a maximum saturation current capacity, said antifuse having a programming time defined for a predetermined time duration, said stray capacitance on said bit line being charged to a power level such that said saturation current is achieved through said antifuse and transistor during said programming time of said antifuse.

6. A method of programming an antifuse having a minimum programming time at high speed and low power comprising:

charging a bit line coupled to said antifuse to a predetermined voltage and thusstored predetermined power level, said bit line having a chargeable capacitance; and discharging said bit line through said antifuse at high speed substantially equal to said minimum programming time required by said antifuse to generate a voltage and current spike through said antifuse sufficient to program said antifuse while utilizing low average power.

7. A method for self-calibrating remote RFID tag circuitry comprising:
receiving an external signal having a characterizing parameter;
receiving an internal signal having said characterizing parameter;
comparing said characterizing parameters of said external and internal signals;
generating an error signal indicative of the difference in said characterizing parameters in said compared external and internal signals; and generating a correction signal which when applied to said remote circuit compensates said internal signal to allow for calibration to said external signal, whereby said remote RFID tag circuit is calibrated with respect to said externalsignal for reliable and low cost communication therewith.

8. The method of Claim 7 where generating said correction signal comprises generating an oscillator correction signal to adjust said internal signal to within a predetermined tolerance of said external signal.

9. The method of Claim 7 where generating said compensation signal comprises generating a correction factor for use in operation of said remote RFID tag circuit where said error in said characteristic parameter between said external and internal signals remains substantially constant during times of operational interest of said remote RFID tag circuit.

10. The method of Claim 7 wherein operational characteristics of said remote RFID tag circuit change over time periods greater than those time periods of operational interest of said remote RFID tag circuit and further comprising repeating the method comprised of receiving said external/internal signals, comparing said characteristic parameters, generating an error signal and generating a correction signal to update said compensation signal as said error signal changes slowly over time.

11. The method of Claim 8 wherein operational characteristics of said remote circuit change over time periods greater than those time periods of operational interest of said remote RFID tag circuit and further comprising repeating the method comprised of receiving said external/internal signals, comparing said characteristic parameters, generating an error signal and generating a correction signal to update said compensation signal as said error signal changes slowly over time.

12. The method of Claim 9 wherein operational characteristics of said remote circuit change over time periods greater than those time periods of operational interest of said remote circuit and further comprising repeating the method of receiving said external/internal signals, comparing said characteristic parameters, generating an error signal and generating a correction signal to update said compensation signal as said error signal changes slowly over time.

13. The method of Claim 8 where generating said correction signal comprises generating a signal to select a compensating RC time constant to be coupled to said osciliator.

14. An apparatus for self-calibrating a remote RFID tag circuit comprising:
a comparator coupled to an external signal and an internal signal which is to becalibrated with respect to said external signal, said comparator generating an error signal indicative of the difference in a characteristic parameter of said external and internal signals;
a processing circuit coupled to said comparator responsive to said error signal to generate a compensation signal which when applied to said remote circuit allows for calibration of said internal signal from said remote circuit to be calibrated to said external signal received by said remote circuit, whereby said remote RFID tag circuit is provided with reliable economic calibration for communication.

15. The apparatus of Claim 14 further comprising a memory coupled to said processing circuit for storing said compensation signal to maintain calibration of said remote RFID tag circuit.

16. The apparatus of Claim 15 further comprising a oscillator in said remote circuit for generating said internal signal and an RC network having a plurality of selectable RC values, said compensation signal from said processing circuit selecting one of said RC values for coupling to said oscillator in order to maintain a characteristic parameter of said internal signal calibrated within a predetermined tolerance to said external signal.

17. The apparatus of Claim 15 wherein said compensation signal generated by said processing circuit is a correction factor indicative of said error between said internal and external signals, said correction factor being applied by said processing circuit to operations within said remote RFID tag circuit for maintaining reliable calibration to said external signal.

18. The apparatus of Claim 17 wherein said correction signal is proportional to the ratio between said characteristic parameter for said external signal and said internal signal.

19. A method for providing data communication synchronization comprising:
checking a communication data stream having a predetermined error correction protocol for an unique data bit pattern;
determining whether said unique data pattern also violates said error checking protocol; and using timing of said unique data pattern as a synchronization signal if said error checking protocol is violated, whereby bit and frame synchronization is achieved anywhere within said data bit stream.

20. The method of Claim 19 where checking said data bit stream for said unique pattern comprises checking for a unique pattern typical of data normally received.

21. The method of Claim 19 where determining whether an error correction violation has occurred determines whether a parity error violation has occurred.

22. The method of Claim 20 where determining whether an error correction violation has occurred determines whether a parity error violation has occurred.

23. The method of Claim 19 wherein said data stream is organized into words and said unique data pattern comprises at least one word subject to said error correction protocol, wherein said word has a bit length at least equal to a predetermined minimum so that the probability of creating in a normal data stream said unique pattern with error correction violation is less than a predetermined acceptable minimum.

24. An apparatus for providing a synchronization marker comprising:
an error correction circuit for receiving a data signal stream; and a decoder for checking said data signal stream for a unique pattern and simultaneous parity error violation, said decoder being coupled to said error correction circuit and disabling said error correction output in the event of simultaneous detection of said unique data pattern and error correction violation to generate a synchronization signal.

25. The apparatus of Claim 24 wherein said error correction circuit is a parity checker.

26. The apparatus of Claim 25 where said decoder checks said data bit stream for said unique pattern which comprises a unique pattern typical of data normally received.

27. The apparatus of Claim 25 wherein said data stream is organized into words and said unique data pattern comprises at least one word subject to said error correction protocol wherein said word checked by said decoder has a bit length at least equal to a predetermined minimum so that probability of said unique pattern arising in a normal data stream with error correction violation is less than a predetermined acceptable minimum.

28. A method of simultaneously powering and communicating data to a wireless remote RFID tag circuit comprising:
transmitting a carrier signal to said circuit for providing power to said circuit;
modulating said carrier signal to reduced levels using pulse widths equal to or less than a predetermined maximum, said predetermined maximum being determined by thelongest duration for which said carrier signal may be turned off before said remote RFID
tag circuit loses stored power to a degree sufficient to make operation of said remote RFID tag circuit unreliable.

29. The method of Claim 28 wherein said carrier signal is modulated by pulses having at least two distinguishable pulse widths, said pulse widths being correlated with transmitted information to said remote RFID tag circuit.

30. The method of Claim 29 wherein said carrier signal is modulated by at least three pulses of different pulse widths to communicate binary data and control signals.

31. The method of Claim 28 wherein said modulation is at a frequency substantially less than said carrier signal so that said remote circuit is operated at said reduced frequency at lower power.

32. The method of Claim 31 wherein said carrier signal is modulated by pulses having at least two distinguishable pulse widths, said pulse widths being correlated with transmitted information to said remote RFID tag circuit.

33. The method of Claim 28 wherein said carrier signal is modulated with a duty cycle at or less than a predetermined maximum as determined by the minimum duty cycle by which said remote RFID tag circuit will still reliably operate.

34. An improvement in a diode rectifier having a plurality of diodes in an RFID tag comprising:
insulating material disposed beneath and between each said diode in said rectifier to electrically isolate each diode from each other diode within said rectifier to prevent forward biasing of any of said diode junctions at high frequencies.

35. The improvement of Claim 34 wherein said insulating layer comprises an insulating substrate upon which said diode is formed.

36. The improvement of Claim 35 wherein said substrate is sapphire and said diode is formed by a silicon-on-sapphire process.

37. The improvement of Claim 34 wherein said insulating layer is a silicon substrate surface of an integrated circuit having an overlying oxide layer, and said diode is a stacked diode disposed on said oxide layer.

38. The improvement of Claim 37 wherein said stacked diode is a Schottky diode operable at high frequency carrier signals at which said RFID tag is operated.