CA2185908A1 - Architecture and methods for a hardware description language source level analysis and debugging system - Google Patents

Abstract

A digital circuit is synthesized from a text description of a digital system. During synthesis, a parse tree with parse nodes is constructed and retained. The relationship between the parse nodes and the circuit elements synthesized from those parse nodes is retained. Using that relationship, analysis results associated with circuit elements can be related to the text that generated those circuit elements. In particular, the analysis results can be used to set the display characteristics, such as font or size, of the text associated with those results.

Description

2 1 8 5 q O ~ Pcr/u~i551`~ 1660 AR(~ ;CTURE AND METHODS FOR A HARDWARE DESCRIPI`ION
LANGUAGE SOURCE LEVELANALYSIS AND DEBUGGING ~Y~
Background of the In~ention Field of the In~rention S This in~ ~ion relates to the field of cc!~ n~ aided design for digital circuits, and particulariy to analyzing and t~ e~ng digital circuits constructed from HDL source text using logic or behavioral ~ .rc c Statement of the Related Art A digital circuit ~l~,s;~ er needs to ensure that the digital circuit I~Çul~l~s the co~rect 0 ftlncti~n subject to many design cc,n~ ls. For eY~mrle, the digital circuit should "~r~
the correct co...l-,JI~l;nn in the proper ~-..o~ l of time. The area that the digital circuit oc-cupies on a sem ~ol.~ r die should remain within certain bo~ln-ls The power that the digital circuit con~ s while op ~ should also remain within *,6~;r,r.1 bol)n~lc To be cc~-~ 1y manufacturable, the digital circuit should be testable. An ec~ lly use-15 ful digital circuit should not talce too long to design, ,,",,..r~ , test or use.
The digital circuit design ~ Ce;~S typically involves tr~nc~ ng the ~esign~r's some-times in~ir;Ç-~I thoughtc about the r--.-~ ,- and co~ "h-lc into the tooling ne~ess~ to uluce a working digital circuit. For e~A .~ e, ~ c;-~g a full-custom sçmiconlluctor chip l~uil~s ~ u~ masks that define the de~os;~;Qn of c-~ s into a subs~te as 20 well as l~1V ~ test ~ln - ..C that CA.~.CiSe the final prvducl. As ano~l,cl eY~mrle of tool-ing, l~luducillg a field l~lv~ hle gate array ~quil~s genc.dling the bit pattern to be downlo~l~ into the chip to specify the confi@lrati~ of the ~.-hi~ e. CO~ C~ Aided Design (CAD) tools f.~ilit~tl the itcrative t~n~l~tion of the ~lçci~n~'s developing thoughts into the tooling required to plvduce a working digital circuit that s~ticfies the design con-25 straints. The ~lvcess of iteratively adjusting a design to meet its co.~c~ is called debug-ging. The pl.~cejs of id~ ifying various l~l~clues of dirr. l~ parts of a digital circuit is called analysis. In order to debug a digital circuit, the ~eCignçr must first analyze the circuit - -woss/27s4s 218~90~ Pcrlu~3~01~co to asc~l~in where yl~lc"ls occur.
The typical hict~ric~l model of the digital design yÇuCf SS using conventional CAD
tools for a sf mi~ 3~ or chip is as follows. The ~esi~nPr first conceives of a particular function to ;..~pk--..f,-~t, as well as co~ such as timing or area that the imrl~ ;Qn S must meet. Next, hicto~ic~lly, the lPsignp~r mP-nt~lly ~ r~ll1S the desired function into a high level generic t~ alDOy circuit co~.~;cl;i-~ of cc,~yor.en~s such as gates, adders, reg-isters and RAMs.
The ~f signPr then choosf s a tfxhno!Gb~l provided by a semicon~uctor vendor from which the circuit ccJmyon~n~ will be chosen. The y.ocess of choosin~ circuit components 10 from a specific teçhnology is called mapping; mapping creates a ~apped circuit. To map a circuit, the ~eSi~pr draws a SC-I~ I;G of a mapped circuit that ;---yle-~ the desired function with a CAD SC'h~ t;C capture tool. The mapped circuit includes parts from a soft-ware lf~se .l~lion of a spePfic technology library which is supplied by a silicon vendor.
The sch~ t;c shows how more y~ e functional ~lc "e n~, such as gates or transistors, 15 com e~ tcJg_ll.eI to form more soyh;~l;c~t~ filnctiQn~ such as ~ IIIIFI;~ logic units. In ad-dition, .. .ocl~ . . 5(`h~ 1 ;C capture tools allow the desi n~r to divide the design hierarchical-ly into in~ ;ol ~c~t~ pieces, and then allow the user to specify the details of each of the pieces seyalal~ly. For c ;."~l~k, Design A~-,hit~ by Mentor Glayhics of Wilsonville, Or-egon provides these sc~h~ capture fimctir~n~
Conventional CAD tooLs, such as those in~lic~ted above, can then take the connec-tions in the sçl-r ..~I;c and other ;..r.J....~;o~ to evaluate the mapped circuit and to specify the tooling nr~e ss,.- ~ to COII~hu~ the circuit. Such tools evaluate the mapped circuit in _any ways. For e-~.n~lP.~ co....ne-, ;al CAD tools often have a simlll~tQr that predicts the l~i,ponse of the Illayy~d circuit to desi~n~r ~yer;r.~d input y~ . ..s QuickSim II by Mentor 25 t'~raphics of Wilsonville, Oregon is a co.. ol-ly used ~imlll~tor Another colllmon CAD
tool is a path delay analyzer that i~1entifies the longest timing path in a mapped circuit de-sign. DesignTime by Sylloy~s, Inc. of Mountain View, California is a tool that provides path delay analysis.
There are con~e ~l;on~l CAD tooLs that have the ability to O~llcn~l~ the geometric lay-30 out of the digital circuit with layout tools. Cell3 rl-~ hle by C~ nce of San Jose, Cali-fornia is an ~ lP- of this type of tool. Layout tools are l~ uil~id to produce rnasks to make WO 95/27948 PcrluS9S/04660 a semicol..l.,.;lor chip.
There are convention~l CAD tools that have the ability to check that the digital circuit meets the design rules, and to idenlifr the loc~tir,n of any errors to the designr r. Design rules help ensure that the ~l,ec;r;rA digital circuit will operate once ,..A~...r.~
There are conve~ n~l CAD tools that are used to l-,t - ~ r7. how test~ble a ~ pcd circuit is, and to genr,r~te test IJ~Ih -c ~-lo-.~l;r~lly. Showing the designer the parts of the l..al~pc~ circuit that are not tesP~.e allows the ~esignr~r to make molifirAtionc that will in-crease the probability of m~l~ing a ~.~ccessrul chip or circuit. C~e"e~a~hlg test p~ttcrnc auto-m~tir~lly allows for more thorough testing of the digital circuit ;.. ~ no.ly after 0 ...~,...r" ,,..;"g As ~çs~ibe~ above, the concel)L of analyzing a ~l,l,ed circuit design historically re-fers to the I, vcess by which a digital circuit decigner speçifi-~ a particular ;..~l.4 ..e~ l;0n with a sçh~ m~ti~ capture tool, and then used various circuit evaluation tools to verify that the impk.. ~ l;on did what the digital circuit decigner wanted. For example, the decignçr 15 would use a cim~ tnr to det~ e if the mapped circuitproduced a~yl~,y-iate outputs from specified inputs. The ~esigr er could use the path delay analyzer to dete,l--i-le whether the current design was fast enough to meet the timing COnsLI~ltS. The layout tools could in-form the r~eCignr r whelLel the design meets the area con~ ls.
When a particular design did not meet the ~l~sign~r~s constraints, the rlç$ign~or then 20 m~ifie~ the design. For eY~mrl~., if the ..la~ed circuit was too slow, the designçr identi-fied the part of the ~y~d circuit that was too slow, and revised it to increase yelro ance.
If the l,.a~ul circuit was too large, then the design~,r revised the mapped circuit to use few-er or smaller CO~ )OnelltS. If the mapped circuit did not behave as required, the designer changed the COmpOne,l lS and the inlelcolll eclions to produce the correct function. Rec~lce 25 the conventional CAD tools began the analysis with the lla~ped circuit, the timing or area problems could be readily irl~ntifi~ to the ~eSi~.r. nec~ce the ~ecign~or specified the - structure of the ~ped circuit, the A~ -si~lq-r could thoughtfully make adj~lctm~.nt~. Howev-er, the CAD tools were limited in their ability to identify functional problems because the de-signsr had mtont~lly y~lçul~ed the tran~ l;on from desired function to mapped cir-30 cuit. In other words the CAD tools in~ d~ ~ clul~ tion about the digital circuit, but did not include data conce I ;n~ the high level functionality of the digital circuit.

WO 95/27948 2 1 8 5 ~ 0 8 PCI/US9S104660 Logic ~lllllesis was developed to provide the d~ci~n~,r with an ~ u.~ mP~h~nicm to ll~lslate a h~d~e de~l;plion l~n~age (HDL) des~ ion of a desired function to a ~ll u~;lulal ~lesc- ;1l1 ;ol- of a digital circuit that ~lr-l~ed the desired ~mction- Logic synthe-sis begins with the ~eSignçr ~eS~ihing the desired rv~ ;on using VHDL, Verilog, or any 5 other logic ~ he;.is source l~nguage, to specify the behavior. This allows the ~leci~n~r to specify the digital circuit at a higher level, and allows the CAD tools to assist the flecignçr in Aefining the ru~ n~lity of the digital circuit. A SOn~ , tran~tor then converts that I;Qn into generic t~'~hnology ~llu~;lul~s that di~e~Lly ccll~,s~nd ~ r~l by state-ment with the lesipn~r's descliplioll.
In logic ~r,.~l,e,ic, ~nslation is followed by logic c~ ,.l;on Optimi7~tion in-volves two steps. First, it replaces the &~lly tr~n~l~tetl structure with a filnction~lly equiv-alent, yet improved ~7llu~lule. Second, the o~!;.n;~ n pr~cess incllldes an optional step called mapping the design. ~pping replaces the generic technology structures with struc-tures from a specifie technology library. Technology libraries are provided by silicon ven-15 dors to specify the types of parts which the vendor can m~nuf~ct~lre. Technology libraries include specific ;nro.~ ;o n l~g~dillg the fimCtic~n~lity and physical char~tçrictics such as area and delay of gates which can be built by the silicon vendor. Technology libraries are designP~d to work with ~,yllll,e~s ~ .,~,. A s~ llesis system can use a tP~hnology li-bra~ to choose available gates from which the silicon vendor can f~hric~te the digital cir-20 cuit.
Unr~llullalely, the ll~sr~ ;ons ~-- rv~ d by the logic optimizer usually modify the structure that was present in the pre-o~t;.~ ;on circuit. This results in a mapped cir-cuit that is not easily recogr~ized by the ~lesigner The fact that the lecignPr gener~lly can not readily recognize the origin~l function ~clr,lllled by the ~ed circuit makes analyz-25 ing optimized mapped circuits lifficlllt Convçntion~l ev~ln~tirn tools can ~1~t~ e the timing or area problems in the mapped circuit, but the ~Çci~er often can not relate those blcmc easily to the HDL source specifi~tion Theoretically, the designer could manu-ally ~letr n~ine what part of the HDL spe~fic~tion caused the problem. With that insight, the decign~r could make the desired ch~ngec at the HDL specifi( ~tion~ and resynth.osi7e the 30 entire digital circuit. If the desi~r's problem oc-;ull~d in a part of the mapped circuit that passed through the optimizer with few ch~nges, manual backtracking might work. Howev-21 85~08 WO 95/27948 PCr/US95/04660 er, dle Op1;. . .; ~ 1 ;on ~ ce,ss ~onç~ally makes many ch~nges~ m~king it either ~ifficlllt or im-possible to backtrack be~ ~ many points in dhe ~i in~l generic t~hnology circuit do not exist in dhe llla~ped circuit.
~ul~ the level of circuit improv~ent pr~luced by logic o~ 1;on is not S c~h~ t~ Due to the co"~l-vl~l;rn~l cc)n~rl~Yity of dle optimi7~tion problem, optimizers must rely upon a~pro~ te, radher dhan optimal ~l~o. ;11~ c The effect of the optimizer is, in some senses, l~do.l~, because a slighdy dirr~ t initial circuit can signifir~ntly affect dhe choices that dhe ~ih~ er ma_es. TlJ~"~fc,l._, it is impoccibl~ to predict con~ictently the nlage improvc~nl dhat the optimizer will deliver. A small change in the HDL spec-ific~tion may result not only in a ~ub~ ially diff~,n~ al~l,e~l circuit, but may also result in a ~ J~d circuit which is subst~nti~lly larger or slower.
As one possiUe sol-ltion, the decigner can directly modify dhe mapped circuit pro-duced by the synthesis sofl~. d~. However, dlis does not allow dhe ~esi~rr to resynthesi7e the design from the HDL s~c~;l;rA~;on because dhe ~lecignPr~s logic changes is o~,elwliuen 15 by subsc~u~,nt trAn~l~ti~n and 0~ n steps. This reduces the value gained by using the s~lltllci~is appl~ach to design.
One prior system which A l 1~ teld to link ~L source text to generic tec-hnolQgy and mapped circuits was "Source to Gates" which is in~luded as a feature of Design Analyzer by Synopsys Inc., located in ~olln~in View, CA. Source to Gates allowed the decign~r to 20 trace ~t..cen HDL source and SÇI.I- .UI~CS Source to Gates did not prove useful because its ability to trace post syl~ll~sis mapped ~lluc~,s to the HDL source was limited to Oph---;~I;Q-~ invariant circuit ~llu~;lul~S that were present in the HDL source. Although Source to Gates did allow the ~l~ci~r to trace ~~ sel~ AI;~s of the generic technology cir-cuit and the HDL source, this feature was not particularly useful ber~llce it required view-25 ing of the generic technology circuit which was not di~clly m~Aningfill to the ~esigner andno analysis link to the source was provided.
An ar~ tionAl limitAtiQn of Source to Gates is that it stores text location in terms of row and colnmn ~ . Thus, when tracing from a SChP~AI;C to HDL text, Source to Gates only hilightc the first ch~n ctP~ of the a~lo~iate parse node. There is no in~ tion 30 of the range of the parse node. There are two modes in Source to Gates when tracing from text to the sCl~ Exact match mode forces the user to place the cursor on the first char-Wo95/27948 2 1 8~ PcrluS95/04660 acter of a parse node in order to enable tracing to the sc~ ;c Closest match mode s~ches fv~ alds and backwards in the text to find the closest t~ceable character. In this mode, the user does not know exacdy what will be traced.
Another m~thod for .,.h.;..,;,;..g the backhacking l,lvblel., in the analysis of an opti-5 mized ,ndl)~d circuit is to partition the design into l~ hical cc ..~.on~ , and translateand optimize the smaller pieces. Because the h~ ;on and o~l;---;,~l;on tools generally do not ha~ inputs and outputs, the HDL dc~cli~livn can be correlated with a particularres~llting lllalJ~cd sub-circuit, thus re~çing the size of the backtracking problem.
However, l~l;l;~ning has the disadvantage that the ~l~cign~r may have to rewrite func-10 tionally correct, but non~ ele~ prvblematic, HDL source code to isolate the tro~lblesomeparts of the ~pped circuit. In ~ tion, this ap~lu~ will greatly limit the optimizer's abil-ity to reduce the area and ir,~ the speed of the rec~llting circuits bec~-lse the optimizer will be cur.~h~ned by the l~igner~s partition.
In a~ltlition, it is possible for a ~çci n~r tO be micl~rl by the results obtained by anal-15 ysis by par itioning- The ~lecipn~r's bug in the circuit might be that it is too slow or too big.
Partitioning the HDL source to locate the cause will likely result in a dirr.,lcnt circuit than the u"~ ~ source. Th~ ,Çvl~" the problem that the lesi~r iS çh~cing may be affect-ed by the analysis l,locess itself.
ConvçntiQnslly, using a ~ ,l to h~,srvlll, an HDL source speçifi~tion into a 20 ~pped circuit can also cause ~bs~Anl;~l co...l~ulAl;~n~l problems if one needs to incorpo-rate minor ch~nges into a design late in the design ~r~cess. For eY~mple, a ~i~Signer could have the design fairly close to co..~l lel;nn when the ~3eSi~r discovers the need to make a small fimctinn~l change, such as inverting a particular signal. Intuitively, one would expect that such a small change would require only a small change in the digital circuit all the way 25 to the layout level. However, it is quite poscible that, with conv~-nti-n~l tran~l~tion and op-timi7~tisnl tools, a small change could require subst~nti~l ch~nges in the ,lla~ed circuit and the circuit layout. With current tools, a decigner can often limit this kind of problem by par-titioning the design into s~ller pieces and thus limitin~ the effect to the directly implicated pieces. However, as ~es~ihe~ ,iously, ina~lul~l;ate or unduly narrow partitioning can 30 l~it the ability of the optimi7~ti~n tools to consLIucl a _apped circuit which meets the de-sign cor,~il,ls.

2 i ~ 5~08 ~ED S~ET

7 P~TEII~
RYEY DOU~El' 110: 34175.0Wl~

A Con~tiooal 1~ alld Debu~ne Pro~ o~1rk~r Fguro 1 show~ ~n overv~e~ of VJe c~.. _t_ -1 proc~is for ~ g, and debu~g ~igital c~i~c c~fi-~d w~th a H~rdw~rc D~ pt;~ I~uago (~DL). T~e process begi~s with ~he desig~e$ ~rW~g HDI, ~uroe cdo 10~. A tS pical hP~agc u~d for specifyi~g digital circ~ts is V~L w~ich Is dLi~l~bCd ill tlle IEEl_ St~ rd VHDL L~e Refon~ Manuak, ~ om the I~titute o~ 1~1ech-ical Im~ P"~
Eng~ccr~ m Pis~_.~y, ~ew~e~cy. VHDL stand.~ fa~ V'ery h;~ specd i~Lc~ated ~ t Hard~i nee~
l~gl~ A~dheJ la~aD: used for s~i~g d~ al cirç~s is vcr~cg t~ is d~s il~-l ~n Hard~are li.~ w~tl~ ~er~o~ HDL by Eli~r Stc.~;r4 R~ Singb, a~d Ya~L Triv~di, E ' t -1r ~ by ~nt~mata Publishin~ Company, Pala Alto, C~ ornia, 1~0. Verilog L5 also (h~ f d in thc ~ter~g Hardw~re n~
La~l~ Refer~ MAnual (LR~ul), ~osl lD, November 1991, w~ioh is p. I~ rd b~ Opcn Verilo~
t~l. 1t; ~ ~ u~l ill this d~ are i~ t t~ inc2ples ro~dily a~p1y to nthl:r circuit ry- r Aftor ~i~g a HDL ~ -. ;ptir\- of a desired ~ ~iw~, t21C d~f;ipner thc~ ~ulates the ~3nctian 101 cmkdded ~ tbe de~;~ vi~ a HDL ~ ror. ~n e~amplc oE a r~ n~ mn~ is YE~L S~em S~ or that LS ~ ' - from Sy~oys~s, Inc. of ~r,~ ~ - ' V~, C~lifi~ The f~ r' ~I~tor ~lJWS
t~e de~i~er to del~e w~ot~er ~c arc~it protuc~ corre~ values n ~Spu~ pUtfi witbo~ prd to ~-ng, 8roa ~r po~cr .: ' A fu~c~onal ~.nul-~fi~ pcrro~n funcda~l~ly s~ulat;.~ uick-ly, 1~ abliDg t~ de~er to /1~ t~ ; that l~ Cil'C~t WiD protuc~ t~c desired outpu~
Jf thl:rc is a p~o'olem wil~ t~e ~ d; t~c d~i~ can fi~ ~ction proble~s 10Q by ~ the si~ula~crl oulput alld goi~g bad~ to WJi~g ~lDL code 100. F~ n aD~ tes the s~uru ~;f~ .~w~t~ ~nen~t~ 'c~ mapp edcir~u~t~. Tberef~re,p~ulJl~ de tU~ulg r ~ 0n can read~y be ~i~ed to their ~ause in tbe ED~L
If ~ de~ es t~,.r ~e di~ital ~it d~ "c ;l~d by ~e HDL u)u~ce pro~ide4 the comc~ u~
the de~i~oer specifies co~s~s for the ~ occss 103, e.~. maximum cl~g ~ods, tallil cirenlt uea, l r- powcr. This p~rt o~ the rrnoess i~ dcs~i~ m ~es~ ,"er Pa~ly Refero~: Ma ~rsh3 3:~, which i~

LtUiOPJ .P511 AMENOED S~ET
~1~5~8 PJ~TEIIT
Y PaelCET I~ 34175,DOO1~

atr~il.,hle~ro~Sy~opsys,Inc or~ m~ Ylew,CA. Examplc~fComputorAitodDesy~o~ etb~tuso - n.i..~ ~pcc;r;~-~n arc Sy~ by C-'~ d ~llt~ by Ment~r Gr~ph;c4 and ~esign ~nmp~er ~y S~nD,~Ly9, ~ ftcr dL~ ~ ~ the t~er ~u~ c4~ to ~J ~ f 104 a mapped circ~t ~rum l;be H~l. d~o~ produced m t~c w~g HDL 100 step. T~i~ step ~l~es trRn~ e thc HDL ~urcc;pt;oll into a~ ric tCÇ~ r~ cu~t t~at c~csporlds &~ctly w~th the ~ c ~ ~e source ~1.. An ~amplc of softw~ro ~t ~ this functio~ is dcs~;~d m the VE~L Co~pilc~ Re~ercnce M3~ual, Ver~ion ~.la, whic~ ble from .~ ~ ,v. A~ter tr~ n~ eriç h .' ~'~,,~ drcu~
J inlo ~ mapped C~c~ tbat mec~ the pc,f,,~ c w~straints c~t~b~ e~1 iD step lU3. Prior lo u~ 7 ~;n~, it is a strai~Lfo~ d task to id~ y whic~ cIcment of ~o ini~al ~eDenc I ' -'~", circuit curro~poDds to what part of thc HDL source coto. C~ se Of thC ~E~..s;._ ',"~'' ~~
d duri~g thc ~ ' ' ~oces6, suC~ ide~ n~ k;r o~ i~dt-~ bec~ne~ a~wt ;~E ~-CXOEpt at regi~te~ d ~odule --t~'- r-re l~o~d~es.
PiS~ure 2 ~ tPrm~d~ ~ 6t~u~ 4 ~ s~lthe616 process ~
pr~cess be~ wit~ HDL ~ource ~00. The Ir. --1?tor creates a ~a s~u~u-~ called ~ parse ttec 901 that rep~:se~OE thc ~ r ~ ~h~l~c of thC H~L ~e 1 1~'or ~Cn turn~s ttc p~C tree ;nto ~ i~;;al ic tech~obgy aTalit ~0~ Rl:~ B. Scgal~s Maste~ BDSY~; Logic ~ugn Tr~ at the Us~ ~iLy of California at Bakelcy, Memo,#UC33fERL M8~/33, dr~r-~ mc~ tc.. U~ited S~tes Palc.~l A~ 07/632, 439, ~ilct o~ De~mher 21, 19~U~ e~titled ~Me~hod a~d Appar~tus for Sr~h~.C;
HD L l:~s~t' ~ ~r ' " Drq ~ P ' ~ by Gre~o~ et al, ~d ~ .;l assi~ed to ~mop5~ also d6~ JC~e~ such a t~l4. ~ rY~plo of a tool ~Lt doc~ version31a ~f ~e HDL compil~r a~ilabl6 All o~ Lr7 ~d to produce the mapped c~rcu~t g~3 ~om th~ ini~al g~nc tc ~' . ' "~ arcui~ ~
1~ optimizati~ pro~ess is e~ "Logic .Syn~esiç T~-ou~ 1 T., ,- ~ ati~" by J. Da~ r, W.
~oyler, L. Be~ , a~7 L. lrç~an m ~e 1131~ Journal o~ Researcb, a~l D~ p~ V ~, volumc 2~, number 4, IUI~ 7 pag :s ~ 2&0.

LPU ~J.P50 21 ~3 ~9~8 ~MDED ~

5~ PATEIIT
ATTC~R~r DOCI~ET RO: 341J5.XCl~

It i5 3]so ~ n ~LSS:A Sy~ r Plr ' ~ ~giC Syn~csis~ by ~. DamD~cr, V. Bra~ld, J. Gerbi, W.
~oyn~r, ant ~ Trc~a~ ,~ tbe ~B~ J~ of ~5~p~Tr~ ant De~e~ o}umc 28"1umbes 5, S~
1~84 p;~gcs 537-545. It iA Muhiple-le~el Logic ~ - -- Sy~em" by ~ BraytoD, . 17 udell, A. Sa.,~,;u .. ' Vince~tel~ d A. Wa~ the ~ Tr ~ ^t;~ ~ ~ on CompUte~ Aidet De~
Vo]~r~e 4 number 6, N.,.~l~ ~', p~o~ lD8L It ~s ~bu ,J~' led in t~ D. &sv.i "~ nLo~ic SyD~C8~a ,f~ y R. R~dff~f~ e U~ of C~91;r --'n a~ B~ y ~ 1'Y~5~. T~ p~ . ~t .
proc~ is al~o ~h~- ;kd ~ the Dfesi,~ C~ Referellce M,3~ wrs~ 3.1a w~ich i~ ' le fr.~
Syncpsy~ A~ e~nple o'~ so~e that F~ ~on is the ~ ~rl~ at~ilable ,~o,2n Syllopsy~"
I~c. 0~ex~ p'~sofsoftw~6~l,~.f~o~ ;,optimi~tior~clu~IeSy~ler~ ~C~C-"r~!,Loc.,and~v~Jl~
cnto~ Graphics Or~c appr~ 1. ' to Op~ '-D is to ~rollp ODO or more b,g~c ~.~ f~ toge~,~, and rcplafse f~o~E
k; ~i~ a *nrri,~qll~"f ~ t c~ or of ele~s Lh~ ~as bett~ ~har~ ~ D ~ ~ f~
of e] e~ents rf4I~Iaf. f~ i5 r~6ul~s ~n ~ ,'~tcr~e~diate c rcu~t tht i~ t;o-~ ~lly cqu-~leD~ to tbc miginal. Thu i~-media~ arcDi~ cn haw s~e ~r a31 of its clG ~r ~(~ ~o~pcd for ~other ~ -- n~t. The pr~s c~ b~ F~ d o~ cit~cr ~et~ic te~olc 3y or mapped logic circllit,q. 1~ ~r~cess ~s r~ ; d until the op-~ee~ the w.~stl ai~ imposed ~n step ~3 of Figure 1, or ii u~able to mal~e a~y hrdler impro~c~
The ~~ F; ol he i~itial ~en~r~ ~ ~l~2y dra~ u two ~roups: those; ~ atm~
~c ~ resen~d throu~ ; ~t' i7~1r- pro~ d ~C6C t~at can bc replD~t wi~ ~ ~ 1 e -~ b~ Por pl~, a b~jc o~ m~ repl~ce a blod~ of booban log~ ~nth another blocl~ so loDg a~ f~ction is m~t3~ ~ere~11y~ .c;?~ v~l~ c~ ~ r ,~!- of colnpoaents tha~ are rally pros~ d thlough the ~ s are pr~ i~putS pnmary aulpul;~ d ~Q, stPrc After dc~l~pu~g a mawcd circui~ the des~gner can ~on mlalyze t~e mappc~ 5 us~g w~ 3r analy~is tools~ 3S sho~ in Fgurc L F~r eD~ple, t~o desi~er could ebtimah the area th~t t~e ~pcd cirwi~ ~o~s~ PQ ar w~t ~hC lo~ge6t delay path L~PJ .~5D

WO9~/27948 2 1 8 5~08 PCT/US95/04660 in the ll apl)ed circuit. This analysis can ide.lliry plublc.lls to the ~Çsign~r The analysis re-port 904 is often a text doc~ t as shown in Figure 1.
After id~ ç~ rillg timing, area, testing or power ~luble~s with the analysis tools, the ~eSignrr then adjusts the lllap~d circuit to fix these l~lub~~m~ 108. Ideally, the designer S goes back to the HDL where the function is spe~fi~l and make adj~ enlc there. Howev-er, be~ se it is ~;ull~nlly hard to identify the spe~ific places in the source HDL that led to the problem, llloJirying the a~lul~liah part of the HDL is ~;u~ llly not an effective debug-ging t~,ch~ ue. The tl~Sign~r can usually identify which hierarchical m~nle cont~in~ some of the problem. The ~lesign~r can then m~nn~lly rewrite that module to create more primary 10 inputs and outputs to c~ e. This is very time con~ in~ and is generally done as a last resort. A metho~ for ~J~o...~;r~lly adding adrlition~l pli~al~ inputs and outputs is needed to make this ap~loacll practical. ~lte~T ~tively, the dçsigner could adjust the COnSlla~lki 103 and synth~ci7e the llla~l,ed circuit 104 again to see if the problem is alleviated.
After analyzing the mapped circuit 105, the ~signer then releases the design for fab-15 rication 106.
System Performance In ~ltlition to the analysis problems ~l.,sen~d by the transf~rm~tiQn~ made by thelogic synthesis process, there are also ~liffir~lties ~ccoci~tr~3 with efficiçntly and ecol1ol..i-cally conslluc~ing CAD ~t~,llls that co~ ule and display analysis results. Conceptually, 20 after s~rying a design, analyzing a digital circuit involves having the ~esign~rrepe~t~ly (1) ~&~ ~ ...;..e a particular ch~ct~isti~ or pl~ y that the ~l~sign~r wants to know about, such as area, timing or power, (2) ide ~Liry a kind of analysis that will provide i.lfr.. ~;on about that ch~,lf - ;~tic, (3) insllucl the CAD system to ~lrOllll that analysis, (4) display the results of that analysis, and (5) gain insight into the desired eh~ract~ri~ti~ from the dis-25 play. The ~esi~ is int~ ,st~d in cc.. .-l~le~ g these steps as quickly as possible. Digital cir-cuit CAD tools have hicton~lly f~cilitAted this goal by m~king the instruction and display steps cr~ AI;on~lly efficient To improve response times, digital circuit CAD tools have often tightly co~ W the sorl~ that ~clrol,ued the analysis to the sorlwale that per-formed the display filn~ti~n This was often done by having the display sorlw;~e depend 30 heavily on the dau slluclul~ used to process or store the results of the analysis.
For eY~mrlG~ timing analysis often reveals the portions of the mapped circuit that are wo 95t2794s 2 1 8 5 9 0 8 PCI`/U:,~5~ 60 too slow. Reviewing this analysis hi~tQn~ ly has involved e~s . ;n;.~g the sc~ ;c and tracing the critical path. However, as A~es~beA previously, the scl.~ I;c may have little to do with the A~ci~'s HDL source ~Cc;r~tinn of the digital circuit. Thus, the convention-al analysis method does not relate the L~d circuit plub~rm to its HDL source. There-5 fore, it is not easy for the ~eign~ to know what HDL to change to meet the design CO~
Background Conclusion Using HDL ~ le~is can simplify the task of digital circuit design by allowing thedecign~ to specify the ~quired function in an HDL textual des.;, ;l-l;on without specifying 10 thedetailsofthe--~a~pe~lcircuit;--~ I;on Aftercreatingamappedcircuitusingsyn-thesis, the desi n~ can use con~e~.l;on~l mapped circuit analysis tools to ~temline char-~ct~icti~s of the Llla~)pCd circuit. Convention~l analysis will des~ibe such things as the area Co~ ....~ by dirr~ t paIts of ~he ~ ~ ~al~ circuit, or what the longest delay path is through the circuit. Using these analysis results, the Ae~cign~r can then identify which portions of the 5 LU~pCd circuit are ~lub~ I;c However, bec&u~ the op~ ti~n portion of synthesis of-ten llallsr~,lL ,s the design subst~nti~lly~ it is liffi-~ llt if not ;...pos~;ble, except in certain special cases, to relate spe~ific ~olliûns of the LUa~)pUl circuit to the HDL source that gen-erated those portions. This inability to trace the ~ed circuit analysis results easily to the HDL source ~ ,se.lb a ~ul ~t~ l baIrier for analyzing circuits effiriently. Thus, there 20 has been a need for a system which allows the decign~r to analyze a digital circuit design in terms of the source HDL.
Summa~y of the Invention An aspect of the present invention provides a m~th~l for displaying the results of ~y~ P~i>~d circuit analysis visually near the HDL source sperifi~ on that generated the 25 circuit. Circuit analysis provides inr ....~1 ;on about the çh~ ;ctics of each portion of the synthesi7~d circuit. An aspect of the present invention relates the analysis results of each portion of the synth~si7pA circuit to the particular part of the HDL specification that gener-ated that circuit portion. This p.,.~ils the ~1~Si~ner to modify the part of the HDL speçifica-tion that is l~,sponsible for ~l~b'-mC i~ l;1;r.d by circuit analysis.
The ~ lllhei iS ~l~ess works by tr~n~l~tin~ HDL source code into an initial circuit.
F~h point in the initial circuit collGsponds di,cclly with a particular construct in the HDL

Wog5127g48 2 1 85908 P~rUSg5104660 source. A final, more effirient circuit is constructed from the initial circuit by logic optimi-zation. (`I l.nf~~ the results of the analysis to the source l~u~-.,s ide.l~irying points in the final circuit that be traced directly to the initial circuit. Circuit analysis results col~ ,ond-ing to these ill~,ui&~l points in the circuit can th~role be dirf~lly related to the a~ pliate S part of the HDL source, and thus can be displayed near that part.
Another aspect of the present invention provides a methotl for intro~lncin~ lition~l points in the design t_at re_ain tr~ce~hle through the o~ ;on pl~ocess wilh~ul requir-ing ~ n; ~ n or m~lifir~tio~ of the HDL source. The present invention provides these- ~tlitir~n~l points, for eY~mple, by ar*ficially injecting primary inputs or outputs into the 10 initial circuit, and noting where in the HDL source these points came from.
In another aspect of the present invention provides a meth~l for linking information glf ~nf~ from ev~ly~tin~ and analyzing a ~y~lhf~s;~l circuit to the source code that pro-duced the circuit. The present invention est~bli~hf,s the link by providing a de~igner with the ability to mark the synthesis source code in the places that the designer wants to be able 15 to debug. In a current e Y~;...- .~, the fdesignf,r marks the source code with a particular text phrase, such as "probe", along with some ~iitior~l optional il~....~t;on During tr~nSl~tion the tr~n~l~tnr gr .~ es a circuit the provides the same func*on as it did without the "probe" ~ t~..,...nl, but adds ~ it*on~l infc~ - or COIll~On~,lltS tO the ini*al circuit that intlir~te that certain cc,~nf n~ should not be repl ~ed during op*mi7~tion. Reca--ce 20 those CO---pQ~ will not be repl~rerl during opl; --;,~l;on, the circuit analysis results cor-r1ing to any unrepl~~e~ components that are in the final circuit will be directly andl.~re~hly related to those co..~l~l-c~ in the initial circuit. Because those co~-~onents are traceably related to the source HDL, the results are tr~r-e~hly related to the source HDL, and ll.~e Ço lG be displayed near the a~,lu~liate portion of the HDL. Allowing for the inter-25 jec*on of unrepl~re~ co~onent~ by the designf,r f~rilit~tes debugging without rewritingthe flf~signf,r's origin~ ;l ical design or m~nll~lly backtracking through the op*miza-tion l~lvcess.
In anull,cr aspect of the invention, the ~ ignr.r can assign a priority level to each probe to help m~na~ the ~ebug~ing l~lvcess. These priority levels could then be used to 30 activate or deactivate s~ e~l probes as a group. An ac~v~led probe would est~bli~h a link through the sy--ll-ci,is ~ cess to f~^ilit~t~ ~ebugging An inactive probe would have no ef-wo 95/27948 2 1 8 5 9 0 8 Pcr/u~ss,~ o fect on the s~nllle.,is l,locess, and would not est~blich a debugging link. Establishing many links would provide the decign~r with a large degree of debuggin~ n, but could limit the ability of the ~nllle~ cess to provide a good circuit. Fct~hli chin~ too few links may not provide enough ~iA~nce to the AeSign~r to resolve circuit problems. By selective-S ly activating groups of probes at dirr~ times duling the Aebllg ing ~,r~)cess, the Aesi ~n~Jcan analyze di~r~.~,.-l portions of the design without the probes th~mcelves unduly il~
tclÇ~l-ing in the l,locess.
By providing a facility for displaying the results of circuit analysis near the HDL that created the circuit, the present invention allows a Aeign~r to make more effective use of 10 logic S~rnI1Ie;~iS and reduce the CO~ of the circuit debuggin~ plOCeSS.
An aspect of the present invention provides a methf)A~ and system for ~nxe;,s;~.g re-quests from A~signers about the dl~u~ tc ;ctir,s ~c~of1~t~A with the HDL synthesis source ~e~iryh~g a circuit, and di~lajing the results of circuit analysis with a concictent set of display tools that are not inl;...~lely tied to the data ~llUCIUU~, used for the circuit analysis.
1~ Decigning a chip involves con~lluc~g dirr.,.enllc~lcs~ nl; l;onC for a circuit. Some of these Ic~ se -l~l ;onc~ such as a synthesis Aesc~ ;on l~n~l~ge are relatively comp~ct and contain prim~rily fimr,ti~)n~l h~....~l ;on Other l~l)~s~nl~;Qn~, such as a gate level net list, contain COIl~S~Onfl;ngly more ;nr~ ;on~ such as the spe~ifir, types of co.ll~onents to be used~
Still other re~ sç-ll~l;on~ such as a layout ~e.~ ~ ;pl;on, contain even more inro- ---; l;on, 20 such as the spe~fi~ locvtioll of the co~ollenls on the chip. The dirr~ t representqtions can be p~l;l;ol-~ into ~o..-~i-.c with each domain conl;~;ning circuit ~ senl~tion~ with a co.~ n structure. Then the tool builder can develop ~lnmqin dependent display tools for e~7 ...;..;--g the state of the design in that (lnmqin In ~d~lition, the tool builder can also de-velop tools that evaluate or analyze the state of the circuit in a particular ~omqin Display 25 tools showing the circuit sllucluie in one domain can obtain il~' --~I;on related to analysis obta-ned in another ~omqin by the f~l w~d and backward link~q~ges - The ~lesi~n~-r can inquire about the charact~ri~ti~s related to a specific part of the de-sign by first t~--;nil~g part of the design in one domain with a display tool. This domain is the inquiry ~1nmqin After ide~llir"il~g a relevant portion of the design in the inquiry do-30 main, the rlPsigner selects a con~ enl piece of the design to evaluate, and makes an inqui-ry about that piece. This illfc.l~-on con~tit~tes a query. The display tool fc.l~ ls the id~ ,.,;r.c"~ of the object in the inquiry ~Qmqin and an identifier inrli~qting the ~ue~Lt;d analysis or ev-q-lu~inn to a data mqnager The data mqnag~r then ~1ete~ ~ ~ ; nF~s the ~c-mqin that would contain the ~le~al~t analysis results. If those results do not yet exist, the data man-ager invokes the al~ploplial~ analysis tool to cc~ u~e those results, which then may be 5 cached in the data mqnag~r Using the linkage est-q-hlicheA with the HDL-debu~ging meth-od, the data mqnqger locates the related object in the analysis ~Qmqin From the related ob-ject, the ap~ia~ inl~lLu~lion is passed back to the display tool where the ~ecign~r can see it displayed a~plopliately.
One aspect of the present invention provides display tools that are not ~lr,pf n~rnt on 10 the SLI~Clul~ of the ~nmqin in which the analysis is actually 1~,. r.,....~ Another aspect of the invention provides analysis tools that are not depen~çnt on the structure of the display ~omqin Another aspect of the invention is to allow the di~L,~"~t display and analysis tools toremainin~epen~entfromoneano~ .Thedisplaytoolscan...Ail.lAilltheirindeFen~ nce by relaying all of their queries through a central data mqnqgrr. The central data manager 15 l,elrwLus both domqin mapping and analysis tool srlecti~n for each query issued by a dis-play tool. Thus, neither the display tools nor the analysis tools need to be aware of the source or ~estinqti~n of any query.
One aspect of the present invention provides a selecti~n m-q-nage,r which co.. ~
cates a circuit selectiQn made in one display tool to all of the display tools in the system.
20 The sel~ctiQn mqnq~r allows the tl~sipn~r to select a circuit object via a display object in a display tool, and then to view an qlt~nqte display of the circuit object in an qlt rn-qte dis-play tool. For ey-qn~ple~ a circuit object can be sek~tcd using a histogram display, and then that circuit object can be viewed using a text display.
One aspect of the preænt invention cinlrlifies digital circuit analysis before optirni-25 zation. The direct rel-q-tionchir ~l~r~een the trqn~l-q-ted circuit and the HDL text is leveraged to allow the desigl-er to improve the trncl-q-t~d circuit by improving the HDL. An aspect of the present invention allows the decign~r to obtain ChalA~ A~ ionc of attributes such as area and timing of parts of the t~n~l~ted circuit and then to relate ~lltomAtic~lly selected trancl~ted circuit parts to the source HDL from which they were created.
The HDL Analysis System has several advantages over prior art systerns such as Source to Gates. First, the HDL text l~c,wse~ uses the text to parse node links ~esc~ibed ear-WO 95/27948 PCr/US95/04660 lier to draw a box around the entire ~ 1eclc~1 parse node. Such boxes are drawn both when the cursor is moved across the display of the HDL text, as well as when a portion of the text is s~1P~t~ The boxes around the HDL text are much easier to see, and in~lic~te the entire range of the source for the s~1ecl~ ~1 circuit object. Second1y, the HDL Analysis System cre-S ates many more links than simply bel~. ~n HDL source and sCl~ ;es As des~i~l pre-viously, many display and analysis tools can be linked to the ~L source. ~(1 tition~l display and analysis tools allow many dirr~n~ kinds of digital circuit analysis to be per-formed, rather than simply viewing the sc-he .~
One aspect of the preænt invention allows a ~l~signer to relate circuit analysis results l0 visually and quickly back to the text that produced the portion of the circuit that was re-sponsible for those results. This is achic~ed by the . . ~;n~ g the parse tree generated dur-ing the trancl~tion po~ion of sy~lhr.;~, and est~bli~hing a bidire~tion~l re1~tion~hir ~l~. cen a parse node and the circuit cll .u~nlc ~y..lt.~Si7P~ from that parse node. In partic-ular, the present invention provides for storing the parse tree node n~ .~ with each creat-15 ed circuit c1c...~"-1, and storing a list of created circuit e1e.,.. nl~ with each parse node.
One aspect of the present invention allows the ~si~r to display a n~1mcrit~1 phys-ical cha.~t ;~tiC of a circuit ele...~-nt near aleLrcncc to the portion of the source HDL text l~nsible for that circuit Ple"~ This is ~chie~cd by - .,.;..t~i~,;ng references ~lween the parse nodes derived from the text and the circuit clf ~ y~lhesi~d from dle parse20 - nodes. Among the kinds of ~hy~ical ch~ tics dhe ~esi~nP~r would want to know about are the area used by the circuit, dhe time delay from an input or a clock edge to a particular pin on a cell, the l.l1.1~r of gates forming part of the design, the nnmbpr of logic levels from an input to a particular net, or dle power ~ ;p~1. A by one or more cells. Among the kinds of display t~l~,iques sup~lbcd are a st~ PA bar graph, a histogram, text, a padh dis-25 play, a logic il.~cto~, a selPc~ion ~ ~lo" and a virtual schem~ti~. Among the kind oftext display techniques ~u~ d, are hi1ighting, dilr~,~nt fonts, dirr.,..,nl colors, and dif-ferent sizes.
A Brief D~. ;plion of the D- a~
Figure l: A flow di~am showing an earlier synthesis-analysis process.
Fig~re 2: shows ;~ , 1l,c 1;~tP data ~l~uClu~S and dc-m~in~ involved in the synthesis s~.

W095/27948 218~90~ PCTtUS95/04660 Figure 3: shows the general design and debug~ng l"~ess in accordance with the present invention.
Figure 4: shows the rel~tior-chip ~I~.~n HDL text and the mapped logic which makes up a ...~l~pcA circuit.
Figure S: shows how ~d and GTech circuit structures are related to HDL
tokens.
Figure 6: shows how HDL text is related to ~pped and GTech circuit ~llu~iLul~,S.Figure 7: shows how probe sl~te.-.f ..lc are tr~n~l~tf~
Figure 8: shows how a ~ input/}~l~ y output p~ur is created.
Figure 9: illu~llal~S a parse tree ~c~i~ted with some text.
Figure 10: ill~ nt~,s a text le~ sr..l~ n of the parse tree" using " {" to mark the be,L;~ ng of a node and " )" to mark the end of a node.
Figure 11: An e ~n~l-le of VHDL source with no probes.
Figure 12: A parse tree coll~i,~n-ling to the source fr~gmf nt in Figure 11.
Figure 13: shows the HDL source of Figure 11 as a text array.
Figure 14: shows the text array of Figure 13with embe~ ed brace "{" characters sullo~n~ing each portion of the text that forms a parse node.
Figure 15: shows the ~.ln~lf~ text aTray of Figure 14 with each left brace "{"
llUlll~d.
Figure 16: The VHDL source in Figure 11 with a sl~lf .. ~nl probe inserted.
Figure 17: shows the text of Figure 16 as a linear aTray of characters with parse node b~aces ins~,,t~d.
Figure 18: shows the ~)L source of Figure 11 with an improper probe directive.
Figure 19: showsthebracelel)~sf-nl~l;QnofFigure 18.
Figure 20: shows some HDL source with a pair of embeA-lf~ block probe direc-tives.
Figure 21: shows the brace l~ nl~;on for the HDL source of Figure 20.
Figure 22: Tr~n~l~ti~n of the source in Figure 16 accor~ g to the present inven-tion.
Figure 23: An ~ e meth~ of imple.. f n~ g probes in accordance with the present invention.

W095/27948 2 1 8 5 9 0 8 PCTtUS95tO4660 Figure24:A second ~ l;ve mFthod of ;~ F'..~F.~ probes in acc~ ce with the present invention.
Figure 25: A third ~1l. ..~l;ve m~thod of imrle~u~ g probes in acco~lcc wvith the present invention.
Figure 26: shows a GTech circuit with an optimi7~tion invariant circuit structure ;,.,l.le.. ,t.'~ as a yl~ output.
Figure 27: shows the ~ypcd circuit res-llting from the GTech circuit of Figure 26.
Figure 28: A GTech circuit arising from the convention~l tr~nCl~ti~n of the source fragment in Figure 11 Figure29:An oy1;.~ ~d circuit created from the GTech circuit of Figure 25.
Figure 30: An Oyl;~; ~ m~rped circuit derived from the GTech circuit of Figure 22.
Figure 31: An eA~ylc of a display relating il~f('J~ n found from analysis of the15 cly~ized ~yyed circuit of Figure 30 to the source HDL.
Figure 32: shows some V~L source without probe directives using two process blocks.
Figure 33: Convention~l t~ncl~tion of the source in Figure 32 into a GTech cir-cuit.
Figure 34: An Oylillli~d lllaypcd circuit derived from the GTech circuit of Figure 33.
Figure 35: An eA~ylc of a display relating data found from analysis of the opti-mized ~yyul circuit of Figure 30 to the source VHDL showing that infol.llation can only be related to the highest level in the descl;y~ioll.
Figure 36: The VHDL source from Figure 32 with a block probe directive inct~lled - Figure 37: A GTech circuit ge.~ aled by tr~nCl~ting the VHDL source of Figure 36.
Figure38:The mapped circuit obtained by optimi7ing the GTech circuit of 30 Figure 37.
Figure 39: An eY~mrle of a display relating data found from analysis of the opti-2 1 8~0~
WO 9S/27948 PCI`/US95/04660 mized ~ ~ circuit of Figure 38 to the source VHDL showing in~ aLion related to theblock probes.
Figure 40: shows the C~ pOI~t ~ of the HDL Analysis Tool.
Figure 41: shows how the selechon m~n~ger ~l~ce~es the selection Figure 42: shows how the Data Manager yn)cesses a query.
Figure 43: shows a stacked bar graph display of "lapl)ed circuit ih~....~I;on.
Figure 44: shows a st~r~ d bar graph display of llld~ circuit ~.fo....~I;on show-ing the relative crnhibu1ion of one of the sub-blocks in Figure 43.
Figure 45: shows a stacked bar graph display of ~l,l,ed circuit i~ lation show-10 ing the relative cQnhibuhon of one of the sub-blocks in Figure 44.
Figure 46: shows a histog~am display of mapped circuit timing il~ ;or~
Figure 47: shows a text display of HDL source code and GTech circuit informationrelated to that source code.
Figure 48: shows a virtual schc ..~lic display showing the inputs and outputs asso-15 ciated with a particular part of VHDL source code.
Figure 49: shows a ,u~ . virtual sçl.- ...-I;c display tracing the output of the dis-play in Figure 48.
Figure 50: shows another virtual sç~ l;r display tracing the output of the dis-play in Figure 49.
20Figure 51: shows the Path B~Uwsel wil~dow.
Figure 52: shows the logic ;n~eclvr displaying a graphical ,~lese~.t~hon of logic created by the logic i~-s~k~
Figure 53: Display of the transitive fan in trace of a particular signal in the source HDL in accoldance with the present invention.
25Figure 54: Display of the ~ .y inputs reached from Llansi~ e fan-in trace of aparticular signal in the source HDL in acco,dance with the present invention.
Figure 55: shows the stacked bar graph displaying co~ ûllent counts for the AMD2910A.
Figure 56: shows the stacked bar graph displaying co~ ~nt counts for the 30 STACK_BLK mo~ le of the AMD2910A.
Figure 57: shows the HDL text ~,~wser with the source code for the STACK_BLK

W0 95/27948 2 1 8 5 9 0 8 ~crtusgs~ 660 hilighteA
Figure 58: shows an eYvmple of the relq-l;onsl.i~ ~lw~n the text description, the parse tree, the circuit and the display of a circuit analysis result in accorl~lce with the present ill~_nlioll.
S Figure 59: shows the details of the circuit used in Figure 58.
Figûre 60: shows an example of the inter-domain sPle~ n relqtiQTl~hir.
Figure 61: shows the co..~n.~ irq-tiQn flow as the ~3eCignpr analyzes a specificdesign.

Detailed Description of the Invention The present invention comrrises a novel mt~thod for analyzing a digital circuit using the HDL source desc~ ion from which the digital circuit was created. The following de-scription is pleS"-nlf~l to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular applirq-tion and its lcquil~ Various mod-15 ifir,q~tionc to the ~ler~l~d e...~;.. - nl will be readily a~ ,nl to those skilled in the art, and the generic ~ .ks ~tfineA herein may be applied to other eml~l;...c nlc and appli^
cations wi~ Jul d~O~ g from the spirit and scope of the invention. Thus, the present in-vention is not in~.~-lcd to be limited to the e ..kY~ .t shown, but is to be accorded the widest scope c~ t with the ~ ples and fealul~,s ~ seA herein.
In one e~bo~ t-~t the present iml~le-~ I;rn is a sorlwd~e system which is imple-mentedusingcG,.~e~l;onq-l t~-!.ni~l!uessuchasm~ss~qgeFqc.~ing,objectorienteddesign,and opaque data ~h uClu~S. These COnC~JlS are r1Ps~~ in many books on prog. ,.. - .; ng Two such publir~tions are ~ of ~u~ q~lS~PC by Ellis Harowitz, 2nd PAi*on pllblicheA by co~ t~ Sc~enre Press in 1984, ISBN 0-88175-004-2 and Program-25 mir~ in C~t by Stephen De~hu~l and Kathy Stark, publiched Prentice Hall in 1989, ISBN
~13-72315~3.
- 1.0 Digital Circuit Synthesis HDL Synthesis creates a mapped circuit netlist ~les.~ ;on from an HDL description of the digital circuit's funcLionality. The present invention eYtenrl~ an HDL Syn~esis tool.
30 The following sec~ ;Q~ es~ the sll uilul~,s created w ile ~ ;7ing the mapped cir-cuit, and how the ",a~p~l circuit is created.

1.1 Domain Delinitions.
A digital circuit is a physical piece of h~d.~ G.The outputs of a digital circuit are a r....~ of its inputs. Thus, a y~ y of a digital circuit is its fun~ti~.n~lity. Another prop-erty of a digital circuit is the area l~u~d to build it. Another yloy~ ly of a digital circuit 5 is the ~mollnt of time l~uil~,d after a signal has been applied to its inputs for its outputs to contain a valid value. ~uyc.~ies such as area and delay are called cOn..l.~inlS. A digital cir-cuit desi~ s~ s con~ . during s~ ;c The design of a digital circuit can be l~ senlcd or spe~ifie~l in dirr~ t ways within the lllelWl,~/ of a cc --~y~lle~ system. Each type of digital circuit l~)r~s~ l;on is called a do-10 main. Dir~.,nl do.. ~ contain dirr.,l~,nl ~-.-o~ lc of inf ,....~l;on lGga,~ling the physical structure of a circuit. D~ih~s which contain more inf .. ~I;on l~g~ding the structure of the circuitrequire more of the c~ t., 's ~u.,lllul~l and require more of the cc.~yul~, 's time to construct and manipulate. In some cases, a l~ se-~ ;on of a digital circuit is treated as if the lG~ se~.lAI;Qn were the actual digital circuit. Some l~ ,senlAI;onc contain enough 15 ih~fu. ~ ;on to build a version of the digital circuit. This section describes the dirrGlGnt rep-;onc of digital circuits which are used in CAD ~ 7l~,LuS as a digital circuit is being ipned Dc,~il~s are used to store d;rf~ ,n~ l;ol~ of a digital circuit design in aCAD system. In going through the digital circuit design pl~cess, the ~si~e, through the 20 CAD system, manipulates and ll~ul~rulllls digital data in one domqin into other digitAI data in a new dl-mqin Many digital circuit analysis tools are desi~e-l to work with a speçifi~
mqin For e~Q~l le, the timing ~ ~,irlw works in the ~p~ed logic rlomqin Rec~q~lse more ~l.o,t,qil-~A ~<"..~;n~ are larger and slower to manipulate, it is desiraUe to manipulate the cir-cuit in less ~.-tqil--A ~O...q;..c where possible. The following paragraphs des~be what a do-25 main is and the Lrr~l~,l t domqinc used in the HDL Digital (~ircuit Analysis Tool.
A domain is a surl~G lG~ s~ t;on of digital circuit design data that inr~ des com-mon :~llUC~Ulal ch~Uorb ~;cti~s Each dcmqin 1`~1~SG1IlS a particular level of abstraction of the digital wrcuit design illf -~ Some co------on ~o...~i"c include an HDL source do-main, a generic t~l.,-ology Anmqin, which is also known as a GTech domqin, a gate do-30 main, a layout ~c~mq-in In ~litinn, other ~o...~;n~ may be poscibl~.. The digital circuit design data in one domqin can be the result of a l~ulsr~ tinn of digital circuit design data -W095/27948 ;2 1 ;8 ~ qO8 PCT/US9S/01CC0 from anotl,~,. domain using digital circuit design tools, such as a logic synth~ci7er, and li-I"~;es of co...l)ol~rQI~. The int. ~ lte data ~hu~;lules shown in Figure 2 are all members of various ~J~ C
The source ~nmAin cQ~ c the HDL source f~es that the ~ç,ci ner creates in step 100 S of Figure 1 or step 150 of Figure 3. Circuit l~y~ -tAt;ons in this dc mAin may also be called HDL source. The HDL source 900 is also shown in Figure 2. The source domAin also CQnlA;~C the parse tree 901 and symbol table ge~ lcd during the tr~nCl~tinn step of logic s~nll~.sic .Altho~lgh the HDL text and the parse tree are dirr~,e~ epl~se- .l;~t;ons of the cir-cuit, they are in the same domain bec~ce they contain the same il~,...~l;on about the 10 ShuClul~, of the digital circuit. However, it is I~CeS~CA. ~, to estA~lich çffi~ient links ~l~ee.
the ~)L text and the parse tree. A method for ~çcc~ .lishing this will be des~ribe~ later.
In the source ~lnm~in, the digital circuit design r~,s~v-.lAI;Qn cor.lA;nC- infJ...~AI;on about the desired Çu--c~ion of the digital circuit without l~,r~ ce to digital circuit topology. Al-though it is possible to eYpliCitly inctAnti~te technology depend~nt co.l-})o~lents in the 15 source rl()mAin, the source domain generally does not refe,~,nce a specific te~-hnology pro-vided by a silicon vendor.
The generic te&hnology, or GTech, domain cont~inc the initial generic technologycircuit 902 that arises from the t~ncl~tirn step of the ~ lLe~is pl~cess, as shown in step 104 of Figure 1 or step 154 of Figure 3. Circuit ,el,r~sel t~l;on~ in this domAin may also be 20 called the GTech circuit. VHDL co nril~ by S~..opsys, Inc. of Mountain View, California is a tool that creates GTech circuits. Data stored in the generic te~hnology ~om~in cont~in~
inÇo- - -1 ;on about the topology of the digital circuit, but does not have infi,....~ l ;c~n about the specific tf~hnolQg,v to be used. Thus, GTech circuits do not have exact timing or area dat~ However, one can ch~,Gtf~7e the timing and area of a GTech circuit by ascertaining 25 the logic levels and co~ )onf .lt counts of the GTech circuit lcs~ecLi~ely. The logic levels of a path in a GTech circuit is the nun,~. of 2 input GTech gates used to construct the logic co...l";~;..g the path. The cO...pOI.f nt count of a GTech circuit is the number of 2 input GTech gates used to construct the GTech circuit.
The gate, or ~pful logic, doma~n coht~;nC the mapped circuit 903 that anses after 30 the mapping step of the ~nthf ;,is process. Circuit ,~,~Jr~s~ l ;on~ in this tlQm~in may also be called mapped circuits. Design C'omril~ by Sy..opsy~, Inc. of Mountain View, Califor-WO 95/27948 2 1 8 5 ~ Q ~ PCI/US95/04660 nia is a tool that creates marpe~ circuits. Like the generic teçhnology ~lomLq-in, the data in the gate ~om~qin col lA;,-c inlc ~ ;on about how co~one,nls are co,~nP,cl~ tGgelllel. How-ever, in the gate dQmqin, a paTticular te~hnology from a specific silicon vendor is spe~ifi~d) thus providing; n ~ I ;nl~ about the physical charact~i ~hcs of the co~nerll~ used to im-5 pl~ the desired filnctiQn It is in this domain that prel;---;l-A-~ timing, area, power, test-ability, and other cql~)lqtionc of step 105 of Figure 1 and Figure 3 can be _ade.
The layout ~omqin co~ c ih~ n about the ~,. ..f l . ;c plq-cem~nt of the com-,r...Ic on the chip CV~ f and the COI~CC~;ol-c b~ the C-J~ Onen~C. Circuit repre-~ AI;onS in this ~nmqin may also be called the laid out circuit. Cell3 Fnsemble by 10 Ca '~n~e of San Jose, California is a creates laid out circuits. The digital circuit design in-formq-tiQn in the layout ~mq-in is obtai~ed from the digital circuit design informAAtion in the gate dc~mAin by using pl--ement and routing tools.
It is also possible to have ~dtliticnAl dc,--~ as shown by other ~omAinc However, the ll,ajolily of analysis for HDL speçifi~A digital circuits occurs in the ~omAinc ~esc~ihe~l 15 above.
1.1.1 Objects witlun a Domain The digital circuit design ;~v~ ,--AI;nn within a domain is a collectiQn of interconnect-ed objects, with the objects and the c~nl~e.l;~ l.c ~ctccing certain C.~ ;ctics For ex-ample, in the source ~lomAin the objects may include the text of the HDL source code or the 20 nodes of the parse tree cOIlslluCt~ from the source code or the entries in the symbol table.
In the gate 13nmAin~ the objects may include s~f~w~ c~l~se-n~ ns of the individual gates or other library parts or the c~.nn~l;o..~ b~ l.. ~n them.
Sub~u~"l sectionc dçsc~ibe how intra-domain relationships are established and Ained Objects in dirr~ ~, t dc,---A;n~ can be related to each other using links ~ c~lssed 25 in subs~u~.nL sectior~ For ;nClAi~ce7 objects in the source domain can be related to objects in the generic tç~ nolQgy domqin by tracking the parse node which creates each trqn~l~te~
gate. The system leverages the inll~lo...A;n links to allow the ~lesigne- to yelro~ analysis in one ~omAin and view it in another.
1.2 Digital Circuit Definitions This section defines some terms used to d~sc ibe digital circuits. The same terms are also used for s~ rl~ data ~ll u.ilul ~,s which ~ sel t digital circuit comyollents in the var-wog5,27948 2 ~ ~592~ PcrluS95/04660 ious ~
A digital circuit is an int~..;ol-l-~te.1 collectioll of parts. Parts may also be called cells. Ihe digital circuit lcce;~ es signals from eYt~n~l sources at points called ~lhllal ~ in-puts. Ihe digital circuit ~JlOdUCe,s signals for rYt~Pirn~l ~e ,~ ns at points called primary S outputs. Each partreceives input signals and col~.l..,t~s output ~ Each part has one or more pins forreceiving input signals and~l~lu~;ng output si~l~ In general, pins have a ~Ih~~ . Most pins are either input pins which are called loads, or output pins, which are called drivers. However, some pins may be bidirection~l pins which are both inputs and outputs. Bidirectinn~l pins must be h~n-lled s~lly by alg-,. ;11--.-~ which manipulate dig-10 ital circuit desi~ Usually one of two strategies is used for bidirection~l pins; either theyare treated as both an input pin and an output pin, or they are disallowed by the algc, in ~l~estion In this case, the ~lgo~ ;~I,,,, cannot manipulate that part of the circuit.
One or more pins from one or more parts are cr nnr~,d together with a net. Each net establishes an electrical conn~Pction among the c-nnnect-p~A pins, and allows the parts to in-lS teract with each other. Pins are also conl~Pcl. A to primary inputs and primaTy outputs withnets. For the sake of simFlicity~ parts may be said to be "conneclc~" to nets, but it is actually pins on the parts which are col-l-P~te~ to the nets.
Pins, cells, nets and ports may all be l~,fi,.l~l to as circuit clP ~rn~s One or more cir-cuit rl- .. c nl~ form a circuit clP--~.c nl set.
A digital circuit can be spe~fi~A hi~chicdlly. Some or all of the parts in the digital circuit may ~ ...cel~es be digital circuits C0..~ll03e~ of more illt~ ;onnrcled parts. When a high level part is speçifiP~A as a digital circuit of other, lower level parts, the pins of the high level part ~-..e the p~ / inputs and ~ outputs for the digital circuit comrri~ing the lower level parts. If a high level part is co...l osed of lower level parts, it is called a level 25 of hiel~chy.
In the GTech ~c)m~in a l~ic.~cl~icdl digital circuit speçifi~tinn must termin~te with lJlill~i~i~e parts. Primitive parts are not spe~ifi~A as a GTech circuit, but with a fLlced defi-nition provided by the GTech ~l~ç;r.c~l;on or model maker. The ~efinition for a primitive part ~l, e4-;r.P-s the logical function ~çul~lle~ by the part. Typically, these parts are function-30 ally simple, such as nand gates, or gates, inverters, or flip-flops. Some primitive parts per-form a more s~h;~ at~ f....c!;QI~, such as addition In some cases, the primitive part WO 95/27948 ~ ~ ~8 ~ 9 0~ PCI'tUS95tO4660 ~.r~..ls a very sophi~tir-q-ted fimrtio~ such as a micr~lvcess.~.. The GTech spe~fir-q-tion orlogic model supplier1es~ibes thefilnrtionqlity andcharact~i~tics of the ~ eparts.
This may inrlude~ but is not limited to, the logic pc r~.. ~d by th,e ~ e part.
As with GTech circuits, ~d circuit spe~firqtion~ must also t~ q-le with prim-S itive parts. In this case, the ~l~Li.~e parts are supplied by a semi-ccndllct~rvendor and are stored in a technol~gy library. Each part in a semi-cor.-l.,ctol vendor te~hnology library a dc~l;lJlio- of its fimrtion, as well as physical ch-q-r.qct~i~tics such as area, timing and power usage. Primitive parts in both the GTech and ll-a~ed ~omqinc are also known as cells.
10 13 Synthesis ~ ce~s Oven~iew Digital Circuit Synthesis con~i~t~ of trq-nC1-q-ting an HDL description into a netlist with equivalent fimrtionqlity and then o~l;...;,;.-g that netlist to create an improved mapped cir-cuit with the same fimr,tinnqlity. The following section~ ~le~ibe this process in more de-tail.
15 13.1 Transla~on rr~ce..~ Over~iew The conventinn-ql trqn~lqtiQn portion of the ~nll.esis ~lvcess first converts the HDL
text into a parse tree. This is done using conventinnql parsing techniques such as those de-scribed in Comrilers. ~inci~,les. Tcchni~ues and Tools by Alfred V. Aho, Ravi Sethi and Jeffery D. Ullman. A parse tree l~l.,sellb the fim~tionql relq-tinnshirs estqhli~hPA by the 20 HDL text. Various nodes on the parse tree cc,~ ond to filnçtinn~ The trqn~lvtor then con-structs an initial GTech circuit using the parse tree as the guide to sele~ g the a~l,r~liate yfl~ parts and estq-hliching nets among the pins of those parts. The initial GTech circuit will also be hi~,~.;hically ~;irled as l~quil~,d by the parse tree. Illl~ol~lly, every char-acter in the HDL text is related to a node in the parse tree, and every parse node is directly 25 related to a net or a part or a llfllll~ y input or a pfl~ y output in the inidal GTech circuit~
For eY~mrle, each variable declared in the HDL will cc,llG~l~ond to a net in the GTech cir-cuit. Also, registers speçified in the HDL will co~ ,ond to flip-flops or other ~elll~l~y el-ements in the GTech circuit.
13 2 Genen~ Op~mization rrocess The conve-ntinn~l tr~nSl~tion process produces inidal GTech circuits that, if mapped ly to a teçhnology library and built, would be slow and large. To l~ ledy this, the 2 ~ ~q~
WO 95/27948 PCI`/US9S/0 1~60 t~nC~ on ~,locess is followed by an o~ n;~-l;nn process to create a ~ped circuit with lioi charact~ictics than the initial GTech circuit, but that ~e. rv. ~s the same function as the initial GTech circuit. Using a GTech circuit co~ g solely of pl""i~ e parts as an r 1e the convemirln~ ;on pmcess l"~ceeds generally as ~les~ih~e1 below.
SOy ;---;,;--~ a GTech circuit inrl~ es improving the slluc~ of the initial GTech cir-cuit æ well æ mapping the logic in the initial GTech circuit into gates available in the spec-if ied t~ h ~l~gy library. Circuit improve.u~nt ~lgn, ;ll....c may function in either the GTech oq the ~p~d logic ~lom~in.c Thelefol~. mapping may occur at dirr~,cllt points in the op-I;...;,.~l;on pl~1CeSs. Conventinn~l logic ~ ... tools generally ~ r,l"~ some logic 10 i~ e~nt both before and after the GTech circuit is ~ed. The following paragraphs ~es~ihe a general approach to improving the logic in either a GTech or a mapped circuit.
Forl.Pd~hility, the following d~ ~ion of the o~ n;~tion ~lvCeSs ~1esçril~es optimi7.ing GTech circuits. However, the same o~l;...;~l;on techniques are applied to ~ed circuits as well.
15First, the optimi7~tion process identifies oné or more parts in the GTech circuit. This - may include idenlirying all of the parts of the GTech circuit. Those hlt~;on.-~d parts collectively form an id~n*f1~A GTech suh-circuit. The identifi~A GTech sub-circuit has in-puts and ou~put~. An jclentifi-~d GTech sub-circuit output is a net that col ne~l~ an output pin of a part in the id~ntifi~-A GTech sub-circuit to an input pin of a part not in the id~ntif ~d 20 GTech sub-circuit or to a ylhl~ output. An i~ll mifie~ GTech sub-circuit input is a net that con~ a yli~ y input or an output pin of a part not in the id~ nl;r.~l GTech sub-circuit to an input pin of a part in the idPntifieA- GTech sub-circuit. The i~l.o.ntifi~l1 GTech sub-cir-cuit II.e,~Ço~ C~ yut~,S one or more outputs from one or more inputs.
Second, the oy~ l ;on yr~xess devises a new GTech sub-circuit that p."rO~ s the 25 same function as the ir1~ntified GTech sub-circuit. The new GTech sub-circuit has the same inputs and the same outputs as the i-l~ntified GTech sub-circuit. Generally, the new GTech sub-circuit should be better than the id~.ntifi~A GTech sub-circuit in some measurable man-ner. For ~ e, if the ~esign~ iS see~in~ to Consl~uCl a digital circuit with the smallest areapossible,thenthenewGTechsub-circuitprovidedbytheopl;...;,~-;onprocessshould 30 use fewer gates than the i~lentifi~A GTech sub-circuit. If the ~eCigner seeks speed, the new GTech sub-circuit should have a faster timing esl;...AI~ than the i~l~.ntifieA,, GTech sub-cir-W095/27948 2 1 85qO8 PCI~/US95/04660 cuit. In some U~ ;Qn ~loces~s, such as sim~ t~d ~nne~lin~ the id~ontifl~d GTech sub-circuit is SQ~f-~ S repl ed with a new GTech sub-circuit that has worse character-istics than the iA.o...l;r;~ GTech sub-circuit.
~ P on the particular op~ ;on l,locess used, the measurable criterion used S may be a ~ullu~,. t~ for the actually desired ~easule~ . For e~ -1c~ a l~ci n~ may want to ~..;n;...;~r, area of an entire digital circuit being placed on a chip. The opl;...~ ;Qn vCe;~S m ay e~ e the actual new GTech su~circuit area by collntin~ the ~ ûf gates, ûr adding up an area esl;~ e for each GTech part where the area esl;...AIe comes from the GTech part library. Obt~ining a more r -cll~te m~ul~menl generally requires 10 further analysis of the llla~d circuit.
Third, the optimi7~tion process replaces the identified GTech sub-circuit with the im-proved GTech sub-circuit. Rep1ac~-m~-nt means de1eting the parts associated with the iden-tified GTech sub-circuit. The new GTech sub-circuit's inputs are Conl~ecle(1 to the same nets that were con1-ccle~l to the identified GTech sub circuit's inputs. The new GTech sub-cir-15 cuit's outputs are cQnl~ct~l to the same nets as the identifi~l GTech sub-circuit's outputs.
This results in an inle. ~ te GTech circuit.
The c~t;~ lvcess then repeats these dlree steps on the inle~ te GTech circuituntil an ap~lv~liate t~-- ...;n3l;on con-lition arises. ForeY~mp1e, the process could ter-minate when no further impro~e~ was made, or the total llu.ll~l of iterations reached 20 a spe~ifi~d nu~l. If n~e~ , the GTech eireuit is ma~ed, and the optimi7stio~ process may be l~ f~ on the ~d eircuit.
lA Optimization Invariant Digital Circuit Structures Several kinds of eireuit sllucluu~s have a l to 1 evll~ p~e bcl-.een the GTech and _apped dc-msins Such parts are lGr~l~d to as ~1 ;. . .;,~1 ;on invanant. Relating an anal-25 ysis result for a partieular net or part in a ~ ed eircuit back to source text is straight-for-ward when that part of the eircuit is not ehsng~A in the optimi7~tion process. The details of how this coll~;~n~ n~e is estsh1i~hed will be ~1ss~ihetl in a subsequent section Converse-ly, it is .liffic.llt if not ;. . ~1 os~;~e to relate a llJapped eireuit strueture baek to the HDL if that ~d eireuit ~llu-;lul~ has no c-ull~nding part in the ul~o~l;...;,~ GTech circuit.
30 This seetion les- - ;hes severaldirr~ ,nldigit. l eircuitçeatu~s that typical optimi7~tion pro-eesses leave 11nrhsnged during ol~!;"-;7; I;ol-wo gs/27948 2 1 ~ 5 9 0 ~ PCI/US9S/04660 First, u~ generally do not e.l;.n;n~le registers and A~.fin~oA ~ lUl,y e~
such as latches and flip-flops. The tranc1~ti~n ~,locess typically creates a part in the initial GTech circuit for each bit of a l~st." ~l~finPA by the HDL text. These initial parts have a one-~one cc~ ~n~le~ce with final library parts which are chosen by the optimi7~tio~
5 ~locess. Th~l~ro~ partial analysis results ~ teA with the register (such as its area) or nets co~-n~ ~l~ to the register relate dil~ll~ to those in the initial GTech circuit. Further-more, the final l~;ist,r can be related back to the HDL which caused it to be created.
Second, op~ gen~11y do not e1;.o;n~te pli~y inputs and primaIy outputs.
Thw~,ful~ post optimi7~tiol~ ~l~ y inputs and outputs can be related back to pre-op~imi-lO zation parts.
Third, op1; . . .; , ~ gen- ~lly do not 0~4 across levels of hierarchy. If a GTech cir-cuit co~lS; nC a part that is imple. - -- ~t~cl as another GTech circuit, then the oFtimi7~tion pro-cess will op~i.ll-Lc the GTech circuit within that lower level part s~ ely from the rest of the GTech circuit at the higher level. Hie.~u.;hy is also l~s~e~tel in mapped circuits.
Fourth, the u~ i~r can be i~slluct~ not to "touch" a given cell or net. Thus, such cells and nets will exist in both the pre- and post~1;...; ~l;on circuit. However, such direc-tives limit the ability of the c~ izel to improve the GTech or l~ ped circuit. In one em-boJ;...--~t this insL~uclioll is called "dont_touch." In one embo~1;...- n~, dont_touch is a c~ w_ich refers to a particular cell or net in the GTech or ~ cd circuit. In another 20 e--.~1;~-~--t, dont_touch is an ~ttnbute in the HDL 1~ngl1~ge which refers to a part which iS j"Cr~.,1;5~t'd in the source HDL. Cells or nets which are labeled dont_touch are not ~h~n~e~ in any way by the o~..
2.0 Relating Digital Circuit Structures to HDL Source The goal of s~,-tl.esis is to create a ~d circuit netlist ~1es~ ;on from a high level 25 descli~lion of the digital circuit. The ~pped circuit must meet a set of design constraints.
Typically, an HDL is used to specify the high level desc.ilJIion. It is desirable to analyze the final result in terms of the Qrigin~1 source des~ ion.
Analysis of the digital circuit can be done in many ways. Generally, analysis involves taking a digital circuit and co~l,u~lg a n11m~ic~1 ç1~-.~ t,~ of that digital circuit or of 30 parts in t~he GTech or . . . ~l pcA circuit or of nets c~ P~~ g parts in the GTech or mapped circuit. The il,t~ te results of dlat analysis are often Acsoc;Ate~ with parts or nets or WO95/27948 2 1 85~ PCT/US95/04660 both in the GTech or ,na~ circuit. For eY~mple one way to esl;...AIe the area of a ~l"~d circuit is to add up the areas of each of the parts in the n . ~ e~l circuit. The area of each pnmitive part can be found in the library of primitive parts provided by the semicon-ductor vendor. The area of a l~i~ llical part is obtained by applying this area ~u.. ;~-g S lccl~4-.e l~u~ el,~.
As a~lot}~ eY~mrle~ the prop~tion delay through a ..~p~A circuit is ~lele~ ;ne~
by first co~u~-ng the longest delay from the pli~l inputs to each pin in the ~l)ped cir-cuit. This ~cs~tP,s delay illft - .. ~;on with each pin in the I~ ed circuit. For a hierarchi-cal part, the i~ l;. n could be con~ol~ te~ to be the delay f~m each input of the part 10 to each output of the same par~
Results such as area or proF~tion delay refer to the o~limi;~ e~ circuit. If a problem is discovered in analy_ing such results, it is useful to asctl~in which portion of the HDL des l;p~,oll caused the prob!,em~tic mapped circuit Sl1UCIU1G to be synthPsi7Pd It is also useful to analyæ the tr~ncl~ted GTech circuit. ne~ ce generally it is not 15 reliable to depend upon the optimi_er for major impro~ell,en~ in circuit perfo~ nce it is useful to improve the tr~n~l~tP~l GTech circuit before optimi7~tiQn As there exists a direct c~ia~ndPnce ~t~.~ll the :~l1UCI,I1`G of the source ~)L and that of the tr~n~tPd GTech circuit, improving the ~ cl~t~ GTech circuit is accompli~hP~A by modifying the source HDL. I~lh~-~...u~e, it is also pos~;ble to characterize the area and delay of the tr~n~l~ted 20 GTech circuit. Thus, it is useful to relate the ~U.;lulG and l,r~,l~ies of the tr~n~l~te~
GTech circuit back to the source HDL. Th~lef~l~" the rrl~l;nl~ n the tr~n~l~t~-d GTech circuit and the source HDL can be used to create an HDL source level digital circuit analysis tool. GTech analysis will be ~ ceA in further detail in a later sectionThe following sectionC des~be how the rPl~tiQn~hirs bel~ n the source HDL, the 25 parse tree, the tranCl~tP~ GTech circuit, and the optimized mapped circuit are created and used. These rel~tio~hips form the basis for HDL source level digital circuit analysis and debugging Once these rel~tion~hirs are est~bli~heA, digital circuit analysis tools can be linked to the source HDL to assist the dPsignPr in analyzing and modifying the HDL.
2.1 Overview of HDL Soum to Mapped Circuit Link This section provides an overview of how the rel~tion~hip ~I~.~n the source HDL
text and the ~ r~ circuit is est~blish~d Each of the links will be ~es~ibPA in more detail 2 1 8590~3 - ~NDED Slt~ET
2~ P~TEltT
~TTO~NEY WCKE~ NO; 341r5.00014 in :.u ~q'l~ sectios~.
F~ure 4 sllow6 the r~ s~?p betwe~ HDL t~n ~d the mappet ~ T~ HDL te~t 3610 is tbc sour~ repr~ e ~;g~t~l c;rc~. Thc p~fO trco 36~ Y ~2 t~ by par~;n~ ~54 the EII:IL te~
a~J ~ c~ ;~A~ n~ - p?~rsins ~~ ode m t~e parse lree u a~ed a un;que Du~er~cal id calle~ t~e parsei tre~i nnde n~mbcr wl~ ed tO idend~ the ~ode. Bo~ t~ HI)L
le~d; m~l the F~ tree l~elo~ to thc SOUTCe do~ l1~L; gcncric 10~ or GTech d~main 3~ n of ~h~ d;gi~~ nit is cre~te~ Cl ~' E 3~ dac pa~c t~cc. Thc ~n~ppet ~ 3~40 r~ tion of ~c c.;~ptal ~cmt i~ cre~ted ~ 3674 the genenc loe~c Nt)te that each of th~ ~Oft~are 1~ AI~U~L~
of th~ ital circuit ~;;~n i~ ~L Te~ 3~10, pa~e trec 36~ Ta~ dom~ ~30, aT~d mappc~ dc,~ 3640 a~c f mr~ ly ~ rhc ~u~ atio~s cr p~ HDL ta~ 3~54. tral~sla~ng ~i4, ~d o~- ' ' 3 367 ~#D~C tbe way L~ &gltal drel~it is r~.p.f ~ed, ~US not its L de~lr~ n~inn~oDce each O~c these .~r~ n~fE of the d~gital eircu~t has beien cr~ate~ in the vano~ , h poss~ble to rehte c~p~ - in one r.~ 1if.~ ~ ' ilt e;thcr the pre~ or ~d ~
of tb e di~tal circuit. tt is po6Q~le to dcn~o t~ r~ r 1 ~ip betwooE~ ~ any t~o domains by ~ac~g thc 1'4r..r~ C-tn~;otr ~Cp~
Li~ 365~ i~dic~tes tbat t~e HI)L text 3610 can ~e relaud ~ the parse tree ~ A~ " the parPe ~ee to filld t~le node w~i~ rep~e~ t~ the releva~t te3ct.
~ h7~r the parse ~ee 3620 ~an be r~larcd to thc ~L le7¢ 3~10. One ~c~ for rel~ ing p~ ~cc~ ur ~ ith corscs~ or ~ g p~s of a pi~te trcc ~ ~ in a co-pen&~ appl;e~
by C~y c~lcd ~lct~d a~d ~pp~ far Context Se~sitiYe IXsplays"~ ~e 3, LqS14 as US
~yl':~ - T~ber ~81~53,4$~. Anot~er . ~li~c ~l for this stor~s th~ r~ o~t of the ~art a~d cnd of e~ch par~: ~ode. Ano~thçr em~"..t", ..~t StOI~ea the StlC aDt cO~ l IlUmbCT ~rum t~c source ~L ill tho pa~c ~dc.
L3~ 3~G2 i~;c~ t~at t~ ee 3620 ~n b~ rehtet k~ the CTcc~ tl)~ 363a ~ st~r~g ~ list of c~ll its crc2~tcd from ea~ E~arsc no~e with ~o ~ r~t;l~ ~ of that p~r~e nndc.

L~tP.I .PS~

WO 95/27948 2 1 8 5 9 0 ~ ~crlUS95104660 Iink 3666 in-lir,q-tes that the GTech ~lomqin 3630 can be related to the parse tree 3620 by storing the parse tree node nu~r with each cell that is created in trqncl~q-tion Link 3672 inAir~qt~s that the GTech flomqin 3630 can be related to the _apped do-ain 3640 by relating o~ invariant digital circuit ~h u~:~ul~s. O~ I; . . .;, A l ;on invari-5 ant ~llu.;~,s in the GTech ~lomqin 3630 have a one to one cc,.~ P~-~.c with Sllu~;lules in the ...a~ domqin 3640. Th.,.~Çc,l~., link 3672 can be imple ~.e~lt~A by seal~ g for a :~llU~IUl~ of the same type with the same name in the optimi7ed ~ed circuit. An alter-nate e.~ l;.. nt of ~qr~ing o~ ;on invariant ~lluclul,s crn~ ices qccigning a unique l~,f~ nce 1.. .l~ to each l~ vl~ GTech circuit structure and then lelAi"il-g this 10 unique l~f~ ~,nce .. -n~h~. in the COll~ optimi7~ circuit ~I-uclur~.
Iink 3676 i s that the ~l~d do_ain 3640 can be related to the GTech do-m~in 3630 by relating ~I;...;,_l;on invariant digital circuit Sllu.;lulGs. This link is imple-mented using the same mPtho l as link 3672.
2.2 M~l- o~ for ~ qti.~ Mapped Circuit to Source HDL
As de~ihe~ above, ~I1UCIU1~S in the ~y.~lhesi~l digital circuit can be related back to the HDL text. Thus, ~ppcd or GTech circuit analysis results can be shown near the re-lated source HDL. ~Plslting an analysis result back to the source HDL is a several step pro-cess. First, the partial analysis result is si~Soci~t~ with a part or a net in the final mapped circuit. That part or net is related to a part or net in the initial GTech circuit. In Cll~ nc-20 es described below, this r~Pl~tirn~hir is easily es~hli~h~ beca.-~ that net or part did not change during the op~ pl~cess. In other c~ -ces, this rel~tion~hip is very ~iffic~llt or ;"~l ossi~le to est~blich Note ho~ ,. that it is always possible to est~hli~h the rel~ . ~n the GTech circuit and the source HDL.
Figure S shows how a "'~ circuit ~IlU~lUlG can be related to the source HDL. In 25 step 3510, a mapped circuit :illU~:1.Ul~ iS s-PleCt~P~ for tracing. In step 3515, the method checks to see if the ~p~d ~l~uuluue was derived from, and can th-lefol~ be traced to, an OlJIh~ AI ;on invariant GTech circuit ~lluclulG. If that mapped circuit structure is not trace-able, then the pl`OCCSS l~ " ~ s~tf,S In one emhorliment~ a m-Ps~ge rnight be issued to the user that the ...ar~A~ circuit ~lluclul., is not tr~ce~ble If the ~L~uclul~ is tr~e~hle~ step 3520 re-30 lates the ,-~l~A circuit sllu~;lul., to the pre-ol,l;...;7~t;o-- GTech circuit ~lluclule which cre-ated it. As ~e~he~A previously, this is possihle bP~ e the l..ay~ed circuit ~llUC~ulG

2 1 ~8 ~
wo ss/27s4s Pcr/usss/04660 di~ co~ ~n~l~ to a pre-optimi7~tion GTech structure with link 3676 of Figure 4. Step 3530 relates the pre-op1 ;. . ; ,~t;on structure to the parse node from which it was t~ncl~t~A
This is pos~ible bec- ~se the pre-op!;...;,~l;nn ~lluclul~ co~ s a record of the parse node from which it was created. This rel~tinnchir is shown link 3666 of Figure 4. Finally, step 5 3540 relates the parse node back to the source HDL token(s) using link 3656 shown in Figure 4. The details of the m~th~ for est~ liching the parse tree to text link are desc~ihe~l in a later se~tion Figure 5 shows the m~,tho~ for tracing from ~1~ circuit ~lluulul~ back to HDL
source text. It is also possi~lF to begin the m~th~ shown in Figure S at step 3520 when one 10 is tracing from GTech circuit ~llu~lul~s rather than f~m ~ped circuit structures.
~ ulll~ ole, as shown in Pigure 4, it is possible to trace from HDL text to a GTech or to a mapped circuit structure. The meth~l is the reverse of that shown in Figure S, and uses link 3652, link 3662, and link 3672 from Figure 4. A m~thotl for tracing from HDL
text to either a GTech or a ~lJ~d circuit :~llUC;~Ul'e iS shown in Figure 6.
15In step 5620, the sel~t~ HDL text is related to the a~pl~,~liate parse node. This is possible by using link 3652 of Figure 4. Step 5630 relates the parse node to the a~proplialG
GTech part(s). As de~ibe~ pr~iou~lr, this is possible bec~ce the parse node is ~I-o~ d during tr~n~l~tion with a reco~d of the GTech part(s) it creates. This al not~lion is in~1ic~t~ ~
by link 3662 of Figure 4. In step 5640, the program checks to see whether it is pos~iblP to 20 trace from each GTech part to a ~p~d part. This tracing, as shown by link 3672 of Figure 4, is posci~'~ if the GTech part l~ lS invariant during op~ l;on If the GTech part l~dins C~.~;...;,t~l;.~n ill~ia~ then the plocGdul~ returns a ~l.ped part for each GTech part. Otherwise it le .~ t.s at step 5650.

3.0 Probe D;r~cli~s 25As described previously, it is possible to relate .,lap~ed circuit structures back to the HDL if there is a 1 to 1 cc.ll~ ondence to GTech for them. Although several kinds of GTech circuit sllu~ lul~s are preserved by typical ~ti~i~.~, these parts might not exist in rr~ to derive a sllffi~ient cC~ enr~e between the source HDL and the c,~ e~ ,pcd circuit in some cases. I~u~ .e, the ~ tribution of where these parts30 are located in the ~ap~cd circuit might not cc,ll~ond to the parts of the ~yped circuit l.,quili,-g analysis. Th~"~ÇulG, it might be ncces~ ~ for the design~r to specify ~ddition~l Wo 95/27948 2 1 ~ 5 9 ~ ~ PcrluS95/04660 parts of the HDL which can be traced to the final ~ed circuit. An aspect of the present invention uses "probe" directives in the source HDL to specify the ,leal,on of ~q~ itinn~
op-;...;,~l;nn invariant parts in the GTech circuit.
Probe directives irl~h ucl the tr-q~ vtnr s~ flw~i to co,.;,h u~il an initial GTech circuit 5 with certain points in the GTech circuit mqrk~,d so that those points are preserved during the ~ubsequ~nl optimi7-qtion ~l~ucess. In ~dditinn, the usual o,~ l;0n invariant struc-tures will also be preserved during optimi7-q-tion The following se~!;o..c ~es~ibe how an HDL desc,i~lion of a digital circuit with probes is sy--~ ;>~ and the res-llting mapped circuit is analy_ed. An e ~ r sho-wing how prob,es guide the construction of the mapped 10 circuit and allow analysis ~n Ç -- n 'I;~:?n to be related to the HDL source text is then provided.
3.1 Probe D;.~ Usage It is i~l~lt that the ~esi~ can easily control when and where probe directives cause op~ ;0n invanant ~lluclul~,s to be inst.~d into the ~pped circuit. The follow-ing sections describe diff,rcnt types of probe directives as well as a nlethod for enabling 15 and rlicq,k1ing probe directives will~oul modifying the HDL source text.
3.1.1 Types of Probe Direch.~s In a ~,~sw.lly ",~,f~ ,d e~bo~ F-nt, a probe directive is a single text string that is a cc,... ~,nl in the HDL l~ngll~gÇ. The probe directive begins with c-h~-acte s that in~ te the be~;.. ning of a co.. ~t In VHDL, this is a " ". In Verilog, this is "/r~. The next word is 20 a ~yw~.ld that intli~tes to the tr~nCl~t~r that this cc~ 'l is a tr~n~l~tor direcdve, and not a mere co.. ~ nt In one e.. ~ l, this k~"~wul.l is "Sy.. ù~.. y.. ". After the keyword, comes a probe declaradon to ;~ tc what type of probe it is. In one e nho.l;..~ t, a state-ment probe is inflic~t~ with the phraæ "probe~ t~ nl". After the probe declaradon comes an opdonal search string that is used to id~lLify the type of nets in the GTech circuit 25 to insert optimi7~ti( n invariant GTech circuit ..l~uclu~us. An eY~mrle of an optional search string is "all_mux_controls" intli~ting that the control lines to any mllltirleYQrs should be probed. The search string il~ ,..zl;on will be desç~ later. After the search stIing comes optional probe strength ;~fo....-l;Qr~ Probe strength is an aspect of the present invention which provides a convenient meth~ of activadng or deacdvating groups of probes. In one 30 e nl~;.~ -l; probe strength is inflic~tç~ using a nllm~i~zl value from 1 to 5. This feature will be ~sçr~ further in a later se~tir.n W095/27948 ~ 1 859~`~8 PCI/US95~ fiO

Thus, a sample probe directive in the VHDL l~n~)a~e is:
- Sy,.~s probe_sl ~e ..~ nl all_mux_controls 4 A basic type of probe du~i~e is a ~ . ,Y nl probe. S~ -tf .,,rn- probes use the syntax rlf~ beA above, but do not include any search string. In one c,llbo~ f nl a s~ t S probe sdects the first parse node following it.
Another type of probe directive is the block probe. A block probe is flf fine~l by two text strings. The first text string is the block starting string. Like the sli~t~ ..rnt probe, it be-gins with a CO~ f nt starting symbol and a ke~lwuld. In one embo~imf-nt, the keyword is followed by the phrase "begin_block_probe". This phrase is followed by an optional search 10 string. This phræe is followed by an optional string with probe strength info....~l;on. The second text string is the block ending string. In one emho~liment, the keyword is followed by the phræe "end_block_probe". A sample pair of block probe directives in the VHDL
l~n~?ge iS:
-- Synopsys begin_block_probe <VHDL ~I;.I~.. ,~rnl~
- Synopsys end_block_probe In one e~ n~, the begin block ~r~bcJf nd block probe phrase pair cause all of the ~b. l-. ~n the begin and end phrases to be probed. Details of how block probes are ;~ le~ n~ nl~ will be eYrl~ine~d later.
Multi-probes are imple .. ~ulfcl by using Sl~ t probes and block probes with search strings. Search strings are text ~Je~ ;nn~ that are used to choose the nodes or nets to probe. In one e.-lbo~l;..~f-nt, the search string is used to select particular types of nets as-soci~-~ with the GTech circuit parts. For eY~n~rle, multiplexf~rs are Cc!.. o,-ly used to im-p~f~- ...,.~l col.~;l;Q~ ,s~;nnc The multiplexor control lines are lin~ed to GTech circuit 25 ~llu~;lu~,S :~cso~t~d with the con~1iti~n and the data lines are linked to GTech circuit struc-tures ~CcO~tf~l with the ~kf~n~tives. A search string such as "all_mux_controls" could probe the nets that are connf~te~ to m~lltirley--r control lines. This would allow the design-er to gain insight about the c~n~ ;ons. Pollowing is an eY~mple of a multi probe which se-lects all mux controls in the VHDL l~ngu~e' - S~-l~sys probe_sl ~tf ~enl all_mux_controls WO95/27948 2 1 ~908 PCI/US95/04660 3.1.2 Selecting Probes The . . .-ppc~ circuit p~;luced when probes are used most likely will be dirr~r~nL from the ~ circuit that occurs when probes are not used. Because probes int~,r~ with the ability of the op~ to pru.luce higher quality - - al-~f~ circuits, the l~f Ci~f r generally 5 willonlyusethemwhenthe ~ ;r,nf ~ needstogatherparticular;..fv....~ ?n Duringthede-b~ n~ Ce,SS, a ~ .r may insert many probe directives into the HDL source at var-ious times to dis~o.er the char&,~ ;cs of dirr~ parts of the ...~p~e~ circuit. As the design ~ Cf ss l~lo~,sSeS, the tlesignf r should require fewer probes. One of the tasks that the ~es~ f r faces is then m~n~ing the probes as the ~eb~lgging needs change. One way to 10 do this is for the ~f ~ignf r to add and remove the text of each probe directive as l~UilGL
This burdens the ~eSigner with a tedious text editing chore.
An aspect of the present invention use a probe strength field in the probe directive in the HDL source text. Before initi~ting the ~ I.esis ~loce ss, the ~lf si~f r speçifies a pro-cessing strength. All probe directives with a probe strength greater than the ~loces~ g 15 strength are treated as active probes and lh~ f~l~ should be ~,loce~sfA All other probe di-rectives are ignored. This means that a ~esignf r can set the probe strength to a small value in the ~let~ilf~ po~tions of the design, and then set the probe strength to a larger value at higher level ~ulliolls of the design. By ~,ccirjing a large p~ces~ strength, the designer would get a ...al ~ circuit with fewerprobes, and provide the ~I;...;7~ with greater flex-20 ibility, but COll~ ;ng less il~f ~ ;on dil.,clly related to the source text. Specifying asmaller l~l~e;r~ g strength would in.il~ase the nun~bel of probes, but would also impact the ~pcd circuit.
One m~thod of ;--~ g this probe strength field is to modify the tr~nsl~tionl,locess shown in Figure 7. In particular, in step 4120, the parse nodes collG*~onding to 25 probe directives are m~rked At this point, the probe directive's strength can be extracted from the text and cc,llll~. d with the speçified pl~cessh-g strength. A probe directive lack-ing the requisite strength is sirnply ignored.
Anot_a m~thod would involve ~ hing the probe strength to the nets that get m~rk~A, and allowing the opl;---;7~;- n process to selectprobe nets with probe strength less 30 than or equal to the ~loces~;ng strength.
In anotll~, emk~d;.n~nt, the probe directive could include a ~eçifi~tion field tnat WO95/27948 2 1 ~ 5 9 D 8 PCI/US95/04660 cQI-lA;~ text. The ~lçcign.o,r could specify a text search cont1itiQn Such a cQn~lition could include a regular eA~ ion used for ~efining text s~cl~s. The sy..tl.e;,is ~)cess would then ~ cess probe directives that satisfy the cQn~lition, and ignore probe directives that do not satisfy the con-litiQn 5 3.2 Synthesizing with Probe ~ s Figure 3 shows the general design and ~lebu~ing pl'~cess in accol~nce with the present invention. The deci~çr writes HDL with probe dh~~ ,3 150. The probe direc-tives identify the places in the reslllting mapped circuit that the ~lei~e~ might wish to ex-amine. The fl~i nçr might not initially know where probes will be required until later in 10 the design ~lucess. The probes have no impact on filnctiQnqlity so runc~ional cimlllvtioll 101 and r~ c!;o~l repair 102 proceed as before. The ~lecign~ also consL,~-s ~y~lhesis 103 as before.
Srth~ci7ing with probes 154 differs from conventionql s~y.ltl-esis 104 in the transla-tion step. When an improved tranclqtor e ~co!~ e :- a probe directive, that tr~ncl~qtor creates 15 an optimi7~tiQn invariant ~ UClul~ at that point in the GTech circuit. The C~li lli~e, then lJ~luces a new ~ circuit with ~l~litir~nql o~ l;Qn invariant structures. In one embo.l;.. ~t, the probed portions of the HDL source are treated as both primary inputs and ~Ih~ y outputs during tr~n~l~tion and optimi7~tion ~ltPrn~te ~ --.t~ of imrlemPnt-ing probe directives are clesçribeA later.
The . . ~ circuit analysis step 105 p~vceeds as before. After analysis, the tool then uses i lfb....~l;On developed dunng l.~ zl;nn to rdate the results of the analysis to the ~)L source a in~ tPll by step 120.
With the lllf~ n glP~n~d from the probes, the cleci~er can now identify prob-lems and evaluate solutionc that du~lly change the ~)L, as shown in step 121.
After completP~ly analy_ing and debugging the design, the mapped circuit is fabricat-ed in step 106.
- 33 Method for Implementing Probe D;recli~es Figure 7 shows a m~.tho~ of ;~ .le ..~ g probe directives. The ~-vcess begins instep 4110 by con~l-ucLing a parse tree from the HDL source text using co..~el;l ;on~l parsing 30 techniques. The data structure ~ .,se l~ of the parse tree should effi~iently link the ch~l~ in the text to the parse node cQ~ ;n;-.g those ch~l~, and ~1tlition~lly~ it ~1~8 5 9 (~ ~3 ~Er~ Sl-l~ET

~ ATE11T
A~ToRNE~' DOCKET .1lO: 34175.C~

shouli err;~ allo~ c~Li~3 tl~c c' ~ sC~ et with a parsc wdo. O~e l~c~ f'or rela~
p~~;~ r p eces of t~t with c~-r: '1 ~ pa~s of a ~se tree u~ d~;b~t m a co-pe~tmg, ~ n ~y Grcgory cntided "M~t~od a~d Apparatu~ for COD,tCS~ Sr~ ~ph~, filCd on Julle 3, 19~4 a~ US ~l~Y' ~ ~

1~ ~Lep 4~20, the parsc notea cu,~l~h~ ~ to vanous probc .Lc~t;.~. ~e ~srkct. The detail~ of t~
process l~rC C141~-'- ~ a iu a l;~ter 5CC~iOII. Tnere ore three ~pes of prche directi~e~: ~l~we--l probes., bloc~
plO~;5, an~ m~l~i probes. b~u~ be t~r-~c ~ ~ into zero or ~ore st~t~ -~~ or block probes .~nd then t~eated as such. Tni5 ~ ~u~ ;u ~diil be de~cribed m a lal&r 9cction; th;s s~tion a~uma ~hst multi prob~s have been pr~ tran~forme~
A ~ robe is a sil~gle te,~ string. The p~ie ~ode that ~foltcn~ he siDgle tu~ stri-lg ~s tb~ parse notc to marl~. A blocl~ probe con~i~ of two te~ ~tring~: ~ be~ bbcl~ aud a~ eDd bloclc st~',c Tn gL~eral tem~ he parse ~ 'be~3~n" the b~ ~ d e~d blocic ~tatcmcnts ~e the po~s6 nodes to marl~
413~ thC u~plo~cdGToch ~ 6 ~ ted~m the~arlc~ ars ce co~t~ucteti~
412C u~ u~ve~iA~ Prh~i ~UOS T~e ~Tech circu~t ~ r E~rocess also co~structs a lid ~f parts ant nets asso~ted with each par6c node.
I~ step ~ iL~p 4150, allt StCp 4160, o~Jt; " ~.t~nn Lu~;~l CTes;h ci~c~it s~ucturcs ~re added ~or each mar;~ct pa~6c ~odc. One ap~.v~ to addin~ an o~A ~ GTech drcui~ s~L,c.u~ is to cre~te a p~ y mput ~n~ ap~ output. l~he foll~ pl~ t - oQhow t~ils is da~c. .~ t~
mct.~od6 far crcating opdmi~tioQ .~ ~ . ' arcuit a~ uC~u~ cs will be t~iked ~ a late~ sectio~ r~Ote ~t the digi al a~cuit fuDct;o~ is ~re~ d by CODUCC~mg t~a~ primary ~nput a~d prir~ary outpuS aS the ne3~ er L ~ _t ~, Thcrc~ n st~p 4135, ~ adrl;t;on~1 Icvel o~}lier~yi~ added if t~ ~igital dra~it d~es not ha~h, 8 bi~ lcvel of 1 c,h~ a~t ~ore ~e ~nar~ed pa~se ~odet~
hl 6tep 414~, all ol~ the par~ that wcrc ~ olu n~rkcd pa~c rlotles ~se markct. T~s, some p~s ar~ marke~
IP st~p 4150, ncts ~ d wi~ t~c maJl~ed parts ale m~l~et. T~ose marlccd r L~IJPJ .PSO

WO 9S/27948 2 1 8 5 9 0 8 PCI/US5S~ 0 will be broken by new ~ input/pl~ y output pairs in order to form ~1; . ";7~ n in-variant GTech circuit ~u.;lul~,s. The nets to mark are ide-ntifie~A as follows. First, note that the mqrlr~A parts fc,l~ a GTech sub-circuit. The GTech sub-circuit has input nets and output nets. A particular net is a GTech sub-circuit input net if the particular net is connpcle~ both 5 to an input pin of a part in the GTech sub-circuit and to an output pin of a part not in the GTech sub-circuit or to a pl~y input. A particular net is a GTech su~circuit output if the particular net is co~ r~-lrA both to an output pin of a part in the GTech sub-circuit and to an input pin of a part not in the GTech sub-circuit or to a primar,v output.
By probing the input nets and/or the output nets of the GTech sub-circuit, the behav-10 ior of the GTech su~circuit can be observed. Thus, there are several c-hoices for m~rking the nets qCC~qt~d with the mqrkÇd parts to allow the insertion of opl;...;~;~l;Qn invariant GTech circuit ~lluelules. One choice involves mqrkin~ only the input nets to the GTech sub-circuit. Another choice involves mqrking only the output nets to the GTech sub-circuit.
A third choice involves mqrking both the GTech sub-circuit's input nets and output nets. A
15 fourth choice involves sP~ g nets that meet a search criterion AefinrA in the search string portion of the probe dil~ c~i~
One of the ~ ceAi--~ opdons is chosen for mqrking the nets. Then, each of the mqrk~A parts is c-~".;~rA The order in which the mqrk~d parts are eYqmin~A is unimpor-tant. Any nets which are co~nr~tc~A. to the part and which meet the mqrking criterion are 20 mqrk~A There is no si~nificq-nce to mqrking a net more than once.
In step 4160, an Op1; ..;~-I;QI~ invariant GTech circuit ~lluclule replaces each net ".~ A in step 4150. There are several choices for creadng such a structure for a mqrke~
net. As . .w ~,l ;o~rA. previously, one choice involves creadng a new primary input and a new primary output for each mqrkçA net. Another choice involves creating only a primaIy out-25 put. Another choice involves attaching the net to a rt~isl. l . Another choice involves attach-ing a ~ ly or a chq-r~ct~ictic to the net that instructs the optimizer not to modify the net.
Another choice involves creating a new ~I; ..;,~l;on part which is mqrk~ so that the op-dmizer will not modify it during optimi7qtion. This part has one input pin and one output pin. The net is then split into two parts. One part remains col nr~;l~ to all of the input pins 30 on the ~ riginql net and is also co~ r~l~A to the output pin of the new part. The other part lclllalnS c~ r~t~d to all of the output pins on the cngin-q-l net and is also coluleclc;d to the wo ss/27s4s 2 1 8 5 9 ~ 8 Pcrlu~sslo1cco input pin of the new part.
An advantage to creating the optimi7qtion invariant ~lu-;lul~ by adding a new prima-ry input/p~ output pair is that optimi7~s treat 1~ inputs and outputs as invariant.
Figure 8 shows how a new pl~r input/~.~a"~ output pair is created for each mqrk~S net.
In step 3810, a new ~l~y input and a new ~y output are created.
In step 3820, an input net is created and ~ ched to the new ~ U.~ input. An output net is also created and q.~i.cl~e~l to the new pl~l output.
In step 3830, l~c~.use the GTech circuit being plucesse~ is part of a hi~ ;hical de-10 sign with a higher level, the new lJl~y input and the new lJli~ output are connectecltogether with a new net at the higher level in the design.
In step 3840, the input and output nets are connf,cl~l to the eYisting GTech circuit.
The output net is connected to every ~ / input Conne~te~ to the mqrkP-l net. The output net is also co~n~rted to any output (or driver) pins that are cr.nnr~t~.l to the mqrk~l net.
15 Note that if net mqrking was chosen to ~ only output nets from the mqrk~A GTech sub-circuit, then the output net will be connected to the pins connf~t~3 to the mqrk~l net that belong to parts that are not in the mq~rk~d GTech sub circuit. The input net is conl-P~e~l to every p~hl~ output conl-ecte~ to the mqrk~d net. The input net is also conl-ec~e~l to any input (or load) pins that are col...ect~ to the mqrk~l net. Note that if net mqrking was cho-20 sen to mark only output nets ~om the mqrk~d GTech sub-circuit, then the input net will be connr~te~l to the pins conn~cte~ to the mqrk~d net that belong to parts that are in the mqrk~
GTech sub-circuit.
In step 3840, the ~ hod shown m ay treat bidirectinr~ql pins as either input or output pins. However, all bid ~;! ;-~nql pins should be treated in the same way.
25 33.1 Example The m~tho~ ~esç~ l above can be used to create the GTech circuit shown in Figure 22. First, concider the VHDL source shown in Figure 16. The source text is repeated hereforcon ~ n~e:
lOOOif (C and B) then 1001--Syn~psys probe~ ement 1002Z c= not ( A oq B);
1003else 1004Z <= not B;

W095~7948 21 85908 PCT/U~5~1CC0 lOOSend ~;
r~y~ nt 401 in Figure 16 is a probe directive which causes ~ .... nt 402 to be probed. The parse tree for the VHDL source is constructed in step 4110 of Figure 7, and is shown in Figure 12. In step 4120 the probe parse nodes are mqrk~A In this case, node 1004 5 of Figure 12 is mqrkPA In step 4130, the parse tree is tr.qn~lqted using coll~,e.-l;onq-l meth-ods. The reS~ ng GTech circuit is shown in Figure 28. In step 4135, a level of hierarchy is added if necess~ ty. For the PU~1JOSC of this eYqmrle~ it is q C,mmP~ that a level of hierarchy eYists above the circuit fragment shown. In step 4140, the parts and nets from the mqrkPt3 parse node are mqrkPA In this case, net 280 is mqrket1 bec-.~se it was created from state-10 ment 402. In step 4150, nets qCsQc~-q-teA with mqrkP~1 parts are mqrkPA Since there is only a mqrk~d net, no - ltlitiorlql nets are mqrkPA III step 4160, an o~ l ;on invariant circuit u~ , is added for each mqrkPA net.
In this eYqnlrle, a pl~ input and ~lilllal~ output pair will be added as shown in Figure 8. The reclllhnP GTech circuit is shown in Figure 22. First, a new primary input 203 and primary output 221 are created in step 3810. Next, input net 223 and output net 222 are created in step 3820, and cQn--e~e~ to pl~ input 203 and plilll~U~/ output 221 respec-tively. In step 3830, primary input 203 and pl~y output 221 are conn~lefl at a higher level of hi~,.~chy. In step 3840, the input net 223 and output net 222 are col~nc~leA to the rest of the GTech circuit. Input net 223 is con~ le~3 to all of the driver pins that wGre con-20 nected to net 280. In this case, input net 223 iS connc~lcd to driver pin 224 on nor gate 233.Output net 222 iS col~ ~t~A to all of the load pins that were col-nf~lcA~ to net 280. In this case, output net 222 iS con~ t~ to loadpin 225 on mllltiple~r 231.

4.0 Implementation Particulars This section cont~;l-.c ~ ;l ;f' details of how the links bel~.~n the flom~inc are estab-lished and ...
4.1 Creating the Text to Parse Node Link ~ )L source is first parsed to create a parse tree. The nodes in the parse tree must be linked back to the ori~in~l HDL source in order to enable tracing from the HDL source to the ~ )pcd circuit. This section ~es~iheC how the parse tree to HDL source relationship is est~hlich~ and used.
Parsing involves creating a parse tree from an array of text in accordance with the wo ss/27s48 2 1 ~ :5 ~ ~ 8 Pcrluss5lo466o rules of a l~n~u~ Co-pçn~lin~ appli~ ~tion by Gregory çntitled "Method and Apparatus for Context Sensitive Displays", filed on June 3, 1994 as US applie~Qtion ~.. 1~ 08/
253,453, provides an overview of the parsing process and provides an effi~içnt data struc-ture for relating text and parse nodes. This section eYrlQinc how to use the rel~tionchir be-S tween text and parse nodes. In particular, a mPthf~ to relate a probe directive to the ap~ ;ate parse node is fl;c~ c~A
4.1.1 NoJation Demarcahng Text into Parse Nodes Figure 9 ~ tes a parse tree QCcociAtp~ with some text. This eYQmple comes from a}~ U.S., ~ l;r"l;Qn 08/253,453. The parse tree consists of nodes 39100, 39101, 10 39102, 39103, 39104, 39105, and 39106. The cl~ . t ~ 3901 through 39013 ~ sent ge-neric characters. Using conv -nti~ n~l parsing mPth~c, characters are ~oul,ed into parse nodes. When parsing is cc-n~rlete, chQ~Q~ ters are Qcsoci~ted with the parse node they define.
In this ~-~-..ple cl.~ 3901, 3902, 3903, 3904, 3905 and 3906 are associated with node 39102. C~ 7~-t~ ~ 3907 and 3908 are QCSOC ;At~ with node 39103. Characters 3909, 15 3910and 3911 are QCSc~Qtr~ with node 39105 andchQ~ctPrs 3912 and 3913 are associated with node 39106.
Figure 10 illu~hates a text ~ ;on of the parse tree using "{" to mark the be-g~nning of a node and "~" to mark the end of a node. This .~ s~ nlAI;on is called a parse array. For ~ . .l,k, left brace 3930 and right brace 3940 log~ contain all of the text and 20 nodes QcsQ~Qted with node 39100. Left bra_e 3931 andrightbrace 3941 d~ ale the text and nodes ac~oc :~l~ with node 39101. Lef~ brace 3932 and right brace 3942 de~.;ate the text 2~sOci~t A with node 39102. Left b~ace 3933 and right brace 3943 de.,.al~ate the text QCso~iQt~ with node 39103. Left brace 3934 and right brace 3944 d~ar~ate the text asso-ciated and nodes with node 39104. Left brace 3935 and right brace 3945 de.~ ate the text 25 QCcoeiQtp~ with node 39105. Left brace 3936 and right brace 3946 dc~ ucate the text asso-ciated with node 39106.
Note that pairs of left and right braces are nested within each other. For example, brace 3933 and brace 3943 are nested within brace 3931 and brace 3941. They are also nest-ed within brace 3930 and brace 3940. Thus, ch~ctPrs may be ~ul~uu~lded by mllltiple pairs 30 of braces. For cY- , lc. c~ -,h~ 3907 is surrounded by all three of the pairs of braces men-tioned above. However, brace 3933 and brace 3943 make up the inn~ -OSl p_ir of braces woss/27s4s ` ~ 1 8~9û~ PCT/U~9S/01~0 which sul.ou-.d character 3907. The conce~ts of l~,r~...o~l and ri~ l are also useful. An a~lay is con~ ~ed to be a cont~ oll~ list of characters, the first of which is the leftmost chal~t~,l of the array. Each succes~;~e chal~t~,l is concidered to be to the right of its pre-decessor. The last character in the array is the ri~ O~l cll~t~,l of the array. Thus, a char-

5 acter is concitl~ed to be ~lerl--~sl~ if it is the ç~ ,te~ fulllle;-l to the left which fills a cc n-lition R~ c~ ely, acharacteris cnn~:de ~,d to be"n~ " if it is the ch~t~l fur-thest to the right which fills a con~ition For eY~rnrle brace 3943 is the lerL~.O~ right brace to the right of character 3907.
4.1.2 Text-To-Parse Node Mapping and Parse-Node-to-Text Mapping ~l~rping text to and from the c~.hl~;n;l-g parse node is e l~l~in~A in co-pen~ing U.S.
application by Gregory filed on June 3, 1994 as US applif~tion 1------~l 08/253,453. The previous section showed a not~tion that related the parse nodes to braces imrlicitly embed-ded in the text. A given character in the text is ~ pe~ to the parse node that coll~sl,on-l~
to the ;.-n~ ....OSl braces that contain that çl-~ t I.
Figure 11 shows an eY~mrle of HDL source. Figure 12 shows the parse tree which is g~nelalcd from this source. Figure 13 shows the same HDL source as a text array.Figure 14 shows the text array of Figure 13 with e -l~edde~l brace "{ )" ch~act~ luulld-ing each portion of the text that fonns a parse node. Figure 15 shows the annotated text ar-ray with each left brace "(" ~.. k~ ~ The line breaks in the figures ~iepicting arrays exist 20 only to allow the drawings of the arrays to fit on the page. A co. ..l..lt~, ~u~alll treats arrays as ccnti~loll~ lists of Çhpr~sct~rs. The characters '~n" and '~\t" inAi~ste l~. line and tab char-acters l~s~c~.~ely.
Note that Figure 15 shows an slt~n~ste ~l~,S~ l;on of the ch~-~cte s as "X" as ex-plained in co-penAing U.S. appli~s-ti~ n by Gregory filed on June 3, 1994 as US application 25 nul~ 08/253,453. For the pul~Joses of clarity, the figures in this appli~tion will show the actual chs. ~ , although the technique e~ ed in co-penAing U.S. application, by Gre-- gory filed on June 3, 1994 as US appli~ation number 08/253,453 may be used to improve the ~lr~ sn~e and lll~.llVl,~ S of the system.
- As an c ~ le ch~s-~çtçr 4132, the "o" in "or", will be traced to its coll~spollding 30 parse node. First, the parse node co~ çhsrs~t~ 4132 is l-,t ...;. ~A This is the parse node that begins with brace 4307, since it is the parse node cull~ )onding to the ;n.~ç.. . .O~, WO 95/27948 ` ~ l 8 5 9 D ~ PCr/US95/04660 braces co~ ;ng ch~ct&!r 4132. Next, the parse node m1mher is Af,te ..~ &~ This is done by counting the l.u~r of left braces which l,l~ede brace 4307. Since there are 7 left brac-es prior to brace 4307, it ,.,~l~sents node null.~. 7. Note that this ..~ is the same num-ber that is c~1c~ t~ by ~lrul.lling a p~ ~ traversal of the ~ridn~1 parse tree and 5 ~ each node as it is traversed.
T~c~tin~ the text which cc,ll~,~nds to a given parse node uses the same data struc-tures. First, the l,ll~ f,l of the parse node is asc~l~ned. In one ~mbo~1;...f .-1, the ~ .. kc of the parse node of interest is stored with the parse node. In one emb~1;...- .n, the number of the parse node of interest is c~1C~ t~3 from the parse tree by ~ ~r~ g a preorder travers-10 al and ------hc- ;ng each node as it is traversed. In one e.llbo 1;...- -.l, the nl~ h~' of the parse node is c~lc~ t&~3 from the parse array as Aescriber3 above. In one & ..,~l;,..f -t, the number of the parse node is available be~uc~ it has been previously stored. Once the 1l1ll l .~l of the parse node is r3f t~ ~, the ~soci~1~3 text is found by co11nting left braces in the parse array until the correct number is reached. Any text ~ e n the correct left brace and its lS b~1~ncin~ right brace is related to the parse node.
For ex~lnrle, the or e A~ n can be found by connting to the seventh brace, brace4307 (starting from 0), in the ~ ol;~t.~3 text array.
4.2 Parsing Probe D;re.li~
Inoneç--ha~ nl,probedirectivesareco~............... f-nl~withintheHDL1~n~ge.During 20 COI,~,C ~ n~1 lexical analysis and p~r~in~, CC~....h nl~ are discar~f d by the lexical analyzer or the parser. Th~ ol~, probe d ~ S must be parsed spe~lly in order to ~eh ...ine which parse nodes are ~rLct~ ~ by each probe directive. This section describes how probe directives modify the parse tree. The mfylified parse tree is used to ~letf rmine where addi-tional u~l;...;7~l;On invariant ~l uc~ ,s must be created during tr~n~1~tion 25 4 2.1 Pr~ces~.ng Staternent Probes In one emhot1;~f l~t, the parse node ~soci~ted with a ~ f ...~nl probe collc~,onds to the HDL sl;~ nt following the ~ f -~- Iu probe. One way to imp1emf nt this is to deter-mine the parse node ~SOC;~IfY1 with the text imm~i~tely following a sl~tf ....-~ probe using the text-to-node mapping previously descnbeA and mark that node. This is possible be-30 cause the parse array cc l -l~ all of the ch~cte s in the source text. The parse array em-beds the parse node bo 1n~ries into the text. The probe directives can be iflt ntifif~l by WO95127948 2~ 90$ PCTIUS95/04660 sC~nn;~lg the parse array after it has been built. They are then used to mark the a~lu~iate parse nodes.
Figure 12, Figure 16, Figure 17, and Figure 11 illustrate l~lvces~ g probe directives with an ~ p'e Figure 12 shows an HDL code f~nlo.nt Figure 16 shows the same HDL
5 code fi~P.nt conl~;ni~ a sl~h- ~ nl probe 401. Figure 17 shows the text of Figure 16 as a linear a~ray of ch~cters with parse node braces ills~. t~d. Figure 11 shows the parse tree.
After parsing is co..~ ,~, a cO~ t;ol-~l text sedlcl~lg lccLnique such as used in the "grep" cn.. ~ in UN~ can identify ch~h~ct~" 4450 as the first character of the st~t~m.ont probe. The text-to-node mapping will identify the parse node be~ n;np: at brace 4304 as 10 the first parse node following the sl~le ..~,~-l probe. This parse node is the node whose open-ing left brace is the first left brace to the right of the probe directive beg;n~ g at character 4450.
Note that text of the probe directive can not contain a parse node nor can it be divided by a parse node be,c~ce the probe directive is within a cc.. ~-nl in the underlying HDL
l~ng~ gç
Figure 18 and Figure 19 illustrate a Citu?tinn that, in one emhotlimlo.nt, should be treated as an error. If the text of a ~t~.."~f~l probe does not ;~ Ai~tely precede an HDL
s~ - "~l then there is no next ~le .. -t to selecL The HDL text in Figure 18 illustrates this sitll~tinn S~te..~ -l probe directive 4520 should be treated as an error. Figure 19 20 shows a brace l~ S~ I;Qn of the situation. This error occurs v~hel~eicl a right brace ")"
- is located after the probe ~li,~li~ _ text and before the next left brace " { ". Brace 4660 is such a brace.- One . .~. 11.~ of dealing with this 5;~ iS to stop l"vce s~;ng probe directives.
Another..- ~h ofh~n~llingthis ~;lu~ istoignoretheprobe.Inonec~ubo~ u~ames-sage can be sent to the ~eSigner by the HDL analysis system eles~rihing-the problem and 25 the action taken.
An ~lt~n~te c."bo~ l would use Sl~lf ..~l probes to select the HDL st~tem~ont ,c~l;i-g the text of the probe. This would require that the parse node ;~ f,A;~tely preced-ing the probe directive be m~rk~A This parse node can be found by finding the first right brace ")" to the left of the text of the probe directive. The C~"~ n~ling left brace "(" for 30 this right brace is then i~1~ -1;rPA and the parse node number is asccl~."ul from this left bracc as ~es~ihed pl~,viously. One disadvantage to using probe dircctives which select the W095127948 ~ 3 859~ PCT/U~5~ 60 pl~ceJ;ng text is that the probe ~ must follow all lines of a comrleY s~e .u .-4 72 r) Jce~-ng Block Probes Block probe directives are ~l~.fin~.A by a starting text string and an ending text string.
The starting and ending text strings are pl~xes~ in a very similar ~nn& tO SIAI~ nYnt S probes. The parse nodes to mark for block pr~bes are found as follows. Identify the parse node ;.. ~A;~te]y following the starting text string of the probe directive with the text-to-node m~rpinp ~es.~ d earlier, and call this parse node the starting parse node. Identify the parse node plo~ l;ng the ending text string with the text-to-node ll,ap~i"g described earlier, and call this parse node the ending parse node.
In a~1Aitinn id~ ify the parse node which cor,~ins the starting probe directive and the parse node which col~Ains the ending probe directive. As ~e~ibeA earlier, the contain-ing node is the parse node whose ~fining braces are the inl~( ....OSI pair of braces which fully enclose the probe directive. If the starting probe directive and the ending probe direc-tive are not conlAin~ by the sarne node, then a logical error has occurred.
C`~nci~l~ the HDL source text shown in Figure 20. The parse nodes for this source text using the brace not~tion are shown in Figure 21. As before, the parse node bollnA~ries are ~enote~1 with the brace characters "{" and "}". Probe directive 4750 iS the starting block probe di~ e. P~be directive 4760 iS the ending block probe directive.
Applying the text-to-parse-node m~rping fimCtio~ des~ibe~l earlier to starting block 20 probe directive 4750 ~luduces starting parse node begun by brace 4804. This is because brace 4804 iS the le~ right brace to the right of starting block probe directive 4750.
Sirnilarly, applying the text-to-parse-node rnapping r.~-.c~ to the ending block probe di-rective 4760 yields ending parse node begun by brace 4810. This iS because brace 4840 is the ngl~ln~ right brace to the left of ending block probe directive 4760, and brace 4810 25 the left brace coll~,;.~nAinP to brace 840.
The ;n.., ...osl conl~;niQ~ parse node for both starting block probe directive 4750 and ending block probe directive 4760 is the parse node defined by starting brace 4800. A parse node is the ;nn. - ...O~t c~n~i..ing parse node for a probe directive if its left brace is before the probe directive, and its right brace is the lef~nost right brace which comes after the 30 probe &~cti~e but has its ...d~ g left brace before the probe directive.
Note that brace 4845 is the l~fi~ St right brace to the right of starting block probe WO95/27948 2 1 8~9~ PCI/US95/04660 directive 4750 which has its ...A~ g left brace before starting block probe directive 4750.
Brace 4845 is also the lcrll..o~l right brace to the right of ending block probe directive 4760 which has its ...~l~l.;..g left brace before ending block probe directive 4760. Thus, this is a legal pair of block probe di~ s.
S Once it is Af t~ A~ which are the starting and ending parse nodes, those parse nodes and all parse nodes which fall ~I~.~n the starting and ending parse nodes are msrlr~A Dunng tr~ncl9tinn, the m~A parse nodes are plOCf c~A as ~lescrihe~A~ previously.
For example, in one emboA;~ , the outputs of the logic block ~efine~A by the block probe will be preserved by optimi7~tion invariant sllu~;lul~,s.
One troublesome ~ l;Ol- that might arise is that the text-to-parse-node mapping iA.ontifies Lrr~ t col~lA;nil~g parse nodes when applied to the starting block probe direc-tive and the ending block probe directive. This s;~u~;ol- arises if the begin and end block probe directives are not placed within dirr~ C blocks. Another trol~blesom~ sit-uation occurs if the starting block probe directive is not placed ;~ tely before a parse 15 node or the ending block probe directive is not placed ;~....~rAiAIely after a parse node. In one embod;...~ Jrùcess;ng stops once an e.luneous citnqtion is dJet~l~A In another em-bo1;...--n~, the ofr~nding probe directives are ignored. In one emboAim~nt, a message can be sent to the A~ignçr Aes~ihing the problem and the action taken.
4~.3 Proce~ng Mul~i-Probes A Multi-probe is a ~ .e-~l probe or a blockprobe with a search string which further ~;r~es which logic is to be probed. In one e-.~;...f~nt, a multi-probe uses the phrase "multi-probe" following the L"~wul~l. The parse nodes qcsociq-t~ with a multi-probe direc-tive are id~ nl;r~eA using the ~h,l~ C A~e-s(~ibe~A earlier if either a ~l~lf ..- -t probe or a block probe is used. These parse nodes will be lef~ d to as the initial parse node s~o,le~tiQn In one embo-Aim~-nt, the search stnng is used to mark some, or possibly all, parse nodes in the initial parse node selectiQn The marked parse nodes are then plocessed as be-- fore. There are difr~.. ,.lt types of parse nodes, such as qcci nm~nt, C~,~alOl, or variable. The parse node types are ~efineA by the particular HDL lqn~l~e. One use for the search string - is to select parse nodes of a particular type. For eYqmple~ the search string ~all qci~ e~
30 would result in mq~ing the qCc~ nt parse nodes in the initial parse node ~-l~-cti~ An-other search string is "all ~r5.te. "~ n~ sC~ue ~Ce~". This inAic~qtes that the parse nodes that cor-wo gsn7948 2 ~ 8 5 9 0 8 PCIIUS95/04660 ~ nd to the first and last ~l~lf ~ in each ~ f ..- ~1 sf~u~nce of the ~ri~in-q-l celectiQn are probed. Sl~t~ 1 se~lu~llces are ~lefinPA in the VHDL ~ qnFIla~e Reference Manual.
In anotll~, e~llbo~ -u, the search string is used to specify which nets connf~t~ to the mqrkf~ paTts are mqr~f~ Recall that mqrlc~ nets will be broken with opl;..-;,~ - in-5 variant Sllul;lul~S. For~ -; -.ple~, the search string "aU_mux_controls" inr1i~qte s that the nets controlling muxes should be mqrl~A in the initi. l sele~tinn This wiU cause all of the pcd mux controls to be linked to the HDL source after 0~1;..~;7~ n P~be directives can be used to selectively group blocks of logic so that the effects of such logic blocks can be observed. Thus, a~ her search string is "all case stql~ ..f l-t~". This 10 marks all parse nodes cu~ 1;ng to case y~lillf ~ A further search string is "all sub-routine calls" which marks the parse nodes coll~*,ol--ling to subroutine calls. By using probe directives, which can be fli~qbled using the priority feature, the rl~signfr can easily create le~l~ ~ levels of l~l~cll~ which can be used to analyze the l"appf d circuit struc-tures created by spe~ific portions of the HDL and then disabled once analysis is complete 15 Case ~I; If --f'l-tC and suLl~,u~inf caUs are two eYq-mples of co------ol- structures that the de-signer might wish to e- z- ~ C.
43 All~. ..ate Implementations of Optimization Invariant Structures Following are ~Irli ionq1 ~-e!~ s for creating opl;...;-,~l;on invariant GTech circuit ~ u~ s for probe directives. Any of these methorl~ can be used in step 4160 of Figure 7.
20 Figure 22 shows an eY~mrle of extracting both a ~ / input as well as a primary output.
43.1 Attaching Properties to Nets Another .~e!l~od of cl~ing an initial GTech circuit with ol,l;..-i7At;on invariant GTech circuit ~11 u~.lul~S COll~ rl;np to the probe directives involves modifying the iden-tifir~tion step in the optimi7~tion process. During the tr~n~l~tiQn ~lvcess, a net or a part cor-25 l~,;,~nding to a probe directive is "~ r~l ~' The identifi-~tion step in the optimi7~ion process is ch~nged to allow only "v~ e~l" nets or parts to be mo~lified during optimiza-tion. The m~rking iS impleu.r led by ~ d~3itionS~l infc~ tion to the net list pre-pared during the t~n~l~tinn process. ~lt~-rn~tively, a m~rk~A net can be divided into an input net and an output net as before, and a new part added that COl).llCCki the nets. This part 30 is given a pl~ that it may not be deleted during o~1;...;7~l;on Figure 23 and Figure 24 show two ~.;...,pl~ of a GTech circuit with o~ ;on invariant ~LIuC~ ,S. Net 391 is a WO 95/27948 .~ 1 ~3 5 '~ Q8 PCIIUS95/04660 3 net which cannot be mt~ifit~d during ~~ ;on Part 270 is a mqrktA part which cannot be ...t~;r.~ during o~ Al;on. The disadvantage to mqrking a net as not modifi-able is that if the net cannot chqrge, then the total ~.. her of input and output pins on the net must rem. in the same. This means that none of the parts which are ~ttq-~het1 to the net S c n be deleted or co...~.;t ed during o~ ;tm 432 Extracting Only a Pnmary Output Another methot~ of creating an initial GTech circuit with o~1;...;,Al;on invariant GTech circuit ~I.uclul~,s c~ ~ndil-g to the probe directives involves creating only a pri-mary output at a higher level in the hierarchy. A sample GTech circuit with a primary out-10 put extracted is shown in Figure 25. The method shown in Figure 8 created both a primaryinput and a ~ output. If only a pl ,~ output but no primary input is e~ctTqcte~l, the mqrkt~ net does not need to be divided into an input net and an output net. However, this technique might lead to ul-~lcli',P-ble results during o~ll;...;,~l;on Con~ r the GTech sub-circuit shown in Figure 26. Part 4201 colllpules function f, 15 and ~loduces an output on net 4220. Part 4202 COm~JUI~ S lunt,l;ot~ g. Net 4220 is marked and probed by Al l f ~ p only a pl~ output. In some cih.iu~ An~es~ the optimizer may crr~ ly ~loceed by ~l~l.,c;..g a ~d sub-circuit as shown in Figure 27. For example, such a lna~pcd sub-circuit might be ~ luc~l if the optimizer is ~ g to minimi7e the critical path. Here, part 4200 is a replica of part 4201, and co~ ules f, which drives net 20 4220 as before. Part 4201 and part 4202 have been co...l-il-ed by the optimi_er to produce part 4203, which CO~t~u~S h, a cc -..~ I;on of f and g. While this ~ypul sub-circuit will lucc the co~rect output, the timing il-fc,. ".~ n A~A~At~ with the created primary out-put might not be useful bec~ e it is not 3ssor ~t~ with a signal path in the f m~tio~ing part of the Illa~d sub-circuit. II~ el, adding only a ~ output is simpler than adding25 both â ylilllal ,~ input as well as a primary output, might enable the oy~ill~izel to yel r~ bet-ter than if a primary input~l~u y output pair were added, and might allow the designer - sufficient ~r,eAhility back to the ~rigin~l prohe directive in the source HDL.
4A E~amples 4.4.1 Mapped CircuitAnalysis with Probe Direc~ves Figure 11, Figure 12, Figure 25, Figure 29, Figure 16, Figure 22, Figure 30, Figure 31, Figure 32, Figure 33, Figure 34, Figure 35, Figure 36, Figure 37, and Figure 38 W0 95/27948 2 1 8 5 9 ~ B PCr~US95/04660 illnct~tç by ~ ~; nl lc how probe directives work and how the llla~el circuit analysis in-Ço....~,;Q.-isdisplayedtoauser.The~n.l,lesuseVHDLasthesourcel~n~l~ge Theprin-ciples ill..~ t~ do not depend on the particular l~n~)~ge~ For eY~mple, the system works with Verilog as well.
S Figure 11 shows a text editor window 300 c~ ;.. h.g an eY~mrle of a VHDL code fragment 400 that does not contain any probe directives. The code fr~gm~.nt shown in Figure 11 is lc,peot~ below:
lOOOif (C and B) then lOOlZ c= not(A or B);
1002else 1003Z c= no4B);
1004end if;
Figure 12 shows a ~rhir~ ,se~ l ;ol of the parse tree con~ll u~;led while trans-lating the source code in Figure 11. The "if" ~ e~ -l in VHDL has three parts: a condi-tion, a VHDL ~ t to process when the con~1ition is true; and a V~L ~l~t~ .-.. .-t to ~lucess when the con-litio~ is false. The conrlitinn is dealt with in the tree ~lescentling from node 1001. The true con~lition is h~ntlled by the tree ~escen~ing from node 1004. The false con~ition iS h~nrll~d by the tree ~escen~ F from node 1010. The ~si~ -t~ ,senledby nodes 1004 and 1010 are used tû link the signal values r~l.,senled by node 1005 and node 1011 to their fimrtinnc le~ in the trees ~escçn-ling from nodes 1006 and 1012 rely.
Without a probe directive, the VHDL fragment trAn~lRtes into the GTech circuit of Figure 25 using conven~ nAl s~ llei"s trAn~l~tion te~hni~ es ~es~ibeA earlier. Inputs A, B, and C are sc-~ l ;rally l~ s~ n~ by the conne~ 200, 201, and 202. The "if" state-ment ~ -clqtes into multiplexor 231. The con~litil~n "(C and B)" would tr-A-nsl~te into and gate 232. The "true" cont1ition trAn~lAtes into nor gate 233 while the "false" condition ~rans-25 lates into inverter 230.
Figure 29 shows a ~ ~d circuit ~!;...;~;d from the GTech circuit of Figure 25. In particular, the logic function that this code fr~A~nt really performs is not(B). At this point, willloul probes in the conve .l;nnAl synthesis design process, the decign.o,r can not obtain much i-~- ...~I;Ol~ about the intern~l timing il~ escen~l;n~ from the fragrn,o~t For 30 example, if the ~esi~r needed to knûw when the value of not(A or B) was cûl~uled to help analyze some other a~spect of the design, then the 1e~i~Pr wûuld not be able to deduce wo 95n7948 2 1 8 5 9 ~ B rcrlus9slo466o that info....~l;orl from the res-llting analysis of the circuit in Figure 28.
Figure 16 shows a probe directive 401 inserted into the source description. The code fragment is ~ t~ below:

1005if (C and B) then lO~Sync~psys p~be_statement 1007Z <= not(A or B);
1008else lOO9Z <= not(B);
lOlOend if;
In VHDL, "--" begins a co....... -f-nt The word "Syno~ys" ;~.. f~i~tely after the "--"
lir ,3t~S that this is not an or~i,laly CQ~ - ~ .~t, but rather a directive to the tr~n~l~tor or other part of the Cc?.~ ,- aided design tool envilo....~ The word "probe~ lf ...- n~" indi~tf s that the subse~.f~-nt VHDL ~l ~t~ - - -- .nt should be pl`~Cf ssful by the tr~n~l~tor so that it will be possible to relate subsf~ucl~ly ob~ned analysis il~O~ l ;on to this point in the HDL rep-resc nt~tion of the digital circuit.
Figure 22 shows a GTech circuit produced by a tr~n~lator from the code fragment shown in Figure 16 with the probe directive. The parse tree pl~luc~ with the probe direc-tive is the same as before, namely the tree of Figure 12. However, the probe directive will cause the signal l~,~lesented by node 1005 to behave as both a primary output and a primary input.
In one embcYlimf-nt the tPncl~tor adds tC~l~y input 203 and new l~.~c.l~ y out-put 221 while creating the GTech circuit of Figure 22 from the parse tree. In ~ddition to creating this GTech circuit, the t~n~l~to CO~ the new te,l.~l~y input to the new out-put at a higher level in the net list produced from tr~n~l~tin~ the whole specification. This effectively makes this int~rnAl node visible at a higher level in the design hierarchy.
Figure 30 shows the mapped circuit of Figure 22 after optimi7~tion. The optimizer is not ~e....;l~ed to ~i,l-ize GTech circuits past the bolm~lA-ies estAhli~he~l by the prohe di-rective. This means that nor gate 233 of Figure 22 would be t~sÇoll.led into nor gate 253 of the optimi_ed mapped circuit. The ~I; n;~AIion process begins with a GTech circuit that does not have timing or area il~fc.. A';on A~soriateA with the GTech co"ll)onents. After the optimi7~tion ~locess, the ~ ed Col~ o~ nL~ do have area and timing inr~l"a~on asso-ciated with them. Th~ rc,l~, nor gate 233 in Figure 22 is not "the same" as nor gate 253 in 2 1 859Q~
WO 95/27948 PCTrUS95/04660 Figure 30.
necal~ce the logic ~1h~ pl~)cess left t~,LU~l~y input 203 and ICLU~)Ch~,Y OUt-put 221 alone, and those points c~~ ,ond to a particular point in the HDL source, any an-alytic result related to t~LU~)U~O.l,~ input 203 or t~,LU~l~y output 221 can be ide~";r~pA with 5 the probe directive 401 in the HDL. Figure 31 shows the relation of timing UL~OI ~AI;Qn to the HDL source text through a special text w~ndc,-v 301. For e~..ple, ~uppose a critical path analysis tool r~ .P~ that it took l .O n ~ ~-03e~0~ to plu lucP tl~LUpul ~ ~ output 221 of Figure 30 after a clock edge arrived at a flip-flop SULU ~ , else in the L~cd circuit.
By using the fact that leLù~l~ output 221 came from this line of the source, the timing 10 result 500 can be lispl~l next to the ~l"ul,liat~ line of the output.
4.4 2 Example of Block Probe Direc~ve Figure 32, Figure 33, Figure 34, Figure 35, Figure 36, Figure 37, Figure 38, andFigure 39 show ano~ way to use probes to evaluate the p~lr~ Au~e of blocks of HDL
code. Figure 32 shows a text window with an HDL entity desrnbeA This text has no probe 15 directives inserted, and the code is l~;peAI~A below.
101 lendty interrupt_cont~olla is 1012 ~ request: in bit_vestor(3 downto 1);
1013 current_level: in bit_vecta~(l downto 0);
1014 should_service: out bit);
lOlSend;

1017architecture synthesizable of interrupt_controller is 1018signal new_level: bit_vect(l dowl~to 0);
lOl9begin 1020 desode: process(new_request) 1021 begin 1022 if(new_~ '3) = '1~ then 1023 new_level <= "11";
1024 elsif(new_ . 7 '~2) = '1~ then 1025 new_level <= "10";
1026 elsif(new_~equest(l) = '1~ then 1027 new_level <= "01";
1028 else 1029 new_level <= "00";
1030 end if;
1031 endprocess;

1033 compare: process(cmrent_level, new_level) 1034 begin 1036 if(new_levd(l) ~ current_level(l)) then 1037 should_service <= '1';

W095/27948 2 1 8590~ PCI/U~5~01C~0 1038 ~lcifi(n .._1evel(1) < cmrent_level(l)) then 1039 should_senrice c= '0';
1040 elcif(n .._level(0) > cmrent_level(0)) then 1041 should_service c= '1';
1042 else 1043 should_svice cz '0';
1044 end Lf;

1046 endprocess;
1047end;
The r~ ;on of tbis VHDL source code model is to COLU~UIe v~l,ethe, a new int~ u~t of a particular ~ lily should be ser~iced given priority over the ih~t~ upl being serviced.
A request for a ~cessor int~, lu~l arrives on inputs new_l~uei~l[3]~ new_request[2], or 10 new_l~uei,l[l]. The input current_level[l:0] in~1irAtes the priority level of the inl~lupt ~;LUl~ / being serviced. If tbe request for an int~.lupl comes in on a higher level input tban tbe current level of the int~lupt being serviced, tben tbe should_service output is set. Oth-erwise, it is set low.
Tbis source code COLUPUI~S the il~ lu~l senrice request in two steps. First, it deter-mines tbe level of tbe highest pen~ling inle,lupl request in tbe ~lvcess labeled decode. Sec-ond, it COLI~P~U~S that level witb tbe current iut~,.lu~l level.
Figure 33 shows tbe GTech circuit res~ll*ng from ~n~l~*ng tbe VHDL source.
Figure 34 shows tbe ...al~pcd circuit tbat results from op*mi7ing tbe GTech circuit in Figure 33.
Figure 35 shows a special text window tbat ~ ;,es some of tbe l,elfu. ~A~ e in-fv.~ ;o-- about tbe ~ ~ circuit. The analysis tool can provide inrc~lLlaLion about the design as viewed from tbe inputs. For example, one analysis tool would provide an e;,l; . . ,AIe of the area of the design by col~n*ng gates. Anotber analysis tool would co. . ~ lc the long-est delay through the entire design. The designer could COLU~ this infolLùaL,on with the ~e-sigr-~r's l~uu~ ,nls to ~et~ -e if this mapped circuit is too big or too slow. The op-*mi7~*on p~cess blurred the ~ *n~*on ~I..~n the decode func*on and the compare function. It is not feasible for a ~eSigner to ~let~ e the area or the delay associated with each r...e~;On To ~lc,t~ ;ne where the problems lie, the ~eCign~r would insert "block probes" tex-30 tually ne?r the ~ r~n;l;on of the ~e~ing and cc~ g ~vces~es, as shown in the textwindo~v of Flgure 36. This would probe all signals çntcring or leaving the sequence of ~)L

- 2 tl ~ 5 9 Q ~ ~DED SlffT
- .~2 PATENT
,~TTOIINE~ DOa~ NO; 3 t1~5.0001~

eli~ by the beym 'olock and ~Qd bloc~ b~ Whe~ tr~,~5~ , ~.tS prol~ed HDL becomes the GTo:h circuit of Fgurc 37. T~e tra~ or woul~ creatc l~p~,a.~l mpu~ 010 ~ "~ nu~s 2000 3~d 200L, muc~ a~ it did ~ t~ str~rm rt prc~e.
~he oyt; .¢e~ orms the Grech orc~t of Figurc 37 into ~e mappcd ar~uit of F4~re 38. T~i~
allo~ annly~ tools to c~mputc ~ aIld area ~ of both puts of the ~spped arcnit. A
spcc~l purpose display toal c~n thc~ ~play, fM eY~ple, ~ming a~ld area ana~i~, as s~ u ~e 39. In tl~i6 .~mple, the de~ '' g mapped circuit i~ ,~ately thc sam~ si7c a~t d~hy a~ tbe compara~or mapped C LTCs~t.
.0 L~nldng ~DL S-~urcc to Clr~ult ~al~i~ Tuub ~ c pse~i~us s~c~ons descn~c ~crw l~c HDL source c~ bo rol3ted to tll8i C~Tech ar m~pped circu~t.
Onc~ t}~c HDL ~ourcc to &Tec~ ~ mapped CiTC~it reT^~in~h~p ha~ bu~ ~ lt t ~ 1, GTe~ or d analysi~ ~0015 can ~se thi~ to e~able th~ d~er to al~alyzc the GTech or maypcd circuit ~o ~icw~g thc SO l~0 MDL This section des~s ~ow ~ ~1, s~urce le~l allalyas syttem ia Wt Ufi~g a ~anety o~ GTec~
~d mappcd Q~1,Ut anaiysis tools w~i~ arc linkcd ~clc to the E~L ~ourc~, Many types of GTech ~d mapped circ~it aD~is so~twar~ tools ~ le~rer3ge ~L source leYcl analy~
There~r~, ~c system i~ des~ed to sul~porL a~y ~ulnber of GTed~ a~t mapyed ci~cuit ~al~ tools. ~c 5y5t~m inciud~ a central d~ta ~ ~ar- Thi~ data n~r-~r r~eives ar~aly~i~ q~u frorll user Ic~
tool~ w~ alysistodcal~rctpalldtothcq~e~y,~dw~- '- ~ the.~ tothc~.o~
ll5er ~1 ti~play ~ool(s). Note also tha~ t~e ~t~ he GTech or ~apped ~c~ o te~ li~ to di~ply dlc por~ o~ tl e ~L t~ c~c~ to the p~st of tl~ GTech or r~appcd c ircult w~ relcva~t to tl~
cut~ cllt ~ery. D~B sour~ leYcl analysis, the ~L so~cc t~, ~ . - ' - - of thc parsc tree, the ~Tech citc~t, ~d d~c ruaype~l ~rcuit are ~11 r~ u~ ~ rcudcDt ~ the ~ ~ '~'8 r~e~ory.
Onc cm~o~ of an HDL so~c~ leYel ~tal circuit ~nalysis system ~ d~cribe~ ~ lhe H~L A~i~or U~t r Guide, 'V~n 3~a, ~hich i6 aYaila~le fhm Sy~ ~ ' View, CA.
Thc ~L ~d~sor has ~ ce~al data ~oae~,r. T~e ce~ral data ma~a~r sl pports two t~a of tools;
dis]-1lay tool6 ~d a~l~5is to~ y too1 c~ tiapla~ iD, 3 cer-LMA~PJ .~50 W095/27948 ~1 8~90~ PCI`/US95/04660 tain fv~mat. Fvr eY-s-~nple, the HDL Advisor inC~ es a stacked bar graph display tool, a his-togram display tool, and a text display tool, among others. Each analysis tool can answer queries about a certain ~lv~~ of a digital circuit. Fvr e~ e, the HDL Advisor incllldes - a timing verifier which can pc r -- - timing analysis on a ~ed circuit. The central data S rnsns~g~ counl;~ ~r~ s co~ ni~ ~t~. ecn the display tools and the analysis tools.
The HDL Advisor l~ s the current se~ nn The user makes a selection by using an input device such as a ~l~d or mouse to ;...1;~,~ one or more display objects on the screen. Display objects are displayed in display tools and may have many ~lirr.,l~nt hi- Al l~ sc nl~l ;on~- Fvr eYs-mrle, a bar in a histogram, a fragment of text, or a draw-10 ing of a GTech gate are all display objects. Display objects are drawn by display tvols to,sent circuit objects. Each display tool ,,.~ tg;i.~ the correlation ~~ w~ each display object that it draws and the underlying circuit object. Circuit objects include any l~,~l.,sell-tation of a digital circuit sllu;tu-~, in any ~1~msin For eY-s-mrl~, a ~l`OCe,SS stgt~nlpnt~ a GTech gate, and a ~ap~d pin are all circuit objects which can be sele~ted via a corre-15 spon~ling display object.
Display objects ~ n,sent circuit objects in a speçific domq-in Thus, display objects can be used to select a circuit object in mllltirle ~Qmqins For ~ r lct ports can be selectP~
in the source ~lomqin by sele~tin~ the line of HDL text which defines the port, in the GTech flnmqin by sele~ g the syrnbol for the GTech port, or in the ",apped ~omqin by choosing 20 the symbol for the ~a~yed port. Chosen display objects are called the visual sel~ctiQn. The und~"lyillg circuit objects they represent ~re called the circuit sel~ction The HDL Advisor in~ C~ a s~lectinn m~na~cr which cu~""";~es the circuit s~ ;ol- to multirle display tools in mllltiple ~o- - ~ . The se lPction m~nag~ will be ~les~bed further in a later sec-tion.
25 5.1 SystemA~I ;t~h~ Oven~iew This section provides an overview of the circuit analysis system a~.h;l~,el...c using - two r~ s 5.1.1 Rela~ngAnalysis Results to Source Figure 58 shows the rel~tion~hip ~ . ~n the text des.,l;p~ion of a digital system, the 30 parse tree denved f~om that text des.~ ion, the circuit srthf s 7ed from the parse tree, and a visual display of a circuit analysis result. The text dcs.,li~lion 6003 compri~es a sequence WO 95/27948 PCI/US9S/01C~0 2l54a59~

of characters 6003. The parse tree 6004 conlr~ices parse nodes 6010, 6011, 6012, 6013, and 6014, and is consllu._t ,d by parsing the text ~f',~ ;on 6003. The parse tree is stored. A
relstions~ir ~t-. ~n the text and the parse nodes is ..~ ~l as in-lir~te~ by rel~ti~-nchir 6018.
S The digital circuit 5900 shown in Figure 59 is s~ l.f ~;7~A from the parse tree 6004.
The digital circuit 5900 concict-C of circuit cl~ e~ Digital circuit 5900 inrl~ es input pv~s 6030, 6031, 6032, 6033, 6034, and 6035, and output pvrts 6036 and 6037. The digital circuit also inrl~tles cells 6040, 6041, 6042, 6043, 6044, and 6045. The cells include input pins 6050, 6051, 6052, 6053, 6054, 6055, 6056, 6057, 6058, 6059, 6060, 6061, and 6062.
The cells include output pins 6070, 6071, 6072, 6073, 6074, and 6075. The digital circuit also in~ .s nets 6080, 6081, 6082, 6083, 6084, 6085, 6086, 6087, 6088, 6089, 6090, and 6091.
An aspect of the present invention . -~it.li-;--c the rel~tionchip 6019 ~l~.~,en the parse nodes and the circuit çl .~h nl~ In this eY~mple, parse node 6011 is related to ~vu~hlg 6020. Parse node 6013 is related to grvuping 6021. Parse node 6014 is related to grouping 6022. Parse node 6012 is related to ~vupihlg 6023, andparse node 6010 is related to digital circuit 5900.
Analysis tools can be used to AC~ ~ , n-----~ 1 circuit analysis results with the cir-cuit ele .u -l~ Fvr example, if the circuit is in the G-Tech ~lom~in, then each net could have 20 the r.umber of logic levels from input port to that net. If each cell in this eY ~"l le was one gate, then net 6090 is 1 logic level frvm an input, while net 6091 is 3 logic levels from an input pv~ The gate count is anv~ A .ple of aTech analysis. Suppose each cell has one gate. Grvupings 6020, 6021, and 6022 each have two gates. Grouping 6023 has 4 gates.
Similar results can be ob~ined in the mapped circuit ~om~in The analysis tool could gen-25 erate the results for all of the relevant circuit el~mPntc upon inquiry or the results could be stored with the circuit c~c .~n~ or cached in the system.
Analysis results are displayed in a window 6095 on a COIll~ut~,l screen 5420. The size vr display characteristics of a display object 6097 can be set by the n-lmf~ic~l circuit anal-ysis results. The ~l~siEn~ can choose a display object in window 6095 that is linked tO a 30 parse node. For C~ ~lr, the text ~es(~ ;on could be in VHDL. The window 6095 could have a list of VHDL p ocesses near or cQin~lent with visual display object 6097. Using a W O 95/27948 PCTrU5~SI01660 ~ 1 859~
s5 mouse or ~rboz~i, the ~eSi~r selects a visual object c~ s~n~ -g to part of the text or a parse node. The ~lesigrl~ also selects a type of analysis desired. The system then id~ntifies the cc,ll~ .g circuit group from the sclc~t~l parse node using relationship 6019. For upl~ose the .3~cign~ selects parse node 6012 and wants to know the gate count.
S The gate count will be ob~ined for col~ l.or.~ g circuit ~UU~illg 6023.
The system then ag~gales the results ~ .ecl to the circuit ele ~ to ~loduce a agE;l~ t~l result acso~te~ with the circuit E;luu~,~g. For a gate count, ~e ag~,~,aLion c.~ l.. ;ces adding up the gates in the circuit ~oup~g. For circuit group 6023, this is 4. For delay, the ag~eEa~iol function would be the -- ~ . - value on a net or pin within the cir-10 cuit ESlUU~lllg.
The ag~at~l result could then be used to set the display ch~u ~-t~ ;stiCs of a display object For;~ nce the height of a re~t~nglP- cc,~ on-l; ng to parse node 6012 in a st~r~d bar graph could be set to the l-lJ---h~ ~ of gates in circuit ~UU~ lg 6023 divided by the num-ber of gates in the whole design. This would permit a ~esign~r to ~e~ ....n.c what fraction 15 of the gates in a design were ~ttnhvt~ to a parse node, and hence to the source HDL text.
Visually relating the design ch~'`t~ ;CtiCs to the source text l~ on~ e for those charac-t~i~tiCS quickly and ~,rricicnlly l~pl~senls dr~m ~ic~lly improves ~lesi~ pludu~ ity.
5.1.2 Inter-Domain Se~e-h~.. O~erview Figure 60 ill..~l.;.t~,s the ~hu;lul~ of an inter-domain selerti~n In this eY~mrle text 20 6103 is parsed to ob~ed the parse tree cC~mrri~ing nodes 6110, 6111, 6112, 6113, 6114, and 6115. The digital circuit is ~ hPs;,-~ in M~c~ n~-c with the parse tree. The digital circuit in this example has pOItS 6130, 6131, 6132, 6133, and 6134. It has cells 6140, 6141, 6142, and 6143. It has input pins 6150, 6151, 6152, 6153, 6154, 6155, 6156, 6157 and 6158. It has output pins 6170, 6171, 6172, 6173, 6174 and 6175. It has nets 6180, 6181, 25 6182, 6183, 6184, 6185, 6186, and 6187. In particular, text string 6102 coll~sponds with parse node 6112 which cUll~ s~nds with a circuit elc ..~ n~ using rel~tinnchip 6196. In this case, the c~l~,spûnding circuit elc " "~ is cell 6140.
Inter-~om~in s~lectiQn involves choo~;..g a display object linked to a circuit object in one r3Qm~in, and ch~n~in~ the display cl~ " ~t~, ;cti~ of another display object that is linked 30 to a circuit object in another domain where the two circuit objects are related by the parse node-circuit rel~tion~hi~. In this P~ 1e, display object 6104 is in window 6100. It is W095/27948 2 1 85908 PCTrUS95/04660 linked to cell 6104. This type of linking would be found with the path l~r~ tool. Using the inter~ mAin ~lection techniques ~esc~ 1 later, the desi~er could select display o~
ject 6104, and change the display ch-q-~ct~ictics of text string 6102 displayed in window 6101 using ~l~l;O~ ) 6196. This type of linking ~ ;r~es the ~eci~nçr's job of finding 5 the source code co~ ling to problematic paths in a digital circuit.
5.2 System Architecture DetaiLs Figure 40 shows the co..~ e~ of the HDL Advisor. The Designer 520 uses con-ventional input tools such as a 1~ 5410 or a mouse 5411 to ih~ with display tools which appear on a c~uler screen 5420. There can be any ~ --bc~ of display tools in the 10 HDL Advisor. For the sake of clarity, a st-q~l bar graph display 5430 and an HDL display 5440 are shown ~pe~r.~Ally. The st-q.~l bar graph display 5430 and the ~)L display 5440 will be ~es~ihe~ in further detail in a later se~tion This section ~escribes how these display tools int~acl with the other CC,...1~ of the system. ~ A1 display tools behave in a similar ~al~n~l.
The histogram display 5430 and the HDL display 5440 each send queries to and re-ceive responses from the central data mqnA~gçt 125. The data mAnpg~ 125 uses analysis tools to assist in pl~)cc~;ng queries. Any r~ of analysis tools may be registered with the data manager 125. For the sake of clarity, two sample analysis tools are shown, a logic levels analysis tool 5470, and a timing verifier 5480. A methal for ~lucGC~;ng queries is 20 shown in Figure 42.
Display tools also co.. ~ni~ , with the sf~ mqnA~g~r 5460 l~a-ding which circuit object or circuit objects the user selects. This process is shown in Pigure 41. The data mqnager 125 in~ d~s a dom-qiTI ~p~l 5450. The domain ~ per takes as input a cir-cuit object in a source ~lomqin, the initial domqin, and a target domain and finds the corre-25 sponding circuit object in the target domqin This process is shown in Figure 4 and Figure 5.
5 ~.1 A~ehitect~ ~e of the Data Ma~tager The HDL Advisor enables diverse display and analysis tools to co.. -;~,qte with one alloth~l. A data mqnqg~r central to the system. It pc,lr~l~s several filnctionc Most im-30 pOl l~ y~ dle data mqn~g~r allows display tools to pose a query in a particular ~omqin and receive an answer in the same domain even though the answer is com~uL~ in a dif~_r~nt 21 ~9~
WO 95/27948 ` PCI/US95tO4660 ~omqin Thus, the role of the data mqnager is to r..n. I;on as both a ~om-q-in l,laplJ~, and as a mP~s~age cGoidil~ator ~l.. ~n the display and analysis tools. ~ - 'rlition the data mqnqgsr can break complex queries into series of simpler queries. It asc~l ~ins which analysis tool can answer a given query. To enh~-r,e p~,r.,....~nce the data mqnagPr co..~ a cache of S l~enlly posed queries and the an~- _.s. This section ~les~ibes how the data mqnqger is built, and how display and analysis tools are connecte~ to it.
The data mqnagPr uses global ids to identify objects. In one e ~ t, a global id is a llulll~r. A glob. l id can be passed with a ~lomqin to the data mqnagçr. The data man-ager will a~ t to return an object in the passed tlnmqin which c~ onds to the global 10 id. In one c~bo~ nt, the data mqn-agP,r uses the global id as an index into a table to look up a circuit object in a flnmqin The data mqn~çr uses the domqin Illa~h~g cqp~bility de-scribed e. rlier to map the circuit object to the desired ~lnmqin Figure 42 shows how the data mqnagPr pl~)cesses a query 4910. A query con-qin~ an in~1ir,q,t~r as to what type of query this is (e.g. area, power), a list of circuit objects being 15 queried, a flag intlirqting if the result of the query is to be cq~chPA and a fimr,tion for aggre-gatingtheresultsofpl.ces~;ngthisqueryforeachcircuitobject.Ag~,gatingisthel,locess of cc,. ..b;n;ng m~lltirlP- results into a single result An ag~ e fullc~.oll is a function which is used to co...bil-e the results of ~ ~lJ~ ;es Su~u~.;es are t~ seA with step 4940. The a~ ;ale func~.on is ~1Fte .nin~ by the query and can be stored in a table with the query.
20 For i~ e, a area queries are ag~,~;at~ d by s~ -g the area results produced by sub-queries. ~ 4ngest dday queries are aggregated by finding the ~ . . . result lelwl,cd fromthe set of qu~PfiPs~
In one emho~im~nt~ the type of query is provided to the display tool by the data man-ager when the display tool is l~E,ist~"~,d. ReE,i~ ion of display tools will be ~liccllcseA fur-25 ther in a later section The query is created by a display tool interface in response to anaction from the desig~P~ 520. The query a~Tives as a mps~e from a display tool, and will be alls~ ~ l.,d by one of the registered analysis tools. Note that the query may allive in one ~om~in, be l,loces~e~ in ~nother, and the re~pon~e sent in the Of igin~ om~in The domain in which the quefy is issued is l~ r~ d to as the initial ~lom~in The domain in which the 30 query can be pl. ces~eA is l~r.,ll~l to as the target ~omain Neither the display nor the anal-ysis tool need know about the ~c-m~in tran~î.. -1;~ 1-wogsn7948 ;~ 1 8 5 q ;Q 8 PCI/US95/04660 Step 4920 ~lf te ~ eS the initial and target Aon.~in.~ for the query. The initil ~omqin is the ~nmqin in which the objects passed in the query are ~ 3e.~A The target ~omqin iS d~ -t~- .--;nc~ by the type of the query. The target ~c mqin for each query is stored in a table which is ;nd~,~ by the type of the query. For ;f~ Ce" a timing query can be alls~ ,d 5 using inf ,~ I;nn conl~;nf~ in the gate ~omqin A logic level query, which can be used to analyze paths in a trqnClqtf~ circuit, can be arls~.f r~,d using i, Ço. .-.~ n co..l~;neA in the GTech ~nmsin Step 4920 also sets the ag~at~ func.*on for the query.
Step 4930 maps the circuit objects in the query frûm the ini*al to the target ~omqin This ~ pi.-g is done by mapping through co..ce~ e flo...~inc as described previously 10 and shown in Figure 4 and Figure 5.
Step 4940 subdivides the query in the target rlomqin This is ~-fces,-.y if the circuit objects in the query are composod of ml)l*rl~ circuit objects. Note that the circuit objects in the queIy are subdivided varies with the type of the query. For eY~mple, suppose the que-ry is finding the area of an HDL ~l~Cf s~" circuit object. Since a l,lucess is made up of 15 many logic co- "l~nrnlc, the query must find the area of each of these coLu~)one~nls and add them ~ogether. This subdivision is ;~,q~lf ...f ~ 1 by k~epin~ a table of luuL~es that is in-dexed by the type of query. Each routine in the table takes a circuit object in the target do-main for this type of query and returns a list of circuit objects in the same domain which have been subdivided if nc~esc~
Loop 4950 loops over each subdivided query. AIrow 4955 is the return branch of the loop.
Step 4960 checks to see if the result of the given subdivided query on the given circuit object is in a cache of query results.
If the result is in the cache, branch 4963 causes step 4970 to be pluces~e~ and the re-25 sult is lellic~fA from the results cache.
If the result is not in the cache, branch 4966 causes step 4975 to be processe~l and an analysis tool is s~lecte~l for this subdivided query. The query is sent to the analysis tool and a result is ~ . ..ed Step 4990 caches the query and its result if the cache flag was set in the origin~l que-30 ry. Noto that the only ~ose of clching results is to improve y~ rO. .~nce~ In another em-bo 1;...~ , results may be cached, and the cache cl-~LeA at dirr~ nl points in the pr~cess.

WO 95127948 ` 2 1 8 ~ 9 PCr/US95104660 For ;~.cl~ ce, results might be cached after the results are ag~5at~1 in step 4980.
Step 4980 ag~.,gates the results of all of the subdivided ~ueries~ Ag~ga~.ng the re-sults of the subqueries cc ..~ es them to pr~luce a single result which will be ~ ..eA for the ~ri~nsl qucry. The results are a~,gal~d using the ~qg~t', filnctinn in the query.
S Step 4985 maps the ag~gated result ~om the target ~nm~in to the initial ~lQm-qin This ~ ph~g is done by marping through c~ ul;~e ~ inc as ~lesç~ibed previously and shown in Figure 5.
Result 4995 is a -~s~ge which is sent from the data mqn-q-ger to the display tool which ~riginqlly l~quejt~l the result.
10 5 ~.2 A~ch~iterture of the .C~e~ec~ ~n Manager The selection mqnag~r uses intra-~omqi-~ m-q~rFing to track circuit s~ tin~ in multi-ple ~lomqin~ When an display object is s~leclc~l by the user, a m~ssq-~ is sent to the selec-tion manager in~lic-qting the cc,ll~ ondu~g sP1e~t~ circuit object. The selPcti~n manager then bro~dc-qctc h~fo---~l;on l~ig~dillg the current circuit 5~ !;ol- to all of the display 15 tools. Each display tool uses the circuit selection inf ~ I;on to select the correct display object within its display. The selGcl;~n mqnqgP,r can co.. ,~iC~Ie the circuit selPcti~n in any ~lQm-q-in by using the intra~mq-in _apping capvqbility. By cc,.. ~;~ qting ihfo.. ~I;Qn about the circuit sele~iQn~ the ~PlPctirn mqnqgP,r allows the user to easily find an circuit object of interest using one type of display tool, and then further eYq~minP~ that circuit object 20 using another display tool.
Figure 41 shows how the s~ n mqnagPr hqm1lPs the circuit se-lectiQn First, the ~P~cigJlpvr 520 uses an input device 5510 such as a l~l~d or mouse to make a visual se-lection within a display tool 5520. Next, the display tool 5520 notifiP~s the selPction man-ager 5460 of the circuit selectiQn The selection m-q-n-q~gPr 5460 brovdcastc the circuit 25 selecti~n to each of the available display tools 5560. Note that the display tool 5520 which tf.d the circuit selectiQn is also included in the b~,adcast mesc~ge. The selectiQn is ct using a list of one or more global ids. Each display tool may optionally ask the data m~n~ger 125 to map the global ids to circuit objects in a particular ~lom~in In Figure 41, display tool 5560 sends a query to data m~n~r 125 ~ucs~ng the GTech value 30 of the l;,lo~ lr~l global ids. The data m~nager then returns the requested GTech objects to display tool 5560.

W O 95/27948 2 1 8 5 9 ~ 8 PCTnUS95/04660 The ability to track the circuit selec!;on ~l-.~n mllltiple display tools is used throughollt the HDL Advisor. The uses of circuit selP~tion tracking can be grouped into three ~n calc~ ;es: idell~irjing a circuit s~ in a non-text display tool and viewing a visual s.~l~cl;on of that circuit s~ n in the HDL source, id~ltirying an HDL source S Col sllucl and viewing a visual s~PhPctiQn of that circuit s~Pl~PctiQn in a non-text display tool, and the "follow scl~" in HDL source feature.
Concitler the display tools of Figure 40. Suppose that the ~e~ ~-er520 selects a visual ,S~ of a particular GTech pl~ output which is shown within the st ~P~d bar graph display 5430. A mPthod for mql~ing a visual sel~ n within the stqrlnP~1 bar graph 10 display will be ~lescnhe~ further in a later sectinn The sP-r~-P,d bar graph display then com-es the CC,ll~ ;.pOI ding circuit selectinn in the GTech ~c)mqin to the selection manag-er 5460. The s~le~l;. n mqn-qger then uses the ~mqin mqn~cr 5450 to _ap the circuit selec~ion to ~ullpol~d do~ inc The rel-q-ti~nc~-;ps and pl~CeSS of I~ g between do-_ainS was shown in Figure 4, Figure 5, and Figure 6. Thus, the selection mqnqgP,r deter-15 _ines the source do_ain parse node which l~ senls the se~pct~pA l,l~y output. The selection m~nagPr then bro~rqctc the id of the parse node and the HDL display 5440 re-ceives the parse node id of the circuit scl~ l ;n.~ Sel~cting a display object, and thus the cor-responding circuit object, in the HDL display 5440 and viewing it in the GTech display is ?~-con-l-lich~ in the same ~ r A feature of all display tools in the HDL Advisor is called "follow selGcteA " The fol-low s~ t~ feature causes a display such as the HDL text display 5440 to track the GTech or ~)td circuit ~lluc~e being analyzed by the 3e.ci~ ~r 520 in another display such as the ~!t~`-L'~ bar graph display 5430. For ~ le, this feature enq 'es the HDL text display 5440 to always show the current HDL source. Thus, the ~esi~çr can eYqmine a GTech or 25 ~ap~d circuit structure, and cim~ n~o..cly view the HDL source from which the GTech or lllalJ~ d circuit sllu~lul~ was created. This feature assists HDL source level digital cir-cuit analysis by ~ ;r~llylinking con~e~l;on~l analysis to the HDL source. Each time the s~1e~ 1 ;o n m~na~rbq~ r~ctc the sçle~tion, the HDL text display 1~4uesLs the &~l(*)li-ate circuit object in the source domain and visually selects the cc,ll~ onding display ob-30 ject. The HDL text display S440 will scroll the text display to make the s~-lr~teA text appear in the HDL text display window.

wo 9s/27948 2 1 :8 5 9 D~8 Pcr~us95/04660 A special case of for the s~ c~tinn m~n~g~,r and for the display tools is if no spe~ifi~
circuit object is sclP~te~l In this case, the s~lecti~ n ...Anag" and display tools assu_e that the ~eci~ desires ;n~. ---~I;nl- about the entire design being analyzed by the HDL Advi-sor. Thus, the first s~lP~ which the selectiQn m~nager bro~dc~ctc when a design is load-5 ed into the CO~ t~ lwly used by the HDL Advisor is the entire design.
523Archi~echlre of D~splay Tools Within a co...~ h- syste~ the i~o. ~ t;~n ~cirying the design is l~ se~leA in bi-nary form. For the human flecign~,r 520 to d~,lop and analyæ the design, il~.... l;on about that design must be ~l.,~nt~ in a form that can be ulld~ ood by the hllm~n, such0 as by a visual display on a ~ o~ itinn, the ~le-ign~r 520 must also have a way to te the design info...-~in~ such as by l~yl)oald and mouse. Display tools such as5430 and 5440 provide a .n~ for that int~r^tir~n IIo~ el, digital circuit design info- ~ on is con~rlic~teA~, and effi~ently allowing the ~lesign~r 520 to control and analyze the design l~U~,S that the display tools allow the 5 ~eSigllÇr to take advantage of the ~hu~;lulG of the design data.
One way to take advantage of the ~lluc~ , is to design particular display tools to CQ~ e with a particular ~ mqin in the data mqna~r. However, rnany display tools ;nte."cl with mlllti. '~ dv~ c For ~-A..q~lc, a stacked bar graph, which will be ~1es~ibe~l in a later section~ can cc,.. ~ ih~o-.. -~;on lGg~`~illg both area, which conc.,l"s the 20 gate ~omqin and gate count, which cQ~c~ -C the GTech ~lomq-in Regardless of whether a display tool is tuned to display ;-- r~ ;on from a particular ~omqin, each display tool uses the data mqna~er to gather the i~-rr ....~ n which it di~la~
Regardless of which do-..~ c are hqndled, each display tool interacts with the data ll,anag~r by u~ ni~-l;ng m~C~qges back and forth. These m~s~qges involve s~e~ifyillg 25 a circuit object in a ~lomqin and some related query to ~P rv.... on that circuit object. A dis-play tool is able to display a display object which ~ s~ a circuit object and store a list available of queries that can be ar~s~ d for that circuit object, although the display tool does not answer those queries. The data mqn-ager, in con~ l, is able to provide the display tool with circuit objects and process queries q~ qted with objects. In one em~im~nt~
30 at start-up time the data m-q-nq~r also provides each display tool with a list of queries which can be a~ lcd. This allows new analysis tools to be added to the system more easily. In-wogs/27948 2~1 8`59~B Pcr/us~s,~ o rc~ ;On about available analysis is stored centrally in the data mqnqg~r, rather than du-Flir~qt~,d in each display tool.
Display tools cC~ nir~e with the data ~ g~ - through display tool i-.~. .ri~çes The pUI~JOSe of adisplay tool in~ - ri`~`,e iS toprovide alayerofdataabstraction to the display 5 tool. This allows the display tool to be as generic as possible~ For t ~ C, a stacked bar graph, which will be .l;C~sse~ in a later section, can analyze dilr.,l~nt digital circuit prop-erties, h-clu(l;ng~ for ~- ~ .l-lc, area and power usage. A display tool interfq-re frames que-ries con~ ng the spe~ific type of data which the tool is displaying. Thus, the tool only needs to be able to frame general queries and the display tool in~. ri-ce will translate each 10 query into one which the data mqr~qger can undc.,~d.
The display tool is Ul~a-. alC of how its queries are an~ ~d. The fact that many anal-ysis tools are available to cc...-l~ule al,s~ , perh~rs in a dirr~,~nl ~omqin from the domain in which the query was issued, is hidden from the display tool interface. This enables dis-play tools to ~Up~l I display in a di~"cnt domain from that which the data ~ri ~inqtes~ This 15 ability is i~ nnt b~ ce much circuit ;- rc~ ;on is available in the GTech or mapped logic ~c~ ;nc but display objects are often desired in the source domqin At system start-up, each display tool registers itself with the data mq-n~g~r when the system is initiqli7~d At this time, the data mqnag~r inrc.l.-c the display tool of all of the queries to which it can l~,qn~
Display tool in~ ri ~es send ~ -ss~ges to the data mqnqg~r leques~illg inf~.. ,.. ~l;on about digital circuit structures in a given ~lomq-in, and receive l.,i,~onses. The data manager respon-lc to a query in the same ~omsin~ regardless of which ~lomqin an analysis tool used to cc~ ulc the answer. For ~ rlF. ~u~llo~ that a source text display tool wants to know the arrival time for a particular parse node. The source text display tool sends a message to 25 the data manager with the parse node and the request for an arrival time. If the information is available, the data m~n~ger l~ ondc with the same parse node and the actual arrival time.
As les~ihed earlier, display tools also cQ~ ni~Lqte with a sel~c1 ;ol- manager to in-fonn the sele~tiQn mqnagcr when a circuit object is selerted when the user interacts with 30 that display tool.

21 8~8 WO 95127948 ~ /US95/04660 5 ~.4A~ ecture of Analysis Tools Analysis tools are used to ~l-)CeSS i,lr~ I;nn CCU-~ within a ~c-mqin In generalterms, there are two kinds of analysis that one might want to ~lrwlll in a given clom-q-in Co"~rcr-.l;c!n~l kind of analysis tools take one or more circuit objects in a ~1Omqin and com-S putes ch~ - ;ctics q~Coci-q-te~l with those circuit objects. Por e - A'~k, in the gate ~omqin, a timing analyzer is used to cc...~l-v~, the delay times and slacks to various parts of the Illap~d circuit. The timing an. lyzer ~e~ es the time that the data signal on an output pin will bc~-~-e valid after a clock edge. In the GTech ~smqin a logic levels analysis tool c~ t~,s the longest path of c~ d 2 input gates through the GTech circuit. In the gate 10 ~omqin~ an area analysis tool cc....l~l~hs the area l~u~l to build the mapped circuit. In the GTech ~smqin a cc -.~ ,r t count analysis tool co~utes the ~ " of 2-input gates that would be used if the GTech circuit were ;...~le....,..t~A with 2 input gates only.
Another kind of analysis involves ~ ;.-g the chq~ctçri~tir s associated with a par~cular group of circuit objects. Por eY-q-mple, esl;...~ the total area in a mapped cir-15 cuit at the gate level involves ~ ;. g the area q-~so~-q-t~A with each CQ.~.l o~ and con-n~ction For an analysis tool to ~ f- çh'~ t~ ;Ctics of circuit objects, the analysis tool l~Uil~,S inrJ~ 1;9n about the :~llUClUI~ of the circuit objects and the connections ~~ ell them. Th~ rol." analysis tools are -q-ssoc ~qt~d with a particular ~c)mqin For example, a tim-20 ing verifier 5480 deals with the ~d ~omqin while a logic levels analysis tool 5470deals with the GTech ~nm~in In general terms, analysis tools CC~ ;r ~ with the data m-q-nager 125 by messag-es. The data mqnqger provides the analysis tool with one or more circuit objects, and the . nalysis tool returns one or more clla~ tirs of those circuit objects or a ~ of 25 the chalacl.,listics of those circuit objects, or both.
Analysis tools pclr~,llll three kinds of int~rqctinn~ with the data mqnager. First, each analysis tool regi~te~ itself with the data m~n~g~ when the system is initiqli7ed Registra-tion consists of infolu~i~g the data mqnqger what kinds of queries and in which domain a tool can answer. For eYqmple the timing verifier can answer timing queries in the gate do-30 rnain. Later, the analysis tool can receive and answer queries.
The data mqnq~r is l~s~ 'e for asc~ inE, which analysis tool can respond to WO95n7948 21 ~ 9~?B PCI`/US95/04660 a given query. In -1rlitir n, the data mqnsger is l~;,~n~ible for posing queries in the correct ~msin for the analysis tool. The data mqn-s~ger uses the lel~l;nncl~;ps ~I~.~n ~lo~n~inc to tr.sn~lste queries to the correct ~r msin for the analysis tool. For e~c-s-mple, co,.~ , a query cn~C~ --;ng the arrival time of a signal on an output port ~ ;r.~d in the ~)L source. In S one ,...bo~ 1, a timing verifier is l~E~ist~d with the data msns,g~r. The data manager will aS~;G.lail that the timing ~ r can provide arrival ti_es, and will ~1- ~-...;--e which port in the gate ~omqin c~ Ac to the port s~; r~ in the ~L source. The data man-ager will then send a m.ocsage to the timing verifier asking for the arrival time on that port.
The timing verifier ~ tr ...;I-es the arrival nme, and then sends a return moss~ge inrli~ting lO the arrival time of the port in the gate ~nm~in The analysis tool is not aware of the source of the query, or of the fact that ~omqin _apping may occur. It simply answers the query in the ~om~in which it undc~ ds.
5.2.5Analysis in the GTech Domain An aspect of the present invention allows for m~ningftl1 digital circuit analysis in the 15 GTech ~nm~in Re~ ce the GTech circuit is a direct tr~ncl?tinn of the HDL source, the quality of the HDL source is .lh~ related to the quality of the GTech circuit. By deter-mining which parts of the GTech circuit are problematic, and improving the source respon-sible for those parts of the GTech circuit, the start point for o~ ;7~l;on will be improved.
As it is .liffic.llt to predict the effect that o~ l;on will have on a trqn~lqte~l GTech cir-20 cuit, it is ~lku~t to create the best possible GTech circuit before optimi7Ption When ther~rig~nq1 GTech circuit is of good quality, there are fewer choices that the opLi~zel must make. This causes the finalresult to be _ore reliable, andprobably of better quality bec~..ce the op~ has a much smaller range of chq-nges to make.
Some query types spe~fi~ vqlly refer to the GTech ~l~mqin. For eYq-mple, a query type 2S such as "GTech_GateCount" lGquesb the gate count that a GTech part would require if ~a~ to simple logic gates. This gate count can be used to analyze the initial area re-quired before o~1;---;,-l;on Another possible query type is "GTech_LogicLevels" which l~uei~b the nulll~r of levds of logic that a longest path in a GTech circuit would require if ~d to simple logic gates.
GTech analysis uses the intra-do~in _apping c~pqhility to select structures in the gate ~omqin~ relate those ~llu~;lu~,s to the GTech lomqin~ and then ~lrOl~l, analysis in the W09St27948 `~ ~ 8;~9~ PCI/U~9_J~1C~O

GTech ~lomqin where complete HDL source to GTech circuit ~iblg is available. An ex-ample of this sort of analysis is start/end mode in the Path 13~w~, willd~w, which will be cvc~1 further in a later secti--n 53 Example Digital Circuit Analysis with Reference to HDL Source This section e plqinc how a d~;pJ~,r uses the HDL Advisor to relate cha~ ;ctl~s of the design found in one domqin to aspects of the design found in another ~omqin For this ex-q-mple, the design includes ~pl~sç..lAI;Ql-s in the source, GTech, and gate ~oIn~in~
The ~esigrle~ 520 selects a display object to evaluate by se~ ling some text, such as the ~ecode: l~lvcCSS sl~t~ in the text of Figure 36. HDL text selection uses the text to 10 parse node re~ ;p ~es~be~ e. rlia. Methods for text selection will be des~ihe~ fur-ther in a later section The text to parse node mapping is used to ~ -;ne the parse node which ~ ~J1~ the s~ text, and tbe p rse tree node ..---..1:~- is sent to the selection mqn~ger.
The designer 520 of Figure 40 then obtains a display tool such as the stqcL-ed bar 15 graph display 5430. Next, he obtains a visual l~l)r~s~ ;on of an aspect of the design, for e ~ 1e~ in the source dc~m~in using the HDL text display 5440. The display tool 5440 dis-plays tbe text of an HDL source file. The ~ e lçser he~ in this section is shown in Pigure 32, Figure 33, Figure 34, Figure 35, Figure 36, Figure 37, Figure 38, and Figure 39.
The ~lf cignçr 520 also selects a type of analysis to be ~.r,lllled from the available 20 ehoicec One ~luach is that the ~e~ t r 520 selects it from a menu or a push button. An-other ~pl~ a~h would be to have the fleigner 520 select it before selfxting the text. In this e- -..l le assume that the lf ci~çr 520 asks for the area of the gates which make up of the decode l~lvcess.
The parse tree node ...~...~.~ and the query type comr ice a query that is sent to the 25 data m~n~g~r 125. Suppose that the desired analysis COnf~f,-~'~ the area of the gates that make up the selecte~ parse nûde. neC~ of start up regic~tiQn, the data m~n~ger 125 can identify that the lcquil~d i, rv.... -l;on is in the gate ~lom~in The data m~n~ger 125 com-putes the area cUll~,po,~ g to the ide~;r~cd parse node. The data m~n~g~r does this by using the intcr~nm~in m~pring shown in Figure S to identify the gates in the gate domain 30 that c~ s~ond to that parse node. In this f ~ e, the rlecigner 520 wants to know what the area of one of the l~lvcesses is, and the ~1f.Ci n~r ~20 used probe points to se~ ate the WO95/27948 ` 2 1 8~9~`13 PCI~/US95/04660 design to permit the intra domq-in mapping to the gate level.
Thus, the initial query sent to the data mqnqgPr c~,-r-f ,.c the area of a V~L ~cess t~.. .-1 in the source dom~in First, the data mqnagf~r ascG.~ins that an area query must be an~. _,~l in the ~ dcmqin. Th~ rul~" the data mqnagfr uses the intra-domLq-inS mapping c~pvqbility to find the gates related to the plOcf ss sli~h~ f nt Next, the data man-ager det~ es that the query must be divided into a ~u~uC y for each gate. In this situa-don, the data ...~ lf te-...;~-es that the total area for the plocess can be co...~ ccl by .. ~... ;I~g the area value for each gate.
After the data mqnager 125 i~1PntifiPc the relevant gates, it then colll~ules the total 10 area coli~u~ l by these gates. In the gate domqin each gate has several chz.~cle. ;ctics as-soc~q-tP~ with it. One of these charactericti~s is area. The data mqnagPr çhooses an area anal-ysis tool 5480 which can answer queries l~ ing gate area. In one ~.llbo~ area analysis tool 5480 dete ...;ne,C the area of a gate by lorl-ing up the area value for the gate in a technology library. The te~hnol~gy library is provided by the se_icontlllctor vendor who 15 mqnnfqctllres the physical gate.
For each subquP-ry, area analysis tool 5480 then l,loduces a nllmPri~ql value for the area that is sent back to data mqn~gP,r 125. Each area value is the area of one of the gates coll~sl,on-1ing to the l,l~ei,s. The data mqnage~r then ag~,gates the area values r~ullled by each ~ul~u~,.y by adding them lc,L !l.e The final area result is then sent to HDL text display tool 5440 which can display the result dilcclly or use it to _odify the display cl-~ t,. ;~ti~s in the display tools.
5.4 Sample Display Tools The flPyihility of the ~.;l;;te~ ~ shown in Figure 40 ~l ,Is mllltiple display tools The display tools relate digital cir~uit analysis u~....~l;On about parts of the GTech or 25 llla~ped circuit to the source text that g.~ -e~ ~tes those parts. This section desç~ihes a number of display tools but by no means all display tools. An example is used to clarify the use of the display tools.
By linking display tools to the data mqnqg~r, display tools are able to display results in one domqin that are co.~ "~A in another domq-in F~ ~, the ~:lesign.o.r is able to 30 use a tool such as the s~qr~ bar graph desç~ihe~ below to investigqt~, a design attribute such as gate count. The ~eSigner can then view the source HDL from which the part of in-2 1 a 5~9~ ~DED Slt~ET
~7 Pl~T~NT
ArT~RN~ WCI~ET 1~0: 3~ln.00014 teres~ FC.~ d ~or examplc l;hc doeigner can use tho stadccd b~ to fi~d a pc~ of tke mappct circuil wlJic~ a hi~ ~a~e cou~ mappet ~c~it partian c~ n bc ~ c~ thc ~oosc~ ~L
Fgure 43, F~c 4~ urc 4~, Figl~ro 46~ Flg~c 47, Fi~ure 48, Flgore 49, a~d F~uro ~0 sbovr di~ y t~ for d;s~la~g ti~ital circi~ anal~ data Fl~uro 43, F~uro 4~, Figure 4~, Pig~ if Fy~urc 47, F~-c 48, F~gure 4~, a.~d Fgure 50 ~w thef ~pl~y tools displ~ n ~0~ d~lL Thc sotlrCC at~d res1~ mapped C~CUit is t~r~i ~l cd ~ Lt~on tct Hl)~B3scd De~ign U~ VE~L, by Steve Carl~on, publ;~cd ~n 7991. l~is book i5 availablc f~om S~llopsys, I~c., 70~) ~st Mid re' ' ' P.oad, MouDtaill Vic~
g4043-4033. T~e displ~y tool~ are ~rther ~I~;bet ~ t~e ~L Ad~- User C~uid4 which ~ aYail~lc ~om SYDLPSYS, I~ Moun~ Yi~w, Cf~
The ~IDL source f~r thc A~10~ dosi~ ~ ti~ cd into multiple filo~. A 4ep~rate pan;e tree is a~t for cac~ of t}lc ~e~ ' 3 to cv~VL~.;Onfil parf;ing ~ ~' ;_~ Each parse t-oe ~s ~ced Iv the HD;, sour d to the C;Tech arcuit created ~ t acw~s ta t~o med~ods des~bwl aboYe. Tbe ~IDL
~ouscc f Ihe A~D~ ff;~ infers le~cls of des~ hicrarc~. The kvels o L~.aL~ arc liolccd t~ o~e an~ hc~ accwdiIIg to con~na~ t~ socll ~c tho~c ~cd in D~ C, ~ ~ - p, ~ ~ by S~.~b,~
o~ Vlcw, C~
5.4J. Stoc~et 8ar Gr~ph Di6play Figure 43 ~hows a s~ackcd bar gr~ph ~ playi~ information ab~lu thc rclati~e contributions of part6 of the HDL sowce. Oftcn, a desig~ ~rit~ in ~ ~L i5 ~cs ~t ~i~ c~;c~l~y, wi~ hi~her le~l mod~e8 co~ lowe- level ' '- ~t ~ F - ~ll~- levol ~ the lliG.~.;h~, thc desi~ ~ wa~t to know tl~e cha arte~stirs of the mod~cs Yisible at that levl:L Thc 5tac~ed bar graph of E;~re 43 ~ rdative areas as60ciated with di~e~t parts of t~e defii~ Al t~ hig~e~t le~rcl of the Ah~ A, there are fi~ ' ' - ' sub-blocks: CN~BIX, MUX_OI~T-RIX, REG_~I~, UPC_BIIC, and STA~BL~C. The ~a Of tbo6e bl~ m ~e displa~ ob~cct list arca 2610 Of wi~do~ 2~;00. Thc tot~l measured area is ~1~1 at t~c bottom of ~hc wi~do~v. l'he t~tâl area of the mapped ciralit 1~ sbo~ AS 1~4.0 g~ IQ thi~ ~amplct tbe C~q~".t~;C iç area. Howc~er, other ch~U~Pi~c suc~ a5 pow~r a~d time ca P.I.P50 WO 95~7948 ~ ~ 8 ~ 9 0 8 PCTrUS95~ 16~0 Each of the sub-blocks has a IllCaSUl~,d d~ istic which is shown by text state-ments 2680 through 2684. For eY~mrle, CNIL_BLK uses 74.00 gates, which is 3.8% of the total as shown by S~; le~ nt 2680. MUX_OUT_BLK oc.;u~:es 148.00 gates, which is 7.5% of the total as shown by ..~ t 2681. REG_BLK oc~ ,es 225.00 gates, which is 5 11.5% of the total as shown by ~ nl 2682. UPC_BLK occ~p es 237.00 gates, which iS 12.1% of the tot~ as shown by .. l~ 2683. STACK_BLK occ~p es 1280.00 gates, which is 65.2% Of the total as shown by ~ 2684. A st~r~ bar graph is constructed by ~L~willg a ~,i,phir~l box cc~ g to each filncti-~n~l sub-block with the size of the box plo~ ional to the ~,c~,ntage of the sub-block's ch~t~ ;ctir to the total characteris-10 tic. This is shown with boxes 2630 through 2634.
The st~r~ bar graph display of Figure 43 can be COnSLIuCt~d wili101l1 reference to the lJh~..ical nature of the particular ch~ -~1. ;ctic The.~,fo~, power, timing, or another dl~u ~.el~ 1 ;r, can be dis~ ~ by the same sorl~c. The data m~na~r need only transfer the names of circuit objects, the nllm~nc~l value ~oc~ 1 with those circuit objects to the 15 display tool, and a global id which the display tool can use to initiate further queries and updatc the sele~ti~!n m~n~g~o.r.
I~l1.-,-....J.~" each box, such as box 2630 through box 2634, f~rming part of the st~rl~l bar graph is a select~hlç button. The user can "push" the button using convçntiQn~l rinting and çlir~ g techniques and gain illrQ~ l;c!n about the sub-block ~c~oci~ted with 20 the box. Figure 44 shows the result of th~ user selecting the sub-block MUX_OUT_BLK
box by s~le~ g box 2631. Here, the sub-block MUX_OUT_BLK itself conlQil-s two su~
blocks, OUT_BLK and MUX_BLK. The total measured ch~9~t~ .;ctic 2620 changes to 148.00 to reflect thc size of MUX_OUT_BLK. The sub-block OUT_BLK has 49.00 gates.se~l;ng33.1%of the area ofMUX_OUT_BLK, as in~lir~ted by slAl8-~ 2780. This 25 inroll~-on is also shown gr~rhir~lly by box 2730. The sub-block MUX_BLK has 99.00 gates ~~ s~nt;n g 66.9% of the area of MUX_OUT_BLK, as in~liC~t~ by ~ e --~ .-t 2781.
This inl'~-----l;on iS also shown gr~phi~lly by box 2731. In ~ iti~n~ the window also shows the current l~tirn in the hiel~;hy with a path sl~len.. .t 2705. In ~ltlition state-ments such as ~ t~ ---- --~ 2780 could also act as buttons to change levels.
Figure 45 shows the inr~ displayed if the ~leign~ selects MUX_BLK to see how the 99.00 gates are ~llocate~

21 ~ D~3 ~lENDED SH~ET

ei~ PATE~lT
E~ o~ET ~0: S~175.W014 Note also that when the uscr "pU~Ch~:5~ Ollt: Of ~ ~ butto~ or selccts onc of dle c4, ~p~
of ~le 17ar graph such ~8 ~c yh~w~ m F~ro 45, tbe 5~ o~ is upd3hd w;l~ t~e all~CDt cuc~it scl~ion. Thu~, t~c profilcr allow~ t}lC ~i~ncr to qoick~g selec t a portio~ of the tes~ wh;C~ meet6 oertain s well ~c to ~iew oYerall stati~ for the d~si~.
SA~ tolram l)lsplay Tbe bist~ diiplay of Fgl3re 4~ provide~ ~ d~ c- ~ infior~ about the e~te~t of probbr~s in t~,c tcsi~L For ,', ~QC ~spcct of thc pcrfornL~ncc of a mappe~ ~t ~s t~e lo~8est ~ y alo~g ~ny pat~ from ~ outp~t a one flip-~op to the input of anot~er. nD~:e a desigller speci~es the clocl~
a ~3~ v:rificr ca3~ t~.c~ a~al a~d requir~d t~ uuu~/ut th~ mapped Qrcl~it. At anr poin~ in the ma~ pe~ c~ciit, the a~al ti~e ca~ be llrl ~ ed rda~vc Lo a clvc~ cdgc by _~v~l~g the lon~est path ~om all 1 e~istors a~d by thc dod~ to thc po~nt ~itlliD t]lC m~ppcd circuit. Si~ilar~, roq~rod tu~es may bc co~puted relatiYe to a clo~k edge hy -- ~ ~he longes~ path ~rom tbe p~ tbc mappe~ c~rcuit to a rcgi itcr affe~te~l ~y t~e clock O~cc ~c re~ h;rs between all clocks and all clocl~ ~ -..~6 are ~r~f;e~
the im;Tlg verifier can d~termulc t~e wors~ slaclc ~or e~ch point w~t~is t~c mappod arcrDt by cu~ cti~g ~val l~r~l rcquired t~ for cach posd~blc ~ ~ -~ - of rele~ ~locll edgos. T~o sm~est, cl~ most ne~i~e res~lt c~ be cossideret theworst clarlr for t~at poi~t in t~e mapped circuit. The Des~ Cnmpiler Reference Ma~ual ~3. la ~om S~Op~yS dPc~he6 ~ g a.~lyus. 1~ any no~c has a negali~e ~laclc bme, thc~ t~e imi~
h~LC I~Ut bCGII mBt. If only a fcw nodcs a~e havc DC~aliVC slacks, or thc rleg~ivc sl~cks ar~ closc to zero, then the dc~yLcr m;~hr ~a~e a small problem t~t can bc fixc~ by mi~;ng a portio~ of tl~c dc~. IIc~ ' m~y nod:~ ha~e ~cga~ive sl~c~s or t~e sl~c~ times ~re large, t~ e designer f~c46 a 6ubstaII~al desi~ re~1e l~e hi~l~,..u., tool nf Flgurc 46 can ptov~ w~ t~c ~nt of a problem faang a ll~c 1-;51 o~m displ~ usoe con~rcntiollal hi~t~ nt acation tc~:q~~ t." tool dis~
a n ' ~ e ;~lic of the GTedl or mapp~t ~ it and anows a uscr to scc a ~t a~ pl~y obje~ ~ oC.4;l~g ciscl~t objects ~nv~g t~at ~ ...tY,~:-~ The ¢~ample ~ P'l~e 46 6~1~w~ t;ming analysis for ~e AM~910A. Thc hjs~gram displa~ ~nl fntm~ ~ query asking Ihe d~ ma~gel about the te~ifed a~-L~UI IP~I .p50 WO 9S/27948 PCT/U~9S~'~ SC~0 tribute, in this case the slack time, of circuit objects in the design. The data m~n~gP,r uses a timing analyær to co...r~u~e the slack times at several points in the circuit. The ~ed cir-cuit nodes with similar slack times are grouped into cat~g~lies, cc,~ ,d and a histogram is created.
S Hi~lu~-list willd~w 2900 co~ s two sub-w~ldows: the hislugl~ w-ndc,w 2920and the list wLndow 2910. The hi~ oLI wmdow 2920 col.~ bars 2930 through 2937 with one bar per range of values. The height of the bars indi~t~p~s the l,....~r of nets that fall into that range. If the user selects one of the bars, the list window 2910 shows the list of names that identif,v the nets that are in that range. Individual items in the list display can 10 be s~ , as ;ll~if lted by s~lGct~l item 2915.
These ...~ch~ni~ c allow the ~lesi~P~ to narrow the circuit sel~pction to a circuit ob-ject with a particular plo~,ly. The sel~Pction m~n~gPr is ~ r~ as the ~P-si~p~r explores the design. For ~ lc, the circuit object with the least ~ mt of slack time can be found by creating a slack hiS10~ and viewing the display objects which make up the worst 15 range of values. The de~ignPr can then use other display tools to gain more il)fO~ l;
about the SPkPCt~Pcl circuit object.
5.43 HDL Browser Display Figure 47 shows H~L Llow~ which is also called the HDL text display window.
The HDL I~c,w~ provides textual display of ~)L source code that ~nl~olAIes that source 20 code with at1~1ition~ C)~ n. In one embo~ , text display wihldow 3000 con~ ns three smaller windows. Text willdow 3010 c~ ;n~ the source text. Select window 3040 shows GTech or ~ ~d circuit inr~ .n~l;on related to text that has been selPct~P~l Cursor window 3030 shows GTech or ll~a~d circuit infc.~ t;o~ related to text that is under the cursor. (~lnmn report 3060 shows GTech or ~l~d circuit info....~ion ~csoci~t~A with 25 lines of the text. In an ~ltPrn~te e...ho.l;n~f nl, the select window and cursor window are in-~epen~l~P-nt windows and not cor.l~h-ed within the HDL br~ w~r.
In one embollimpnt selPcting text can be done with the usual window based text se-lection me~h~nismc For PY~mpl~e~ the ~le-cignp-r could move a cursor to the relevant portion of the screen and push a button. ~ltPrn~tely, the ~lecignPr could drag the cursor across an 30 eYte-n~led portion of text to be selecte~
An ~ltern~tp~ e-..bo~ l allows the tlPci~er to select all of the text coll~,s~nding WO95/27948 21 8~`~ PCI/US95/04660 to a parse node with a single visual sçlectio~- The ~leci~e in~lir~tes the initial point for the visual selection as usual by moving the cursor and çlirL ing a button. However, the text win-dow 3010 coll~hucls a text box 3020 around the entire parse node ,~ sen~A. by the text at which the cursor is pointin~ In ~ ition~ wh~ the user moves the cursor acrossS some Lext, the text w~d~ ~ draws a box around all of the text ,~,. se ~ ,d by the first parse node which fully conlA;nC the text. Furth~ .. ,.~, the text display window shows the visual S lo~!;. n by drawing a box around all of the text ,.,~,~sen~ g the SPkCt~ parse node. One fast meth~ of ~ete-..~ the limits of text box 3020 uses the parse tree ~ se IA~;on le~ibeA in co-~-.A;.-g U.S. application by Gregory entitled "Method and A~alus for 10 ~nt~Yt Sensitive Di*,la~" filed on June 3, 1994 as US applirqtir)n nllm~r 08/253,453.
Here, cursor wi,~dow 3030 shows a gate count of the GTech circuit parts qcso~iqted with the display object under the cursor. The phrase "gtech Area = 6" in~1irqtes that the im-ple.. -~lAI;nn of the cc.. ~ ;co-l f .-.cl;ol- ~.r.. -~ by contlition "PSH_PTR >
STK_LOW" in~lirqteA~ by cursor text box 3020 l~Uil~S 6 area units in the generic technol-15 ogy domqin in the data mqnag~r. Cursor wil~dow 3030 could display other char-qrte ictirs ACSC~i_tt~ with the text ~i~t~d to by the cursor.
Sdect wihldvw 3040 shows il~Ç ,,,,,~I;nn qccociqtPA with se~ e~l text. Here, the size and font of the s~l~ch-1 text 1050 is chqngPA One fast m~thod of ~lete....;n;.~g the limits of s~le~::t~A text 1050 would be to use the parse tree ,~se.-~fll;~n ~ec~ ibPA in co-pending 20 U.S. ~rplir~qti~n by Gregory entitl~A. "Me~od and Appalalus for ~ntPYt Sensitive Dis-plays", filed on June 3, 1994 as US applir-tinn nu."ber 08/253,453. In this c-s ,,.plf, the select willdc.~v 3040 shows ~etqilP~A inr-....ql;~n about the HDL construct MEM[PSH_PI~] 3050. Sl;~t~ l 3080 shows the type of HDL collsllucl that the sele~te~
circuit object is-in this case, the cor,sl, ucl is an atTay index. Sl; te---ent 3083 shows the es-25 I;---ol~ area of the construct in the G-Tech domain 1510, here 530 area units. S~fl~e...~nt 3084 shows the length of the longest path in levels of logic from a l~E,isl~l to the gates that le--~- nl the cvnsllucl~ here 18 gates. S!~le~ 3081 shows the parse tree node number.
A ~let~il~ list 3082 shows the netlist co~onen~ in the G-Tech ~lomoin imple ..~ .I;.~g the COQ~IIu~;l 3050. Foreach c~ l in this list, the following inro....~l;Qn is displayed: the 30 c~....l~e~.l's netlist ;~ nce narne 3087, the type of netlist co~l,onelll 3088 (l~Ç~,nce name), its con1lih~ltitn to the total area esl;~ e 3089, and the class of netlist co~ onent woss/27s4s :2 1 `8 5 9D~ PCI/US5Sh1C60 3090 e.g. cell, pin, net, or porL Other inf~ ;nn could be displayed at the Ae-~;~P,~S op-don.
r~ mn report 3060 shows ih~[,....~ csQci~tP~A with each line. Here, the column report is showing the area ~cso~ ~ with the HDL co~ uc~ on each line.
5 5.4.4 Virtual Schematic Display Part of the digital circuit analysis l,locess involves tracing the drivers and dIiven or, inputs and outputs of ~ GTech or ~l)l)ed circuit parts. The virtual scl~e ~ ;C display shown in Figure 48 provides the de-signPr with the ability to find the HDL source that pro-vides inputs to and takes outputs from ano~ point in the HDL source. The virtual sche-10 matic display ha~s a virtual SCh~ ~";C whldow 3100 which has three window regions: aninput region 3110, a current region 3120, and an output region 3130. The ~l~P.si~çr uses the cursor to intlic?t~P s~ t~3 text 3150 in the current region. This SP-I~P~t~P~ text 3150 corre-sponds to a GTech circuit object 3151 (not shown) in the data m~nagPr. GTech circuit ob-ject3151hasinputsandoutrllt~ Thedatam~na~Prthenlinkstheinputregion3110tothose 15 portions of the HDL source text that show where the inputs of GTech circuit object 315Icngin~t~A Here, the input "DATA" comes from an input to the modllle MULTIPLEXOR
as ;nf1;~ by input ~:.J~e~l 3145. The data m~nag~ also links the output region 3130 to those por~ons of the HDL source text that show where the outputs of GTech circuit ob-ject 3151 go to. Here, as in~li(?~e~ by output alE;u~nl 3155, output "Z" goes to the OUtpUt 20 of module MULTlPLEXOR.
By cli~ ng in the output region, the ~esi~er can trace the Ll~u~ e fanout.
Figure 49 shows the çh~ngÇs t_at occur in the regions. The text of the output region now moves to the current region 3120. The text of the output region çh~nges to show synthesis source text co~ onding to circuit objects driven by output al~uLu~lt 3155. Here, output 25 ar~uLuc~ 3155 drives another output at the next level module boundary, as shown by out-put ar~uLu~llt 3156. Input region 3110 çh~nges to show all of the places in the source text that set or define the ~çk~ output ~U,~ULUC~Ilt 3155. Here, there are five text sources for output ~E,uLuenl 3155 as shown in windows 3271, 3272, 3273, 3274, and 3275. The orig-inally s~le~ted sl;~t~ 3150 is shown again in wuldow 3272.
An ~liti-~n~l input comes from the MULTIPLEXOR input al~uLu~llt SEL as shown in window 3271. Z is also takes on values at dirr~l~nl points in a case sl~t~ ~cnl as shown 2~85~0ls in window~ 3272, 3273, 3274, and 3275.
Figure 50 shows the results of pursuing the output arE~ 3156. Here, the high lev-el module ~efinitinl- a~ in the current region 3120 while the input region 3110 dis-plays the mlylule interface shown in the cu~rent region of Figure 49.
Inputs can be ~Jul~ucd in the same ~am~ as Olltpllt~. Note that by sele~ P circuit objects via display objects in the virtual sçl.P~ , the fl~i~r is ,.~ g the selection mqnag~r so the HDL ~lu~v~r wind w is also ..~1~ as the GTech fan-in and fan-out is analyzed.
The co~ tif)n of all of the points in a circuit leading to a particular point is referred 10 to as the transitive fan-in of that point. The coll~ctiQn of all of the points in a circuit that depend on the value of a particular point is the ll~.si~ e fan-out. The pl~ g example showed how to trace tl~sili~e fan-in and ll~r.sili~e fan-out using the virtual scl~p~ l;c During analysis, the ~e i~r might need to cons:d~. the impact that a change in one part of the design would have other parts of the design. If the ~esigner is conc~ ring chang-15 ing the source HDL, the dei~r would find it useful to identify how the pl~posed changewill i~ e~ce the reS~ ng GTech circuit. Suppose that the tl~igner wishes to change a particular function in the source HDL. The (~e~igner will find it useful to ~et -~ c all of the inputs to that function or all of the outputs to that function to see how the change will affect the lG.~ l of the GTech circuit. While tracing all of the inputs (or outputs) of a 20 particular part of the source HDL is a ~im~-llt task using only the HDL source, using the direct CC~ ce ~t~. ~n the HDL and the initial GTech circuit formed during trans-lation makes it pos~i~le to hi~hlif~ht the inputs (or outputs) in the source HDL.
5.4.5 Logic Inspector The logic in~pector window displays the transitive fan-in logic to selected endl,oinl~
25 in the design. This logic is c~ ted from the GTech r~ se ,I; l ;on of the design. The log-ic incpector window displays the inputs that are used to co---~v~ a value within the design, the initial boolean ~l~ uCI~, implie~d by the HDL source, and the probable effect of boolean .
mlnlml7~tl1~n after c~ ?n Rool~n ...;n;..~ l;on can be invoked from the logic ;..~p~lol window to show the 30 ~t~ntial reduction of the origin~l logic structure, which is based on logic level or compo-nent count re~npion goals before logic optimi7~tiQn Note that a portion of the GTech cir-WO 95t27948 2 ~ 8 ~ ~ D 8 Pcr/uS95/04660 cuit is ~ terl for boolean l--;n;~ ;on when the ll~u~ e fanin of an e~ is s~ech~
To view ~l~qn logic CC.~ iQg to the eurrent cireuit æleetiQn, the ~C,cignf,r çl-ooses the "New Logie" option in the logie ;Q~pcclor by çl-oos;.~g a menu item orp-lching S a button. The logie ;~.C~I~I eauses logie ec,ll~ ondillg to the eurrent circuit selection to be created as follows. First, the logic ;..-~lol (~ete~ .eS the current circuit seleetiQn in the GTech dc~m~in by querying the Selectic!n m~nag~r The seleetiQn m~nagçr sends the logic in~pcclQr a GTech circuit object. The logic i~.~cclo~ may limit the logic created by asking the ~esi~r to specify the bit pOSitiQn in the circuit seleetion from which to create 10 the logie.
First, the logie ~ to~ queries the data mqn~g~r to cc.~u~ulc all of the cireuit objects whieh make up the ~ e fan-in for the s~k~tecl eireuit object. The logie ~ ol then asks the data manager to ænd the group GTech parts to a logic Op~ .;,.,. In one embodi-ment, the logic optimizer o~ es the logie l~r~,æ.llcd by the GTech parts and returns a 15 string whieh rel~resellls the logie ~uali~ns p~duced after the logie has been o~ i- çd Note that the op~ to improve the GTech logic using s~ d~d optimi7~tion techniques such as those ~es~r~ above, but does not map it. In one c ~bo l;...- -1, the de-signer can specify the optimi7~tiQn effort used when o~l ;-- ~;7; -g the logic. The logic inspec-tor then displays the string 1~ ~ as a ~l.-- ..-~;c.
Figure 52 shows the logic i~ . displaying a graphical r~l~ nl~l;Qn of logic created by the logic;~.~10l . This logic was o~ ~ using a .. eA;.. level of effort. The Op~ ;Q~ effort level ~ -es the complexity of the opl; ~ . ~; 7~ strategies which are invoked.
The sckf --~lics displayed by the logic ~ e~lo, l~rcsen~ GTech boolean logic, rath-25 er than ~,la~pcd circuit ~luclul~s. A ~lu~lly of GTech boolean logic is that simple gatessuch as AND, OR, NAND, and NOR gates do not dirr~ Liate bcL~.~,en their inputs. Thus, there is no need to route signals ~1~. ~n such gates. The~fol~, the logic in~rector symbol n~alor is very fast because it simply draws a gate for each O~latO~ in the boolean equa-tion. The gates are connP~t~ di~ y to one another, creating comrleY gates which repre-30 sent the boolean C~lualion.
The logic; ~ lor symbol ge ~ tOI creates co. .~ symbols from boolean equa-woss/27s4s 2 1 8 5 9 08 PCIIU~9S~ 0 tions using a two step p~ccss. First, the symbol e~ or traces f~m each input to the out-puts it drives in order to ~o~ t.~ the size of the gates driving each symbol. Next, the symbol g~n~,alur starts at the output of the equalion and works backwards. Each boolean eAp~ ioll is displayed as a simple logic gate. As the symbol ~ "~lol works bacLwd,ds S it places new gates &~11~ behind the previous level. The gates are placed far enough apart so that there is room to place the driving gates before them. When the ~- ~ of the equa-tion are reached, they are simply con~t~d to the pins of the last layer of logic. Note that the same ~,.",;I-ql may be added t ~ more than one pin, wi~loul nee-ling to route the signal sent~ by the t~ ...;nql from a single port.
10 5.4.6Pa~ ..sc, Figure 51 shows the path blc,w~r window displaying a path in a GTech lG~lesell~.a-tion of the AMD 2910A.
The path l~1VW~G~ whldc~w enables the ~lesi~npr to explore grrhir-qlly the connec-tions in the design. This window displays a single path in the design, inrlu~1ing all of the 15 fan-in and fan-out logic of the ele-..~ along the path. The paths may be displayed in either the GTech or the gate domqin ro.~nc~ ity implirqtir~nc of the HDL source can be under-stood by using the intra-domqin mapping cqpqbility to relate any point on a GTech path to the source HDL. The path ~W~G~ wil~dow shows the fanout of drivers on the displayed path. And example of this is GTech part 5240. Showing fanouts allows the ~lpsignp~r to view 20 the effect of lo~ding on the path. The path l~l~wS~ window also shows the fanin onto the path. An eYqmpl~ of this is GTech gate 5230. Levels of hi~.~.,l~ are displayed as boxes 5220 around logic on the path. Levels of hi~ l"~ are illl~l ~ll becqllce they m ight influ-ence the Op!;---;,~ - 'S ability to improve the GTech or ~d circuit.
The path ~lOW~Gl wind~ is ih~ c~i~e. By çlirl-ing on a display object in the path 25 b~w~. wh~dc)w, the user can expand that display object to show all of the inputs to and outputs from the circuit object le~iese-~l~ by that display object. GTech part 5210 has been - c~ d~ in this ma~ ing on a logic cle--~nl also ~ es the circuit selection stored in the ~k~l;ol- mqnqgPr. An !qltPmqt~ path can be displayed by choosing a new pin or port and using that pin or port as the ~ oint for al~olh.,l GTech or lllalJ~ed path.
A ~ n,~,,, for GTech analysis, "start/end mode" further leverages the intra-do-main mapping car-q-bility. Star~lEnd mode allows the de~ignPr to choose a path in the 2 1 8 ~ ~ ~r~ ~ED SH~ET
- 76 P~TE~IT
ATTORtlE~r Dl1CI~ET Nl~ 0014 m~lped logic doma~ T~e ~t~t and end poi~ts of the path are mappcd to tho t~Tech doma~ lls~ e intra-doL~ 'rhe GTech ~g Yer~her t~ Lo~ ~he longest path ~ Tech circui ~c~o~ the s~t a~d cnd poi~t~. Usmg the mappi~g bctwee~ the GTech ~d the source domains, the path ifi l~ S~t i~
DL t t. T~ pro4c~6 ~o~s ~e ~c.i~ to pcrf~ ti~ning aD~ c o~ al E~L a~d to ir~pro~e the ~g ~h~ t~ , cf the design at t~e 60~rce ~e~L
~ ote ~ thc HDL ~d~or d~c~ rot aeatc t ~ GI ~ult~-6beet ~ ;~ Thc path brow~r win l~w di~pla~ a grapl~ r ~ ~t~o~ of a path throu~h the digit~1 ar~uit ~ from an HDL ~e path t bc com~ d of e;t~ Toc~ ot m~ppcd logie ~p~ -~tC
55 A~ s~ Tools As d~il,ct ea~licr, the arc~i~ of ~e ~L Advisoe allow~ a~y ntlmber ~f digit~l arcuit a~alyss tool, to be ~ rc d to z~vns ~uenes. ~oe w~ple~ a ~ - - e,~haust;.7~ ~st of aDalysit tools i~
A t~ verifier ~n area ~al~4~s tool ~ po~er a~al~ss to~l A path tTa~ tool A laywt analy~s tool A GI ecb logic l~eh a~alysis tool A GTe~h ~m~ a ulysis tool S.6 ~ ltd F .?~
This sectio~ desc~bes ~ e~mple ~ing tlle tllre~ pArt arc~itecn~n; --~h~A in Pl~s sediar~ T~
exan ple u~es ~ A~l~A des~ T~e ~nurce and res~ mapped arc~it i~ d~scribed in Intn~ tioll to ~IDI -Based I~e~en Us~n~ ~L, by St~ve Carlsou, pl~bli~ot iD 1~g1. Th~ bool~ is ~. '1- 1 ~om Syl~ops~, 1D~, 700 Ea~t 1~ ~t ~d Road~ ~Jo~ , CAg4043~3. ~heA~2910A des~ ha8beerl1Oadc~; ItO
~ L AdYisor as ~ cd i~ t~e HDI., Advisor U~r Gu~de~ whi~ is ~ fro~ Sy~ . Inc n~
M~ Vew, ~A.

LIU0PJ .P50 wo gsn7948 2 1 ~ PCIIUS95/04660 5.6.1 The Designer* View In this eY~mrle~ the ~Pcign~r wishes to evaluate the co...~ enl count of a GTech de-sign before sy~lhesis and then id~,nLify the portions of the ~)L code that con~.ne a large ...... ~l,f,. of cc~
First, the dP-ci~pr uses the st~^lfPA bar graph display tool to display a st~r~A bar graph of the cc n ~l.ol.f nt counts of the entire GTech circuit. Figure 55 shows the stacked bar graph dis~la~ing cn..~pQn~ nl counts for the AMD2910A. To obtain this display, the design-er first opens the stacked bar graph display window using a con~lenl;on~ 1,~ such as ;ng a menu item. The dPcigner then clicks on the Colll~onent Count icon 5710 in the 10 st~L-ed bar graph display. The data that ap~ in this display shows the lictriblltiQn of the se~ nl~ within the "CORE" design of the AMD2910A. Notice that the display is pani-tioned in terms of the HDL source. F~t~h section of the st~r~eA bar graph ~ eSe.ll~ a circuit object in the source ~lom~in Analysis is done in the GTech domain, but the results are g~uped by objects in the source dnm~in In the st~c~A. bar graph display, the decigner sees that the majority of the compo-nents are used in the "STACK_BLK" co~ onent. This is in~lic~te~ by the display object, in this case a large bar, rc~r~.l;n~ the cc~q~one~ in the STACK_BLK 5720. The de-signer now wishes to obtain further inf~ l;nn ~ ling the distribution of the compo nents within the STACK_BLK. The decigr~ selects display object l~rt;senl;ng the 20 STACK_BLK 5720 by rlic~ing on it. The ~esi~er looks deeper into the STACK_BLK by çlirlrin~ the PUSH IN icon 5730. An ~ltrrn~te mrtho l of cimnl~ r~..~ly se~ tin~ the dis-play object and looking deeper is to double click on the display object.
When the ~lesi~ner looks deeper into the STACK_BLK the st~elr~ bar graph displayçh~nges to show the co..~ nt counts of mr~-lles within the STACK_BLK. Figure 56 25 shows the st~r~l bar graph displaying cG...~onent counts for the stack module of the AMD2910A.
- In addition, w_en the ~eSi~Pr selects the display object l~,pn_senlh~g the STACK_BLK 5720, the ~)L text ~luw~ displays the HDL source which inst~nti~te~ the STACK_BLK Figure 57 shows the HDL text bf~wse. with the source code for the 30 STACK_BLK 5910 hilighted By hilightin~ the source code for the STACK_BLK, theHDL text b~ . se. is imlir~ting both that the STACK_BLK circuit object is selected, and W095/27948 21 8~D~ PCI/US95/04660 also providing a cc"l~c,nif . t ~ Anicm for the user to see the s~-k~t~l display object.
At this point, the tlf s~ r selects the largest single cl~ - ..f~.nl bar in the STACK_BLK
display 5910. This bar ~ ,~nb a variable array index in the GTech circuit. The HDL
r highlightc the HDL source code for the variable array index, and the deci~f r may 5 ~1.~ ~1f.1 if the col~tlu~;l could be l~i~ lilt~, to reduce the u~ onf nl count. For eY~mple, the array size may be l~ c~, or the data may be cALI..ct~,d with a shift operation which co..~ ..es less c-~ nl ol;~nt~ ~ltem~tively, the ~esigr ~r can select other large bars in the STACK_BLK so he can cc~ hlg their related source HDL.
This tool &~]~ , helps the circuit ~eSi~r by ~l hir~lly displaying illl~oll~nt 10 design ~ 'Ct' ;Ctics~ such as co~ponel t count, and providing the ~l~.cign~-.r with a simple icm to display the portion of the HDL source that is l~,sl~-~;ble for the particular chara~t~ ;cs 5.6 2 Implem~ ~t~hon This section ~esçribes how the HDL Advisor sor~wdl~ creates the displays viewed by the ~e-ci~r in the previous ~ l-le Figure 61 shows the co.. ~ tiQn flow as the de-signer analyzes the design.
First, the ~Sign~r 520 uses the stacked bar graph display tool 5430 which is also shown in shown in Figure 55 to display a st~rL-~A bar graph of the co..~l o~ t counts of the 20 entire GTech circuit. The st~^lr~l bar graph display tool 5430 a~ in a conve..t;. n~l windc~w on the screen of a cc.~ t - -When the ~eSi~r pushes the CO..~ lf-.~l count icon 5710 in the st~rl~ed bar graph display 5430, the st~rl~ bar graph display tool 5430 issues a query to the data m~n~g~r 125 to find the CO--~ f,~t counts of all of the circuit objects which make the entire design.
25 In one embo~im~nt~ there is a special global id called the <design_id~ which r~les~llls the entire design.
In one embo~lim~n~ finding Com~onCnt counts for the entire design is a two step pro-cess. First, the stacked bar graph display toolS430 issues a query 6403 to the data m~n~ger 125 asking for a list of the colll~n~,nl~ which make up the design in the source iom~in In 30 one e-..k)~ -t, the query 6403 has the following fields: ("composition", [<design_id>], False, Null). ~'CQ~ oS;I;~n"iS the type of query and in~1ir~te W O 95/27948 2 ~ ~ PCTrUS95104660 that the query is l~ue~ g the circuit objects which make up the objects in the object list, which is ~ cignid>]. False in~ ?tes that the results should not be c ^h~ Null is the ag~ion filn~tion bec~.~ none is needed for a cc....l.os;l;on query.
The data mqna~o.rl25 then cc..~ nes the answer to the query 6403. In one embodi-ment, the data mq-na~.rl25 ~ es that a co...l~s;~;on query 6403 can be answered by a cc,~ osi~-ol- analysis tool 6400 which o~l~tes in the GTech ~omqin The data mqn~g~r 125 uses the dnmqin ~l)~r to _ap the <design_id> from the source ~lc.m-qin to a circuit object in the GTech dom~in Note that analysis tools do not use global id's, but rather cir-cuit objects in a lnmqin The data mqnqg~'rl25 then sends the co~l~osilion analysis tool 10 6400 a query 6406 to find the co...l o~;l;nn of the design. In one embo-1im~nt, the query 6406 has the fo~owing fields: ~"composition", <design>, False, Null)."co-.-~ ;nn"iS the type of query and in~ir~t~s that the query is requesting the circuit objects which make up the design, which is inAirqtPd by ~esign~. False in~ tes that the results should not be cached. Null is the aggregation function bec qll~e none is need-15 ed for a co.--l os;~;Qn query. The cc.~silion analysis tool 6400 then traverses the GTech circuit, finds the co..~os;l;on of the design, and returns the data mqn-q~gf,r 125 a message 6409 with the result. In one ~ t, the messa~e 6409 is: message( "composition_result", [<CNTL_BLK>, <MUX OUT_BLK>, <UPC_BLK>, <REG_BLK>, <STACK_BLK>]). The data mqna~er 125 then ~let~ es global ids for each of these objects. In one emWim~nt, the data mqnqg~.rl25 uses the objects as indices into a table to look up the global ids. In al~h.,~ bo~ n~nl~ the global ids are stored on the objects. The data ~ n~ge 125 then sends the stq-rl~ bar graph 5430 a response 6412 to the query. In one ~,.,~kyl;..~,nt, the return m~osC~e is message( "composition_result", [<CNTL_BLK_ID>, <MUX_OUT_BLK_ID>, <UPC_BLK_ID>, <REG_BLK_ID>, <STACK_BLK_ID>]).
Next, the stq~ bar graph display tool 5430 issues a query 6415 to the data manager 125 asking for the co~ollc.ll count of each of the circuit objects in the composition list. In one e..~;..~ . the query 6415 has the fo~owing fields: ("component_count', [<CNTL_BLK_ID>, <MUX_OUT_BLK_ID>, <UPC_BLK_ID>, <REG_BLK_ID>, <STACK_BLK ID>], False, Sum). '~CO..~ f-~t_ count" is the type of query and in~ stes that the query is lC~Uesling the circuit objects which make up the objects in the W095/27948 2 1 ~ ~ ~ D 8 PCT~S95/04660 object list, [<CNTL_BLK_ID>, <MUX_OUT_BLK_ID>, <UPC_BLK_ID>, <REG_BLK_ID>, <STACK_BLK_ID>]. False inr1i~stF,s that the results should not becached. Sum is the ag~gaL-on func~ion be~ se a co...l~onf nl countresult is ag~,galcd by ;,~.. ;ng the results of subqueries. In one ~-.. hoA;.. nl, sum is chosen as the aggregation 5 r.~ l;ol- by looking up the co. nl~n~F ~ count query type in a table.
The data mqnagFr 125 then Cc!...p-,t~,s the answer to the query 6415. In one embodi-ment, the data mqnsg~r 125 ~ct~, ...;~-es that a cc.~onenl_count query can be alls~ ,d by a co~ one, l count analysis tool 5470 which O~lat~,S in the GTech lom-q-in The data man-ager 125 uses the ~ mqin ~ to map the objects in the object list from the source do-10 main to a circuit object in the GTech domqin The data mqn~ger 125 then creates a subqueryfor each of the objects in the object list. In one emboA;. . .~ nl, the first subquery 6418 has the following fields: ("component_count", <CNTL_BLK>, False, Sum) ."~nent_count" is the type of query and in(1i~qtes that the query is requesting the circuit objects which rnake up the CNIL_BLK, which is il~A;~ l by eNTL_BLK>.15 False in~ q,tes that the results should not be cached. Su_ is the ag~ga~ion fimction be-cause ~..lpO~ count results are ag~Ggat~d by ~n....;,~g the cc.~ onenl counts ~
The cQ...~ F---~ count analysis tool 5470 then traverses the GTech circuit, finds the com-ponent count of each de n. --.l in the CNTL BLK, sums all of the co~llponen~ counts togeth-er, and returns the data mq-nagF,r 125 a mF Ccqge 6421 with the result. In one embo limF nt, 20 themessage6421is:message( "component_count_result", 119.0).Thedata mqnager 125 issues a series of su~ ;es 6424 for each of the objects in the object list and the co~ enl count analysis tool 5470 sends ~ ~nce mF~ss~q-~s~ 6427. The data manager 125 then sends the st~e~d bar graph a l~ e to the ~riginql query. In one embo limF~ nt, the return message 6430 is message ( "composition_result", [1 1 9. 0, 25 124 . 0, 1 94 . 0, 2 94 . 0, 1 97 8. 0] ) . The stacked bar graph display uses these num-ber to create the stq~ ed bar graph shown in Figure 55.
The ~lesign~ then selects the display object l~i~S~ -g the STACK_BLK to obtain more in~o....~l;o~ about this part of the design.
When the ~eCi~n~ selects the display object l~ s~- u;,.g the STACK_BLK 5720, the Ct~lr~d bar graph sends the sele~tion m~n~g~ 5460 a mes~ge 6433indic~ting the new s~lcc~i~n. In one emkYlim~nt the m~Ssage 6433 ismessage( "selection_set", WogS/27s48 PCT~S95/04660 <STACK_BLK_ID>). The s~PlectiQn mqnqger 5460 in turn broq-~lc~ctc the selectiQn to all of the display tools using a meScqge In one c ~bo~ f ~t~ the mPsQqge 6436 isrnessage( "selection", ~STACK_BLK_ID>). One of the l~ ;p:e~ of this mPsc~ 6436 is the HDL text l~ 5440.
S The HDL text l~ G. 5440 sends a mes~qge 6439 to the data . . ~ g~- 125 to get the sc~ ;on as a source Ar~mqin circuit object. In one em~;..~ ~l the mÇssqge 6439 is: mes-sage ( "GetGlobalId", [<STACK_BLK_ID>], Source). ThedatamqnqgP,r125 returns a mP~csrqgp- 6440 to the HDL text bl~J..s~. 5440 which in~ Aes the global id which ,senls the STACK_BLK in the source ~omqin The HDL text l~luw~,r 5440 then sends 10 a meSsage 6441 to the data mqnqg~r 125 r~1~esl ;.-g the parse tree node 1.- ..nk.l cc~llG*)ond-ing to the global id. In one e n~;---f ~l, the m~-ss~g~ 6441 is: m~ssq-~"G1Oba1Id-ToLocalID", [<STACK_BLK_ID>]). The data mq-n~ger 125 returns a m~ss~q~ge 6442 which incllldes the parse tr^e node IIUI11~. CC,11~,;,~l A;. g to the <STACK_BLK_ID> to the HDL text 1~ G1 5440. The HDL text bl~wsGl 5440then hilightQ the text which corre-15 sponds to the parse tree node l~ ,sent~d by the parse tree node l. ~ ..bel. In one embodi-ment, the text is hilighteA by drawing a darker bac~ound for it as shown in Figure 57.
The ~lesi nçr now obtains further inr .. ~ n l.,~ lulg the Aictrihlltion of the ele-ments within the STACK_BLK and the stacked bar graph display ch~nges to show theco~llenl counts of m~llles within the STACK_BLK. The st~ çd bar graph display de-t~ es the c~ ûs ~;on and the co~l)onenl_count of the STACK_BLK modlllG.
In one e-..hQ l;...- nt the stacked bar graph 5430 sends the data m~n~ger 125 a query 6445 ("composition~', [<STACK_BLK_ID>], False, Nu11) . The data man-ager 125 then dete ...~l~es the answer to the query 6445. In one emhoAiment~ the data man-ager 125 d~ te~n~;"es that a co~l,o~ilion que~y can be an~ "ed by a co~poS;l;~n analysis 25 tool 6400 which o~l~les in the GTech dom~in. The data m~n~er 125 uses the domain llla~er to map the ~STACK_BLK_ID> from the source dom~in to a circuit object in the - GTech Aom~in The data m~n~g~r 125 then sends the composition analysis tool 6400 a que-y 6448 to find the co~l,osilion of the STACK_BLK. In one emboAim~-nt, the query 6448 has the following fields: ("composition", <STACK_BLK>, False, Nu11) ."CQ...l~O~;I;Qn" is the type of query and inAi~tes that the query 6448 is requesting the circuit objects which make up theSTACK_BLK, which is inAic~teA~ by <STACK_BLK>.

wo g5/27948 2 1 8 5 9 0 8 PCT~S9S/04660 False ;~ ;r~tes that the results should not be cached. Null is the ag~gahon function be-cause none is needed for a co...l~o~;l;on query. The co.~ o~;l;ol- analysis tool 6400 then lla~ s the GTech circuit, finds the cc....l~s;l;Qn of theSTACK_BLK, and returns the data ...~n~.,. 125 a mf ssq~e6451 with the result. In one e ~ l;.nf-n~ the mPsc-qge 6451 is:
5 message( "composition_result", [<Bool_Mem>, <soo1>, <Sel_MEM>, <Bool_STK_DATA>, . . . ] ) . After co~ ling from objects to global id's, the data man-ager 125 sends the stacked bar graph 5430 a r.,~l,onse to the query. In one e~ubo l;...f .-~ the return ...es~a~ 6454 is message( "composition_result", [ [<Bool Mem_ID>, <Bool_ ID>, <Sel_MEM_ ID>, <Bool_ STK_DATA_ID>, 10 . . . ] ] ) .In this example, [<Boo1_ Mem ID>, <Bool_ ID>, <Sel_MEM_ID>, <Boo1_STK_DATA_ID>, . . . ] is a partial list of the rk ~.f~ in the STACK_BLK
The other global ids are o..-;~ l for clarity.
Next, the st~ PA bar graph display tool 5430 issues a query 6457 to the data mqnqgP,r 125 asking forthe co~ onf n~ count of each of the circuit objects in the co...l-osi~;on list. In 15 one c~ fnt~ the query 6457 has the following fields: ("component_count", [<Bool_Mem_ID>, <Bool_ID>, <Sel_MEM_ID>, <Bool_ STK_DATA_ID>, ...], False, Source, Sum).

The data ...~a~ 125 ans. ~... the CO.~q~l-~ count query 6457 for this new objectlist using the c~q~onf ~l count analysis tool 5470 in the same fashion as ~es~bed above.
20 The s~-~PA bar graph display 5430 uses the lel~- ..f~ results to create the stq~f~1 bar graph shown in Figure 56. At this point, the dP.~i~Pr 520 selects the largest single cl~ ...f ~-t bar 5810 in the STACK_BLK display. The ~1P,C!;~n mqnagP,r 5460 co.. ;~qtP,s the new se-lection to the HDL text display 5440 in the same fas_ion as desc-ribP~l above. The HDL text display 5440 then highlightc the HDL source code for the vanable array iridex.

Claims (40)

We CLAIM

1) A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising:
a parse tree generator (3654) generating a parse tree (3620), stored in a memory of the system, in accordance with the text description (3610), said parsetree including a parse tree node that relates a portion of the text description to the parse tree node; and a digital Gtech circuit representation generator (3664) generating a digital circuit representation (3630), stored in the memory, the digital Gtech circuit representation synthesized from said parse tree and including a Gtech circuit element, said Gtech circuit element referring to said parse tree node, wherein said parse tree node also refers to said Gtech circuit element.

2) The computer-aided circuit analysis tool of Claim 14, wherein said circuit design language is Verilog.

3) The computer-aided circuit analysis tool of Claim 14, wherein said circuit design language is VHDL.

4) The computer-aided circuit analysis tool of Claim 14, Claim 2, or Claim 3, further comprising:
a numerical physical characteristic of said second element, stored in the memory; and a computer window generator (5240) causing to be displayed a visual object linked to said parse tree node and having a visual display characteristicdetermined by said numerical physical characteristic.

5) The computer-aided circuit analysis tool of Claim 4, wherein said second circuit element includes one or more circuit parts, with each circuit part possessing an area, and said numerical physical characteristic is the sum of the areas of said circuit cells.

6) The computer-aided circuit analysis tool of Claim 4, wherein said second circuit element includes a circuit part pin and a primary input, and said numerical physical characteristic is a time delay from said primary input to said circuit part pin.

7) The computer-aided circuit analysis tool of Claim 4, wherein said visual object is a rectangle having a height, said visual display characteristic being said height.

8) The computer-aided circuit analysis tool of Claim 4, -84a-wherein said visual object is a text character and said visual display characteristic is a displayed font of said text character.

9) The computer-aided circuit analysis tool of Claim 4, wherein said visual object is a text character and said visual display characteristic is a displayed color of said text character.

10) The computer-aided circuit analysis tool of Claim 14, Claim 2, or Claim 3, further comprising:
a first display window generator causing to be displayed in a first display window, a first display object linked to said parse tree node; and a second display window generator, causing to be displayed in a second display window, a second display object linked to said second circuit element.

11) The computer-aided circuit analysis tool of Claim 10, wherein said first display object includes a sequence of one or more characters from said text description, and wherein said sequence of characters includes a subsequence of characters related to said parse tree node in accordance with said circuit description language.

12) The computer-aided circuit analysis tool of Claim 11, wherein said subsequence of characters is displayed with a visual characteristic distinct from the visual characteristic of said sequence of characters -84b-not included in said subsequence.

13) The computer-aided circuit analysis tool of Claim 10, wherein said first display object includes a sequence of one or more characters from said text description related to said parse tree node in accordance with said circuit description language -84c-

14) A computer-aided circuit analysis tool for analyzing a text description of adigital system written in a circuit design language, comprising:
a parse tree generator (6018) generating a parse tree (6004), stored in a memory of the system, in accordance with the text description (6003), said parsetree including a parse tree node (6014) that relates a portion of the text description to the parse tree node;
a digital circuit representation generator (6019) generating a digital circuit representation (5900), stored in the memory, the digital circuit representation synthesized from said parse tree and including a first circuit element, first said circuit element referring to said parse tree node, so that there is a traceable path between the first circuit element and the parse tree node; and an optimizer (3674) that optimizes the digital circuit representation, yielding a mapped circuit representation (3640) stored in the memory, the mapped digital circuit representation including a second circuit element, the second circuit element referring to one of said parse tree node or said first circuit element, so that there is a traceable path between the second circuit element and the parse tree node.

15) The computer-aided circuit analysis tool of Claim 14, wherein there is a traceable path (3676) between the second circuit element and the first circuit element.

16) The computer-aided circuit analysis tool of Claim 14, wherein said parse tree node also refers to one of said first and second parse tree -84d-elements, so that there is a traceable path (3662, 3672) between the parse tree node and the second circuit element.

-84e-

17) A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising:
a parse tree generator (6018) generating a parse tree (6004), stored in a memory of the system, in accordance with the text description (6003), said parsetree including a parse tree node that relates a portion of the text description to the parse tree node;
a digital circuit representation generator (6019) generating a digital circuit representation (5900), stored in the memory, the digital circuit representation synthesized from said parse tree and including a circuit element, said circuit element referring to said parse tree node, so that there is a traceable path (3666;
3666, 3676) between the circuit element and the parse tree node; and a stacked bar graph window display generator (6104), causing a stacked bar graph to be displayed on a display screen, the stacked bar graph representing a numerical physical characteristic of said circuit element, stored in the memory.

18) The computer-aided circuit analysis tool of claim 17, wherein the numerical physical characteristic represented by the stacked bar graph is power.

19) The computer-aided circuit analysis tool of claim 17, wherein the numerical physical characteristic represented by the stacked bar graph is area.

-84f-

20) The computer-aided circuit analysis tool of claim 17, wherein the numerical physical characteristic represented by the stacked bar graph is time delay.

21) The computer-aided circuit analysis tool of claim 17, further comprising:
a text window display generator (6197), causing a portion of the text description that is traceable to the stacked bar graph to be displayed with different physical property.

22) The computer-aided circuit analysis tool of claim 21, wherein the entire portion of the text description that is traceable to the stacked bar graph is displayed with a predetermined physical property.

23) The computer-aided circuit analysis tool of claim 21, further comprising:
a user input receiver that receives an indication that a user has selected a portion of the stacked bar graph;
wherein the text window display generator causes a portion of the text description that is traceable to the selected portion of the stacked bar graph to be displayed with the predetermined physical property in accordance with the user selection.

24) The computer-aided circuit analysis tool of claim 21, further comprising a user input receiver that receives an indication -84g-that a user has selected a portion of the stacked bar graph, and wherein the stacked bar graph window display generator causes a second stacked bar graph (2620) to be displayed on a display screen in accordance with the user selection, the second stacked bar graph representing the numerical physical characteristic of a lower hierarchy of said circuit element.

25) The computer-aided circuit analysis tool of claim 17, a user input receiver that receives an indication that a user has selected a portion of the displayed text description;
wherein the stacked bar graph window generator causes to be displayed a stacked bar graph that is traceable to the selected portion of the text description in accordance with the selection of the user.

-84h-

26) A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising:
a parse tree generator (6018) generating a parse tree (6004), stored in a memory of the system, in accordance with the text description (6003), said parsetree including a parse tree node that relates a portion of the text description to the parse tree node;
a digital circuit representation generator (6019) generating a digital circuit representation, stored in the memory, the digital circuit representation synthesized from said parse tree and including a circuit element, said circuit element referring to said parse tree node, so that there is a traceable path between the circuit element and the parse tree node; and a path browser window display generator (Fig. 51), causing a path browser summary to be displayed on a display screen, the path browser summary representing a representation of said circuit element, stored in the memory.

27) The computer-aided circuit analysis tool of claim 26, wherein the circuit representation is a Gtech circuit representation.

28) The computer-aided circuit analysis tool of claim 26, wherein the circuit representation is a gate level circuit representation.

29) The computer-aided circuit analysis tool of claim 26, further -84i-comprising:
a text window display generator, causing a portion of the text description that is traceable to the circuit representation to be displayed with a predetermined physical property.

30) The computer-aided circuit analysis tool of claim 29, wherein the entire portion of the text description that is traceable to the circuit representation is displayed with the predetermined physical property.

31) The computer-aided circuit analysis tool of claim 29, further comprising:
a user input receiver that receives an indication that a user has selected a portion of the path browser summary;
wherein the text window display generator causes a portion of the text description that is traceable to the selected portion of the path browser summary to be displayed with a predetermined physical property in accordance with the user selection.

32) The computer-aided circuit analysis tool of claim 26, further comprising a user input receiver that receives an indication that a user has selected a portion of the path browser summary, and wherein the path browser window display generator causes display of a different hierarchical level of the path browser summary in accordance with the user selection.

-84j-

33) The computer-aided circuit analysis tool of claim 26, a user input receiver that receives an indication that a user has selected a portion of the displayed text description;
wherein the path browser window generator causes to be displayed a path browser summary that is traceable to the selected portion of the text description in accordance with the selection of the user.

34) The computer-aided circuit analysis tool of claim 26, further comprising:
a user input receiver that receives an indication that a user has indicated a "start/end" path in the circuit representation;
a text window display generator, causing a portion of the text description that is traceable to the start/end path to be displayed with a predetermined physical property.

-84k-

35) A computer-aided circuit analysis tool for analyzing a text description of adigital system written in a circuit design language, comprising:
a parse tree generator (6018) generating a parse tree (6004), stored in a memory of the system, in accordance with the text description (6003), said parsetree including a parse tree node that relates a portion of the text description to the parse tree node;
a digital circuit representation generator (6019) generating a digital circuit representation, stored in the memory, the digital circuit representation synthesized from said parse tree and including a circuit element, said circuit element referring to said parse tree node, so that there is a traceable path between the circuit element and the parse tree node; and a virtual schematic window generator (Fig. 48), causing a virtual schematic to be displayed on a display screen, the virtual schematic representing fanins and fanouts of a user-selected portion of the circuit representation.

36) The computer-aided circuit analysis tool of claim 35, further comprising:
a text window display generator, causing a portion of the text description that is traceable to one of the fan ins and fanouts of the selection portion of the circuit representation to be displayed with a predetermined physical property.

37) The computer-aided circuit analysis tool of claim 36, wherein the entire portion of the text description that is traceable to the circuit representation is displayed with the predetermined physical property.

38) The computer-aided analysis tool of claim 36, further comprising:
a user input receiver that receives an indication that a user has selected a displayed fanin or fanout.
wherein the text window display generator causes a portion of the text description that is traceable to the selected portion of the fanin or fanout to be displayed with a predetermined physical property in accordance with the user selection.

39) The computer-aided circuit analysis tool of claim 36, a user input receiver that receives an indication that a user has selected a portion of the displayed text description;
wherein the virtual schematic window generator causes to be displayed a portion of the circuit representation, along with its fanins and fanouts that istraceable to the selected portion of the text description in accordance with theselection of the user.

-84m-

40) A computer-aided circuit analysis tool for analyzing a text description of a digital system written in a circuit design language, comprising:
a memory storing:
a) a parse tree (6111-6115), stored in a memory of the system, in accordance with the text description, said parse tree including a parse tree node that relates a portion of the text description to the parse tree node, and b) at least one digital circuit representation (6130-6186), stored in the memory, the at least one digital circuit representation synthesized from said parse tree and including a circuit element (6140), said circuit element referring to said parse tree node, the at least one circuit representation being stored in one or more different circuit domains;
a plurality of analysis tools (5470, 5480), each analysis tool capable of performing analysis on one or more of said circuit domains;
a plurality of display tools (5430, 5440), each display tool capable of displaying data from one or more circuit domains;
a domain mapper (5450), capable of mapping between ones of the plurality of circuit domains; and a selection manager (5460) that informs the plurality of display tools when a user has selected a displayed element of the circuit representation within a one of the display tools.