CA2194695C - A direct conversion receiver - Google Patents
A direct conversion receiver Download PDFInfo
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- CA2194695C CA2194695C CA002194695A CA2194695A CA2194695C CA 2194695 C CA2194695 C CA 2194695C CA 002194695 A CA002194695 A CA 002194695A CA 2194695 A CA2194695 A CA 2194695A CA 2194695 C CA2194695 C CA 2194695C
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/233—Demodulator circuits; Receiver circuits using non-coherent demodulation
- H04L27/2332—Demodulator circuits; Receiver circuits using non-coherent demodulation using a non-coherent carrier
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/30—Circuits for homodyne or synchrodyne receivers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
- H03D3/007—Demodulation of angle-, frequency- or phase- modulated oscillations by converting the oscillations into two quadrature related signals
Abstract
The receiver includes input means comprising an antenna and blocking filter, the output of which is connected to an amplifier. The input signal is split and mixed with an in-phase and quadrature phase signal generated by an oscillator in a mixer circuit, respectively. An output from each mixer circuit is applied to a low pass filter and to an input of a limiting circuit. The output from each low pass filter is applied to an input of a summator circuit respectively, a first of which is arranged to sum the in-phase and quadrature phase signals, and the second of which is arranged to subtract the in-phase and quadrature phase signals to generate a respective output signal having an axis intermediate of the in-phase and quadrature phase signal axes. These signals, together with the in-phase and quadrature phase signals are passed through a limiting circuit respectively, to a decoder circuit for recovering the data. The output of the limiting circuits represents signals quantised to eight possible phase states separated by 45~. When the input signal is GFSK
modulated the vector will always cross at least one axis, so the direction of rotation can be established prior to data recovery. In an alternative embodiment a ratiometric combiner may be used instead of the summator circuits, and this is particularly useful for .pi./4-DQPSK modulation, where the phase excursion per symbol is ~ 45~ or ~ 135~ depending upon the bit pair combination, and in this embodiment a minimum of eight axes are generated giving sixteen sectors and 22.5~ phase resolution.
modulated the vector will always cross at least one axis, so the direction of rotation can be established prior to data recovery. In an alternative embodiment a ratiometric combiner may be used instead of the summator circuits, and this is particularly useful for .pi./4-DQPSK modulation, where the phase excursion per symbol is ~ 45~ or ~ 135~ depending upon the bit pair combination, and in this embodiment a minimum of eight axes are generated giving sixteen sectors and 22.5~ phase resolution.
Description
WO 96136104 ~ ~ ~ (~ ~ C~ i~ PCTIGB95101058 i A DIRECT CONVERSION RECEIVER
The present invention relates to a direct conversion receiver for use in radio systems.
It is known to use direct conversion in radio receivers which avoid the use of bulky and expensive bandpass IF filters. Also, the use of RF filters is considerably simplified and a complete receiver may be integrated onto a single chip.
In practice, one of the main obstacles to the successful implementationof direct conversion, the digital particularly in communicationsenvironment, is requirement automatic a for gain control (AGC}.In a direct conversion must be receiver, AGC
derived from makes it too baseband, slow for use which often with the bursted used in modern digital signals comtnoniy systems.
Referring to Figures 1 and Figure 1 shows an arrangement :?, which is often used in low data rate paging receivers and includes an antenna Z connected to an input of a blocking filter 4, the output of which is connected to an input of an amplifier 6. The output of the amplifier is applied to an input of a mixer 8, 10 respectively, which receive at a second input thereof, an output from an oscillator 12. The mixer 8 receives a signal which is at 0°
phase from the oscillator 12, and the mixer 10 receives a signal ~ which is at 90' phase from the oscillator I2. The outputs of the mixers 8 and 10 are applied respectively to an input of a low pass filter 14, 16, the output of which is applied to Iimiters 18, 20 respectively. The output from the limiter 18 is an in-phase signal SUBSTITUTE SHEET (RULE 26) w0 96136104 ~ ~ ~ ~ ~ ~ h PCTIGB951010.58 I, and the output from the limiter 20 is a quadrature phase signal Q. The circuit thus described does not require any AGC. , If the inputs of the receiver is a frequency shift keyed (FSK}
signal, it may be represented vectorialIy as shown in Figure 2.
The left hand diagram of Figure 2 shows that the input can have any phase angle, whereas the output, after hard limiting, the I and Q signals are quantised to any four possible phase states, as Shawn in the right hand diagram of Figure 2.
In order to demodulate the FSK modulation, it is necessary to establish the direction of rotation of the vector. This is straight forward in paging systems where the modulation index is high, since the vector will rotate several cycles for each data bit. The limited I and Q output signals then become a burst of square waves at 90° to each other, either leading or lagging, depending upon the direction of rotation. By comparing the limited I and Q
signals in a phase sensitive detector (e.g. a D-Type flip-flop}, the polarity of the phase difference, and hence modulation can be recovered.
However, in more spectrally efficient, low modulation index schemes such as Ganssian frequency shift keying {GFSK), the vector can rotate as little as 50° per data bit. This means that the vector can remain entirely within oae quadrant, so there is no change at the limner outputs. In this case the data is not recoverable.
An aim of the present invention is to provide a direct ' conversion receiver for use with phase modulation signals, which does not require AGC.
SUBST1T1JTE SFiE~T (RULE 26y According to one aspect of the present invention there is provided a direct conversion receiver comprising:
means for receiving an input signal transmitted across a radio medium and represented by a vector; means for generating in-s phase and quadrature phase signals from the received input signal; means for generating in-phase and quadrature phase output signals in the form of first bursts of hard-limited signals; circuit means arranged to generate additional axes intermediate to axes of the in-phase and quadrature phase signals, from which additional axes second bursts of hard-limited signals are generated; and a decoder circuit arranged to receive the first and second bursts of hard-limited signals and to generate data corresponding to the received input signal; wherein the decoder circuit comprises: a combination logic circuit arranged to receive said first and second bursts of hard-limited signals, and to give a sector output value from zero to seven, when four axes are used, representing a phase sector in which the received input signal instantaneously resides; and means for subtracting a previous sector output value from a present sector output value to generate a series of pulses dependent upon a direction of rotation of the vector.
According to another aspect of the present invention there is provided a direct conversion receiver comprising:
means for receiving an input signal transmitted across a radio medium and represented by a vector; means for generating in-phase and quadrature phase signals from the received input signal; means for generating in-phase and quadrature phase output signals in the form of first bursts of hard-limited signals; circuit means arranged to generate additional axes intermediate to axes of the in-phase and quadrature phase signals, from which additional axes second bursts of hard-limited signals are generated; and a decoder circuit arranged to receive the first and second bursts of hard-limited signals -3a-and to generate data corresponding to the received input signal: wherein the circuit means comprises a ratiometric combiner arranged to generate eight axes intermediate of the in-phase and quadrature phase signal axes; output signals from the ratiometric combiner, and the in-phase and quadrature phase signals are applied to respective limiting circuits, output signals from which are applied to an input of the decoder circuit respectively: and the decoder circuit includes: input logic means arranged to receive the output signals from the respective limiting circuits and arranged to generate a sector output signal in the range of 0 to 15, when eight axes are used; and means for subtracting a previous sector output signal from a present sector output signal in order to generate a series of output data pulses.
Various embodiments of the present invention will now be described with reference to the accompanying drawings, wherein FIGURE 3 shows a direct conversion receiver using four limiters, FIGURE 4 shows the vector signal representation in a four axes receiver, w0 96136104 G PC1'1GB95101058 FIGURE 5 shows a block diagram of an FSK decoder, FIGURE 6 shows a block diagram of a direct conversion , receiver using 'n' Iimiters, and, FIGURE 7 shows a block diagram of a iI !4-DQPSK ' (differential quadrature phase shift keyed) decoder.
Referring to Figure 3, there is shown a block diaa am of a direct conversion receiver using four limiters. The receiver as shown overcomes the drawback mentioned with respect to the prior art by effectively introducing additional axes, intermediate to the axes of the in-phase I and quadrature phase Q signals. The simplest realisation of this is to add two additional axes at 45° and 135°, by taking the sum and difference of the in-phase I and quadrature phase Q signais, and hard limiting the two new signals designated A and B, as shown in the drawing. The receiver comprises an antenna 22 connected to a blocking filter 24, the output of which is applied to an amplifier 26. The output of the amplifier is applied to a first input of a mixer circuit 28, 30 respectively. The mixer circuit 28 receives an in-phase signal i from an oscillator 32, and the mixer circuit 30 receives a quadrature phase signal Q from an oscillator 32. An output from each mixer circuit d8, 30 is applied to an input of a iow pass filter 34, 36 respectively. The output of the filter 34 represents the in-phase signal and is applied to an input of a limiter 42, an input of a summator circuit 38, and to an input of a summator circuit 40.
Sunilarly the output of the filter 36 which represents the ' quadrature phase signal, is applied to an input of a Iimiter 48, a further input of summator 40 and to a further input of the SUBSTITUT~ SH~ET(RULE?6) summator 38. The summator 38 generates an output signal A
which is the summation of the two input signals, and the summator 40 generates an output signal B which is the difference of the two input signals. The output of the summator 38 is applies to a limiter 44, and the output of the summator 40 is applied to an input of a limiter 46. Each of the limiters 42-48 generate an output signal which is applied to a deco~~er 50 from which an output data signal is generated on an output line 52.
The vector diagram in relation to Figure 3 is shown in Figure 4. With four axes there are now eight sectors, and the hard limited signals effectively represent the signals quantised to eight possible phase states, separated by 45°.
When the input signal is a GFSK modulated signal, the vector will now always cross at least one axis, so the direction of rotation can be established and the data recovered.
With reference to Figure 4, the left hand diagram shows that the input signal can have any phase angle, and the right hand diagram shows that after hard limiting the output is quantised to eight possible phase states.
The decoding of the data may be achieved digitally from the binary signals at the outputs of the limiters 42-48 in Figure 3, and the decoding is shown with reference to Figure 5.
Figure 5 shows an FSK decoder comprising combinational logic circuit 54 which receives the I, A, B and Q inputs from the limiters 42-48 in Figure 3. The output of the combinational logic circuit is connected to an input of a delay circuit 56 and to the input of a summator circuit W09Gl36104 , ~ PCTfGB9510i058 58. The output of the delay circuit 56 is connected to a further , input of the sumtnator circuit 5$. The output of the summator circuit 58 is connected to an input of an averaging circuit 60, the ' output of which is applied to a hard limiter 62 from which data is output on an output line 64.
The simple combinationaI logic may be used to give a binary sector output from 0 to 7 representing the phase sector in which the signal instantaneously resides. By subtracting the pree~iaus sector value from the present sector value (modulo-8 arithmetic), a series of pulses is obtained which are either positive of negative, depending upon the direction of rotation. Effectively, a sampled frequency discriminator is farmed. To avoid aliassing, the delay element should be less than half a bit period. The puise train is then averaged in the circuit 60 and Limited by the circuit 6? to extract the data.
Tn modulation schemes where the phase excursion per bit is even less (such as >t/4-DQPSK or GFSK with a very la4v BT factor where B is the bandwidth of the modulation filter and T is the bit period), the technique can be expanded by introducing mare axes, hence improving the phase resolution. This concept is Shawn in Figure 6.
Referring to Figure 6, a further embodiment of the present invention will now be described, and shows a direct conversion receiver using 'n' limiters.
The receiver comprises antenna 66 which feeds an ItF filter 68, the output of which is connected to an input of an amplifier 70. The output of the amplifier is applied to the input of a mixer SUBSTtTUT~ 5H~~T (RULE 26) WO96/36104 ~ 19 4 D l ~ PCTIGB95/01058 _7-circuit 72 and to an input of a mixer circuit 74, The second inputs of the mixer circuits 72, 74 receive an output from an oscillator 76 in the form of an in-phase signal applied to the mixer circuit 72, and a quadrature phase signal applied to the mixer circuit 74. An output of the mixer circuit 72 is applied to a low pass filter 78, and similarly the output of the mixer circuit 74 is applied a low pass filter 80. The outputs of the filters 78, 80 are each applied to ratiometric combiner 82 respectively, and to an input of a limiter 84 and a limiter 92, respectively. The ratiometric cambiner 82 generates a number of output signals, each of which is applied to an input of a limiter 86-90 respectively. An output from each limner is applied to an input to a decoder circuit 94 which is arranged to generate an output signal on an output line 96.
In a/4-DQPSK modulation, the phase excursion per symbol is ~ 45° or ~ 135° depending on the bit pair combination (00, Ol, or 11 ). In the receiver the arrangement as shown in Figure 6, a minimum of eight axes (and eight Iimiters) would therefore be required giving sixteen sectors and 22.5° phase resolution. The decoding would also change slightly from the FSK version, since three decision thresholds evould be needed to detect the magnitude as well as the polarity of the phase shift. The decoder is shown in Figure 7.
Referring to Figure 7> a decoder circuit comprises a logic circuit 98 which receives the input signals from the limiter circuits 84-92 (Figure 6). An output from the logic circuit is applied to the input of a summator circuit 1()2 and to input of a delay circuit 100. An output from the delay circuit 100 is SUBSTITUTE SHEET (RULE 26) WO 96136104 . ~, ~ ~ PCTIGB9510I05$
_$_ connected to a further input of the summator circuit 102. An , output from the summator circuit 102 is connected to an input of an averaging circuit 104, the output of which is applied to three ' threshold devices 106> 108, 110, which are arranged to compare the output of the averaging circuit 104 with a threshold signal applied to a second input thereof. The output of each threshold circuit 106-110 is applied to an input of a logic circuit 112, respectively> which is arranged to generate an output data bit on an output line 114, and an output line 116.
It will be appreciated by those skilled in the art that variations and modifications are possible within the scope of the following claims. The receiver is primarily aimed at phase ar frequency modulation schemes. However, it will be appreciated that in systems where the envelope variation must be preserved (e.g. for equalisation), the signal envelope could be obtained from the Iimiter received signal strength indicator ( RSSI) outputs. As this would be a log-compressed envelope, an anti-log function would be needed to restore the linear amplitude v ariation.
SUB531TUTE SH~~T (RULE 26}
The present invention relates to a direct conversion receiver for use in radio systems.
It is known to use direct conversion in radio receivers which avoid the use of bulky and expensive bandpass IF filters. Also, the use of RF filters is considerably simplified and a complete receiver may be integrated onto a single chip.
In practice, one of the main obstacles to the successful implementationof direct conversion, the digital particularly in communicationsenvironment, is requirement automatic a for gain control (AGC}.In a direct conversion must be receiver, AGC
derived from makes it too baseband, slow for use which often with the bursted used in modern digital signals comtnoniy systems.
Referring to Figures 1 and Figure 1 shows an arrangement :?, which is often used in low data rate paging receivers and includes an antenna Z connected to an input of a blocking filter 4, the output of which is connected to an input of an amplifier 6. The output of the amplifier is applied to an input of a mixer 8, 10 respectively, which receive at a second input thereof, an output from an oscillator 12. The mixer 8 receives a signal which is at 0°
phase from the oscillator 12, and the mixer 10 receives a signal ~ which is at 90' phase from the oscillator I2. The outputs of the mixers 8 and 10 are applied respectively to an input of a low pass filter 14, 16, the output of which is applied to Iimiters 18, 20 respectively. The output from the limiter 18 is an in-phase signal SUBSTITUTE SHEET (RULE 26) w0 96136104 ~ ~ ~ ~ ~ ~ h PCTIGB951010.58 I, and the output from the limiter 20 is a quadrature phase signal Q. The circuit thus described does not require any AGC. , If the inputs of the receiver is a frequency shift keyed (FSK}
signal, it may be represented vectorialIy as shown in Figure 2.
The left hand diagram of Figure 2 shows that the input can have any phase angle, whereas the output, after hard limiting, the I and Q signals are quantised to any four possible phase states, as Shawn in the right hand diagram of Figure 2.
In order to demodulate the FSK modulation, it is necessary to establish the direction of rotation of the vector. This is straight forward in paging systems where the modulation index is high, since the vector will rotate several cycles for each data bit. The limited I and Q output signals then become a burst of square waves at 90° to each other, either leading or lagging, depending upon the direction of rotation. By comparing the limited I and Q
signals in a phase sensitive detector (e.g. a D-Type flip-flop}, the polarity of the phase difference, and hence modulation can be recovered.
However, in more spectrally efficient, low modulation index schemes such as Ganssian frequency shift keying {GFSK), the vector can rotate as little as 50° per data bit. This means that the vector can remain entirely within oae quadrant, so there is no change at the limner outputs. In this case the data is not recoverable.
An aim of the present invention is to provide a direct ' conversion receiver for use with phase modulation signals, which does not require AGC.
SUBST1T1JTE SFiE~T (RULE 26y According to one aspect of the present invention there is provided a direct conversion receiver comprising:
means for receiving an input signal transmitted across a radio medium and represented by a vector; means for generating in-s phase and quadrature phase signals from the received input signal; means for generating in-phase and quadrature phase output signals in the form of first bursts of hard-limited signals; circuit means arranged to generate additional axes intermediate to axes of the in-phase and quadrature phase signals, from which additional axes second bursts of hard-limited signals are generated; and a decoder circuit arranged to receive the first and second bursts of hard-limited signals and to generate data corresponding to the received input signal; wherein the decoder circuit comprises: a combination logic circuit arranged to receive said first and second bursts of hard-limited signals, and to give a sector output value from zero to seven, when four axes are used, representing a phase sector in which the received input signal instantaneously resides; and means for subtracting a previous sector output value from a present sector output value to generate a series of pulses dependent upon a direction of rotation of the vector.
According to another aspect of the present invention there is provided a direct conversion receiver comprising:
means for receiving an input signal transmitted across a radio medium and represented by a vector; means for generating in-phase and quadrature phase signals from the received input signal; means for generating in-phase and quadrature phase output signals in the form of first bursts of hard-limited signals; circuit means arranged to generate additional axes intermediate to axes of the in-phase and quadrature phase signals, from which additional axes second bursts of hard-limited signals are generated; and a decoder circuit arranged to receive the first and second bursts of hard-limited signals -3a-and to generate data corresponding to the received input signal: wherein the circuit means comprises a ratiometric combiner arranged to generate eight axes intermediate of the in-phase and quadrature phase signal axes; output signals from the ratiometric combiner, and the in-phase and quadrature phase signals are applied to respective limiting circuits, output signals from which are applied to an input of the decoder circuit respectively: and the decoder circuit includes: input logic means arranged to receive the output signals from the respective limiting circuits and arranged to generate a sector output signal in the range of 0 to 15, when eight axes are used; and means for subtracting a previous sector output signal from a present sector output signal in order to generate a series of output data pulses.
Various embodiments of the present invention will now be described with reference to the accompanying drawings, wherein FIGURE 3 shows a direct conversion receiver using four limiters, FIGURE 4 shows the vector signal representation in a four axes receiver, w0 96136104 G PC1'1GB95101058 FIGURE 5 shows a block diagram of an FSK decoder, FIGURE 6 shows a block diagram of a direct conversion , receiver using 'n' Iimiters, and, FIGURE 7 shows a block diagram of a iI !4-DQPSK ' (differential quadrature phase shift keyed) decoder.
Referring to Figure 3, there is shown a block diaa am of a direct conversion receiver using four limiters. The receiver as shown overcomes the drawback mentioned with respect to the prior art by effectively introducing additional axes, intermediate to the axes of the in-phase I and quadrature phase Q signals. The simplest realisation of this is to add two additional axes at 45° and 135°, by taking the sum and difference of the in-phase I and quadrature phase Q signais, and hard limiting the two new signals designated A and B, as shown in the drawing. The receiver comprises an antenna 22 connected to a blocking filter 24, the output of which is applied to an amplifier 26. The output of the amplifier is applied to a first input of a mixer circuit 28, 30 respectively. The mixer circuit 28 receives an in-phase signal i from an oscillator 32, and the mixer circuit 30 receives a quadrature phase signal Q from an oscillator 32. An output from each mixer circuit d8, 30 is applied to an input of a iow pass filter 34, 36 respectively. The output of the filter 34 represents the in-phase signal and is applied to an input of a limiter 42, an input of a summator circuit 38, and to an input of a summator circuit 40.
Sunilarly the output of the filter 36 which represents the ' quadrature phase signal, is applied to an input of a Iimiter 48, a further input of summator 40 and to a further input of the SUBSTITUT~ SH~ET(RULE?6) summator 38. The summator 38 generates an output signal A
which is the summation of the two input signals, and the summator 40 generates an output signal B which is the difference of the two input signals. The output of the summator 38 is applies to a limiter 44, and the output of the summator 40 is applied to an input of a limiter 46. Each of the limiters 42-48 generate an output signal which is applied to a deco~~er 50 from which an output data signal is generated on an output line 52.
The vector diagram in relation to Figure 3 is shown in Figure 4. With four axes there are now eight sectors, and the hard limited signals effectively represent the signals quantised to eight possible phase states, separated by 45°.
When the input signal is a GFSK modulated signal, the vector will now always cross at least one axis, so the direction of rotation can be established and the data recovered.
With reference to Figure 4, the left hand diagram shows that the input signal can have any phase angle, and the right hand diagram shows that after hard limiting the output is quantised to eight possible phase states.
The decoding of the data may be achieved digitally from the binary signals at the outputs of the limiters 42-48 in Figure 3, and the decoding is shown with reference to Figure 5.
Figure 5 shows an FSK decoder comprising combinational logic circuit 54 which receives the I, A, B and Q inputs from the limiters 42-48 in Figure 3. The output of the combinational logic circuit is connected to an input of a delay circuit 56 and to the input of a summator circuit W09Gl36104 , ~ PCTfGB9510i058 58. The output of the delay circuit 56 is connected to a further , input of the sumtnator circuit 5$. The output of the summator circuit 58 is connected to an input of an averaging circuit 60, the ' output of which is applied to a hard limiter 62 from which data is output on an output line 64.
The simple combinationaI logic may be used to give a binary sector output from 0 to 7 representing the phase sector in which the signal instantaneously resides. By subtracting the pree~iaus sector value from the present sector value (modulo-8 arithmetic), a series of pulses is obtained which are either positive of negative, depending upon the direction of rotation. Effectively, a sampled frequency discriminator is farmed. To avoid aliassing, the delay element should be less than half a bit period. The puise train is then averaged in the circuit 60 and Limited by the circuit 6? to extract the data.
Tn modulation schemes where the phase excursion per bit is even less (such as >t/4-DQPSK or GFSK with a very la4v BT factor where B is the bandwidth of the modulation filter and T is the bit period), the technique can be expanded by introducing mare axes, hence improving the phase resolution. This concept is Shawn in Figure 6.
Referring to Figure 6, a further embodiment of the present invention will now be described, and shows a direct conversion receiver using 'n' limiters.
The receiver comprises antenna 66 which feeds an ItF filter 68, the output of which is connected to an input of an amplifier 70. The output of the amplifier is applied to the input of a mixer SUBSTtTUT~ 5H~~T (RULE 26) WO96/36104 ~ 19 4 D l ~ PCTIGB95/01058 _7-circuit 72 and to an input of a mixer circuit 74, The second inputs of the mixer circuits 72, 74 receive an output from an oscillator 76 in the form of an in-phase signal applied to the mixer circuit 72, and a quadrature phase signal applied to the mixer circuit 74. An output of the mixer circuit 72 is applied to a low pass filter 78, and similarly the output of the mixer circuit 74 is applied a low pass filter 80. The outputs of the filters 78, 80 are each applied to ratiometric combiner 82 respectively, and to an input of a limiter 84 and a limiter 92, respectively. The ratiometric cambiner 82 generates a number of output signals, each of which is applied to an input of a limiter 86-90 respectively. An output from each limner is applied to an input to a decoder circuit 94 which is arranged to generate an output signal on an output line 96.
In a/4-DQPSK modulation, the phase excursion per symbol is ~ 45° or ~ 135° depending on the bit pair combination (00, Ol, or 11 ). In the receiver the arrangement as shown in Figure 6, a minimum of eight axes (and eight Iimiters) would therefore be required giving sixteen sectors and 22.5° phase resolution. The decoding would also change slightly from the FSK version, since three decision thresholds evould be needed to detect the magnitude as well as the polarity of the phase shift. The decoder is shown in Figure 7.
Referring to Figure 7> a decoder circuit comprises a logic circuit 98 which receives the input signals from the limiter circuits 84-92 (Figure 6). An output from the logic circuit is applied to the input of a summator circuit 1()2 and to input of a delay circuit 100. An output from the delay circuit 100 is SUBSTITUTE SHEET (RULE 26) WO 96136104 . ~, ~ ~ PCTIGB9510I05$
_$_ connected to a further input of the summator circuit 102. An , output from the summator circuit 102 is connected to an input of an averaging circuit 104, the output of which is applied to three ' threshold devices 106> 108, 110, which are arranged to compare the output of the averaging circuit 104 with a threshold signal applied to a second input thereof. The output of each threshold circuit 106-110 is applied to an input of a logic circuit 112, respectively> which is arranged to generate an output data bit on an output line 114, and an output line 116.
It will be appreciated by those skilled in the art that variations and modifications are possible within the scope of the following claims. The receiver is primarily aimed at phase ar frequency modulation schemes. However, it will be appreciated that in systems where the envelope variation must be preserved (e.g. for equalisation), the signal envelope could be obtained from the Iimiter received signal strength indicator ( RSSI) outputs. As this would be a log-compressed envelope, an anti-log function would be needed to restore the linear amplitude v ariation.
SUB531TUTE SH~~T (RULE 26}
Claims (4)
1. A direct conversion receiver comprising:
means for receiving an input signal transmitted across a radio medium and represented by a vector;
means for generating in-phase and quadrature phase signals from the received input signal;
means for generating in-phase and quadrature phase output signals in the form of first bursts of hard-limited signals;
circuit means arranged to generate additional axes intermediate to axes of the in-phase and quadrature phase signals, from which additional axes second bursts of hard-limited signals are generated; and a decoder circuit arranged to receive the first and second bursts of hard-limited signals and to generate data corresponding to the received input signal; wherein the decoder circuit comprises:
a combination logic circuit arranged to receive said first and second bursts of hard-limited signals, and to give a sector output value from zero to seven, when four axes are used, representing a phase sector in which the received input signal instantaneously resides; and means for subtracting a previous sector output value from a present sector output value to generate a series of pulses dependent upon a direction of rotation of the vector.
means for receiving an input signal transmitted across a radio medium and represented by a vector;
means for generating in-phase and quadrature phase signals from the received input signal;
means for generating in-phase and quadrature phase output signals in the form of first bursts of hard-limited signals;
circuit means arranged to generate additional axes intermediate to axes of the in-phase and quadrature phase signals, from which additional axes second bursts of hard-limited signals are generated; and a decoder circuit arranged to receive the first and second bursts of hard-limited signals and to generate data corresponding to the received input signal; wherein the decoder circuit comprises:
a combination logic circuit arranged to receive said first and second bursts of hard-limited signals, and to give a sector output value from zero to seven, when four axes are used, representing a phase sector in which the received input signal instantaneously resides; and means for subtracting a previous sector output value from a present sector output value to generate a series of pulses dependent upon a direction of rotation of the vector.
2, A receiver as claimed in claim 1, wherein the series of pulses are applied to an averaging circuit and to a limiting circuit arranged to extract the data from said series of pulses.
3, A direct conversion receiver comprising:
means for receiving an input signal transmitted across a radio medium and represented by a vector;
means for generating in-phase and quadrature phase signals from the received input signal;
means for generating in-phase and quadrature phase output signals in the form of first bursts of hard-limited signals;
circuit means arranged to generate additional axes intermediate to axes of the in-phase and quadrature phase signals, from which additional axes second bursts of hard-limited signals are generated; and a decoder circuit arranged to receive the first and second bursts of hard-limited signals and to generate data corresponding to the received input signal; wherein the circuit means comprises a ratiometric combiner arranged to generate eight axes intermediate of the in-phase and quadrature phase signal axes;
output signals from the ratiometric combiner, and the in-phase and quadrature phase signals are applied to respective limiting circuits, output signals from which are applied to an input of the decoder circuit respectively; and the decoder circuit includes:
input logic means arranged to receive the output signals from the respective limiting circuits and arranged to generate a sector output signal in the range of 0 to 15, when eight axes are used; and means for subtracting a previous sector output signal from a present sector output signal in order to generate a series of output data pulses.
means for receiving an input signal transmitted across a radio medium and represented by a vector;
means for generating in-phase and quadrature phase signals from the received input signal;
means for generating in-phase and quadrature phase output signals in the form of first bursts of hard-limited signals;
circuit means arranged to generate additional axes intermediate to axes of the in-phase and quadrature phase signals, from which additional axes second bursts of hard-limited signals are generated; and a decoder circuit arranged to receive the first and second bursts of hard-limited signals and to generate data corresponding to the received input signal; wherein the circuit means comprises a ratiometric combiner arranged to generate eight axes intermediate of the in-phase and quadrature phase signal axes;
output signals from the ratiometric combiner, and the in-phase and quadrature phase signals are applied to respective limiting circuits, output signals from which are applied to an input of the decoder circuit respectively; and the decoder circuit includes:
input logic means arranged to receive the output signals from the respective limiting circuits and arranged to generate a sector output signal in the range of 0 to 15, when eight axes are used; and means for subtracting a previous sector output signal from a present sector output signal in order to generate a series of output data pulses.
4, A receiver as claimed in claim 3, wherein the series of output signals are applied to an averaging circuit, the output of which is applied to an input of three decision circuits respectively, and arranged to detect a magnitude and polarity of phase shift, an output of each decision circuit being connected to an output logic circuit arranged to generate data output signals on output data lines.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/GB1995/001058 WO1996036104A1 (en) | 1994-02-22 | 1995-05-10 | A direct conversion receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CA2194695A1 CA2194695A1 (en) | 1996-11-14 |
| CA2194695C true CA2194695C (en) | 2001-07-24 |
Family
ID=10768263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002194695A Expired - Fee Related CA2194695C (en) | 1995-05-10 | 1995-05-10 | A direct conversion receiver |
Country Status (12)
| Country | Link |
|---|---|
| US (1) | US5943370A (en) |
| EP (1) | EP0772905B1 (en) |
| JP (1) | JPH10504952A (en) |
| AU (1) | AU711257B2 (en) |
| CA (1) | CA2194695C (en) |
| DE (1) | DE69515312T2 (en) |
| DK (1) | DK0772905T3 (en) |
| FI (1) | FI970028A (en) |
| GB (1) | GB2286950B (en) |
| NO (1) | NO970095D0 (en) |
| TW (1) | TW269079B (en) |
| WO (1) | WO1996036104A1 (en) |
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-
1994
- 1994-02-22 GB GB9403318A patent/GB2286950B/en not_active Expired - Fee Related
-
1995
- 1995-05-10 AU AU24147/95A patent/AU711257B2/en not_active Ceased
- 1995-05-10 EP EP95918083A patent/EP0772905B1/en not_active Expired - Lifetime
- 1995-05-10 US US08/765,686 patent/US5943370A/en not_active Expired - Fee Related
- 1995-05-10 DK DK95918083T patent/DK0772905T3/en active
- 1995-05-10 CA CA002194695A patent/CA2194695C/en not_active Expired - Fee Related
- 1995-05-10 JP JP8533843A patent/JPH10504952A/en active Pending
- 1995-05-10 WO PCT/GB1995/001058 patent/WO1996036104A1/en active IP Right Grant
- 1995-05-10 DE DE69515312T patent/DE69515312T2/en not_active Expired - Fee Related
- 1995-05-16 TW TW084104904A patent/TW269079B/zh active
-
1997
- 1997-01-03 FI FI970028A patent/FI970028A/en unknown
- 1997-01-09 NO NO970095A patent/NO970095D0/en not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| CA2194695A1 (en) | 1996-11-14 |
| NO970095L (en) | 1997-01-09 |
| TW269079B (en) | 1996-01-21 |
| AU711257B2 (en) | 1999-10-07 |
| DK0772905T3 (en) | 2000-06-05 |
| EP0772905A1 (en) | 1997-05-14 |
| JPH10504952A (en) | 1998-05-12 |
| NO970095D0 (en) | 1997-01-09 |
| AU2414795A (en) | 1996-11-29 |
| DE69515312T2 (en) | 2000-06-21 |
| GB2286950B (en) | 1998-06-17 |
| DE69515312D1 (en) | 2000-04-06 |
| US5943370A (en) | 1999-08-24 |
| GB9403318D0 (en) | 1994-04-13 |
| FI970028A0 (en) | 1997-01-03 |
| WO1996036104A1 (en) | 1996-11-14 |
| FI970028A (en) | 1997-01-10 |
| GB2286950A (en) | 1995-08-30 |
| EP0772905B1 (en) | 2000-03-01 |
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