CA2197221A1

CA2197221A1 - Programmable logic module and architecture for field programmable gate array device

Info

Publication number: CA2197221A1
Application number: CA002197221A
Authority: CA
Inventors: Khaled A. El Ayat; Gregory W. Bakker; Jung-Cheun Lien; William C. Plants; Sinan Kaptanoglu; Runip Gopisetty; King W. Chan; Marko Chew
Original assignee: Individual
Current assignee: Microsemi SoC Corp
Priority date: 1994-12-28
Filing date: 1995-10-27
Publication date: 1996-07-04
Also published as: US5606267A; AU4405196A; KR100252614B1; EP0800723A1; US5477165A; US5698992A; WO1996020534A1; JPH10507605A

Abstract

A user-programmable gate array architecture includes an array of logic function modules which may comprise one or more combinatorial and/or sequential logic circuits. An interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each including a plurality of interconnect conductors some of which may be segmented, is imposed on the array. Individual ones of the interconnect conductors are connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements. A local interconnect architecture comprising local interconnect channels is also imposed on the array. Each local interconnect channel includes a plurality of local interconnect conductors and runs between pairs of adjacent ones of the logic function modules.

Description

~ W0 96/20534 ~ P~

, ~e F_ lElC~IlQ~I

PROGRAMMABLE LOGIC MODULE AND ARCHITECTURE
FOR FIELD PROGRAMMABLE GATE ARRAY DEVICE
pFI ~TEI~ APPLICATION DATA
10This a,, ' , is a continuation-in-part of co-pending a,, ' , serial No.
08/246,218, filed May 19, 1994, which is a continuation-in-part of co-pending application serial No. 08/002,873, filed January 13, 1993, which is a continuation of : p, " "~n serial No. 07/869.488, filed April 15, 199Z, now United States Patent No.
5,187, 393, which is a continuation of p, " ~ serial No. 07/621,452, filed January 1515, 1991, Now United States Patent No. 5,172,014, which is a divisional of nprl ' serial No. 07/309,306, filed February 10, 198g, now United States Patent No.
5,015,885, which is a continuation-in-part of application serial No. 06/909,261, filed September 19, 1986, now United States No. 4,758.745.
BACKQROUND OFTHE INVENTION
20 1. Field Of The Invention The present invention relates to p,~,y,d",l"at~le integrated circuits. More particularly, the present invention relates to a p,uy,a,,,,l,dble logic module and architecture for use in integrated circuits such as field programmable gate array ... _ .. , . .. . , ..... , .. .. . _ .. .. , ., .. , _ . , .

WO 96120534 ' ~ PCTIUS95/13891~
2197221 ' integrated circuits.

2.The Prior Art Recent advances in user-l ,uy,d,,,l,,able interconnect technology have resulted in the development of field programmable gate array (FPGA) integrated circuits which 5 may be cllctnrr i~~d by a user to perform a wide variety of co"lbi,ldtio"al and sequential logic functions. Numerous architectures for such integrated circuits are known. Examples of such architectures are found disclosed in U.S. Patents 4 870 302 to Freeman 4 758 745 to El Gamal et al. and 5 132 571 to McCollum et al. The architecture employed in a particular FPGA integrated circuit will determine the 10 richness and the density of the possible i"~ on"e. Iio"s which can be made among the various circuit elements disposed on the integrated circuit and thus can profoundly affect its usefulness.

P,uylcll""ablt: logic blocks which are capable of performing a seiectable one of a plurality of user-selectable logic functions are known in the prior art and are 15 employed in FPGA architectures such as the ones cited above. U.S. Patent No.
4 910 417 to El Gamal et al. assigned to the same assignee as the present invention U.S. Patents Nos. 5 055 718 and 5 198 705 to Galbraith et al., and U.S. Patent No.
4 453 096 to Le Can et al. disclose logic modules composed of muitiplexers capable of performing a plurality of co",bi,-dlorial functions. U.S. Patent No. 4 541 067 to 20 Whittaker discloses how to perfomm different logic functions using different colllbil,c,tio~s of pass transistors.

While these circuits provide a degree of flexibility to the designer of user-!~ W0 96/20534 ~ g ~ PCI/US95/13891 uluyldllluldL)le logic arrays there is always a need for improvement of functionality of such circuits.

BRIEF DESCRIPTION OF THE INVENTION
The present invention relates to FPGA architectures and more specifically to 5 the core architecture of an FPGA integrated circuit including the functional circuit modules sometimes referred to as programmable logic modules and the i"ler on"ecl architecture which is used to define the functions of the u,uy,d,,,,,,able logic modules as well as the i"L~" o""eclio,ls between them.

A user-~,uy,d"""able gate array architecture according to the present invention 10 includes an array of logic function modules which may comprise one or more culllbil)dluridl and/or sequential logic circuits. An interconnect architecture cu",p,i~i"g a plurality of horizontal and vertical general interconnect channels each including a plurality of interconnect conductors some of which may be sey",e, ll~d is imposed on the array. Individual ones of the i"l~,-onlle~l conductors are c."",e ;ldLle to each 15 other and to the inputs and outputs of the logic function modules by user-p,Uy,d", "able interconnect elements. A local i"lu, u"ne l architecture colllpliainy local i"le" u"ne~ channels is also imposed on the array. Each local interconnect channel includes a plurality of local i~L~ u,,,,e-;l conductors and runs between two or more adjacent ones of the logic function modules.

20A programmable logic module according to a presently preferred ~Illbodi~

of the present invention comprises three function units. Each of the three functional W0 96/20534 ~ 1 9 7 2 2 1 ~ 3~

units may be selected from among at least a colllbil1dluricl unit and a sequential unit.

According to a presently preferred e",bodi",elll the co",L,indLu,idl unit for the u~uy,c"l",able logic module may comprise three multiplexers. A first two input multiplexer has a first data input connected to a first data input node, a second data 5 input connected to a second data input node a control input connected to the output of a first gate, and an output. The first gate has a first input connected to a first control input node and a second input connected to a second controi input node. A second two input multiplexer has a first data input connected to a third data input node, a second data input connected to a fourth data input node a controi input connected to 10 the output of the first gate and an output. A plurality of i,ILu~ u,,ne, 1 conductors intersect the first through fourth data input nodes and a user-p,u!J,a"""dule illtul~;o~l"e~l element is preferably disposed at each i"le,~e~lion to ailow p,u9,c,,,,,,,al,le conl1e~;liol1s to be made between selected ones of the iulerL;ollllecL
conductors and selected ones of the first through fourth data input nodes. One of the 15 plurality of i~ uu~ ecl conductors is connected to another one of the i~lu~uul1ne~
cûnductors through an inverter.

A third two input muLtiplexer has a first data input connected to the output of the first multiplexer a second data input connected to the output of the second multiplexer, a control input connected to the output of a second gate and an output. The output is 20 preferably buffered. The second gate has a first input connected to a third control input node and a second input connected to a fourth control input node.

~I W0 96120534 1 ~
~7221 According to a presently preferred embodiment of the invention, the sequential unit comprises three multiplexers and a D flip-flop, although other sequential logic circuits will also be usable. A first two input multiplexer has a first data input connected to a first data input node, a second data input connected to a second data input node, 5 a control input connected to a first control node, and an output. A second two input multiplexer has a first data input connected to the output of the first multiplexer, a second data input connected to the output of the D flip-flop, a control input connected to a second control node, and an output connected to the D input of the D flip-flop. A
first four input multiplexer has a first data input connected to a first clock input node, a 10 second data input connected to the c..~ lelllelli of the signal on the first data input node, a third data input connected to a second clock input node, a fourth data input connected to the complement of the signal on the second clock input node, first control input connected to a clock select node and a second control input connected to a clock polarity select node, and an output connected to the clock input of the D flip-flop.

1~ According to another aspect of the invention, the COIIIIJilldlOlidl unit for the ~ Jy,d"""able logic module may comprise a cascaded multiplexer architecture having a plurality of multiplexer planes, each of the multiplexer planes including at least one multiplexer having inputs, at least one control input connected to at least one input node and at least one output. At least one multiplexer in a first of the multipiexer 20 planes has inputs connected to input nodes and the inputs of at least one multiplexer in the multiplexer planes succeeding the first multiplexer plane is connected to the outputs of at least one multiplexer in the preceding multiplexer planes in the cascaded rnll~irleyar architecture. At least one multiplexer in a last of the multiplexer planes has 21~7221 WO 9v/20534 I
~ t at least one output connected to an output conductor which is preferably buffered. At least one inverter has its input connected to an input node and its output selectively connectable to individual ones of the input nodes by user-p,uy,dl,,,,,a~le i~ ;ulllle elements. The general cascaded multiplexer architecture for the cu,,,billdLori~:l unit is 5 more ~pe, ilically described in various aspects of the invention set forth below.

According to another aspect of the invention, the uulllbindloddl unit for the uluyldl,,n,abld logic module may comprise a multiplexer having a plurality of inputs connected to input nodes, at least one control input connected to an input node and an output connected to an output conductor which is preferably buffered. An inverter 10 has its input connected to an interconnect conductor and its output selectively co""ecldble to individual ones of the input nodes of the multiplexer by user-uluuldlllllldble i"l~uo""e~ elements.

According to another aspect of the invention, the culnlJilldlû~idl unit fûr the p~uyldlllll,able logic module may comprise a single two-input multiplexer. First two-15 input multiplexer has a first data input connected to a first data input node a seconddata input connected to a second data input node a control input connected to a control input node, and an output connected to an output buffer. An inverter has its input connected to an inverter input node and its output connected to inverter output node which intersects first and second data input nodes. First and second data input 2û nodes and the inverter input intersect horizontal i~le~,~ul,neul conductors in a general interconnect channel and a user-programmable i"l~,uol"~e~;l element is preferably disposed at each il,l~,:,e~liun to allow ulugldlllmdbld con,-e~ti(,ns to be made ~ W0 96/20!;34 2 ~ 9 ~ ~2 1 P ~

between selected ones of the horizontal interconnect conductors and the inverter output nodes and selected ones of the first and second data input nodes.

According to another aspect of the invention, the c~ lJilldlolidl unit for the ~,ug,d"""able logic module may comprise three two-input multiplexers. First two-5 input multiplexer has a first data input connected to a first data input node, a seconddata input connected to a second data input node, a control input connected to the output of a first gate, and an output. The first gate has a first input connected to a first control input node and a second input connected to a second control input node.
Second two-input multiplexer has a first data input connected to a third data input 10 node, a second data input connected to a fourth data input node, a control input connected to the output of the first gate, and an output. Third two-input multiplexer has a first data input connected to the output of first two-input multiplexer, a second data input connected to the output of second two-input multiplexer, a control input connected to the output of a second gate. and an output connected to an output buffer.
15 The second gate has a first input connected to a third control input node and a second input connected to a fourth control input node. An inverter has its input connected to an inverter input node and its output connected to inverter output node which intersects first through fourth data input nodes.

First through fourth data input nodes, first through fourth control input nodes and 20 the inverter input node intersect horizontal interconnect conductors in a general i~,le,~o""ecl channel and a user-programmable interconnect element is preferably disposed at each i,,le,~e~,L;un to allow ~rug~d~ able co""e,,lions to be made WO 96/20534 2 1 9 7 2 2 1 PCT/US95/13891 ~

f~ ;~; ': ',' ." ,~ . .

between selected ones of the horizontal i~ onne~l conductors and the inverter input node and selected ones of the first through fourth data input nodes and first through fourth control input nodes.

According to another aspect of the invention, the cu"lbi"alo,icl unit for the 5 plu~lGIllllldble logic module may comprise three two-input multiplexers and two two-input control multiplexers. First two-input multiplexer has a first data input connected to a first data input node, a second data input connected to a second data input node, a control input connected to the output of a first two-input control multiplexer and an output. Second two-input multiplexer has a first data input connected to a third data 10 input node, a second data input connected to a fourth data input node, a control input connected to the output of first two-input control multiplexer and an output. The first two-input control muitiplexer has an input connected to a first input control node, an inverting input connected to a second input control node and a control input connected to a first input control multiplexer node. Third two-input multiplexer has a first data 15 input connected to the output of first two-input multiplexer, a second data input connected to the output of second two-input multiplexer, a control input connected to the output of second two-input control multiplexer and an output connected to an output buffer. The second two-input control multiplexer has an inverting input connected to a third input control node, an input connected to a fourth input control 20 node and a control input connected to a second input control multiplexer node.

First through fourth data input nodes. first through fourth input control nodes and first and second input control multiplexer nodes intersect horizontal illt~ll,ùl)n~.;l ~ WO 96/20534 . PCT/US95/13891 ~9~2~1 conductors in a general interconnect channel and a user-l,,u~u,d,,,,,,able i,ll~" onne.;l element is preferably disposed at each il~ e~liun to allow programmable coll,le,liùns to be made between selected ones of the horizontal i,lL~ruollne.:l conductors and selected ones of the first through fourth data input nodes first through 5 fourth input control nodes and first and second input control multiplexer nodes.

According to another aspect of the invention the co,,ll)i,)alu, idl unit for the ylu~ldlllllldblu logic module may comprise seven two-input multiplexers. First through fourth two-input multiplexers each have first and second data inputs connected respectively to first through eighth data inputs nodes have outputs and each have a 10 control input connected to first input control node. Fifth and sixth two-input multiplexers each have first and second data inputs connected respectively to the outputs of first through fourth two-input multiplexers have outputs and have a control input connected to the output of a first gate. The first gate has a first input connected to a second control input node and a second input connected to a third control input 15 node. Seventh two-input multiplexer has a first data input connected to the output of fifth two-input multiplexer a second data input connected to the output of sixth two input multiplexer a control input connected to the output of a second gate and an output connected to an output buffer. The second gate has a first input connected to a fourth control input node and a second input connected to a fifth control input node.

A plurality of il~Lu~ onne~il conductors intersect the first through eighth data input nodes and a user-plug,d"",lable inle,~ù~ne~l element is preferably disposed at each i,llt:,:,e"liun to allow p,uu,dllll,,al)le co""e- Iions to be made between selected W096/20534 2197~21 ~I r r~

ones of the interconnect conductors and selected ones of the first through eighth data input nodes. One of the plurality of interconnect conductors is connected to another one of the interconnect conductors through an inverter. Ones of the plurality of interconnect conductors and the first through fifth control inputs intersect horizontal interconnect conductors in a general interconnect channel and a user-l,,uy,d"""able i~llel~olllle.,l elements is preferably disposed at each i"le,ae.:lioll to allow u,uy,d"""able col-neuliuns to be made between selected ones of the interconnect conductors and selected ones of the first through fifth control inputs.

According to another aspect of the invention, the combinatorial unit for the 1û y,uy,d"""dble logic module may comprise eight two-input multiplexers. First through fourth two-input multiplexers each has first and second data inputs connected respectively to first through eighth data inputs nodes, has outputs and each has a control input connected to first input control node. Fifth and sixth two-input multiplexers each has first and second data inputs connected respectively to the 1~ outputs of first through fourth two-input multiplexers, has outputs and each has a cûntrol input connected to the output ûf a first gate. The first gate has a first input connected to a second control input node and a second input connected to a third control input node. Seventh two-input multiplexer has a first data input connected to the output of fifth two-input multiplexer, a second data input connected to the output of 2û sixth two-input multiplexer, a control input connected to the output of a second gate, and an output. The second gate has a first input connected to a fourth control input node and a second input connected to a fifth control input node. Eighth two-input multiplexer has first and second data inputs connected to ninth and tenth data input 1û

~ W096120534 2~7~21 nodes a control input connected to the output of seventh two-bit multiplexer and an output connected to an output buffer.

A plurality of i"le,~ ~n,)ecl conductors intersect the first through tenth data input nodes and a user-p,uyld~ ai le i,lle,~o""e~il element is preferably disposed at each 5 i"lu,:,e~ lion to allow programmable cu~ e~ lions to be made between selected ones of the interconnect conductors and selected ones of the first through fourth data input nodes. First and second inverters connect one of the plurality of i, lleru-,""e. l conductors another of one of the plurality of i, llt:lUU~ e~l conductors. Ones of the plurality of i"lu~ on,)e~;l conductors and the first through fiRh control inputs intersect 10 horizontal i"l~,~ u""e, l conductors in a general i"lt:,.;u""e~l channel and a user-~,uy,d"""able i~ l u~ e~l element is preferably disposed at each i,~l~,ae.liu,) to allow u,uy,d",i"ai,l~ cc,~ne~;liu"s to be made between selected ones of the plurality of i,,lt,~;u,,,,e~;l conductors and seiected ones of the first through fiRh control inputs.

As previously noted it is presently preferred to combine three functional units 15 into a logic module. These three units may be identical i.e. the logic module may comprise three co",bi"dlulial units or three sequential units or may be mixed i.e. the logic module may comprise one c~lllbind~o~idl unit and two sequential units. In logic modules containing mixtures of cu",bi"ato,idl units and sequential units it may be advantageous to internally connect the prebuffered output of the co,,~billalulial unit to 20 one of the inputs of the first multiplexer of the sequential unit.

In a logic module architecture according to the present invention two or more W096120534 PCIIUS95/13891 ~
21~22~

logic modules as previously described may be combined with a plurality of local i,,L~,~;un,,ecl conductors as previously described. According to a presently preferred elllbod;~ of the invention the local il"~,cu,l"e~ L conductors are ac~oci~t~d with a pair of logic modules. The outputs of the six functional units cr,"",li~ing the pair of 5 logic modules are individually hardwired to different ones of the local interconnect conductors.

Selected ones of the inputs of the six function units cu~ uriaillg the two logic modules are u~uylalllll,ably connectable to selected ones of the local i~lLt"uol,necL
conductors. The interconnect conductors which intersect the input nodes of the 10 multiplexers of the culllLJilldLolidl units also intersect the local il,lt:l. unne. L conductors.
User-p,uy,d"""abl~ interconnect elements are disposed at the intersections of the interconnect conductors and the local iuL~l.;u",)t~ conductors to allow selective ulu~ldlllllldLJlt! interconnections to be made Lh~l~L t~L~ n.

In addition at least one of the inputs of at least one of the first and second gates 15 in the colllL,il1dlolidl units intersects the local i"Lt"~ u""eul conductors and may be u~uu~dlll",ably connected to individual ones thereof by user-programmable interconnect elements.

In a presently cullLt,llwldl~d embodiment of the invention an array of logic module pairs according to the present invention is disposed on an integrated circuit.
20 An architecture of i,,l~,~iu,,,,e~ l conductors is supe,i",uosed on the logic modules.

According to a presently preferred embodiment of the invention groups of generai ~j WO 96120534 , . i .
219~?2~

i"l~" o,1ne~l conductors run in both a horizontal and a vertical direction in proximity to the logic modules. As is known in the prior art these 5eneral illL~uu~ eul conductors may be segmented by user-u,uy,a,,,,,lable interconnect elements. User p~uy~d~ able interconnect elements may be disposed at selected i~ euliu,,s of the 5 horizontal and vertical general interconnect conductors and at the illle~e~;liol,s of the vertical general interconnect conductors and the local interconnect conductors. The general interconnect conductors are u,uyldllllllably connected to the data input nodes control input nodes and output nodes of the functional units in the logic modules.

BRIEF DESCRIPTION OFTHE DRAWINGS
1 û FIG. 1 is a simplified block diagram of a core architecture according to the present invention which may be employed in an FPGA integrated circuit.

FIG. 2A is a block/s~h~llla~i~ diagram of a presently preferred co",l,indlional functional unit according to the present invention showing a portion of the o""e, Liu" architecture of the present invention.

FIG. 2B is a table showing the output states of the co,,,bindlu,ial functional unit of FIG. 2A as a function of the states of the inputs.

FIG. 2C is a blocklschematic diagram of a presently preferred sequential functional unit according to the present invention showing a portion of the i"l~,~o"~eulion architecture of the present invention.

W0 96120534 ~ ,, ' PCIIUS9~113891 !~
2197~21 '' FIGS. 3A-3H are block/schematic diagrams of other exemplary co"~L,i"dliullal functional units which may be employed in FPGA architectures according to the present invention.

FIG. 4A is a block/schematic diagram of one presently preferred logic module 5 according to the present invention cu",~ i"g a combination of the functional units of FIGS. 2A and 2C.

FIGS. 4B-4D are schematic rt~ulusullldliulls of layout al,~"yu"~"L~ for logic function units within logic modules connected by local interconnect channels according to the present invention.

DETAII Fn DESCRIPTION OF A I~H~ ~t~H~I ~ EMBODIMFNT
Those of ordinary skill in the art will realize that the following dts~ ,liu" of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.

Referring first to FIG. 1 a simplified block diagram of an FPGA core architecture 1~ 10 according to the present invention is shown. As used herein the term core architecture~ refers to the architecture of the core of an FPGA array which comprises a plurality of logic function circuits or modules (reference numerals 12-1 to 12-12) arranged in a matrix with an overlay of i~iu~uu~nel l architecture including inlu,uo~nec conductors and user-p~uy~ lable interconnect elements. The logic function W096120534 2~9rl 22 ~ pCl'lUS95/13891 modules 12-1 through 12-12 may comprise any of a variety of circuits either co",bi,1dlio"al logic sequential logic or cu~binalions thereof and need not be identical as will be disclosed in more detail herein with respect to a presently preferred embodiment of the invention.

As shown in FIG. 1 logic function modules 12-1 through 12-12 are disposed in a network of i"le,~ o""e~ l conductors. In order to avoid over CGI11, ' '~ ,9 the figure and rendering it more difficult to c~ ltlh~l1d those of ordinary skill in the art will recognize that the network of interconnect conductors is shown in simplified schematic form. In addition while the drawing shows the i~ ;ol1l1e,~l conductors running 10 between the logic function circuits. those of ordinary skill in the art will readily recognize that the architecture may be a Usea of gates~ type architecture where the i"l~n o,1"e~l conductors actually run directly over rather than between the logic function circuits. In virtually all cases. the il ~ 1e~l conductors will comprise metal lines in layers disposed over the layers which constitute the logic function circuits.

Such a sea of gates architecture is known in the art and is t~ by U.S.
Patent No. ~ 132 571 to McCollum et al. and permits the fabrication of a more dense array than an architecture in which the interconnect conductors run only between the logic function circuits. While such a sea of gates arrangement is preferred those of ordinary skill in the art will recognize that the principles of the present invention apply 20 equally to both types of architectures as well as hybrid architectures having inle,-ol",e~ l conductors both directly above and between the logic function circuits.

219~221 W096/20534 " ~ PCT/US95/13891 ~

FIG. 1 depicts an i"tt!~l o""e.l architecture col"pri~i"g a plurality of horizontal and vertical channels of interconnect conductors. For simplicity horizontal channels are depicted as single lines identified by reference numerals 14-1 14-2, 14-3 and 14-4 and vertical channels are depicted as single lines identified by reference numerals 16-1 16-2 16-3 and 16-4. Those of ordinary skill in the art will appreciate that each channel will comprise a plurality of individual i"l~r. u, ,ne.;l conductors some of which may be segmented and some of which may run the length (or width) of the array. The number of interconnect conductors present in each channel in any actual integrated circuit which embodies the present invention will be dictated by individual design choice based upon such factors as array size and density.

The segmentation of interconnect conductors is known and is .~ ;r;~d in prior art patents such as U.S. patent No. 4.758.745 to El Gamal et al. and 5 073 729 to Greene et al. and is thus not shown in FIG. 1 to avoid over Culll ,9 the figure. As will be app,t~cidled by those of ordinary skill in the art any one of the many available segmentation schemes may be employed in the architecture of the present invention.
Such skilled persons will recognize that the segmented interconnect conductors may be selectively joined to make longer conductors by pl~yldlllllling user-p~,g,d"""able interconnect elements between selected ones of the conductors.

In order to provide for a rich potential of i"l~luol1neclio,1 choices the intersections of selected ones of the individual conductors horizontal and vertical inle~ u~ e~l channels are populated with user ~lugldlllilldble interconnect elements which may be programmed by the user to make electrical cu,,,,ecliuns between ~ WO 96/20534 2 1 9 7 2 2 1 selected ones of them to implement ~;onne~Liul) nets between the inputs and the outputs of the logic function circuits. Groups of such user pluyld~l~r"abl~ ,le,~;o""e.;l elements at the illl~lbuutiuns of the horizontal and vertical interconnect channels are shown schul"ali. ally in FIG. 1 as squares 18-1 through 18-16. inputs and outputs of 5 the logic function circuits are also co""e.:ldble to selected ones of the i~ ,uo""ecl conductors in the channels by user-p,uy,dr"r"dble i"le,uo""e. l elements disposed at the i,lLe,:,e~;liol,s of the individual inputs and outputs and selected ones of the i"lu,~;u""e~l conductors in the channels as shown schematically by squares 2û.

There are a number of available user-p,uy,d"""ai lt~ ;om1e~;l te, hl1oloyies 10 which may be employed in the architecture of the present invention. These include such elements as antifuses and active devices such as pass transistors. Such devices their implementation and the circuitry necessary to program them are well known to those of ordinary skill in the art. The details of these known devices will not be set forth herein to avoid over co",,ulicdli"g the disclosure and thus obscuring the 1~ nature of the present invention. For convenience. the present disclosure will employ antifuse elements as exemplary user-u~uy~dllllllable i~ luuunecl elements but those of ordinary skill in the art will recognize that the present invention is not limited thereto and is intended to encu,,,pass pass transistors and other known devices which are user-programmable element equivalents of antifuses.

An important feature of the present invention is a network of Ulocal i"lt,n;u", lecl"
channels which are shown running between adjacent pairs of logic function circuits in the matrix. In FIG. 1 these local i"lt:rl o""e,_l channels are shown runnino between WO 96120534 ~ 2 2 1 PCT/I~S9~/13891 ~

12-1 and 12-2, 12-3 and 1?-4, 12-S and 12-6, 12-7 and 12-8, 12-9 and 12-10, 12-11 and 12-22, and are indicated by reference numerals 22-1 through 22-6. As will be disclosed in more detail herein, the local interconnect channels provide an enhanced i"le,~;ol1neclion capability between neighboring logic function circuits. Those of 5 ordinary skill in the art will recognize that the local interconnect channels may connect more than a single pair of adjacent logic modules. As a non-limiting example, local interconnect channel 22-1 could also be used in conjunction with the general u""~~ channels to make connections to logic modules 12-5 and 12-6 as will be seen more clearly from FIG. 2A.

According to a presently preferred embodiment of the invention, selected ones of the individual local interconnect conductors are cu, ,ne-ildble to selected ones of the i"le,~;o""ecl conductors in the channels by user-u,uy,d"""able interconnect elements placed at i"l~ iu"s thereof. The networks of these user-programmable interconnect elements are shown :,~;ht:lllclLil,dlly in FIG. 1 as squares 24.

The core architecture of FPGA 10 communicates off chip by means of a plurality of input/output (I/O) modules. Illustrative l/O modules 26-1, 26-2, 26-3, and 26-4 are shown coupled between l/O pads 28-1, 28-2, 28-3, and 28-4, respectively, and horizontal i"le,~;o""ec~ channels 14-2 and 14-3 and vertical i"le,~on"e.;l channels 16-2 and 16-3 respectively. As will be appreciated by those of ordinary skill in the art, l/O
modules 26-1, 26-2, 26-3, and 26-4 each comprise an input buffer, an output buffer and input/output function select circuitry. The design of particular l/O module circuitry is simply a matter of design choice and is well within the level of ordinary skill in the ~ wo 96/20534 2 ~ ~ ~2 2 I . ~

art. Known examples of such circuitry may be found in United States Patent No.
5,083,083.

Programming of the FPGA 10 of the present invention is controlled by program and test control circuit 30. Program and test control circuit 30 contains the necessary 5 circuitry to accept programming data and control signals from off chip via l/O pads 32, 34, and 36. Those of ordinary skill in the art will recognize that the number of such l/O
pads necessary for any actual impiementation of the present invention will vary according to design choice and requirements. The data and control signals are used to program selected ones of the user-,uluyldl~ dble interconnect elements in the 10 integrated circuit in order to define the circuit functions of the logic function modules 12-1 through 12-12 and the l/O modules 26-1 through 26-4 and the circuit conl1eulion paths between them. Program and test control circuit 30 may also be used to provide test data to and obtain test data from the logic function modules 12-1 through 12-12 as known in the art. Examples of testing using such circuitry are found in United States Patents 4,758,745 and 5,083,083.

As previously disclosed, the individual logic module circuits used in the present invention may comprise culllL)illd~ulidl logic units, sequential logic units, or colllLJi"alions of one or both kinds of logic units. Referring now to FIG. 2A, a schematiclblock diagram, a presently preferred elllbo.li",~"L of co,,,tji,ldlurial unit 40 20 for the plu~u,ld~ ld~le logic module may comprise three two-input multiplexers 42, 44, and 46. First two-input multiplexer 42 has a first data input connected to a first data input node 48, a second data input connected to a second data input node 50, a WO 96/20534 ~ 1 ~ 7 ~ 2 1 PCTIUS95/13891 ,~

control input connected to the output of a first gate 52, and an output 54. The first gate 52 has a first input connected to a first control input node 56 and a second input connected to a second control input node 58. Second two-input multiplexer 44 has a first data input connected to a third data input node 60, a second data input connected 5 to a fourth data input node 62, a control input connected to the output of the first gate 52, and an output 66. Third two-input multiplexer 46 has a first data input connected to the output 54 of first multiplexer 42, a second data input connected to the output 66 of second multiplexer 44, a control input connected to the output of a second gate 68, and an output 70. The second gate 68 has a first input connected to a third control 10 input node 72 and a second input connected to a fourth control input node 74. An output buffer 76 is connected to the output 70 of third multiplexer 46. First gate 52 and second gate 68 are shown as an AND and an OR gate, respectively, but persons of ordinary skill in the art will recognize that other gate colllL,i~ldliul,s are possible.

Those of ordinary skill in the art will recognize that several different 15 L~:hlloloyies may be employed to implement a multiplexer structure conLt:"",lal~d herein and that the specific technology chosen will vary according to design choice and circuit requirements. These various implementations include, but are not limited to, pass transistors, logic gates and bipolar transistors. The details of these known devices will not be set forth herein to avoid over co"" ' ' ~y the disclosure and thus Z0 obscuring the nature of the present invention.

A plurality of i"Lell,o""e..l conductors 78, 80, 82, 84, and 86 intersect the first through fourth data input nodes 48, 50, 60 and 62 and user-p,u!J,drr""aL,lt:

~ W096/20~34 PCTIUS9S/13891 2 ~ 1 interconnect elements (shown as hollow circles in the drawing figures) are preferably disposed at each i"Le,~e~liun to allow u,uy~d"~ able connections to be made between selected ones of the interconnect conductors and selected ones of the first through fourth data input nodes. Selected ones of the user-u,uy,d"""able interconnect elements are indicated by reference numerals 88a-88d and will be discussed later with reference to FIG. 2B.

One of the plurality of i"Le,~io,1l1ecl conductors 86 is connected to another one of the interconnect conductors 84 through an inverter 90. As will be appreciated by those of ordinary skill in the art the presence of inverter 90 adds to the versatility of the logic function module circuits by allowing a selected ones of the data inputs to be inverted.
This versatility could be further increased by extending inle~u,,,,e~;L conductor 86 to cross other functional unit inputs in the same functional unit or by making it a part of the local i"l~l- o, " ,e,;l channel to allow cu""e.:tiu,1s to other functional units. The output of inverter 90 can also be connected to any of the inputs of gates 52 and 68 through additional antifuses.

As may also be seen from FIG. 2A the i,,Lt:,~ol,,,eul conductors 78 80 82 and 84 are shown il,l~ ,e~:~i,lg horizontal interconnect conductors 92 94 96 and 98 in an upper general i~ ;u,,ne~;l channel and horizontal inler~ùnne~;L conductors 100 102 104 and 106 in a lower general i~ ILul ~ unlle(l channel. The control input nodes 56 58 72 and 74 of the first and second gates 52 and 68 also cross the horizontal i"le,~ un,,e~;l conductors 92 94 96 98 100 102 104 and 106. Other user-u,uy,a"""aule i"le,~iu""e"l elements are disposed at the illl~ , liolls of these 2 1972~

conductors and may be p,.l~,d",i"ed to selectively make connections as is known in the art.

Those of ordinary skill in the art will recognize that the particular arrangement depicted in FIG. 2A is merely illustrative and that other arrangements using other numbers of interconnect conductors and other schemes for populating the conductor e~ lici1s with user-programmable interconnect elements are possible.

The c~ lbindloridl unit 40 for the l~u~cm~able logic module depicted in FIG.
2A is a compact and flexible circuit, capable of performing a wide variety of combinatorial logic functions. Referring now to FIG. 2B a table is presented showing the output states of the cOI l lbil Idlui idl logic function module block of FIG. 2A as a function of the states of its inputs for a small sampling of the available c~ lL/illdl~lidl functions possible using this unit. Those of ordinary skill in the art will be readily able to detemmine the remaining possible functions. Such skilled persons will also readily recognize that multiple implementations are possible for certain of these functions. In reading the Table of FIG. 2B A0 and B0 represent the first and second control inputs 56 and 58 of AND Gate 52 A1 and B1 represent the first and second control inputs 72 and 74 of OR Gate 68. The input lines L0 L1 L2 and L3 represent illlt~
conductors 78 80, 82 and 84 respectively. The inputs D0 D1, D2, and D3 representthe data input nodes 48 50 60 and 62 respectively, of the first and second multiplexers 42 and 44. Finally the notation !L3 in the entries under alntemal~
represent the output of inverter 90 on i"l~ necl conductor 86. By reading the entries under L0, L1, L2 and L3 together with the entries under D0, D1, D2, and D3, ~ WO 96/20534 PCT/US95/13891 ~g~2'2~ ''. '' those of ordinary skill in the art can readily determine which user-~,,uy,d,,,,,,able interconnect elements to program to implement the desired logic function.

The entries in FIG. 2B are ~lldiyhl~u~vvdld. As an example to configure the p,uyld"""able logic module depicted in FIG. 2A as a four-input AND Gate the 5 following connections are made. The input terms ~a and br are presented to the first and second inputs of AND gate 52 on lines 56 and 58. The input temm ~c is presented to one of the inputs 72 of OR gate 68 and a logic U0" is presented to the other input 74 of OR gate 68. Logic ~0" levels are presented to interconnect conductors 78 80 and 82 and the input term ~d is presented to i,~ler~o""e~l conductor 84.

1 û By examining the entries in the first line of the table of FIG. 2B it is seen that Dû
(first data input node 48 to first input of first multiplexer 42) is connected to interconnect conductor 78. This may be accomplished by programming user-u,uy,d,,,,,,al; le interconnect element 88a at the i"ler~e-;liuu of interconnect conductor 78 and first data input node 48. Similarly D1 (second data input node 50 to second input of first 15 multiplexer 42) is connected to interconnect conductor 80. This may be accomplished by uluyldlll~ ng user-u,uy,d"""aLle interconnect element 88b at the illlel~euliull of interconnect conductor 80 and second data input node 5û. Similarly D2 (third data input node 60 to first input of second multiplexer 44) is connected to i~ ~lu~iO""e~ l conductor 82. This may be accomplished by plUyld"""i,ly user-u,uy,dm,,,able 20 interconnect element 88c at the i"le,:,e~tiun of i"lur~ol)necl conductor 82 and third data inpuf node 60. Similarly D3 (fourth data input node 62 to second input of second multiplexer 44) is connected to the input temm ~d" on il llt:l~;unl1e~_l conductor 84. This WO 96/20!i34 2~9~221 connection is made by programming user-programmable inle~uu~ne~il element 88d atthe i"l~ e"liun of i,,ler-,ur,,,e-;l conductor 84 and fourth data input node 62.

Referring now tû FIG. 2C, a presently preferred embodiment of a sequential logic unit 11 û for a logic module according to the present invention is shown in bloch/~ e,,,clLi~; format. According to a presently preferred embodiment of the invention, the sequential logic unit comprises three multiplexers and a D flip-flop. A
first two-input multiplexer 112 has a first data input connected to a first data input node 114, a second data input connected to a second data input node 116, a control input connected to a first control node 118, and an output 12û. A second two-input 1 û multiplexer 122 has a first data input connected to the output 12û of the first multiplexer, a second data input connected to the output of D flip-flop 124, a control input connected to a second control node 126, and an output 128 connected to the D
input of the D flip-flop 124. A first four-input multiplexer 13û has a first data input connected to a first clock input node 132, a second data input connected to the complement of the signal on first clock input node 132, a third data input connected to a second clock input at nûde 134, a fourth data input connected to the cu",pl~"lenl of the second clock input siç7nal on node 134, a first control input connected to a clock select node 136, a second control input connected to a clock polarity select node 138, and an output 14û connected to the clock input of the D flip-flop 124. The output of D
2û flip-flop 124 is buffered by buffer 142. Finally, D flip-flop 124 is also provided with set and reset inputs connected to set and reset nodes 144 and 146, respectively.

As with the COIllL)indlulidl unit 4û of FIG. 2A, sequential unit 110 of FIG. 2C

W O 96/20534 PC~rrUS95/13891 is con,)ecldble to the i~ o""e~ l architecture of the present invention. As may also be seen from FIG. 2C the various inputs and control inputs of the elements of sequential unit 110 are shown il,lt:,~eclil,g horizontal il,ler~ o""e. l conductors 148 150 152 and 154 in an upper general interconnect channel and horizontal interconnect conductors 156 158 160 and 162 in a lower general interconnect channel. User-programmable interconnect elements are disposed at the i"l~,~e~ Lions of these conductors and may be p,u~,d",i"ed to selectively make connections as is known in the art.

Those of ordinary skill in the art will appreciate that sequential unit 110 is also a flexible circuit. First four-input multiplexer 130 is used to select and control the clock source so that the D flip-flop 124 can be driven from a system clock at first clock input node 132 which would preferably be common to all such units on an integrated circuit or a clock signal from a clock node derived from other signals presented on second clock node 134 from the general i"l~rw, " ,e~;l channels. The con"e. Iio" of clock polarity select node 138 to first four-input multiplexer 130 allows selection of rising or falling edge triggering for the D flip-flop 124. As will be readily au~ idl~d by those of ordinary skill in the art this function is also easily illl~ilt:llltllll~d by a third two-input multiplexer and an exclusive-OR gate.

Referring again to FIGS. 2A and 2C another set of interconnect conductors is provided for cu"ne. Iiol1 to the inputs and outputs of both cullllJindlolidl and sequential units 40 and 110. Unlike the general interconnect channels r~ se"led by interconnectconductors92 94 96 98 100 102 104 106 148 150 152 154 156 21~7 W096/20534 221 PCr/11S95113891 158 160 and 162 these i~Lu~iun~eul conductors are locai inLu~ù~ euL shared between neighboring logic modules. Also unlike the general interconnect conductors the outputs of the culllbindloridl unit 40 and the sequential unit 11û are hardwired to individual ones of the local i~ U~ e~;L conductors.

The local i"lt"- onne, L conductors are given the same reference numerals in FIGS. 2A and 2C. In the illustrative embodiments depicted in FIGS~ 2A and 2C four local i,,lt:,l u,,,,ecL conductors 164 166 168 and 170 are shown although those of ordinary skill in the art will recognize that the number of locai interconnect conductors to be used in any actual realization of the architecture of the present invention will be 1û largely a matter of design choice and the number of co",bi"aliol1al and sequential units in the locally i"L~ u""e~ d logic modules.

The output of buffer 76 of cunlbil-dlu,idl unit 40 is shown hardwired to local i,,l~,uun,,ecl conductor 164. Similarly the output of buffer 142 of sequential unit 110 is shown hardwired to local interconnect conductor 166. Selected ones of the other data and control inputs of cûlllbinalurial unit 4û and sequential unit 11û are shown connectable to local interconnect conductors 164 166 168. and 170 via user-p~uu~d~ able interconnect elements shown as circles at the i, lLt~e. liuns of the data and control inputs of co",bil1dlu,idl unit 40 and sequential unit 11û and local i~Lu~u~ ecl conductors 164 166 168 and 170.

While it is presently preferred to employ the culllbil IdLulidl unit 4û of FIG. 2A in the present invention those of ordinary skill in the art will appreciate that other 2197221 :
W096/20534 PCI~/US9S113891 cu",bi"dloridl units will be usefully employed in the architecture of the present invention. Referring now to FIGS. 3A-3H, alternative c~lllbil l~lUlidl unit circuits are presented.

In FIG. 3A an alternative u~bodill~r-l1l of a cu",bi"dluridl unit 180 is shown comprising a single two-input multiplexer 182. First two-input multiplexer 182 has a first data input connected to a first data input node 184, a second data input connected to a second data input node 186, a control input connected to a control input node 188, and an output 190 connected to an output buffer 192.

First data input node 184 is shown illLer~e.ili"g horizontal interconnect conductors 194, 196, 198, 200 and 202 in an upper general illlur.;u"ne~l channel.
Second data input node 186 and control input node 188 are shown i~Lt:~be~.Li~y horizontal interconnect conductors 204, 206, 208, 210 and 212 in a lower generalillL~I~,0llll2~;l channel. An inverter 214 is shown with its input connected to an inverter input node 216 and its output connected to inverter output node 218. Inverter input node 216 intersects horizontal interconnect conductors 194, 196, 198, 200, 202, 204, 206, 208, 210 and 212 and inverter output node 218 intersects first and second data input nodes 186 and 184. Each of the i"L~,:,e~;Liol1s is preferably populated with a user p,uyld"""able i"Lt~ u""ecl element so that selected ones of the horizontal illL~r~,u"ne~l conductors may be connected to the first and second data input nodes - 20 186 and 184 either directly or through inverter 214 and to control input node 188. As will be also au,ultl~;idLed by those of ordinary skill in the art, the presence of inverter 214 adds to the versatility of the logic function module circuits by allowing selected WO 96/20!i34 P~

ones of the data inputs to be inverted. Those of ordinary skill in the will appreciate that user proy,dn""ci le i"L~" on"e,.l elements need not be present at each i"Lt:,ae.:lio".

In FIG. 3B a prior art embodiment of a co",i i"dloridl unit 220 is shown Cu"l~ i"g three two-input multiplexers. First two-input muitiplexer 222 has a first data 5 input connected to a first data input node 224 a second data input connected to a second data input node 226 a control input connected to the output of a first gate 228 and an output 230. The first gate 228 has a first input connected to a first control input node 232 and a second input connected to a second control input node 234. Second two-input multiplexer 236 has a first data input connected to a third data input node 238 a second data input connected to a fourth data input node 240 a control input connected to the output of the first gate 228 and an output 242. Third two-input multiplexer 244 has a first data input connected to the output 230 of first two-input mlll~iplPyer 222 a second data input connected to the output 242 of second two-input mui~ii lPY~r 236 a control input connected to the output of a second gate 246 and an output 248 connected to an output buffer 2~0. The second ~ate 246 has a first input connected to a third control input node 2~2 and a second input connected to a fourth controi input node 254. First gate 228 and second gate 246 are shown as an AND
and an OR gate respectively but persons of ordinary skill in the art will recognize that other gate culllbind~iu,,s are possible. Persons of ordinary skiil in the art will also 20 recognize that the first and second gates may be omitted entirely and that the control inputs of the multiplexers can be connected to the a control input node which intersects the horizontal i"ler~o"ne~;~ conductors of a general interconnect channel.

2f ~22~
~ W0 96/20534 I ~

The first second and third multiplexers 222 236 and 244 comprise first and second multiplexer planes in a cascaded multiplexer architecture. The first and second multiplexers 222 and 236 form a first multiplexer plane in which the inputs are connected to input nodes 224 226 238 and 240. The outpllts 230 and 242 of first and second multiplexers 222 and 236 feed into the inputs of third multiplexer 244. Third multiplexer 244 forms a second multiplexer plane in the cascaded multiplexer architecture.

First and third data input nodes 224 and 238 and first and third control input nodes 232 and 252 are shown i"le,:,e~;Li"g horizontal i"l~" olllle.;l conductors 2~6 258 260 262 and 264 in an upper general i"l~,~;o""e- I channel. Second and fourth data input nodes 226 and 240 and second and fourth control input nodes 234 and 254 are shown i"l~,~e~li"g horizontal i~ u""ecl conductors 266 268 270 272 and 274 in a lower general i"le,~;onne~l channel. Each of the il~ lae1liolls is preferably populated with a user ~u,u~,du,,,,able interconnect element so that selected ones of the horizontal i"le,1onne. l conductors may be connected to the first through fourth data input nodes 224 226 238 and 240 and first through fourth control input nodes 232234 252 and 254 Those of ordinary skill in the will appreciate that user programmable interconnect elements need not be present at each il IL~ c- lium In FIG. 3C another embodiment of a co",bi"dlo,idl unit 280 is shown The embodiment shown in FIG 3C differs from that shown in FIG. 3B in that an inverter 282 - is shown which increases the versatility of the co",l,i"alu,ial unit 280. (The same reference r~umerals shown in FIG. 3B are shown in FIG. 3C). The inverter 282 has its 21g722 W0 96/20534 . , ~ P~ J/~

input connected to an input node 284 which intersects horizontal i~ o~"ecl conductors 256 258 260 262 264 266 268 270 272 and 274. The outputof inverter 282 is connected to an output node 286 which intersects first through fourth data input nodes 224 226 238 and 240. Each of the intersections is preferably populated with a user programmable interconnect element so that selected ones of the horizontal i~ ol llle~ I conductors may be connected to the inverter input node 284 and that selected ones of the data input nodes 224 226. 238 and 240 may be connected to the inverter output node 286. Those of ordinary skill in the will appreciate that user p,u~,~"""able interconnect elements need not be present at each i"I~, :,e~ li~,.

In FIG. 3D another alternative embodiment of a cu",bi,)alo,idl unit 290 is showncu",p,i~i"g three two-input multiplexers and two two-input control multiplexers. First two-input multiplexer 292 has a first data input connected to a first data input node 294 a second data input connected to a second data input node 296 a control input connected to the output of a first two-input control multiplexer 298 and an output 300.
Second two-input multiplexer 302 has a first data input connected to a third data input node 304 a second data input connected to a fourth data input node 306 a controlinput connected to the output of first two-input control multiplexer 293 and an outpUt 308. The first two-input control multiplexer 298 has an input connected to a first input control node 310 an inverting input connected to a second input control node 312and a control input connected to a first input control multiplexer node 314. Third two-input multiplexer 316 has a first data input connected to the output 300 of first two-input multiplexer 292 a second data input connected to the output 308 of second two-input ~ WO 96/20S34 ~ g 72 2 f PCT/US9~113891 multiplexer 302 a control input connected to the output of second two-input control multiplexer 318 and an output 3Z0 connected to an output buffer 322. The second two-input control multiplexer 318 has an inverting input connected to a third input control node 324 an input connected to a fourth input control node 326 and a control 5 input connected to a second input control multiplexer node 328.

The first second and third multiplexers 292. 302 and 316 comprise a cascaded multiplexer architecture in which first and second multiplexers 292 and 302 fomm a first multiplexer plane and third multiplexer 316 forms a second multiplexer plane.

First and third data input nodes 294 and 304 first and third input control nodes 310 and 324 and second input control multiplexer node 328 are shown i"L~,~e~li"y horizontal interconnect conductors 330 332 334 336 and 338 in an upper general interconnect channel. Second and fourth data input nodes 296 and 306 second and fourth input control nodes 312 and 326 and first input control multiplexer node 314 are shown intersecting horizontal i"~e~;on"eL:L conductors 340 342 344 346 and 348 in 15 a lower general interconnect channel. Each of the i"le~,~eclions is preferably populated with a user p,oy,d"""abld i"lt~ o""ect element so that selected ones of the horizontal il ll~ o""e..~ conductors may be connected to the first through fourth data input nodes 294 296 304 and 306 first through fourth input control nodes 310 312 324 and 326 and first and second input control multiplexer nodes 314 and 328.
20 Those of ordinary skill in the will appreciate that user l,luy,cl"",aL)I~ i"L~,co,l"eu~
elements need not be present at each i"~ e-liu,l.

219~ 22 ~ ;
W096/20534 . .' , '' PCTIUS95/13891 ~
. ..

In FIG. 3E an altemative t",i,o~ l of a logic func~ion module 350 is shown in which a single four-input multiplexer 352 is empioyed instead of the three two-input cascaded multiplexer architecture shown in FIGS. 3B, 3C and 3D. Those of ordinary skill in the art will readily recognize that various a"d,1y~",e"l~ of multiplexers may be 5 employed to implement the four-input logic function modules shown in FIGS. 3B
through 3E.

In FIG. 3F another alternative embodiment of a culllb;ndll~ridl unit 360 is shown comprising seven two-input multiplexers. First through fourth two-input multiplexers 362, 364, 366 and 368 each have first and second data inputs connected respectively to first through eighth data inputs nodes 370, 372, 374, 376, 378, 380, 382 and 384, have outputs 386, 388, 390 and 392, respectively, and each have a control input connected to first inp--ut control node 394 as shown in FIG. 3F. Fifth and sixth two-input ~"ltipl~Yers 396 and 398 each have first and second data inputs connected respectively to the outputs 386, 388, 390 and 392, have outputs 400 and 402, 1~ respectively, and each have a control input connected to the output of first gate 404.
The first gate 404 has a first input connected to a second control input node 406 and a second input connected to a third control input node 408. Seventh two-input multiplexer 410 has a first data input connected to the output 400 of fifth two-input multiplexer 396, a second data input connected to the output 402 of sixth two-input multiplexer 398, a control input connected to the output of a second gate 412, and an output 414 connected to an output buffer 416. The second gate 412 has a first input connected to a fourth control input node 418 and a second input connected to a fifth control input node 420. First gate 404 and second gate 412 are shown as an AND

~ wos6/20s34 1 9 722f PCTIUS95/13891 and an OR gate, respectively, but persons of ordinary skill in the art will recognize that other gate cu/llbil,dliul,~ are possible.

The first through seventh multiplexers 362, 364, 366, 368, 396, 398 and 410 comprise a cascaded multiplexer architecture in which first, second, third and fourth multiplexers 362, 364, 366 and 368 form a first multiplexer plane, fifth and sixth multiplexers 396 and 398 form a second multiplexer plane and seventh multiplexer410 forms a third multiplexer plane.

A plurality of interconnect conductors 422, 424, 426, 428, and 430 intersect thefirst through eighth data input nodes 370, 372, 374, 376, 378, 380, 382 and 384 and each of the inlu~e~,liùns is preferably populated with a user programmable i"le,~,o,)"e~,l element and may be programmed to selectively make con~1e~,liu,~sbetween selected ones of the il ~ ùl1l1e~l conductors and selected ones of the first through eighth data input nodes as is known in the art. Those of ordinary skill in the will appreciate that user p,uy,d,,,,,,dble interconnect elements need not be present at each inlt:,:,e~liu". One of the plurality of i, llt:luul " ,e,,l conductors 430 is connected to another one of the interconnect conductors 428 through an inverter 432. As will be d~J,UI ~::Uidl~d by those of ordinary skill in the art, the presence of inverter 432 adds to the versatility of the logic function module circuits by allowing selected ones of the data inputs to be inverted. The use of interconnect conductors 422, 424, 426, 428, and 430 to connect the input nodes 370, 372, 374, 376, 378, 380, 382 and 384 to the general interconnect channel provides several distinct advantages over directly illl~l~ec~illy the data ineut nodes with the general interconnect channels as shown in FIGS 3A-3E.

W0 96120534 2 ~ g~ 2 2 r~

First it reduces capacitive loading of the net being programmed which provides enhanced circuit pe,iur",a"ce. Second there is greater symmetry and flexibility in connecting inputs to the general i"Le" u""ect channels. Finally the required number of general interconnect channels may remain substantially the same as the number of 5 data input nodes into the cascaded multiplexer architecture increases. It will also be appreciated that the interconnect conductors 78a-86a shown in FIG. 2A have the same advantages as recited for the interconnect conductors 422 424 426 428 and 430 in FIG.3F.

As may also be seen from FIG. 3F the interconnect conductors 422 and 426 and the second and fourth control inputs 406 and 418 are shown intersecting horizontal i, ll~:l. ul ,, ,e.;l conductors 434 436 438 440 and 442 in an upper cJeneral interconnect channel. The interconnect conductors 424 and 428 and the first third and fifth control inputs 394 408 and 420 are shown i"Lt:~se.;Li"g horizontal interconnect conductors 444 446 448 450 and 452 in a lower general i~Lul~u~ eul 15 channel. Each of the i"Lt" ~ecliu,ls is prefera~ly popuLated with a user pl uy~ dl 1111 lable interconnect element and may be programmed to selectively make ~.u~ e~;Li~ s as is known in the art. Those of ordinary skill in the will appreciate that user p,ug,d"""able inl~,uûnne~ elements need not be present at each inl~e~iliù~l.

In FIG. 3G a sixth alternative embodiment of a combinatorial unit 460 is shown 20 comprising eight two-input multiplexers. First through fourth two-input multiplexers 462 464 466 and 468 each have first and second data inputs connected respectively to first through eighth data inputs nodes 470 472 474 476 478 480. 482 and 484 ,, ~ W096/20534 ~tg7~ r.~ .,J;~

have outputs 486, 488, 490 and 492, respectively, and each have a control input connected to first input control node 494 as shown in FIG. 3H. Fifth and sixth two-input multiplexers 496 and 498 each have first and second data inputs connected respectively to the outputs 486, 488, 490 and 492, have outputs 500 and 502, 5 respectively, and each have a control input connected to the output of first gate 504.
The first gate 504 has a first input connected to a second control input node 506 and a second input connected to a third control input node 508. Seventh two-input multiplexer 510 has a first data input connected to the output 500 of fifth two-input multiplexer 496, a second data input connected to the output 502 of sixth two-input multiplexer 498, a control input connected to the output of a second gate 512, and an output 514. The second gate 512 has a first input connected to a fourth control input node 516 and a second input connected to a fifth control input node 518. hrst gate 504 and second gate 512 are shown as an AND and an OR gate, respectively, but persons of ordinary skill in the art will recognize that other gate co",bi, IdIiuns are 15 possible. Eighth two-input multiplexer 520 has first and second data inputs connected to a ninth and tenth data input nodes 522 and 524, respectively, a control input connected to the output 514 of seventh two-bit multiplexer 510, and an output 526 connected to an output buffer 528.

The first through seventh multiplexers 462, 464, 466, 468, 496, 498 and 510 20 comprise a cascaded multiplexer architecture in which first, second, third and fourth - multiplexers 462, 464, 466 and 468 form a first multiplexer plane, fifth and sixth multiplexers 496 and 498 form a second multiplexer plane and seventh multiplexer 510 forms a third multiplexer plane.

WO 96/20534 2 1 9 7 2 2 1 ,~ J~J~
, .,- ~;

A plurality of interconnect conductors 530 532 534 536 538 540 and 542 intP!sl~ct the first thr.ouah tenth data inDut nodes 470 472. 474 476 478 480 482 484 522 and 524 and each of the intersections is preferably populated with a user p,uy,d",l"able interconnect element and may be programmed to selectively make conne.;liul1s between selected ones of the i"Ie~.;onl1euI conductors and selected ones of the first through tenth data input nodes. Those of ordinary skill in the will appreciate that user p,u~,dn)lllal,le interconnect elements need not be present at each be~ liùl). Each of the interconnect conductors 538 and 542 are aiso connected toi"l~,~u""e~ I conductors 536 and 540 through inverters 544 and 546 respectively. As - 10 will be appl~:-,idled by those of ordinary skill in the art the presence of inverters 544 and 546 adds to the versatility of the logic function module circuits by allowing a selected ones of the data inputs to be inverted. As in FIG. 3F the use of interconnect conductors 530 532 534 536 538 540 and 542 reduces capacitive loading provides greater symmetry and fiexibility and limits the required number of general i"~, . unne~;l channels.

As may also be seen from FIG. 3G the i"Ie" u,,neul conductors 530 and 534 and the second and fourth control inpUts 506 and 516 are shown intersectin~
~ horizontal i~Ie~;uune~ I conductors 548 550 552 554 and 556 in an upper general inle~ u,,necI channel. The i~L~ ullllt:~t conductors 532 536 and 540 and the first third and fifth control inputs 504 508 and 518 are shown i"l~,ae~Ii"g horizontalinIt:~unnecI conductors 558 560 562 564 and 566 in a lower general illI~" olllleuI
channei Each of the intersections is preferably populated with a user pro~u"d"""Gble ~ Wos6/20$34 2~ 2I P~

interconnect element and may be programmed to selectively make connections as is known in the art. Those of ordinary skill in the will appreciate that user ~ g,dn""a~le interconnect elements neer~ nct be present at each i,.lela~

Those of ordinary skill in the art will recognize that the first multiplexer plane in 5 both FIGS. 3F and 3G may comprise various arrangements of multiplexers, for example, a single four-input multiplexer and two two-input multiplexers connected to eight input nodes. The second multiplexer plane could then be a single two-input multiplexer with inputs connected to the outputs of the two two-input multiplexers from the first plane. The third plane could then be a single two-input multiplexer with inputs 10 connected to the four-input multiplexer of the first plane and the two-input multiplexer of the second plane. As such, it will be ,~cog"i~td that in a cascade multiplexer architecture, the outputs of the multiplexers in a multiplexer plane do not necessarily have to be connected to the inputs of the multiplexers in the next i"""e.lidlely successive multiplexer plane.

In FIG. 3H an alternative t:lllbodi~,e~ll of the logic function module 570 is shown in which a single eight-input multiplexer 572 is employed instead of the seven two-input cascaded multiplexer architecture shown in FIGS. 3F and 3G. Those of ordinary skill in the art will readily recognize that various arrangements of multiplexers may be employed to implement the eight-input logic function modules shown in FIGS. 3F
20 through 3H.

Local interconnect conductors are not shown for the alternative embodiments of WO 96/20!i34 ~ 7 2 2 ~

the CullliJind~ dl units 180, 220, 280, 290, 350, 360, 460 and 570 in FIGS. 3A-3H to avoid over CG~ " ,g the disclosure. One of ordinary skill in the art will recognize that as shown in the illustr2tive embodiments shown in FIGS. 2A and 2C, selectedones of the data and con(roi inputs showr, i,. the com,binatorial units 180, Z0, 280, 290, 350, 360, 460 and 570 in FIGS. 3A-3H may be connected to local inlu~cu~ne, conductors.

Though the t:",bo.li",e"ls in FIGS. 3A-3H show structures with four and eight inputs into the first multiplexer plane, those of ordinary skill in the art will readily recognize that the invention disclosed herein is not so limited. The cascaded multiplexer architecture described herein is not limited by the number of inputs to the first multiplexer plane, nor the number of planes present in the cascaded multiplexer architecture.

As previously noted, it is presently preferred to combine three functional unitsinto a logic module. These three units may be identical, i.e., the logic module may l i comprise three C(""~i"ato,idl units or three sequential units, or may be mixed, i.e., the logic module may comprise one cGI~ indlG~idl unit and two sequential units. In logic modules containing mixtures of cullll)illdlulidl units and sequential units, it may be advantageous to intemally connect the prebuffered output of the combinatorial unit to one of the inputs of the first multiplexer of the sequential unit. Such an arrangement is 20 shown in FIG. 4A

Referring now to FIG. 4A, logic function module 600 is depicted in t W096/20534 l~ u..,SIl_.,,l iJlock/sul,~",dlic fommat. In the illustrative embodiment of FiG. 4A logic function module 600 is shown to include a combinatorial unit 40 and two sequential units 11Oa and 110b. For convenience, the elements of these units depicted in FIG. 4A will be referred to using the same reference numerals used in FIG~. 2A and 2C although not 5 all elements are numbered in FIG. 4A to avoid o\~u~wudi~g the drawing.

An upper general i"l~,~io""ecL channel includes general interconnect conductors 602 604 606 608 and 610 some of which may be dedicated to clock signal and dedicated logic level functions and a lower general i"Lt,uo""e.;L channel includes generai i"l~,. o""e~l conductors 612 614 616 618 and 620 some of which may also be dedicated to clock signal and dedicated logic level functions. A local i"l~ o""ecl channel 622 includes local i"leruon,1eul conductors 624 626 628 630 632 and 634. The output of output buffer 76 of co",billalo~ial unit 40 is shown hardwired to local interconnect conductor 624. The output of output buffer 142a of cu",L,i"dlu,idl unit 110a is shown hardwired to local interconnect conductor 626. The output of output buffer 142b of cunlL,i,1a~oridl unit 110b is shown hardwired to local interconnect conductor 628. In addition an internal hardwired cu"ne, liun is shown made between the pre-buffered output of culnbilldlulial unit 40 and the first input 114a of multiplexer 112a in sequential unit 110a. Alternatively the pre-buffered output of culllbilldlulidl unit 40 can be hardwired to the control input of multiplexer 112a.

Those of ordinary skill in the art will appreciate that the logic function module of FIG. 4A is extremely flexible and permits illlplt~ llldliull of a wide variety of combinatorial and sequential logic functions. When a plurality of these logic function WO961:10534 21 9 722 1 ! r~.,~

modules 600 are placed in an array as depictèd in FIG. 1 the advant2ge of the local interconnect channel becomes apparent. in such an arrangement the outputs of the combinatorial and sequential elements are individually hardwired to different ones of locali~U~onneclconductors624~626 628 630 632 and.63~. Becausethe 5 hardwired co""euliuns bypass any user-u~uy~dullllable i,lle".ù,),)eci elements in the general interconnect channels any time delay which such i,,l~,..u,,,,e.l elements will normally introduce to signals passing through them are eliminated resulting in a circuit which is in effect a larger faster single logic function module.

FIG. 4A also illustrates the extra versatility which the addition of inverter 9o of 10 FIG. 2A adds to the logic module function. As shown in FIG. 4A the inverter 90 shown physically located in the combinatorial unit 40 may be used with the col,liJi"dlù,idl unit 40 or with either sequential unit 110a and 110b by ulun,d"""ing apu~uUlidle antifuses to connect its output to the data inputs and control inputs of the data multiplexers 112a and 122a ~qsor~ d with sequential unit 110a and 112b and 122b ~csor;~l 1 with sequential unit 110b and to the set and reset inputs of the D flip-flops 124a and 124b in the sequential units l l Oa and l l Ob, respectively.

According to yet another aspect of the present invention the mixture and - placement of the culllbindlo,idl and sequential components of pairs of logic function may be advantageously varied. This aspect of the invention is illustrated in FIGS. 4B-20 4D schematic ~u,~a~"ldlions of the layouts of logic function module pairs connected by local interconnect channels according to the present invention.

W096/~0534 21 g 722 l P.,~ lSI

Referring first to FIG. 4B, a logic function module pair cOIll,u~ g logic function modules 600a and 600b are shown connected by local interconnect bus 622a. Logic function module 600a comprises a leftmost cu,,~ aloridl unit 640, a center sequential unit 642, and a rightmost co,nbi,,dluridl unit 644. Logic function module 600b comprises a leftmost combinatorial unit 646, a center sequential unit 648, and arightmost culllLJilldluridl unit 650.

Those of ordinary skill in the art will recognize that the outputs of the colllbil1dlulidl and sequential units 640, 642, 644, 646, 648, and 650 are hardwired to different individual local i"Le,~o""ecl conductors of local interconnect channel 622a in the manner depicted in FIG. 4A for a single logic function unit 600.

Other variations of the logic module pair layout according to the present invention are shown in FIGS. 4C and 4D. In FIG. 4C, a logic function module pairl,u""~ i"g logic function modules 600c and 600d are shown connected by local interconnect bus 622b. Logic function module 600c comprises a leftmost co",bil1rdlo,idl unit 652, a center sequential unit 654, and a rightmost co,,,bil1dlùridl unit 656. Logic function module 600d comprises a leftmost sequential unit 658, a center sequential unit 660, and a rightmost cul,,billdlulidl unit 662. In FIG. 4D, a logic function module pair cull,~liai"9 logic function modules 600e and 600f are shownconnected by local interconnect bus 622c. Logic function module 600e comprises aleftmost co,,,bi,,d~u,idl unit 664, a center sequential unit 666, and a rightmost sequential unit 668. Logic function module 600f comprises a leftmost co",bi"dloridl unit 670, a center sequential unit 672, and a rightmost culllbindlo,idl unit 674.

WO 96120534 219 ~ 2 21 '~ ~ ~ ; r~l,u ~

According to another aspect of the present invention, the interconnect conductors of the illlull onl1e.:1 architecture of the present invention may be supplied as segments. The ability to temporarily connect the segments together for purposes such as testing may be provided. Further user-programmable i"lu,~onneul elements 5 may be provided to programmably connect the segments together to produce longer interconnect conductors during normal operation of the integrated circuit.

Referring again to FIG. 2A each of i"le,l oll"e-il conductors 78 80; 82 84 and 86 are divided into segments by pass transistors. Thus i"lu,~;o""ecl conductor 78 is connected to one of the source/drain temminals of pass transistor 700. The other 10 source/drain terminal of pass transistor 700 is connected to illlell ulllle..l conductor 78a which may be considered as a clo. ,. ~ily extending vertical extension of illltll~.Ulll)t ~1 conductor 78. In similar fashion i"lu,.u"~eul conductor 80 is connected to one of the source/drain terminals of pass transistor 702. The other source/drain terminal of pass transistor 702 is connected to i"le" u""e, I conductor 80a which may 15 be conside,t:d as an upwardly extending vertical extension of iul~u~ne~;L conductor 80. Interconnect conductor 82 is connected to one of the source/drain terminals of pass transistor 704. The other source/drain terminal of pass transistor 704 is connected to i,,~ ;ù,l,,ecl conductor 82a which may be considered as a downwardly extending vertical extension of i"~ o""ecl conductor 82. I"l~,~;o"l,eul conductor 84 20 is connected to one of the source/drain terminals of pass transistor 706. The other source/drain terminal of pass transistor 706 is connected to interconnect conductor 84a which may be considered as an upwardly extending vertical extension of ~I W096/20534 ~72~

i"l~,~,o""ecl conductor 84. I"lt"~;onl1e~,l conductor 86 is connected to one of the source/drain terminals of pass transistor 708. The other source/drain terminal of pass transistor 708 is connected to interconnect conductor 86a, which may be conside,~d as an upwardly extending vertical extension of i,,l~rcu,,ne~;l çonductor 86.

As shown in FIG. 2A, the locations of the pass transistors are preferably staggered to add to the versatility of the il ,l~n;ol ~I ,e~;l architecture. Thus pass transistors 700 and 704 are located at one vertical position on their aCSQr~i~tP~
interconnect conductors while pass transistors 702, 706, and 708 are located at another vertical position on their associated interconnect conductors. The gates of the pass transistors are driven by the program and test control circuit 30 (FIG. 1). While the gates of pass transistors 700 and 704 are shown connected to a common gate line 710 and the gates of pass transistors 702, 706, and 708 are shown connected to a common gate line 712, those ot ordinary skill in the art will recognize that other arrangements are possible.

Those of ordinary skill in the art will dp~ l,idlt: that interconnect conductors 78a and 82a will be connectable through user~ ,y,d,lllllable i~L~-;u~ne~,l elements to the logic module (not shown in FIG. 2A) located below logic module in the integrated circuit array and that i"~ on,1e~,l conductors 80a, 84a, and 86a will be connectable through user-p,.1yld,,,,,,able i"l~,~,onnecl elements to the iogic module (not shown in FIG. 2A) located above logic module in the integrated circuit array. The particular segmentation scheme used in an actual architecture fabricated according to the present invention will be somewhat arbitrary and largely a matter of design choice 2~g7 22~
WO 96/20534 . ' ' ~ PCr/US95/13891 dictated by the particular architectural layout.

Vvhile embodiments and:,, ' icns of this invention have been shown and described, it would be apparent to those skilled in the art that many more mo~ i,.liu"s than mentioned above are possible without departing from the inventive concepts 5 herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.

Claims

What is Claimed is:

1. A combinatorial logic unit comprising:
a cascaded multiplexer architecture having a plurality of multiplexer planes, each of said multiplexer planes including at least one multiplexer having inputs, at least one control input connected to at least one input node and at least one output;
at least one multiplexer in a first of said multiplexer planes having said inputs connected to input nodes;
inputs of said at least one multiplexer in said multiplexer planes succeeding said first multiplexer plane connected to said outputs of said at least one multiplexer in preceding multiplexer planes in said cascaded multiplexer architecture;
at least one multiplexer in a last of said multiplexer planes having said at least one output connected to an output conductor; and at least one inverter having an input connected to an input node and an output selectively connectable to individual ones of said input nodes by user-programmable interconnect elements.

2. The combinatorial logic unit of claim 1 further including an output buffer connected to said output conductor.

3. The combinatorial logic unit of claim 1 wherein said user-programmable interconnect elements are antifuses.

4. The combinatorial logic unit of claim 1 further including an output multiplexer having inputs connected to input nodes, an output connected to an output conductor and a control input connected to said output of said last multiplexer plane.

5. The combinatorial logic unit of claim 4 further including an output buffer connected to said output conductor.

6. The combinatorial logic unit of claim 1 further including a logic gate having a plurality of inputs connected to input nodes and an output connected to said at least one control input of said multiplexers of at least one multiplexer plane.

7. The combinatorial logic unit of claim 6 wherein said logic gate is an AND
gate.

8. The combinatorial logic unit of claim 6 wherein said logic gate is an OR
gate.

9. The combinatorial logic unit of claim 1 further including a control multiplexer having a plurality of control multiplexer inputs connected to input nodes, a control input connected to an input node and an output connected to said at least one control input of said multiplexers of at least one multiplexer plane.

10. The combinatorial logic unit of claim 9 wherein said at least one of said control multiplexer inputs is inverted.

11. The combinatorial logic unit of claim 1 wherein said inputs of said at least one multiplexer in said multiplexer planes succeeding said first multiplexer plane are connected to said outputs of said at least one multiplexer in an immediately preceding multiplexer plane in said cascaded multiplexer architecture.

12. The combinatorial logic unit of claim 1 wherein at least one of said inputs of said at least one multiplexer in said multiplexer planes succeeding said first multiplexer plane are connected to said input nodes.

13. A combinatorial logic unit comprising:
N integrally ordered planes of multiplexers, wherein N is a positive integer, each of said multiplexers having a plurality of inputs, at least one control input connected to at least one input node, and an output;
inputs of said multiplexers of a first one of said planes connected to input nodes;
said outputs of said multiplexers of each plane up to a N-1 plane connected to said inputs of said multiplexers of a higher integrally ordered plane;
at least one output of at least one multiplexer of an Nth plane connected to an output conductor; and at least one inverter, each inverter having an input connected to an input node and an output selectively connectable to individual ones of said input nodes by user programmable interconnect elements.

14. The combinatorial logic unit of claim 13 further including an output buffer connected to said output conductor.

15. The combinatorial logic unit of claim 13 wherein said user-programmable interconnect elements are antifuses.

16. The combinatorial logic unit of claim 13 further including an output multiplexer having inputs connected to input nodes, an output connected to an output conductor and a control input connected to said output of said Nth multiplexer plane.

17. The combinatorial logic unit of claim 16 further including an output buffer connected to said output conductor.

18. The combinatorial logic unit of claim 13 further including a logic gate having a plurality of inputs connected to input nodes and an output connected to said at least one control input of said multiplexers of at least one multiplexer plane.

19. The combinatorial logic unit of claim 18 wherein said logic gate is an AND gate.

20. The combinatorial logic unit of claim 18 wherein said logic gate is an OR
gate.

21. The combinatorial logic unit of claim 13 further including a control multiplexer having a plurality of control multiplexer inputs connected to input nodes, a control input connected to an input node and an output connected to said at least one control input of said multiplexers of at least one multiplexer plane.

22. The combinatorial logic unit of claim 21 wherein said at least one of said control multiplexer inputs is inverted.

23. The combinatorial logic unit of claim 13 wherein said outputs of said multiplexers of each plane up to a N-1 plane connected to said inputs of said multiplexers of an immediately higher integrally ordered plane.

24. The combinatorial logic unit of claim 13 wherein at least one of said inputs of said at least one multiplexer in said multiplexer planes succeeding said first multiplexer plane are connected to said input nodes.

25. A combinatorial logic unit comprising:
a multiplexer having a plurality of inputs connected to input nodes, at least one control input connected to an input node, and an output connected to an output conductor; and an inverter having an input connected to an interconnect conductor and an output selectively connectable to individual ones of said input nodes of said multiplexer by user-programmable interconnect elements.

26. The combinatorial logic unit of claim 25 wherein said user-programmable interconnect elements are antifuses.

27. The combinatorial logic unit of claim 25 further including an output buffer connected to said output conductor.

28. The combinatorial logic unit of claim 25 further including a logic gate having a plurality of inputs connected to input nodes and an output connected to at least one control input.

29. The combinatorial logic unit of claim 28 wherein said logic gate is an AND gate.

30. The combinatorial logic unit of claim 28 wherein said logic gate is an OR
gate.

31. A combinatorial logic unit comprising:
a multiplexer having a first input connected to a first input node, a second input connected to a second input node, a control input connected to a third input node, and an output connected to an output conductor; and an inverter having an input connected to an interconnect conductor and an output selectively connectable to individual ones of said input nodes of said multiplexer by user-programmable interconnect elements.

32. The combinatorial logic unit of claim 31 wherein said user-programmable interconnect elements are antifuses.

33. The combinatorial logic unit of claim 31 further including an output buffer connected to said output conductor.

34. A combinatorial logic unit comprising:
a first multiplexer having a first input connected to a first input node, a second input connected to a second input node, a control input connected to a third input node, and an output;
a second multiplexer having a first input connected to a fourth input node, a second input connected to a fifth input node, a control input connected to said third input node and an output;
a third multiplexer having a first input connected to the output of said first multiplexer, a second input connected to the output of said second multiplexer, a control input connected to a sixth input node and an output connected to an output conductor; and an inverter having an input connected to an input node and an output selectively connectable to individual ones of said input nodes of said first and second multiplexers by user-programmable interconnect elements.

35. The combinatorial logic unit of claim 34 wherein said user-programmable interconnect elements are antifuses.

36. The combinatorial logic unit of claim 34 further including an output buffer connected to said output conductor.

37. The combinatorial logic unit of claim 34 further including a logic gate having a first input connected to a seventh input node, a second input connected to an eighth input node and an output connected to said third input node.

38. The combinatorial logic unit of claim 34 further including a logic gate having a first input connected to a seventh input node, a second input connected to an eighth input node and an output connected to said sixth input node.

39. The combinatorial logic unit of claim 37 wherein said logic gate is an AND gate.

40. The combinatorial logic unit of claim 38 wherein said logic gate is an OR
gate.

41. A combinatorial logic unit comprising:
a first multiplexer having a first input connected to a first input node, a second input connected to a second input node, a control input, and an output;
a second multiplexer having a first input connected to a third input node, a second input connected to a fourth input node, a control input, and an output;
a third multiplexer having a first input connected to the output of said first multiplexer, a second input connected to the output of said second multiplexer, a control input, and an output connected to an output conductor;
a first control multiplexer having an input connected to a fifth input node, an inverting input connected to a sixth input node, a control input connected to a seventh input node and an output connected to said control inputs of said first and second multiplexers; and a second control multiplexer having an input connected to a eighth input node, an inverting input connected to a ninth input node, a control input connected to a tenth input node and an output connected to said control input of said third multiplexer.

42. The combinatorial logic unit of claim 41 further including an output buffer connected to said output conductor.

43. A combinatorial logic unit comprising.
a first multiplexer having a first input connected to a first input node, a second input connected to a second input node, a control input connected to a third input node, and an output;
a second multiplexer having a first input connected to a fourth input node, a second input connected to a fifth input node, a control input connected to said third input node, and an output;
a third multiplexer having a first input connected to a sixth input node, a second input connected to a seventh input node, a control input connected to said third input node, and an output;
a fourth multiplexer having a first input connected to a eighth input node, a second input connected to a ninth input node, a control input connected to said third input node, and an output;
a fifth multiplexer having a first input connected to the output of said first multiplexer, a second input connected to the output of said second multiplexer, a control input connected to a tenth input node, and an output;

a sixth multiplexer having a first input connected to the output of said third multiplexer, a second input connected to the output of said fourth multiplexer, a control input connected to said tenth input node, and an output;
a seventh multiplexer having a first input connected to the output of said fifth multiplexer, a second input connected to the output of said sixth multiplexer, a control input connected to an eleventh input node, and an output connected to an output conductor;
a plurality of interconnect conductors intersecting said input nodes of said first, second, third and fourth multiplexers, said plurality of interconnect conductors selectively connectable to individual ones of said input nodes by user programmable interconnect elements; and an inverter having an input connected to one of said interconnect conductors and an output selectively connectable to individual ones of said input nodes of said first, second, third and fourth multiplexers by user-programmable interconnect elements.

44. The combinatorial logic unit of claim 43 wherein said user-programmable interconnect elements are antifuses.

45. The combinatorial logic unit of claim 43 further including an output buffer connected to said output conductor.

46. The combinatorial logic unit of claim 43 further including a logic gate having a first input connected to a twelfth input node, a second input connected to a thirteenth input node and an output connected to said tenth input node.

47. The combinatorial logic unit of claim 43 further including a logic gate having a first input connected to a twelfth input node, a second input connected to a thirteenth input node and an output connected to said eleventh input node.

48. The combinatorial logic unit of claim 46 wherein said logic gate is an AND gate.

49. The combinatorial logic unit of claim 47 wherein said logic gate is an OR
gate.

50. A combinatorial logic unit comprising:
a first multiplexer having a first input connected to a first input node, a second input connected to a second input node, a control input connected to a third input node, and an output;
a second multiplexer having a first input connected to a fourth input node, a second input connected to a fifth input node, a control input connected to said third input node, and an output;
a third multiplexer having a first input connected to a sixth input node, a second input connected to a seventh input node, a control input connected to said third input node, and an output;
a fourth multiplexer having a first input connected to a eighth input node, a second input connected to a ninth input node, a control input connected to said third input node, and an output;
a fifth multiplexer having a first input connected to the output of said first multiplexer, a second input connected to the output of said second multiplexer, a control input connected to a tenth input node, and an output;
a sixth multiplexer having a first input connected to the output of said third multiplexer, a second input connected to the output of said fourth multiplexer, a control input connected to said tenth input node, and an output;
a seventh multiplexer having a first input connected to the output of said fifth multiplexer, a second input connected to the output of said sixth multiplexer, a control input connected to an eleventh input node, and an output;
an eighth multiplexer having a first input connected to a twelfth input node, a second input connected to a thirteenth input node, a control input connected to the output of said seventh multiplexer, and an output connected to an output conductor;
a plurality of interconnected conductors intersecting said input nodes of said first, second, third, fourth and eighth multiplexers, said plurality of interconnect conductors selectively connectable to individual ones of said input nodes by user programmable interconnect elements;
a first inverter having an input connected to one of said interconnect conductors and an output selectively connectable to individual ones of said input nodes of said first, second, third and fourth multiplexers by user-programmable interconnect elements; and a second inverter having an input connected to one of said interconnect conductors and an output selectively connectable to individual ones of said input nodes of said first, second, third and fourth multiplexers by user-programmable interconnect elements.

51. The combinatorial logic unit of claim 50 wherein said user-programmable interconnect elements are antifuses.

52. The combinatorial logic unit of claim 50 further including an output buffer connected to said output conductor.

53. The combinatorial logic unit of claim 50 further including a logic gate having a first input connected to a fourteenth input node, a second input connected to a fifteenth input node and an output connected to said tenth input node.

54. The combinatorial logic unit of claim 50 further including a logic gate having a first input connected to a fourteenth input node, a second input connected to a fifteenth input node and an output connected to said eleventh input node.

55. The combinatorial logic unit of claim 50 wherein said logic gate is an AND gate.

56. The combinatorial logic unit of claim 50 wherein said logic gate is an OR
gate.

57. A combinatorial logic unit comprising:
a multiplexer having a first input connected to a first input node, a second input connected to a second input node, a third input connected to a third input node, a fourth input connected to a fourth input node, a first control input connected to a fifth input node, a second control input connected to a sixth input node and an output connected to an output conductor; and an inverter having an input connected to an interconnect conductor and an output selectively connectable to individual ones of said input nodes of said multiplexer by user-programmable interconnect elements.

58. The combinatorial logic unit of claim 57 wherein said user-programmable interconnect elements are antifuses.

59. The combinatorial logic unit of claim 57 further including an output buffer connected to said output conductor.

60. The combinatorial logic unit of claim 57 further including a logic gate having a first input connected to a seventh input node, a second input connected to an eighth input node and an output connected to said fifth input node.

61. The combinatorial logic unit of claim 57 further including a logic gate having a first input connected to a seventh input node, a second input connected to an eighth input node and an output connected to said sixth input node.

62. The combinatorial logic unit of claim 60 wherein said logic gate is an AND gate;

63. The combinatorial logic unit of claim 61 wherein said logic gate is an OR
gate.

64. A combinatorial logic unit comprising:
a multiplexer having a first input connected to a first input node, a second input connected to a second input node, a third input connected to a third input node, a fourth input connected to a fourth input node, a fifth input connected to a fifth input node, a sixth input connected to a sixth input node, a seventh input connected to a seventh input node, an eighth input connected to an eighth input node, a first control input connected to a ninth input node, a second control input connected to a tenth input node, a third control input connected to an eleventh input node and an output connected to an output conductor; and an inverter having an input connected to an interconnect conductor and an output selectively connectable to individual ones of said input nodes of said multiplexer by user-programmable interconnect elements.

65. The combinatorial logic unit of claim 64 wherein said user-programmable interconnect elements are antifuses.

66. The combinatorial logic unit of claim 64 further including an output buffer connected to said output conductor.

67. The combinatorial logic unit of claim 64 further including a logic gate having a first input connected to a twelfth input node, a second input connected to an thirteenth input node and an output connected to said tenth input node.

68. The combinatorial logic unil of claim 64 further including a logic gate having a first input connected to a twelfth input node, a second input connected to an thirteenth input node and an output connected to said eleventh input node.

69. The combinatorial logic unit of claim 67 wherein said logic gate is an AND gate.

70. The combinatorial logic unit of claim 68 wherein said logic gate is an OR
gate.

71. A combinatorial logic unit, according to claim 1, wherein said input of said at least one inverter is selectively connectable to individual ones of said input nodes by said user-programmable interconnect elements and said output of said at least one inverter is selectively connectable to individual ones of said inputs node by said user-programmable interconnect elements.

72. A combinatorial logic unit, according to claim 1. wherein said at least one control input from said first multiplexer plane is driven separately from said at least one control input from said at least one multiplexer in said multiplexer plane succeeding said first multiplexer plane.