CA2198359A1 - Two-transistor zero-power electrically-alterable non-volatile latch - Google Patents
Two-transistor zero-power electrically-alterable non-volatile latchInfo
- Publication number
- CA2198359A1 CA2198359A1 CA002198359A CA2198359A CA2198359A1 CA 2198359 A1 CA2198359 A1 CA 2198359A1 CA 002198359 A CA002198359 A CA 002198359A CA 2198359 A CA2198359 A CA 2198359A CA 2198359 A1 CA2198359 A1 CA 2198359A1
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- Prior art keywords
- transistor
- mos transistor
- channel mos
- node
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/24—Storing the actual state when the supply voltage fails
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356008—Bistable circuits ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- Non-Volatile Memory (AREA)
- Read Only Memory (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
A two-transistor, zero-power, electrically-alterable non-volatile latch element comprises an input node, an output node, and an erase node. A PChannel MOS transistor has a source connected to a source of first electrical potential, a drain connected to the output node, a control gate connected to the input node, and a floating gate capacitively coupled to the control gate. An N-Channel MOS transistor has a source connected to a source of second electrical potential lower than the first electrical potential, a drain connected to the output node, a control gate connected to the input node, and a floating gate capacitively coupled to the control gate and electrically connected to the floating gate of the P-Channel MOS transistor. The floating gates of the P-Channel MOS transistor and the N-Channel MOS transistor are capacitively coupled to the erase node via a tunnel dielectric.
Description
21 Y835~
Wo 9C1212~3 PCrlUSg6~00306 Title Of The Invention Two-Transi.stor Zero-Power Electlically-Allcrahle Non-Volati]c L~tch Background Of The Invention 1. Field of the Inventlon The preselll inventk)n rclates to solid statc s~vitching devices. More p~ u~ y~the present in-cn~ion rclates to a two-transistor, zero-power, clcctrically-alterable non-volatile latch element. Typical e,lvi,u."l,~,lt~ lor thc plcsent invention include using the switch to control a pass transistor for user-progr~mm h1. circuit applications.
Wo 9C1212~3 PCrlUSg6~00306 Title Of The Invention Two-Transi.stor Zero-Power Electlically-Allcrahle Non-Volati]c L~tch Background Of The Invention 1. Field of the Inventlon The preselll inventk)n rclates to solid statc s~vitching devices. More p~ u~ y~the present in-cn~ion rclates to a two-transistor, zero-power, clcctrically-alterable non-volatile latch element. Typical e,lvi,u."l,~,lt~ lor thc plcsent invention include using the switch to control a pass transistor for user-progr~mm h1. circuit applications.
2. rhe Prior Art 1~ 'I'he prohlelll of providhlc non-volatilc l;ltch elemellts has been addre~ssed in the prior art. Several solution.s have becn propo.sed.
Iinited Statcs Patcnt No. 4,132.904 to Harrari, discloses a static-RAM-like structure employing a cros.s-coupled CMOS latch in which the N-C:hannel transistors are provided ;1 r;~ 3 S q Wo 96121 273 ~ I f u~
witll ilonting ~ates which may he l"c~ d to impart a desired state to the latch. While the Harrari circuit does providc a non-volatile latch which providex ~ n ,h ,.~ data which can be ug,.lll.,l.ed. it requircs high-vûltage n-well structures and provides i..~l. ,t~,. .~...,, ~ data on first powerup. In addition. Ihe floating gatc structures are prone to the well known read-disturb 5 ph~ by which repeated rcad operations can degrade the stored data.
United States PaLent No. 4,300,212 to Simko discloses a non-volatile static RAM
circuit. It employ.s a vel~ large cell size including at least eight transistor devices, some of which arecomplicated sr-ll,;. u,,~ stmctures.
United Slates Patent No. 4,8~8,185 to Kowshik et al. discloses a structure 10 employing~ a CMOS non-Yolatile latc~h. While the Kowshik e,t al. Iatch does provide a non-volatile latch which provides cr mrh~m~n~ lry dat~l wllich can be ~ JI u~lLLnllcd, can assume a known state on pvwerup and does not rcq-lire hi~h-volta~c n-well technolo~y, it requires a ver~Y large cell size employin~ ten transistors a~s well as oLher structures.
It is Lherefore an objcct of the present invention to prûvide a rton-volatile latch 15 element which c~vercomcs some of the shortcomings of the plior art.
Another object of the prescnt invcntion is to proYide a non-volatile latch element which employs a small cell Si7.e.
Another objcct of the plCscllt invention is to provide a non-vola~ile latch elemen~
w hich emplûys a minimum numhcr of ~ransistûr devices.
A furthcr object of the present invention is to provide a nûn-volatile latch element which dc~cs noL rcquirc~ hi~h-volta~-: n-well technol()gy.
Yet another obje~t of the plesent invention is to provide a non-volatile latch element which has improved rcad disturb immunity.
It is a further object of the prescnt invcntioD to provide a non-volatile latch element which assumcs a kll(-wn sta~c on powerup.
WO96121273 ~I q8359 r_"~
Brief Description Of The Invention According to a first aspect of the present invention, a two-transistor, zero-power, e.lectrically-alterable noll-volatile latch element includes an input node, an output node, and an erase gate. A P-Channel MO5 transistor has a source connected to a source of first electrical 5 potential, a drain connected to the output node. a control gate connected to the input node, and a floating gate ~a~,ach; veiy coupled to the control gatc. An N-Channel MOS transistor has a source connected to a source of second c.lcclrical potential lower thaul the first electlical; potential, a drain connected to the output nodc, a c(introl gate connected to the input node, and a floating gate capacitively coupled to its control g:ltr and elcctrically connected to the floating gate of the P-10 Channel l-lOS transistor. The 11OQting gates of the P-Chamlcl MOS transistor and the N-Channel MOS transi.stor rue cal-acith!cly coLIplcd to the emse node via a tunnel dielectric. The control gate and the err~se glatc may comprisc l~gion.s in the suhstratc cap Lcitively coupled to the floating gate or may complisc poly.silicon lines cal)acitivcly coupled to the floating gate.
According to another aspcct of thc prescnt invention, a MOS transistor switch may 15 be connected to the OlltpUI nodc of thc two-transistor. zero-power, electrically-alterable non-volatile latch elemcnt of the present invcntion. The state of the latch controls whether the transistor is tumt,d on or oft~. Thc draill and sourcc of lhe MOS transistor switch may be connected to circuit nodes which may bc selcctively comlcctcd togcther by programming the two-transistor, zero-power, electlically-alterablc non-volatilc latch eiemcnt.
Tile two-tmnsistor~ zelo-powcl, clcctrically-alterable non-volatile latch element of the prescnt invcntion may bc l'alllicalcd using a single polysilicon gate process in which the control gate and crasc node.s arc folmrd i;om dillu.scd regiolls hl a s Ill,.olldu~lul substrate. Alternately, the two-transistor, zclo-p()wcn electrically-alterable non-volatile latch element of the present invention may be fabricatcd using a dollble polysilicon gatc process in which the control gate and erase nodes are iormcd t;om regi()ns of thc second levcl polysilicon layer.
Brief Description Of The Drawings FIG. I is a schcmalic diagr.lm of a tu!o-transistor, zero-power, electrically-aiterable non-volatilc latch element acc(llding to Lhe present invention.
FIG. ? i.s a grQrh .showing thc transl'cl Clla~ L~ Li~b of the two-transistor, ~ro-power~ electrically-altrr;lhle non-volrtile latch clement of FIG. I in both its programmed and .. . . . . . . . .. . . . . . . . . .
WO9~/21273 ~qa~5~ PcrlUSs61~03tl6 ~
erased stntes.
FIG. 3 is a top view of an illustrntive ~ o ~dul ivr layout of the two-transistor zero-powcr electrically-allerablc non-volatile la~ch clemen[ of FIG. 1.
Fl('l. 4 is a cross-sccti-mal view of ~hc illustrative s~ ;.. l.. tOl Ltyout of thc two-5 transistor zero-power eleclrically-alterable non-volatile latch elerae~nt of FIG. 3 taken through lincs 4-4.
Fl(G. 5 is a schcmalic diagram of a two-by-two array of two-transistor zero-pouer elcctrically-alLerable non-volatile latcll elcments according to another aspect of the present invention.
Detailed Description Of A Preferred Embodiment Those of ordinary skill in the art will realize that the following description of the present in~cntion i5 illustrati-e only and not in any way limiting. Other embodiments of the invention ~vill madily ~su~gcst themselves to such .skilled persons.
Refcrriny~ finst to FIG l a two-transistor. ~e.ro-power. electrically-a!terable non-volatile la~cll elcme-lt 10 Or Ihe l~rescnt invention is scen ~o connprise u P-Channel MOS uarlsistor 12 and an l~-Channel M~S transistor 14 cmllilL~ured in the martner of a well-lcnown invener. The source 16 of P-Channel MOS transistor l 2 is a difl'u.sed region in a ~t~mi~--nd~lrtor suhstrale and ts connected tn ~icc potenti~l~ it5 drain 18 is a diffused region in a .s~.,.;~ oi~Ju~ substrate and is also lhe drain of N-Channel MOS transistor 14. The source 20 of N-Channel MOS transistor 14 is a diffu.sed re~ion in a ~mic~ { lor substratc and is connected to ground potential. The common drains 1~ of P-Channcl h~OS transistor 12 and N-Channel MOS transistor 14 forra an output nodc 22 t'or the latch clcment.
A common ~loalin~ gatc 24. which may be formed from a layer of doped polysilicon as is ~nown ;n the art. i~s as~sociated wilh both P-Channel MOS transistor 12 aad N-Channel M(3S transislor~14. Fk~ating gale 24 is ~a~ ;Li~ly coupled to an era~se "gate'' node 26 via a tunneling dielccllic as is known in the arL
P-Channel ~IOS transi~slor 12 and N-Channel MOS traasistor 14 share a common contlol "gate'' nodc 28. Control gatc 28 i~S ~--t a.i~ ly coupled to floatin~ gate 24 and raay . . . _ . , . , . _ _ , , WO ~6121273 2 t 9 3 3 5 9 PCr/Uss6/00306 comprisc f'or cxamplt a scpLIrrnc dil'fuscd region in thc .~r~mi~on(h.m. r substrate.
The two-transistor. ze.lo power electrically-allerable non-volatile latch element 10 of the present invenlion is slable in two states a programmed or "on" state and an erased or "off ' stalc. Thc two-transi.slor zero-po- er elecllical]y-alterable non-volatile latch element of the 5 present invenli(m 10 may hc programmcd by raising the common control gates 28 of the P-Channel and N-Channel l~lOS transislllrS 12 and 14 to a programming voltage Vpp while the erase node.26 is held al zelo v()l~s. Thc floaling gale 22 is coupled high because of the capacitive coupling to the control gales 28. If' Ihe eleclric field across the tunnel dielectric exceeds the minimum field required t'or Fo~lcl-N'(lldhcim mnnelil1g elcctrons will tunnel across the tunnel 1 0 dielectric lo thc ffoaling ga~e 24. Thc tmpped el-cctrons increase (i.e. make more positive) the threshold of Ihc N-CIlannel M()S Ir:lnSiSlol 14 alld decrease (i.c. make more negative) the thres}1old of Lhc P-Channel MOS iransi.slor 12. Afler the programming voltage is removed the conlr( l ~alc~S 28 ale hc]d al rlound llolcnlial. The output of thc latch al node 22 will be at approxima~ely Vcc since the N-Challncl MOS Uan.sislor 14 is turned off and the P-Channel MOS
1 5 transistol 12 is turncd nn.
To erase the two-trclmsist()r zero-powcl clectrically-alterable non-volatile latch element 1() of the E~rcscnl inventinn thc contr(il gates 28 arc held at ground potential and the erase node 26 is raiscd to Vpp. Thc clcctrical field established across the tunnel dielectric will cause eleclrons lo tunnel OUI of thc floating ~atc 24 thus makin~ it more positive. l'he positive charge on 20 the. floaling ~ale dccrea.se.s (i c ~ makc.s less positive) thc thlcshold of the N-Channel ~IOS
tr:msistor 14 and incrc.ascs (i.c.. mal;(.s more po.sitive) tl-c threshold of the P-Channel MOS
transistol 12. Af~cr thc pro- rammin~ volt~ge is rcmo~!ed thc control gates 28 are held at ground polential. The OUtpUI c f Ihc la~ch at n(ld. ~2 will hc at approximalely ground since the N-Channel MOS tr tnsislor 14 is turncd on :md Ihe P-Ch tnnel MOS transislol 12 is turned off.
FIG. 2 is a glaph showing lhc tlan~sfercll~ ;LLl;sli~s of the t o-transistor ~ro-pouer ele~ctllcQlly-allcrahlc noll-volatilc latch elcmenl of FIG. 1 in both its programmed and erased s~a~cs. FIG. 2 illus~r:ltcs thc opcralion of thc latch as described above As may be seen from an e~ lTnin ~ l of FIG. Ihe solid line 3(1 represcnts thc llOrmal voltage tranSfer .l~ .L~l~Li. of a C~IOS invertLn. Thc dashcd linc ~2 rcpre.scnt.s the currcnt flo-v through the inverter as a functiol1 of ~hc OU~pllt voltagc. 'I'ht~ nc_ative peak Or the currcnt nOw curve represents the point at ~hich hoth the P-C.hanllel h.lOS Iransist(ll and thc N-Channel h IOS transistor are conducting.
The s~raight dashcd line ~4 in FIG. 2 rcpresent.s the operating point of the inverter when electrol1s have hccn tunnclcd on~o thc floLIting ~ate by the programming operation. The wo 96/21273 2 l ~ 8 3 5 9 PC'T~lJ~96/OfJ306 ~
omput ~olL;t~e is a~ a ma~imum ilnd Ihc currcnt tlow is zel~. The stra~ht dashed line 36 repre.sents Lhe opcr tting point of ~hc inver~ r when electtons have been lunneled off of the floadng~
gate hy the era~se operation. The ou~put voltace is at a m;nimum artd the current flow is zRro.
Thus it may be seen that the latch Or tl c plesent invention exhibiLs no current flow in either its 5 ~J~ alllllled or erased slate.
I'ho~se ot ordinary shill in Ihc. an w ill recognizc Lhat Lhe latch sLructure of the present invention is a stahlc S~l'UC~UIl~. Expcricnce with tloating gate transistor device.s has shown that suchde~ice.srcliahlyreLainthcirlk).llinc gaLe chugcrorpcriodsintxcessQftenyerlrs.
The lalch SLruCtUrC of FlG. I may hc used to drive a number of different devices.
10 ~s will be disclo.sed heieim the la~cll Or ~llc prcscnt invention may be r ~IVUnLU g ~ ~U~1Y employed to d}ive a paSc transistor whosc statc may he used 1() control the selective formation of illLel~ul~lec60n ncLs in an inlcglllt~ d circtlit.
Retclting now to FIGS. .~ an(l 4. ân illusLrative e.mbodiment of the latch of the present invention as cnnhodied in scmiconductoI materiltl is showm FIG. 3 is a top view of an 15 illustrative semi-onductot layout of thc two-transi.sLor~ ~ro-powel electrically-alterable non-volatile latch element of FIG. I . FIG. 4 i.s a cro.ss-sf c~ional view of dle illustra~ive c~ miron~ rtor layout of Lhe two-tran.sistor ~ero-p(twci cle.ctrically-alterable non-volaLile latch element of FIG. 3 tahcn throut~h lines 4-4.
Tllc P-Chttltncl M~ u.Lnsi!;tor 12 of FIG. I is disposcd in n-well 4(1 rlnd its source 20 and drahl comprisc p+ dift;lsc t l~~ioll.s 42 and 44. rcspcctivcly. The N-Channel MOS transistor 14 of F~G. 1 is disposed in ~he ~3-typc semicondllctor substrltte 46 (rno~e easily seen in FIG. 4) and its drain and sourcc re~iol1s complisc n+ diftused regions 48 and 50 respectively. Metal strip 52 is used to conncct p+ diffu~sed 44 tn n~ diffused region 48 viâ contacts 54 and 5G. Vcc metal line 58 is connected lo p+ dit'ftlsion 42 vin contacts 60 and ground metal line 62 is connected to 25 n+ ditfusion 5() via contacts 64 Tho.se of ordinary skill in the art w;ll observe that double contacts are shown in the layo-n ol' FIG. ~. but will realize that single contacts may be employed instead.
Floatillg g~ate 24 of FIC~ I is Lomlcd f rom a single layer of polysilicon 66 having extending finger 62 disp()scd ahovc Illc channel re~ion between diffused regions 42 and 44 30 forming the floating galc p(irtion Or P-Channcl hlOS transistor 12. A second extending finger 70 is disposed above the chamlcl rcgion hctween diftu.sed legions 48 and 50 forming the floating gate portion of N-Channcl 1~10S transislol 14. As will be a~Jl~iat~d by those of ordinary skill in tlte 21 q8359 ~ WO 96i21273 PCT/U596/00306 art. the source and drain diflu.sion.s i;)r iioth the E' Channel and N-Channel MOS transistors 12 and 14 may bc formed usinC ~sclf-aligncd gatc techniques as arG known in the art.
The commou contlol gates of P-Channel MOS transistor 12 and N-Chanrtel MOS
transistor 14 may be formed a.s a high-voltagc n-type. dift;lsed region 72 in the substrate. High-5 voltage n-type difi'used rcgion 72 should be formed so as IO ~vithstand the ci~ t d Vpp voltage vvith an appropriat-c margin as is well understood in the art. The high-voltage diffused region 72 is capacitively couplcd to an en]argcd portion of the overlying polysilicon fioating gate strip 661o enhance capacitive coupling. A dielcctric layer 74, typically forrned from high quaiity oxide as is knowll in the art, to a thickness of tt()m about 50 tn ahout 130 angstroms, preferably about 8() ang~stroms~ .scp:~rate.s tbc diffuscd region 72 t'rom the polysilicon fioating gate strip 66 and lorms couplillg capacitol 76. The III'CI of a typical couplinr capacitor 76 is about 7 to 10 times the area of the, tunnelillg capacitor.
Thc Cl'IISC nodc ol latch I () of FlCi. I is lormed as a high-voltage n-type diffused region 78 in thc ~suhstratc. As ~vith hich-volLagc n-type dit'fuscd region 72, high-voltage n-type 15 diffu.sed regioll 7~ shollld also hc l'ormcd so as to witllstand thc ~u, , ' --i Vpp voltage with an appropriate margin as bi ~ cll undclstoùd in the arL A tlmneling capacitor 80 is t'ormed by the s,~ ", of thc dil1uscd regioll 78 witll thc ovel iying polysilicon strip 66~ The polysilicon layer 66 is separated t'rom thc diffuscd region 78 hy a lunneling dielectric layer 82 typically formed from high quality oxide as is known in the alt, to a thickncss of about 50 to about 130 angstroms, 20 prefcrahly about ~() ancstlom.s. I'he. area of a typical tunneling capacitor 82 is about the smallest feature size ~hich c:ln he prinLtd u~sing phototlitilograrhy techniques, or may be fonned by an overlap of thc soulcc/dlain cliffilsion with UlC polysilicon lloat;ng gate.
Those ot' ordinary si;ill in the art will rccogni7.e that, while the ~mbo iimt~nt iiiustrated in FIGS. 3 :md 4 cmpR~ys "gatc" elcmcnt.s which alc actually disposed in the subsLrate, 25 diffused rcgions 72 tnd 78 could easily hc replaced by polysilicon lines formed in a second layer of polysilicon as is ~!cll-knnwll in thc EPROM and EEPROM art. Such structures are equivalent to the s~ructllrcs depiclcd in thc rlgurcs hcrcin and are thus inlellded to fall within the scope of the present invcntion.
In a typiclll e,n-hodimcnt llf thc pr-scnt invention, the latch elements may be 30 proc~rammed and erascd hy a Vpp ~oltagc in the rangc of about 1() to about 15 volts.
As may he seen t'rom an t~Y Imin ~l ion of FIGS. 3 and 4, because the control and erase ''gates" arc forn-cd i'rom dopcd region~s in thc ~sub~strate, the two-transistor, zero-power, 3 2 1 ~ 3 ~ ~ ~ r~
electrically-nlterable non-volatile latc~h elemenl of the prcsent invention may be fabricated as a part of a c(mve.nlional single-level poly.silic on galc C~IOS integratcd circuit fibrication process. Such a process begins ~vïth Ihe convcnlionlll ster,.s for forming lhe n-wells, the field implant and field oxidation stcps.
Tlle high-voltage n-type regions complising the erase gate and control gate lines are then formed in the. substrate using buried n+ ma.sk and implant. Alternatively, the crase gate can also be t'cllmed in the n-typ. .~u~ c~;naill difrusinn usin~ known high-voltage techniques.
Next~ a tunncl ~indo~ is etched tCl expûse the hi~h-~,oltage n dit'fusion comprising the global era.se line and thc t~mncl diclecuic is iolmcd, prelelahly t;om high qualhy oxide, and is thcn dclincd hl thc tunncl windo~v. Thc poly.siiicon layer u hich will comprise the floating gate is thell forlllcd. dopcd and det'incd, u.sing coll-clltional scmiconductor processing technology.
Thc gate cxidc step ~or thc iormation of o~hc} P-Channc~l and N-Ch~t:tnel transistor devices on thc intcgratcd circuit is thcn pcr.''ormed. follo~-ed by deposition, doping, qnd definition of thc pol~silicon gates fur tho.~ othcr transistor dcYiccs. Il the global erase and control gates an~
to be t'orrmcd from polysilic-~n laycrs, an inter-poly oxid~ is lormed, windows are etched to expose regions of lh. flolting galc, and lhc lunncl diclcctric and control gnte capacitol dielectrics ate forme~d prior to pc rforming lhe g~cltr poly deposition .step. An implant oxide is formed, fol]ûwcd by lhe masking Imd implant ste,os ncccssaly to form both the P-Channel and N-~hannel sel.f-ali,~ncd ~sourcc and drahl rcgions.
Next. BPSG dcposition. contact window formation, and first level metal steps areperformcd usin~ conven~ nal .semic(~nductor pllXesSilig techniques. Subsequent metal layers art~i other back-elld processing muy thcn bc pcr~ormcd as ~s weU known in the ait.
Tllc det;lils of thc individual proccss .stcps uscd in the fabrication of the two-transistor, zelo-p(lwcr, elcctricall~-allcrablc non-volalile latch element, such as timcs, ~e~ e~,~lu~us, doscs, thic~nesses, etc.~ arc well known in the art for fortnation of CMOS devices and ha~ c tllcleforc n(lt hccn r cc itcd herci n. As will bc recooni~ed by persons of ordinary skill in the arl, the proccss dc.scri~cd herein for the fablicalion of Ihe latcll of the present in~entioù may be practiccd using standal d Ch/lOS proccssillg steps. and employing c(mventional layer thinkn~
implant dosugcs. clc. Thc additional processing stcps used to rorm the flûating gate, tunnel dieleclric, and capacitors for ~hc c~mtrol and crase gates are well known in the EEPROM auld EPROM art and alc not repcated hele in order to avoid u~ " ,~g the disclosure.
~ Wo 96121273 2 1 9 8 3 5 ~ r~
As m~y also hc secn l'rom an cxrmination of FIGS 3 and 4, the latch 10 of the presen~ invention may bc formcd as n compact str-lct-llc The layout shown in FIGS 3 and 4 readily lends i~self to the Liyout of ~m allay of latciles Such an anray could be usefully employed in devices ~such a~s u~ser-prt-gl.lmmahlc circuits (e g, FPGA integrated circuits) The outputs of 5 the latches would bc uscd to dri~c tr,lnsislclr switclles to selcctivcly make ;~ c in the user-programmahlc intecralcd CilCUitS
Such an array ')t) oi' two-tr;lllsistor zero-power, electricaily-alterable non-volatile latch clemcnts is shown in FIG 5 in schematic i'orm according to another aspect of the present invention Thc array 90 includcs a plurality of two-transistor zero-power, electrically-alterable 10 non-volatilc latch eTemc,nts al l-lll]gcd hl rows and columns In FIG 5, the latch elements are sho~wn as squarcs and de~signQtcxl witll rcrcrcncc mlmcr.lls 10-1 1()-210-3, and 10-4 Although the illustrativc Irrlly 9() Or FIG 5 is ihown comprisiilg t--o rows and two columns, those of ordinaly skill in thc urt wili rcadily rcco,,T~ c tllat tllc al r~y Or FIG 5 is for purposes of illustraùon and thatmuch lalgcraurays arc pl';lC~iC,II aCCOrdillr tO thc prcsciltinvention Lltch elcments 10-1 and 11)-2 folm Itlc first row of array 90 and latch elements 10-3 and 1()-4 form thc sccond r(lw of an.ly 90 ~imilarly. Iatch elements 10-1 and 10-3 form the first COTUITlll of anay ~() and la~ch clcmcnls 1(1-' und 10- i iolm the second column of array 90 Each latch clcmcm h~s :Is~s()ciQtcd ~ ith it ~ puss tr~msistor These transistors are labellcd witll re~crellcc numcmls 92-1 thlougll 92-4~ thtc numcric suffixes corresponding to the 20 numeric~ sui'fixcs of thc latch clcmcnt willl which c~ch pa~ss transistor is associated The gate of each pass transistc r is conncctcd to thc mltput nodc of its associatcd latch element As illustrated in FIG 5, pass ~r~nsLs~ors 92-2 througTI 92 4 arc shnun as NT-Channel MOS transistors, but those of ordinary skill hl thc ~rt wili rcco,lli~c lhQt othcr types Or devices may be used for different .~pp~ m, ,i without de; artinC l;om ~hc p rinciples of ~hc prcscnt invention 'I'he~ individu,ll latch clcmcn~s 1()-1 throurh 1()-4 in the array 90 of the present in~!ention may hc addres~scd and ~ug, mnn~d or may be erast d ln the configuration of the array depicted in FIG 5 a glohal cmsc modc is provided. althc)ugh those of ordinary skill in the art will easily understand ilOU' to cmlfigurc ~n arrQy in whicl1 the latch elements could be indiiidually erased In ~hc all-lly ~)() ol' ihc p rcscnt invcl1ti()l1 sclect transistors 94-1 through 94-4 are useci to selcct thc indivi(iu;ll latch clcmcl1ts r~., pr ogrammi,lg. As with the pass tr~ncictc r~,thP, numeric suffi~e~s of the sclcct tmnsismns hl rlG. 5 colTespond to the numeric suffixes of the latch 21 ~359 wo 96/21273 P~~
element with which cach pass transislor is associatcd. The select transistors !~4-1 through 94-4 are used to delivcr the ~ lhly voltage to sclected ones of the latch elements to program them .
The gates of selcct transistors 94-1 and 94~2 are connected to a first row line 96.
Thc gatcs of selcct transistors 94-3 and 94-4 are connected to a second row l;ne 98. The drains of select transist()rs 94-1 and 94-3 arc connccted to a first column line 100. The drains of select transistors 94-2 and 94-2 al~ connected to a second column line 1()2. 'I'he source of each of the select transistors is connected to the input node (the common control gates) of its ~;u~ t~ dillg la~ch element.
Glohal crasc I illC 1()4 i.s shown connected to each of the latches 1(1-1 through 10-4.
The glohal cr tsc linc is conncc~cd to th. erase nodc Or each of tlte latches and is u.sed to erase or re.sel all ot' ~hc latcl1e.s simul aneously.
Dul ing ~hc opcratin~ modo of thc array 9r) of the prcsent invention the row Iines 96 and 9g arc kept at T~ro volt.s SC1 that .sclcct transistors 94-l through 9~4 are turned off~ When it i.s dcsircd to pr()gram 011C o f tllc lalcl1 clcments l O- I through 10-4 of the array 90 the row lines and the column lines Irc uscd to sclcc~ thc latch to be programmed and to deliver thent appropriate voltagcs to the selectcd latcll.
To pro~-rrm 011C or morc dcsired latche.s it is llrst advisable hut not necessary to erase all of ~he latcllcs in oldcl lo SCI ~hcm all to a linown statc. This is done by connecting all column lines 1(1 and 1(14 to yro~lnd tulning on all select transistors 94-1 through 94-4 to place ground on the common col1lrol gatc.s of Illc N-Channel and P-Channel MOS transistors and by applying the. proyrammirty~ ~oltay.l Vpp to the global erase linc llM. As de~scribed previously for a sinyle latch examplc. ~his action w;ll causc~. elcctrons to tunnel from the floating gates of all of the latche; thus rendeliny them more positi~c. Altcr crasi1lg all of the N-Chamlel MOS transistors 14(E::lC.l~in~lleilldividuallalch-swill bol-lmcdonandalloftheP-ChannelMOStransistorsl2 (FIC,. I) will bc tumed ~'11. rrhc Olltpllt.S of all of the latches will go to ground.
Oncc all of thc latchc.s are placed in a known state ~erased) any one or more of the latches 10-1 through Ir)-~ may hc prog~arllmed. Ush1g the e~ample of prQErn~n~nin~ latch 10-3 second row linc 9~ is hrought to Vl-p while first row line 96 is kept yrounded. Vpp is also placed on filst columll linc 1 (Nl wllilc sccond column line 1()2 is kept grounded. The global erase line 104 is also kep~ grounded. This action turns on selcct transistor 94-3 placing Vpp on the common control gatcs of thc N-Channcl and P-Channcl MOS transistors in latch 10-3. Under 1() ~ Wo !~6/21273 ~ 3 5 9 Pcrlu~96/00306 these conditions, elec~rons arc causcd to tunncl on~o thc fl()atillg gate inside of latch 10-3, shifting the thresholds of the N-Channel and P-Channcl MOS transistors in latch 10-3 ~such that the P-Channel h,~OS transistor is turned On and the N-Channel MOS tr~msistor is tumed off, causing the output of lalch 10-~ to risc to a voltagc ol approximately Vcc.
Because finst ro-v Iint 96 i.s held at grolllld~ both select transistors 94-1 and 94-2 are tumcd ot'r. Becrlu.sc second column linc 1()2 is hcld at ground, Vpp does not appear at the control gaîcs of lhc tran.si.slms h~ latch 1(1-4 CVCll th(mg~lI thc gate of select transistor 94-4 is at a voltaoc which w()uld tum it on if thele W.l5 any voltage at its drain. Thus, no tunneling of electrolls will occllr Onto thc tk-)ating g;l~CS of IDtchcs 1()-1, 1()-2, anù 10-4.
Thc drivinc of lhc various voltagcs ont(1 lines 96, 98, 100, 102, and 104 is providcd hy progrumming cir-uitly 1(~ . Circuitry for gcnemting and s~wilching the necessary voltagcs lor progmmming thc devicc.s ot ~hc preselll invcAntiml is v.~ell known in the art and is a matter of .simplc dcsign choicc. Th.' volL~gc.s may he g( nemted on-chip by charge pumps as is known in thc art or may hc sul-plicd lrom otf chip viil sclccted l/O pin.s as is well known in the art.
Thc two-trrmsistol~ zcro-powcl~ elcctrically-~Llterable non-volatile latch element of the prcscnl invcn~ion will always power op to a dcsircd state oncc it has been pre-programmed.
Unlike somc of thc prior art latcll elemenls, it employ.s in~ pPn~lt~llr read and write paths, thus minimi7ing the rcad distulh plohlcm. Il docs not rcquirc high-voltage n-well technology. It empk)ys a smlll cell .si7.c, mJkin~ it an c~cellen~ candidate for urray applications, and enjoys excellent long-~cn)l dat.l retelltiOIl.
Wllile cmhodimcl)ts all(i applicatiolls of this invcntion have been shown and describcd, it would he apparcnt to thosc skilled in Ihc art that many more modifications than mcntioncd abo-e arc possihlc wi~hcut departing from thc inventivc concepts herein. The invention, therel'olc~ is not to hc rcstrictcd c~ccpt in tdlc .spirit of the appended claims.
Iinited Statcs Patcnt No. 4,132.904 to Harrari, discloses a static-RAM-like structure employing a cros.s-coupled CMOS latch in which the N-C:hannel transistors are provided ;1 r;~ 3 S q Wo 96121 273 ~ I f u~
witll ilonting ~ates which may he l"c~ d to impart a desired state to the latch. While the Harrari circuit does providc a non-volatile latch which providex ~ n ,h ,.~ data which can be ug,.lll.,l.ed. it requircs high-vûltage n-well structures and provides i..~l. ,t~,. .~...,, ~ data on first powerup. In addition. Ihe floating gatc structures are prone to the well known read-disturb 5 ph~ by which repeated rcad operations can degrade the stored data.
United States PaLent No. 4,300,212 to Simko discloses a non-volatile static RAM
circuit. It employ.s a vel~ large cell size including at least eight transistor devices, some of which arecomplicated sr-ll,;. u,,~ stmctures.
United Slates Patent No. 4,8~8,185 to Kowshik et al. discloses a structure 10 employing~ a CMOS non-Yolatile latc~h. While the Kowshik e,t al. Iatch does provide a non-volatile latch which provides cr mrh~m~n~ lry dat~l wllich can be ~ JI u~lLLnllcd, can assume a known state on pvwerup and does not rcq-lire hi~h-volta~c n-well technolo~y, it requires a ver~Y large cell size employin~ ten transistors a~s well as oLher structures.
It is Lherefore an objcct of the present invention to prûvide a rton-volatile latch 15 element which c~vercomcs some of the shortcomings of the plior art.
Another object of the prescnt invcntion is to proYide a non-volatile latch element which employs a small cell Si7.e.
Another objcct of the plCscllt invention is to provide a non-vola~ile latch elemen~
w hich emplûys a minimum numhcr of ~ransistûr devices.
A furthcr object of the present invention is to provide a nûn-volatile latch element which dc~cs noL rcquirc~ hi~h-volta~-: n-well technol()gy.
Yet another obje~t of the plesent invention is to provide a non-volatile latch element which has improved rcad disturb immunity.
It is a further object of the prescnt invcntioD to provide a non-volatile latch element which assumcs a kll(-wn sta~c on powerup.
WO96121273 ~I q8359 r_"~
Brief Description Of The Invention According to a first aspect of the present invention, a two-transistor, zero-power, e.lectrically-alterable noll-volatile latch element includes an input node, an output node, and an erase gate. A P-Channel MO5 transistor has a source connected to a source of first electrical 5 potential, a drain connected to the output node. a control gate connected to the input node, and a floating gate ~a~,ach; veiy coupled to the control gatc. An N-Channel MOS transistor has a source connected to a source of second c.lcclrical potential lower thaul the first electlical; potential, a drain connected to the output nodc, a c(introl gate connected to the input node, and a floating gate capacitively coupled to its control g:ltr and elcctrically connected to the floating gate of the P-10 Channel l-lOS transistor. The 11OQting gates of the P-Chamlcl MOS transistor and the N-Channel MOS transi.stor rue cal-acith!cly coLIplcd to the emse node via a tunnel dielectric. The control gate and the err~se glatc may comprisc l~gion.s in the suhstratc cap Lcitively coupled to the floating gate or may complisc poly.silicon lines cal)acitivcly coupled to the floating gate.
According to another aspcct of thc prescnt invention, a MOS transistor switch may 15 be connected to the OlltpUI nodc of thc two-transistor. zero-power, electrically-alterable non-volatile latch elemcnt of the present invcntion. The state of the latch controls whether the transistor is tumt,d on or oft~. Thc draill and sourcc of lhe MOS transistor switch may be connected to circuit nodes which may bc selcctively comlcctcd togcther by programming the two-transistor, zero-power, electlically-alterablc non-volatilc latch eiemcnt.
Tile two-tmnsistor~ zelo-powcl, clcctrically-alterable non-volatile latch element of the prescnt invcntion may bc l'alllicalcd using a single polysilicon gate process in which the control gate and crasc node.s arc folmrd i;om dillu.scd regiolls hl a s Ill,.olldu~lul substrate. Alternately, the two-transistor, zclo-p()wcn electrically-alterable non-volatile latch element of the present invention may be fabricatcd using a dollble polysilicon gatc process in which the control gate and erase nodes are iormcd t;om regi()ns of thc second levcl polysilicon layer.
Brief Description Of The Drawings FIG. I is a schcmalic diagr.lm of a tu!o-transistor, zero-power, electrically-aiterable non-volatilc latch element acc(llding to Lhe present invention.
FIG. ? i.s a grQrh .showing thc transl'cl Clla~ L~ Li~b of the two-transistor, ~ro-power~ electrically-altrr;lhle non-volrtile latch clement of FIG. I in both its programmed and .. . . . . . . . .. . . . . . . . . .
WO9~/21273 ~qa~5~ PcrlUSs61~03tl6 ~
erased stntes.
FIG. 3 is a top view of an illustrntive ~ o ~dul ivr layout of the two-transistor zero-powcr electrically-allerablc non-volatile la~ch clemen[ of FIG. 1.
Fl('l. 4 is a cross-sccti-mal view of ~hc illustrative s~ ;.. l.. tOl Ltyout of thc two-5 transistor zero-power eleclrically-alterable non-volatile latch elerae~nt of FIG. 3 taken through lincs 4-4.
Fl(G. 5 is a schcmalic diagram of a two-by-two array of two-transistor zero-pouer elcctrically-alLerable non-volatile latcll elcments according to another aspect of the present invention.
Detailed Description Of A Preferred Embodiment Those of ordinary skill in the art will realize that the following description of the present in~cntion i5 illustrati-e only and not in any way limiting. Other embodiments of the invention ~vill madily ~su~gcst themselves to such .skilled persons.
Refcrriny~ finst to FIG l a two-transistor. ~e.ro-power. electrically-a!terable non-volatile la~cll elcme-lt 10 Or Ihe l~rescnt invention is scen ~o connprise u P-Channel MOS uarlsistor 12 and an l~-Channel M~S transistor 14 cmllilL~ured in the martner of a well-lcnown invener. The source 16 of P-Channel MOS transistor l 2 is a difl'u.sed region in a ~t~mi~--nd~lrtor suhstrale and ts connected tn ~icc potenti~l~ it5 drain 18 is a diffused region in a .s~.,.;~ oi~Ju~ substrate and is also lhe drain of N-Channel MOS transistor 14. The source 20 of N-Channel MOS transistor 14 is a diffu.sed re~ion in a ~mic~ { lor substratc and is connected to ground potential. The common drains 1~ of P-Channcl h~OS transistor 12 and N-Channel MOS transistor 14 forra an output nodc 22 t'or the latch clcment.
A common ~loalin~ gatc 24. which may be formed from a layer of doped polysilicon as is ~nown ;n the art. i~s as~sociated wilh both P-Channel MOS transistor 12 aad N-Channel M(3S transislor~14. Fk~ating gale 24 is ~a~ ;Li~ly coupled to an era~se "gate'' node 26 via a tunneling dielccllic as is known in the arL
P-Channel ~IOS transi~slor 12 and N-Channel MOS traasistor 14 share a common contlol "gate'' nodc 28. Control gatc 28 i~S ~--t a.i~ ly coupled to floatin~ gate 24 and raay . . . _ . , . , . _ _ , , WO ~6121273 2 t 9 3 3 5 9 PCr/Uss6/00306 comprisc f'or cxamplt a scpLIrrnc dil'fuscd region in thc .~r~mi~on(h.m. r substrate.
The two-transistor. ze.lo power electrically-allerable non-volatile latch element 10 of the present invenlion is slable in two states a programmed or "on" state and an erased or "off ' stalc. Thc two-transi.slor zero-po- er elecllical]y-alterable non-volatile latch element of the 5 present invenli(m 10 may hc programmcd by raising the common control gates 28 of the P-Channel and N-Channel l~lOS transislllrS 12 and 14 to a programming voltage Vpp while the erase node.26 is held al zelo v()l~s. Thc floaling gale 22 is coupled high because of the capacitive coupling to the control gales 28. If' Ihe eleclric field across the tunnel dielectric exceeds the minimum field required t'or Fo~lcl-N'(lldhcim mnnelil1g elcctrons will tunnel across the tunnel 1 0 dielectric lo thc ffoaling ga~e 24. Thc tmpped el-cctrons increase (i.e. make more positive) the threshold of Ihc N-CIlannel M()S Ir:lnSiSlol 14 alld decrease (i.c. make more negative) the thres}1old of Lhc P-Channel MOS iransi.slor 12. Afler the programming voltage is removed the conlr( l ~alc~S 28 ale hc]d al rlound llolcnlial. The output of thc latch al node 22 will be at approxima~ely Vcc since the N-Challncl MOS Uan.sislor 14 is turned off and the P-Channel MOS
1 5 transistol 12 is turncd nn.
To erase the two-trclmsist()r zero-powcl clectrically-alterable non-volatile latch element 1() of the E~rcscnl inventinn thc contr(il gates 28 arc held at ground potential and the erase node 26 is raiscd to Vpp. Thc clcctrical field established across the tunnel dielectric will cause eleclrons lo tunnel OUI of thc floating ~atc 24 thus makin~ it more positive. l'he positive charge on 20 the. floaling ~ale dccrea.se.s (i c ~ makc.s less positive) thc thlcshold of the N-Channel ~IOS
tr:msistor 14 and incrc.ascs (i.c.. mal;(.s more po.sitive) tl-c threshold of the P-Channel MOS
transistol 12. Af~cr thc pro- rammin~ volt~ge is rcmo~!ed thc control gates 28 are held at ground polential. The OUtpUI c f Ihc la~ch at n(ld. ~2 will hc at approximalely ground since the N-Channel MOS tr tnsislor 14 is turncd on :md Ihe P-Ch tnnel MOS transislol 12 is turned off.
FIG. 2 is a glaph showing lhc tlan~sfercll~ ;LLl;sli~s of the t o-transistor ~ro-pouer ele~ctllcQlly-allcrahlc noll-volatilc latch elcmenl of FIG. 1 in both its programmed and erased s~a~cs. FIG. 2 illus~r:ltcs thc opcralion of thc latch as described above As may be seen from an e~ lTnin ~ l of FIG. Ihe solid line 3(1 represcnts thc llOrmal voltage tranSfer .l~ .L~l~Li. of a C~IOS invertLn. Thc dashcd linc ~2 rcpre.scnt.s the currcnt flo-v through the inverter as a functiol1 of ~hc OU~pllt voltagc. 'I'ht~ nc_ative peak Or the currcnt nOw curve represents the point at ~hich hoth the P-C.hanllel h.lOS Iransist(ll and thc N-Channel h IOS transistor are conducting.
The s~raight dashcd line ~4 in FIG. 2 rcpresent.s the operating point of the inverter when electrol1s have hccn tunnclcd on~o thc floLIting ~ate by the programming operation. The wo 96/21273 2 l ~ 8 3 5 9 PC'T~lJ~96/OfJ306 ~
omput ~olL;t~e is a~ a ma~imum ilnd Ihc currcnt tlow is zel~. The stra~ht dashed line 36 repre.sents Lhe opcr tting point of ~hc inver~ r when electtons have been lunneled off of the floadng~
gate hy the era~se operation. The ou~put voltace is at a m;nimum artd the current flow is zRro.
Thus it may be seen that the latch Or tl c plesent invention exhibiLs no current flow in either its 5 ~J~ alllllled or erased slate.
I'ho~se ot ordinary shill in Ihc. an w ill recognizc Lhat Lhe latch sLructure of the present invention is a stahlc S~l'UC~UIl~. Expcricnce with tloating gate transistor device.s has shown that suchde~ice.srcliahlyreLainthcirlk).llinc gaLe chugcrorpcriodsintxcessQftenyerlrs.
The lalch SLruCtUrC of FlG. I may hc used to drive a number of different devices.
10 ~s will be disclo.sed heieim the la~cll Or ~llc prcscnt invention may be r ~IVUnLU g ~ ~U~1Y employed to d}ive a paSc transistor whosc statc may he used 1() control the selective formation of illLel~ul~lec60n ncLs in an inlcglllt~ d circtlit.
Retclting now to FIGS. .~ an(l 4. ân illusLrative e.mbodiment of the latch of the present invention as cnnhodied in scmiconductoI materiltl is showm FIG. 3 is a top view of an 15 illustrative semi-onductot layout of thc two-transi.sLor~ ~ro-powel electrically-alterable non-volatile latch element of FIG. I . FIG. 4 i.s a cro.ss-sf c~ional view of dle illustra~ive c~ miron~ rtor layout of Lhe two-tran.sistor ~ero-p(twci cle.ctrically-alterable non-volaLile latch element of FIG. 3 tahcn throut~h lines 4-4.
Tllc P-Chttltncl M~ u.Lnsi!;tor 12 of FIG. I is disposcd in n-well 4(1 rlnd its source 20 and drahl comprisc p+ dift;lsc t l~~ioll.s 42 and 44. rcspcctivcly. The N-Channel MOS transistor 14 of F~G. 1 is disposed in ~he ~3-typc semicondllctor substrltte 46 (rno~e easily seen in FIG. 4) and its drain and sourcc re~iol1s complisc n+ diftused regions 48 and 50 respectively. Metal strip 52 is used to conncct p+ diffu~sed 44 tn n~ diffused region 48 viâ contacts 54 and 5G. Vcc metal line 58 is connected lo p+ dit'ftlsion 42 vin contacts 60 and ground metal line 62 is connected to 25 n+ ditfusion 5() via contacts 64 Tho.se of ordinary skill in the art w;ll observe that double contacts are shown in the layo-n ol' FIG. ~. but will realize that single contacts may be employed instead.
Floatillg g~ate 24 of FIC~ I is Lomlcd f rom a single layer of polysilicon 66 having extending finger 62 disp()scd ahovc Illc channel re~ion between diffused regions 42 and 44 30 forming the floating galc p(irtion Or P-Channcl hlOS transistor 12. A second extending finger 70 is disposed above the chamlcl rcgion hctween diftu.sed legions 48 and 50 forming the floating gate portion of N-Channcl 1~10S transislol 14. As will be a~Jl~iat~d by those of ordinary skill in tlte 21 q8359 ~ WO 96i21273 PCT/U596/00306 art. the source and drain diflu.sion.s i;)r iioth the E' Channel and N-Channel MOS transistors 12 and 14 may bc formed usinC ~sclf-aligncd gatc techniques as arG known in the art.
The commou contlol gates of P-Channel MOS transistor 12 and N-Chanrtel MOS
transistor 14 may be formed a.s a high-voltagc n-type. dift;lsed region 72 in the substrate. High-5 voltage n-type difi'used rcgion 72 should be formed so as IO ~vithstand the ci~ t d Vpp voltage vvith an appropriat-c margin as is well understood in the art. The high-voltage diffused region 72 is capacitively couplcd to an en]argcd portion of the overlying polysilicon fioating gate strip 661o enhance capacitive coupling. A dielcctric layer 74, typically forrned from high quaiity oxide as is knowll in the art, to a thickness of tt()m about 50 tn ahout 130 angstroms, preferably about 8() ang~stroms~ .scp:~rate.s tbc diffuscd region 72 t'rom the polysilicon fioating gate strip 66 and lorms couplillg capacitol 76. The III'CI of a typical couplinr capacitor 76 is about 7 to 10 times the area of the, tunnelillg capacitor.
Thc Cl'IISC nodc ol latch I () of FlCi. I is lormed as a high-voltage n-type diffused region 78 in thc ~suhstratc. As ~vith hich-volLagc n-type dit'fuscd region 72, high-voltage n-type 15 diffu.sed regioll 7~ shollld also hc l'ormcd so as to witllstand thc ~u, , ' --i Vpp voltage with an appropriate margin as bi ~ cll undclstoùd in the arL A tlmneling capacitor 80 is t'ormed by the s,~ ", of thc dil1uscd regioll 78 witll thc ovel iying polysilicon strip 66~ The polysilicon layer 66 is separated t'rom thc diffuscd region 78 hy a lunneling dielectric layer 82 typically formed from high quality oxide as is known in the alt, to a thickncss of about 50 to about 130 angstroms, 20 prefcrahly about ~() ancstlom.s. I'he. area of a typical tunneling capacitor 82 is about the smallest feature size ~hich c:ln he prinLtd u~sing phototlitilograrhy techniques, or may be fonned by an overlap of thc soulcc/dlain cliffilsion with UlC polysilicon lloat;ng gate.
Those ot' ordinary si;ill in the art will rccogni7.e that, while the ~mbo iimt~nt iiiustrated in FIGS. 3 :md 4 cmpR~ys "gatc" elcmcnt.s which alc actually disposed in the subsLrate, 25 diffused rcgions 72 tnd 78 could easily hc replaced by polysilicon lines formed in a second layer of polysilicon as is ~!cll-knnwll in thc EPROM and EEPROM art. Such structures are equivalent to the s~ructllrcs depiclcd in thc rlgurcs hcrcin and are thus inlellded to fall within the scope of the present invcntion.
In a typiclll e,n-hodimcnt llf thc pr-scnt invention, the latch elements may be 30 proc~rammed and erascd hy a Vpp ~oltagc in the rangc of about 1() to about 15 volts.
As may he seen t'rom an t~Y Imin ~l ion of FIGS. 3 and 4, because the control and erase ''gates" arc forn-cd i'rom dopcd region~s in thc ~sub~strate, the two-transistor, zero-power, 3 2 1 ~ 3 ~ ~ ~ r~
electrically-nlterable non-volatile latc~h elemenl of the prcsent invention may be fabricated as a part of a c(mve.nlional single-level poly.silic on galc C~IOS integratcd circuit fibrication process. Such a process begins ~vïth Ihe convcnlionlll ster,.s for forming lhe n-wells, the field implant and field oxidation stcps.
Tlle high-voltage n-type regions complising the erase gate and control gate lines are then formed in the. substrate using buried n+ ma.sk and implant. Alternatively, the crase gate can also be t'cllmed in the n-typ. .~u~ c~;naill difrusinn usin~ known high-voltage techniques.
Next~ a tunncl ~indo~ is etched tCl expûse the hi~h-~,oltage n dit'fusion comprising the global era.se line and thc t~mncl diclecuic is iolmcd, prelelahly t;om high qualhy oxide, and is thcn dclincd hl thc tunncl windo~v. Thc poly.siiicon layer u hich will comprise the floating gate is thell forlllcd. dopcd and det'incd, u.sing coll-clltional scmiconductor processing technology.
Thc gate cxidc step ~or thc iormation of o~hc} P-Channc~l and N-Ch~t:tnel transistor devices on thc intcgratcd circuit is thcn pcr.''ormed. follo~-ed by deposition, doping, qnd definition of thc pol~silicon gates fur tho.~ othcr transistor dcYiccs. Il the global erase and control gates an~
to be t'orrmcd from polysilic-~n laycrs, an inter-poly oxid~ is lormed, windows are etched to expose regions of lh. flolting galc, and lhc lunncl diclcctric and control gnte capacitol dielectrics ate forme~d prior to pc rforming lhe g~cltr poly deposition .step. An implant oxide is formed, fol]ûwcd by lhe masking Imd implant ste,os ncccssaly to form both the P-Channel and N-~hannel sel.f-ali,~ncd ~sourcc and drahl rcgions.
Next. BPSG dcposition. contact window formation, and first level metal steps areperformcd usin~ conven~ nal .semic(~nductor pllXesSilig techniques. Subsequent metal layers art~i other back-elld processing muy thcn bc pcr~ormcd as ~s weU known in the ait.
Tllc det;lils of thc individual proccss .stcps uscd in the fabrication of the two-transistor, zelo-p(lwcr, elcctricall~-allcrablc non-volalile latch element, such as timcs, ~e~ e~,~lu~us, doscs, thic~nesses, etc.~ arc well known in the art for fortnation of CMOS devices and ha~ c tllcleforc n(lt hccn r cc itcd herci n. As will bc recooni~ed by persons of ordinary skill in the arl, the proccss dc.scri~cd herein for the fablicalion of Ihe latcll of the present in~entioù may be practiccd using standal d Ch/lOS proccssillg steps. and employing c(mventional layer thinkn~
implant dosugcs. clc. Thc additional processing stcps used to rorm the flûating gate, tunnel dieleclric, and capacitors for ~hc c~mtrol and crase gates are well known in the EEPROM auld EPROM art and alc not repcated hele in order to avoid u~ " ,~g the disclosure.
~ Wo 96121273 2 1 9 8 3 5 ~ r~
As m~y also hc secn l'rom an cxrmination of FIGS 3 and 4, the latch 10 of the presen~ invention may bc formcd as n compact str-lct-llc The layout shown in FIGS 3 and 4 readily lends i~self to the Liyout of ~m allay of latciles Such an anray could be usefully employed in devices ~such a~s u~ser-prt-gl.lmmahlc circuits (e g, FPGA integrated circuits) The outputs of 5 the latches would bc uscd to dri~c tr,lnsislclr switclles to selcctivcly make ;~ c in the user-programmahlc intecralcd CilCUitS
Such an array ')t) oi' two-tr;lllsistor zero-power, electricaily-alterable non-volatile latch clemcnts is shown in FIG 5 in schematic i'orm according to another aspect of the present invention Thc array 90 includcs a plurality of two-transistor zero-power, electrically-alterable 10 non-volatilc latch eTemc,nts al l-lll]gcd hl rows and columns In FIG 5, the latch elements are sho~wn as squarcs and de~signQtcxl witll rcrcrcncc mlmcr.lls 10-1 1()-210-3, and 10-4 Although the illustrativc Irrlly 9() Or FIG 5 is ihown comprisiilg t--o rows and two columns, those of ordinaly skill in thc urt wili rcadily rcco,,T~ c tllat tllc al r~y Or FIG 5 is for purposes of illustraùon and thatmuch lalgcraurays arc pl';lC~iC,II aCCOrdillr tO thc prcsciltinvention Lltch elcments 10-1 and 11)-2 folm Itlc first row of array 90 and latch elements 10-3 and 1()-4 form thc sccond r(lw of an.ly 90 ~imilarly. Iatch elements 10-1 and 10-3 form the first COTUITlll of anay ~() and la~ch clcmcnls 1(1-' und 10- i iolm the second column of array 90 Each latch clcmcm h~s :Is~s()ciQtcd ~ ith it ~ puss tr~msistor These transistors are labellcd witll re~crellcc numcmls 92-1 thlougll 92-4~ thtc numcric suffixes corresponding to the 20 numeric~ sui'fixcs of thc latch clcmcnt willl which c~ch pa~ss transistor is associated The gate of each pass transistc r is conncctcd to thc mltput nodc of its associatcd latch element As illustrated in FIG 5, pass ~r~nsLs~ors 92-2 througTI 92 4 arc shnun as NT-Channel MOS transistors, but those of ordinary skill hl thc ~rt wili rcco,lli~c lhQt othcr types Or devices may be used for different .~pp~ m, ,i without de; artinC l;om ~hc p rinciples of ~hc prcscnt invention 'I'he~ individu,ll latch clcmcn~s 1()-1 throurh 1()-4 in the array 90 of the present in~!ention may hc addres~scd and ~ug, mnn~d or may be erast d ln the configuration of the array depicted in FIG 5 a glohal cmsc modc is provided. althc)ugh those of ordinary skill in the art will easily understand ilOU' to cmlfigurc ~n arrQy in whicl1 the latch elements could be indiiidually erased In ~hc all-lly ~)() ol' ihc p rcscnt invcl1ti()l1 sclect transistors 94-1 through 94-4 are useci to selcct thc indivi(iu;ll latch clcmcl1ts r~., pr ogrammi,lg. As with the pass tr~ncictc r~,thP, numeric suffi~e~s of the sclcct tmnsismns hl rlG. 5 colTespond to the numeric suffixes of the latch 21 ~359 wo 96/21273 P~~
element with which cach pass transislor is associatcd. The select transistors !~4-1 through 94-4 are used to delivcr the ~ lhly voltage to sclected ones of the latch elements to program them .
The gates of selcct transistors 94-1 and 94~2 are connected to a first row line 96.
Thc gatcs of selcct transistors 94-3 and 94-4 are connected to a second row l;ne 98. The drains of select transist()rs 94-1 and 94-3 arc connccted to a first column line 100. The drains of select transistors 94-2 and 94-2 al~ connected to a second column line 1()2. 'I'he source of each of the select transistors is connected to the input node (the common control gates) of its ~;u~ t~ dillg la~ch element.
Glohal crasc I illC 1()4 i.s shown connected to each of the latches 1(1-1 through 10-4.
The glohal cr tsc linc is conncc~cd to th. erase nodc Or each of tlte latches and is u.sed to erase or re.sel all ot' ~hc latcl1e.s simul aneously.
Dul ing ~hc opcratin~ modo of thc array 9r) of the prcsent invention the row Iines 96 and 9g arc kept at T~ro volt.s SC1 that .sclcct transistors 94-l through 9~4 are turned off~ When it i.s dcsircd to pr()gram 011C o f tllc lalcl1 clcments l O- I through 10-4 of the array 90 the row lines and the column lines Irc uscd to sclcc~ thc latch to be programmed and to deliver thent appropriate voltagcs to the selectcd latcll.
To pro~-rrm 011C or morc dcsired latche.s it is llrst advisable hut not necessary to erase all of ~he latcllcs in oldcl lo SCI ~hcm all to a linown statc. This is done by connecting all column lines 1(1 and 1(14 to yro~lnd tulning on all select transistors 94-1 through 94-4 to place ground on the common col1lrol gatc.s of Illc N-Channel and P-Channel MOS transistors and by applying the. proyrammirty~ ~oltay.l Vpp to the global erase linc llM. As de~scribed previously for a sinyle latch examplc. ~his action w;ll causc~. elcctrons to tunnel from the floating gates of all of the latche; thus rendeliny them more positi~c. Altcr crasi1lg all of the N-Chamlel MOS transistors 14(E::lC.l~in~lleilldividuallalch-swill bol-lmcdonandalloftheP-ChannelMOStransistorsl2 (FIC,. I) will bc tumed ~'11. rrhc Olltpllt.S of all of the latches will go to ground.
Oncc all of thc latchc.s are placed in a known state ~erased) any one or more of the latches 10-1 through Ir)-~ may hc prog~arllmed. Ush1g the e~ample of prQErn~n~nin~ latch 10-3 second row linc 9~ is hrought to Vl-p while first row line 96 is kept yrounded. Vpp is also placed on filst columll linc 1 (Nl wllilc sccond column line 1()2 is kept grounded. The global erase line 104 is also kep~ grounded. This action turns on selcct transistor 94-3 placing Vpp on the common control gatcs of thc N-Channcl and P-Channcl MOS transistors in latch 10-3. Under 1() ~ Wo !~6/21273 ~ 3 5 9 Pcrlu~96/00306 these conditions, elec~rons arc causcd to tunncl on~o thc fl()atillg gate inside of latch 10-3, shifting the thresholds of the N-Channel and P-Channcl MOS transistors in latch 10-3 ~such that the P-Channel h,~OS transistor is turned On and the N-Channel MOS tr~msistor is tumed off, causing the output of lalch 10-~ to risc to a voltagc ol approximately Vcc.
Because finst ro-v Iint 96 i.s held at grolllld~ both select transistors 94-1 and 94-2 are tumcd ot'r. Becrlu.sc second column linc 1()2 is hcld at ground, Vpp does not appear at the control gaîcs of lhc tran.si.slms h~ latch 1(1-4 CVCll th(mg~lI thc gate of select transistor 94-4 is at a voltaoc which w()uld tum it on if thele W.l5 any voltage at its drain. Thus, no tunneling of electrolls will occllr Onto thc tk-)ating g;l~CS of IDtchcs 1()-1, 1()-2, anù 10-4.
Thc drivinc of lhc various voltagcs ont(1 lines 96, 98, 100, 102, and 104 is providcd hy progrumming cir-uitly 1(~ . Circuitry for gcnemting and s~wilching the necessary voltagcs lor progmmming thc devicc.s ot ~hc preselll invcAntiml is v.~ell known in the art and is a matter of .simplc dcsign choicc. Th.' volL~gc.s may he g( nemted on-chip by charge pumps as is known in thc art or may hc sul-plicd lrom otf chip viil sclccted l/O pin.s as is well known in the art.
Thc two-trrmsistol~ zcro-powcl~ elcctrically-~Llterable non-volatile latch element of the prcscnl invcn~ion will always power op to a dcsircd state oncc it has been pre-programmed.
Unlike somc of thc prior art latcll elemenls, it employ.s in~ pPn~lt~llr read and write paths, thus minimi7ing the rcad distulh plohlcm. Il docs not rcquirc high-voltage n-well technology. It empk)ys a smlll cell .si7.c, mJkin~ it an c~cellen~ candidate for urray applications, and enjoys excellent long-~cn)l dat.l retelltiOIl.
Wllile cmhodimcl)ts all(i applicatiolls of this invcntion have been shown and describcd, it would he apparcnt to thosc skilled in Ihc art that many more modifications than mcntioncd abo-e arc possihlc wi~hcut departing from thc inventivc concepts herein. The invention, therel'olc~ is not to hc rcstrictcd c~ccpt in tdlc .spirit of the appended claims.
Claims (3)
1. A two-transistor zero-power, electrically-alterable non-volatile latch element comprising:
an input node;
an output node;
an erase node;
a P-Channel MOS transistor having a source connected to a source of first electrical potential, a drain connected to said output node, a control gate connected to said input node, and a floating gate capacitively coupled to said control gate;
an N-Channel MOS transistor having a source connected to a source of second electric potential lower than said first electrical; potential, a drain connected to said output node, a control gate connected to said input node, and a floating gate capacitively coupled to said control gate and common to said floating gate of said P-Channel MOS transistor;
said floating gates of said P-Channel MOS transistor and said N-Channel MOS
transistor capacitively coupled to said erase node via a tunnel dielectric.
an input node;
an output node;
an erase node;
a P-Channel MOS transistor having a source connected to a source of first electrical potential, a drain connected to said output node, a control gate connected to said input node, and a floating gate capacitively coupled to said control gate;
an N-Channel MOS transistor having a source connected to a source of second electric potential lower than said first electrical; potential, a drain connected to said output node, a control gate connected to said input node, and a floating gate capacitively coupled to said control gate and common to said floating gate of said P-Channel MOS transistor;
said floating gates of said P-Channel MOS transistor and said N-Channel MOS
transistor capacitively coupled to said erase node via a tunnel dielectric.
2 The two-transistor, zero-power, electrically-alterable non-volatile latch element of claim 1, further including a MOS transistor having a drain. a source, and a gate, said gate connected to said output node.
3 An array of two-transistor. zero-power, electrically-alterable non-volatile latch elements comprising:
a row line for each row in said array;
a column line for each column in said array, each column line forming an intersection with each row line in said array;
a plurality of two-transistor. zero-power, electrically-alterable non-volatile latch elements arranged in array of rows and columns, each of said two-transistor, zero-power, electrically-alterable non-volatile latch elements disposed at one of said intersections and comprising an input node. an output node. an erase node. a P-Channel MOS transistor having a source connected to a source of first electrical potential a drain connected to said output node, a control gate connected to said input node, and a floating rate capacitively coupled to said control gate, an N-Channel MOS transistor having a source connected to a source of second electrical potential lower than said first electrical, potential, a drain connected to said output node, a control gate connected to said input node. and a floating gate capacitively coupled to said control gate and common to said floating gate of said P-Channel MOS transistor. said floating gates of said P-Channel MOS transistor and said N-Channel MOS transistor capacitively coupled to said erase node via a tunnel dielectric, and a select transistor, each of said select transistors having, a source, source connected to said input node, a drain connected to the one of said column lines associated with its intersection, and a gate connected to the one of said row lines associated with its intersection;
a common erase line connected to the erase node of each of said two-transistor, zero-power, electrically-alterable non-volatile latch element in said array;
circuitry for selectively connecting each of said row lines to a voltage selected from ground and Vpp; and circuitry for selectively connecting each of said column lines to a voltage selected from ground and Vpp.
a row line for each row in said array;
a column line for each column in said array, each column line forming an intersection with each row line in said array;
a plurality of two-transistor. zero-power, electrically-alterable non-volatile latch elements arranged in array of rows and columns, each of said two-transistor, zero-power, electrically-alterable non-volatile latch elements disposed at one of said intersections and comprising an input node. an output node. an erase node. a P-Channel MOS transistor having a source connected to a source of first electrical potential a drain connected to said output node, a control gate connected to said input node, and a floating rate capacitively coupled to said control gate, an N-Channel MOS transistor having a source connected to a source of second electrical potential lower than said first electrical, potential, a drain connected to said output node, a control gate connected to said input node. and a floating gate capacitively coupled to said control gate and common to said floating gate of said P-Channel MOS transistor. said floating gates of said P-Channel MOS transistor and said N-Channel MOS transistor capacitively coupled to said erase node via a tunnel dielectric, and a select transistor, each of said select transistors having, a source, source connected to said input node, a drain connected to the one of said column lines associated with its intersection, and a gate connected to the one of said row lines associated with its intersection;
a common erase line connected to the erase node of each of said two-transistor, zero-power, electrically-alterable non-volatile latch element in said array;
circuitry for selectively connecting each of said row lines to a voltage selected from ground and Vpp; and circuitry for selectively connecting each of said column lines to a voltage selected from ground and Vpp.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/369,760 | 1995-01-06 | ||
| US08/369,760 US5587603A (en) | 1995-01-06 | 1995-01-06 | Two-transistor zero-power electrically-alterable non-volatile latch |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2198359A1 true CA2198359A1 (en) | 1996-07-11 |
Family
ID=23456803
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002198359A Abandoned CA2198359A1 (en) | 1995-01-06 | 1996-01-04 | Two-transistor zero-power electrically-alterable non-volatile latch |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5587603A (en) |
| EP (1) | EP0801844A2 (en) |
| JP (1) | JPH10510124A (en) |
| CA (1) | CA2198359A1 (en) |
| WO (1) | WO1996021273A2 (en) |
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| US11887930B2 (en) | 2019-08-05 | 2024-01-30 | iCometrue Company Ltd. | Vertical interconnect elevator based on through silicon vias |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4375086A (en) * | 1980-05-15 | 1983-02-22 | Ncr Corporation | Volatile/non-volatile dynamic RAM system |
| US4495427A (en) * | 1980-12-05 | 1985-01-22 | Rca Corporation | Programmable logic gates and networks |
| DE3171836D1 (en) * | 1980-12-08 | 1985-09-19 | Toshiba Kk | Semiconductor memory device |
| JPS59111370A (en) * | 1982-12-16 | 1984-06-27 | Seiko Instr & Electronics Ltd | Nonvolatile semiconductor memory |
| US4617479B1 (en) * | 1984-05-03 | 1993-09-21 | Altera Semiconductor Corp. | Programmable logic array device using eprom technology |
| US4742492A (en) * | 1985-09-27 | 1988-05-03 | Texas Instruments Incorporated | EEPROM memory cell having improved breakdown characteristics and driving circuitry therefor |
| JPS63211767A (en) * | 1987-02-27 | 1988-09-02 | Toshiba Corp | Semiconductor storage device |
| US4885719A (en) * | 1987-08-19 | 1989-12-05 | Ict International Cmos Technology, Inc. | Improved logic cell array using CMOS E2 PROM cells |
| US4851361A (en) * | 1988-02-04 | 1989-07-25 | Atmel Corporation | Fabrication process for EEPROMS with high voltage transistors |
| US4829203A (en) * | 1988-04-20 | 1989-05-09 | Texas Instruments Incorporated | Integrated programmable bit circuit with minimal power requirement |
| US4822753A (en) * | 1988-05-09 | 1989-04-18 | Motorola, Inc. | Method for making a w/tin contact |
| US5343063A (en) * | 1990-12-18 | 1994-08-30 | Sundisk Corporation | Dense vertical programmable read only memory cell structure and processes for making them |
| US5272368A (en) * | 1991-05-10 | 1993-12-21 | Altera Corporation | Complementary low power non-volatile reconfigurable EEcell |
| US5247478A (en) * | 1992-03-06 | 1993-09-21 | Altera Corporation | Programmable transfer-devices |
| US5424985A (en) * | 1993-06-30 | 1995-06-13 | Sgs-Thomson Microelectronics, Inc. | Compensating delay element for clock generation in a memory device |
-
1995
- 1995-01-06 US US08/369,760 patent/US5587603A/en not_active Expired - Lifetime
-
1996
- 1996-01-04 WO PCT/US1996/000306 patent/WO1996021273A2/en not_active Application Discontinuation
- 1996-01-04 JP JP8521270A patent/JPH10510124A/en active Pending
- 1996-01-04 EP EP96907003A patent/EP0801844A2/en not_active Withdrawn
- 1996-01-04 CA CA002198359A patent/CA2198359A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| EP0801844A2 (en) | 1997-10-22 |
| WO1996021273A3 (en) | 1996-09-12 |
| US5587603A (en) | 1996-12-24 |
| WO1996021273A2 (en) | 1996-07-11 |
| JPH10510124A (en) | 1998-09-29 |
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Legal Events
| Date | Code | Title | Description |
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| FZDE | Discontinued |