CA2210502C - Logic filters for resolution conversion of digital images - Google Patents

Abstract

The present invention is a method and apparatus for logic based resolution conversion and enhancement of digital images. The invention employs a selectively controllable architecture wherein a plurality of input resolutions can be converted to a common output resolution. The system has particular use in highlight color systems, wherein the highlight color data may be processed separately for each color plane, using the present invention, and then recombined to produce enhanced highlight color output. Moreover, the hardware preferably employs an interlocked area mapping technique to produce the resolution converted bit planes of digital image data.

Description

I
Any. Dkt. ~lo. D/95~9' This invention relates generally to an architecture and processing method and more particularly to logic filtering operations that are employed to produce a digital output image at a predetermined resolution from input images having one of a plurality of input resolutions.
CROSS REFERENCE
The following is a related patent:
"VIDEO PATH .ARCHITECTURE INCLUDING LOGIC FILTERS FOR
RESOLUTION CONVERSION OF DIGTTAL IMAGES", Robert R Loce et al., US
Patent No. 5,758,034, issued May 26, 1998.
. The present invention is directed to digital printing systems that handle numerous document and data formats. Such systems are preferably open systems t5 where devices from different manufacturers are integrated to provide solutions to customers' needs. A key feature in such printing systems is enablitig electronic documents from various sources to be printed on output devices. In order to achieve device-independence efficient methods of image resolution conversion or enhancement are required. Hence, raster conversion technology, where a bitmap 'o created for a first output device (e.g., at ?40 spots per inch) is altered so as to be adequately rendered by an output device having a different resolution, is a very important aspect of the open system technology.
Digital documents created on mainframe or similar legacy computer systems may be digitized at resolutions as low as 240 spots per inch (spi) . However, many 25 modem printers operate at 300 spi or 600 spi and it is desirable to enable artifact-free . printing of these ?40 spi source images on 300 or 600 spi printers. While it is known to accomplish resolution conversion using bit or pixel-level conversion (e.g., bit replication), as employed in the Xerox DocuTech Production Publisher and Xerox Atty. Dkt. No. D/95497 4850/4890 Highlight Color Printers, the present invention enables device-independent printing using an area mapping technique during image processing to enhance binary input images having a first resolution and producing images having a second resolution while reducing or eliminating image distortions upon printing.
Heretofore, resolution enhancement has been accomplished using various techniques, including those described in the following disclosures which may be relevant:
Torrey Pines Research, ~~hind H wlett-Packard's Patent on Resolution EnhancementT"'Technoloov, (Becky Colgan ed., BIS CAP International, 1990) pp.

t0 60.
James C. Stoffei et al., A ~rv y of Electronic Techniy es for Pictorial Image R~.~roduction, IEEE Transactions on Communications, Vol. COM-29, No. 12, December 1981.
L. Steidel, Tprhnnlnaw Overview- Resolution Enhancement Technolo ig es fo_r I aser Printers, LaserMaster Corp.
US-A-4,437,122 to Walsh et al., issued Mar. 13, 1984, teaches an improved method of converting low resolution images into images of higher resolution for printing so as to simultaneously increase density and smooth character edges.
In a CRT display or hardcopy output apparatus, the invention is accomplished by converting an original pixel into a higher resolution 3 x 3 enhanced representation.
The status of each of the nine elements in the enhanced representation is determined as a result of an examination of the neighboring pixels of the original pixel.
US-A-4,841,375 to Nakajima et al., issued June 20, 1989, discloses an image resolution conversion apparatus that converts image data having a predetermined pixel density to a pixel density matching that of a printer so as to enable printing by the printer. The pixel density converter includes: a conversion-pixe~ position detector for detecting the position of a converted pixel; an original-pixel extractor for extracting a reference original pixel; a conversion-pixel density operation circuit for calculating the density of a conversion pixel; a threshold-value setter for dynamically setting a 3o threshold value; a binary encoding circuit for digitizing the conversion-image density;

Atty. Dkt. No. x/95497 an input interface for inputting image data; an output interface for outputting image data; and a control circuit for controlling the input/output (I/O) and the conversion operations.
US-A-4,847,641 (issued )uly 11, 1989) and US-A-5,005,139 (issued Apr. ~, 1991 ) to Tung disclose print enhancement circuitry for a laser beam printer.
The bit map of a region of the image to be output is compared to a number of patterns or templates. When a match is detected, a section of the bitmap that was matched is replaced with a unique bitmap section designed to compensate for errors. The replacement bitmap section may include predetermined shifting of some dot positions t0 to compensate for the error in the original bitmap section.
US-A-5,539,866 (issued July ?3, 19961 to Banton et al. teaches increasing the resolution of a binary input image to be printed by an electronic printing system. The method includes storing a portion of the binary input image and determining the binary state of a central pixel and a plurality of pixels neighboring the central pixel and comparing the states of the central pixel and the neighboring pixels to a predefined template. Based upon the comparison, the method detects when a match occurs a multi-bit digital signal is generated as a value associated with the predefined template and the multi-bit digital signal is converted into a resolution enhanced output pixel for printing by the system.
p US Patent No. 5,282,057, issued January 25, 1994, and the corresponding Japanese laid-open patent publication 4-227584 published August 17, 1992, to Mailioux et al.
disclose a method to enable the conversion of binary image data originally generated at a lower resolution into representative binary image data of a higher resolution, wherein the conversion ratio, or magnification factor, is an integer value.
Included within the resolution magnification invention are methods for smoothing the interpolated output image and thereby reducing objectionable visual characteristics.
The following pending patent applications describe image resolution ' conversion methods employing morphological processes: Appl. No. 08/169,487 by Loce et al. (filed December 17, 1993) and corresponding Japanese Patent Appl.
No.

Atty. Dkt. No. 0/95497 7,226,884 on August 22, 1995, and Patent No. 5,689,343, issued November 18, 1997, both of which are assigned to the assignee of the present application.
Publication by Edward Dougherty et al. "Optimal binary differencing filters:
design, logic complexity, precision analysis, and application to digital document processing," Journal of Electronic Imaging, )an. 1996. Vol 5, no.l, p 66-86, discloses statistical and logical properties of template-matching filters. Also disclosed are design methods for optimal template matching filters for digital document restoration and resolution conversion and enhancement.
In accordance with the present invention, there is provided a method for processing a highlight color digital input image signal representing a highlight color image, comprising the steps of: quantization slicing the input image signal to produce at least a first binary image and a second binary image; passing, in parallel channels, -each of the first and the second binary images through a binary, template-based resolution conversion operation to yield an intermediate image, wherea the intermediate image is a high-addressability image; arbitrating between the intermediate image available on the parallel channels and associating a marker with each pixel of the intermediate image, said marker indicating the result of the arbitrating step; passing the intermediate image and associated markers to a lookup table, wherein the lookup table outputs, in response to the image pixel and associated marker a digital signal suitable for driving a pulse-width, position modulated marking engine.
One aspect of the invention is based on the discovery of a new technique for improving the image quality of resolution enhanced images, and in particular highlight color images. The techniques of the present invention are intended to enable the processing of highlight color images wherein the techniques increase the resolution of an input image to a common resolution of a highlight color output device while preserving local average density, stroke or line width and edge position in the output image.
. Such techniques can be implemented, for example, by an image processor working in conjunction with a highlight color printing system. For example, a machine implementing the invention can include the Xerox~ 4850 Laser Printing System or 4890 Highlight Laser Printer.
One aspect of the inventions based on the observation of problems with conventional resolution conversion techniques, particularly techniques that result in strong halftone moire when converting from 240 spi input to 300 spi output. This aspect is based on the discovery of a technique that alleviates these problems by employing a computationally simple, moue-free conversion. This technique can be implemented, for example, using interlocked area mapping techniques and pixel averaging in an image processing architecture designed to provide highlight color image processing.
The techniques describe herein are advantageous because they are computationally efficient, simple and do not require modifications to the output device to achieve the improved image quality.
The present invention, therefore, may be adapted to any of a number of output devices where open systems interfaces require the receipt and rendering of images having various resolutions.
Aspects of this invention are as follows:
A method for processing a highlight color digital input image signal representing a highlight color image, comprising the steps of:
quantization slicing the input image signal to produce at least a first binary image with a resolution Rl, and a second binary image with a resolution R~;
selecting, from a region of neighboring pixels within the first binary image, a first set of input pixels to be converted;
mapping, using a binary, template-based conversion operation, the first set of input pixels to a first intermediate set of pixels at a high resolution R3, where R3 is greater than R,;
selecting from the first intermediate set of pixels a first set of output pixels to produce an image segment of resolution RZ, where RZ is greater than R, and not greater than R3; wherein the selection is accomplished as a function of the input resolution R1;
selecting, from a region of neighboring pixels within the second binary image, a second set of input pixels to be converted;
mapping the second set of input pixels to a second intermediate set of pixels at a high resolution;
selecting from the second intermediate set of pixels a second set of output pixels to produce a second image segment of resolution R2; wherein the selection is accomplished as a function of the input resolution R~;
arbitrating between the first and second image segments to produce an output image; and passing the output image to a lookup table, wherein the lookup table outputs, in response to the output image a digital signal suitable for driving a pulse-width, position modulated marking engine to produce the highlight color image.
1 S An apparatus for processing a digital input image having a low resolution R, to produce a high resolution output image having a fixed resolution RH comprising:
windowing means for selecting, from a region of neighboring pixels within the input image, a set of input pixels to be converted;
mapping logic for mapping the set of input pixels to an intermediate set of pixels at a high resolution R,, where RI is greater than R~ and where R1 is not greater than RH.
a buffer for temporarily storing the intermediate set of pixels; and selection logic, generating as a function of the input resolution R~, and the fixed output resolution RH a selection signal, said selection signal being used in conjunction with the buffer so as to select from the stored intermediate set of pixels a set of output pixels to produce an image segment of resolution RH, wherein the selection is accomplished as a function of the input resolution RL.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a block diagram of a system implementing logic filtering operations in accordance with an aspect of the present invention;
Figure 2 is an illustration of an exemplary template-based mapping window and the relationship between the window and an area mapping region;
Figure 3 is another illustration of an exemplary template-based mapping at an input resolution different than that of Figure 4;
5a Figure 4 is an illustration of an exemplary area mapping region;
Figure 5 is an illustration of the area mapping region of Figure 4 with further indications of the mapping between input and output pixels in accordance with an embodiment of the present invention.
Figure 6 is a block diagram illustrating an aspect of an improved system capable of 3t accomplishing the resolution conversion of a nluralitv of different input Atty. Dkt. No. D/95497 resolutions so as to produce a primary output resolution in accordance with area mapping techniques;
Figure 7 illustrates an area mapping region for accomplishing an exemplary 240 spi to 600 spi resolution conversion in accordance with the system depicted in Figure 6; and Figure 8 illustrates an area mapping region for accomplishing an exemplary 300 spi to 600 spi resolution conversion in accordance with the system depicted in Figure 6.
The present invention will be described in connection with a preferred embodiment, however, it will be understood that there is no intent to limit the invention to the embodiment described. On the contrary, the intent is to cover all alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims.
For a general understanding of the present invention, reference is made to the drawings. In the drawings, like reference numerals have been used throughout to designate identical elements. In describing the present invention, the following terms) have been used in the description.
The term "data" refers herein to physical signals that indicate or include information. For example, a binary item of data, also referred to as a "bit,"
has one of two values, interchangeably referred to as "1 " and "0" or "ON" and "OFF" or "high" and "I ow."
A "circuit" is any physical arrangement of matter that can respond to a first signal at one location or time by providing a second signal at another location or time.
z5 Circuitry "stores" a first signal when it receives the first signal at one time and, in response, provides substantially the same signal at another time. Circuitry "transfers" a first signal when it receives the first signal at a first location and, in response, provides substantially the same signal at a second location.

Atty. Dkt. No. D/9549~
A "data processing system" is a physical system that processes data. A "data processor" or "processor" is any component or system that can process data, and may include one or more central processing units or other processing components.
A "logic operation", for example an operation accomplished using a logic circuit, is an operation that obtains a result using each bit of an operand independent of values of other bits of the operand. NOT is an example of a logic operation that uses one operand. OR, AND, and XOR are examples that use two or more operands.
An item of data "defines" an image when the item of data includes sufficient information to produce the image. For example, a two-dimensional array can define t0 all or any part of an image, with each item of data in the array providing a value indicating the color of a respective location of the image. Each location in an image referred to herein as a "pixel." A "pixel" is the smallest segment of an image whose value is indicated in an item of data defining the image. In an array defining an image in which each item of data provides a value, each value indicating the color of a t5 location may be called a "pixel value". Each pixel value is a bit in a "binary form" of an image, a gray scale value in a "gray scale form" of an image, or a set of color space coordinates in a "color coordinate form" of an image, the binary form, gray scale form, and color coordinate form each being a two-dimensional array defining an image. An operation performs "image processing" when it operates on an item of data that relates 2o to part of an image.
Pixels are "neighbors" or "neighboring" within an image when there are no other pixels between them and they meet an appropriate criterion for neighboring.
For example, if the pixels are rectangular and appear in rows and columns, each pixel may have 4 strongly connected neighbors, 4 weakly connected neighbors, r 8 25 connected neighbors, or neighbors defined by a window.
An "image input device" or "image input terminal" (IIT) is a device that can receive an image and provide an item of data defining a version of the image.
A
"scanner" is an image input device that receives an image by a scanning operaion, such as by scanning a document.

Any. Dkt. No. D/95497 An "image output device" or "image output terminal" (IOT) is a device that can receive an item of data defining an image and provide the image as output. A
"display" and a "printer" are both image output devices that provide the output image in human viewable form. The visible pattern presented by a display is a "displayed image" or simply "image."
Turning now to Figure 1, illustrated therein is a block diagram of a system for implementing logic filtering enhancement on a highlight color image. As will be appreciated by those skilled in the art, a highlight color image at a point within the image rendering circuitry typically comprises a pair of binary images, each a different io color, superposed with respect to one another. Often such images employ a black image and an alternate color image such as red. Hereinafter, the highlight color image may be referred to as having three components, black (K), red (R) and a white or non-printed regions (IM.
As seen in Figure 1, the highlight color inputs K, W and R are supplied in a 2 bit/pixel format, where three of the four levels are used to indicate a white, red, or black mark for a given pixel. Any number of image input terminals may be employed to produce the K,W,R input information, including printing systems designed for mass mailing or billing purposes where customized colors or logos are printed on non preprinted stock.
zo In the embodiment depicted in Figure 1 the highlight color inputs 20 are directed, depending upon the input resolution, into one of two distinct channels in the image processing system 24. In particular, channel A is intended to handle 240 spi input and channel B 300 spi input. Once directed to the appropriate channel, the general processing methodology continues in essentially the same manner in each channel. Accordingly, the following description will be directed to a single channel, channel A. At split buffer 28A, the K, W, R signals are divided or split into two bit planes indicated as Blk/NBIk (Black / NOT Black) and Red/NRed. Essentially, the split buffer splits the 2-bit/pixel input into two distinct bits, one for each of the two colors in the highlight color system. Bit-slicing or level-slicing (threshold-based) are 3o quantization slicing techniques employed to separate the signals. The single-color Any. Dkl. No. D/95497 plane pixel values (data) are then fed, in parallel to template maps 30A, where an area mapping process is employed to convert the pixels at an input resolution of 240 x 240 spi to an output resolution of 600 x 300 spi as will be described with respect to Figure 2.
Once mapped to the output resolution, the high addressability output (where each 1 /300" output pixel is represented by 2 bits in the fast-scan direction), having been grouped into 2-bits per pixel is passed to arbitration/serialization block 34A. At block 34A the arbitration process selects the output color should both the black and red planes indicate a pixel is to be marked. In one embodiment the arbitration may be l0 to simply select the black pulse in the case of all conflicts. However, other arbitration schemes may be employed, for example the arbitration circuit, such as disclosed by Cianciosi et al. in US-A-5,479,175 "Method and Apparatus for Enhancing Discharged Area Developed Regions in a Tri-level Printing System", hereby incorporated by reference, may be employed to select between the enhanced resolution black or highlight color output pixels. In one embodiment, the arbitration, step may associate an arbitration marker with the output so as to indicate the results of the arbitration. It will be appreciated that the use of an arbitration result marker or the actual selection of the black or red output are equivalent and one or the other means for arbitration may be employed depending upon the hardware embodiment or subsequent processing necessary. After arbitration, the bit-stream is serialized using a buffering capability also found within block 34A, so that the area mapped output pixels can be output from block 34A as a serialized stream of bits. It will be understood by those skilled in the art of digital image processing that a buffering operation is necessary in order to take a block or array of image pixels that have been mapped and convert them into a stream of data representing a series of scanline delimited rasters for rendering by an image output terminal.
Having produced the serialized high-addressability output 600 x 300, the data is passed through MUX 38, where the channel output, A or B, is selected based upon the input resolution. The output of MUX 38 is then passed to PWM translation block 40, where the resolution converted, high-addressability data is translated to pulse-Atty. Dkt. No. D/95497 width modulated output signals as described by Cianciosi et al. in US-A-5,479,175.
For example, the image data and associated markers (e.g., arbitration) rnay be passed to a look-up table (LUT) 40, wherein the lookup table outputs, in response to the image pixel and associated markers a digital signal suitable for driving the pulse-width, s position modulated marking engine. The possible outputs resulting from the production of high-addressability output being: white, black, black-left (grayl ), black-right (gray2), red, red-left (pinkl ) and red-right (pink2) and perhaps even combinations of pink and gray. This is an enhanced range of output states relative to the K, W and R
previously produced by highlight color systems.
1o Having described the basic operation of an embodiment of the present invention, attention is now turned to Figure 2 which is an illustration of an exemplary template-based mapping window 50 and the relationship between the window and an input pixel region 60. More specifically, the mapping operation carried out in the template mapping blocks 30 in Figure 1 are accomplished using a 6 x 6 observed 15 window of input pixels 42 as seen in Figure 2. Within the observed window, a smaller input mapping region 60 is employed. In the 240 spi to 600 x 300 spi conversion illustrated by Figure 2, the 2 x 4 input pixel mapping region 60 is employed to produce the 5 x 5 output pixel mapping region 60', wherein each input pixel maps to approximately 3 1/8 high addressability output pixels. It will be appreciated that 2o template-based techniques may be employed to determine the output states of one or more of the pixels within output pixel mapping region 60'. As illustrated a template-based mapping window 50 may be employed as indicated to determine the output state for all output pixels that map to the input pixel indicated by the circle 54 in Figure 2.
'S In a similar manner, Figure 3 illustrates template-based mapping at an input resolution of 300 spi - as would be processed in accordance with the steps previously described, but through channel B of Figure 1. Specifically, Figure 3 depicts a 6 x 6 observation window 68. Within the window, a 2 x 4 input mapping region 80 is Atty. Dkt. No. D195497 employed to produce the 4 x 4 output pixel mapping region 80' (each input pixel mapping to 2 output pixels).
Turning now to Figure 4, there is illustrated an area mapping region for the spi to 600 x 300 spi resolution conversion operation accomplished in blocks 30A of Figure 1. In Figure 4 the positions of the input pixels are outlined as rectangular areas 90 whereas the output pixels are indicated by elliptical regions 92. As will be observed, there are approximately 3 7 /8th output pixels for each input pixel.
Moreover, various output pixels are split between one or more input pixel positions so as to make the operation of image-artifact-free mapping input pixels to output pixels more difficult, but enabling the use of interlocked mapping techniques such as those described by R. Loce in Application No. 08/451,376, hereby incorporated by reference, to avoid the objectionable image quality obtained with well-known bit-replicating resolution conversion techniques.
Figure 5 depicts the interlocked mapping that is preferably employed as an aspect of the present invention. Referring to Figure 5, each of the eight input pixels 90 has been assigned a reference number in the form column.row. For example, the upper left input pixel is in the first column, first row position and is identified by the reference numeral 1.1. Most of the output pixels 92 have been mapped or related to one of the input pixel positions and the mapping is indicated by various fill patterns 2o within the output pixe) ellipsis. The output pixels within the 5 x 5 array are referred to hereafter as a cluster. The individually grouped sub-clusters, subsets of the cluster, each contain only those output pixels that will be mapped to a common input pixel value. As will be seen, there are a total of eight sub-clusters within the 5 x 5 array of output pixels. To further illustrate the interlocked aspects of the mapping operation, the centers of the pixels within each sub-cluster have been connected by a bold line, for example line 98. As indicated by the bold lines connecting output pixels With the sub-cluster it is apparent that adjacent sub-clusters preferably do not have a common shape. The non-symmetrical nature of adjacent sub-clusters is preferred so as to avoid t1 Atty. Dkt. No. D/95497 adding structure to the output image. Mirror or rotation orientations of the preferred cluster scheme are also equally preferable.
Although the sub-clusters account for the majority of the output pixels, it will be appreciated that because of the equality in the numbers of pixels in each sub s cluster there are pixels not associated with any sub-cluster. In the example illustrated in Figure 5, the non-associated or remainder pixel 102 is positioned in the center of the S x 5 array. The output state of remainder pixel 102, or for that matter any remainder pixel, is preferably determined so as to preserve the average density of at least the local region surrounding the remainder pixel. In accordance with the present i0 invention, the remainder pixel output value is determined by first averaging the density of at least two input pixels to determine a local average and then binarizing the average value and setting the remainder pixel equal to the result of the binarization operation. In particular, a preferred method of arriving at the output value for pixel 102 would be to average the values for the four input pixels in the 15 center-of the 2 x 4 input pixel array, and then apply a threshold to determine whether the high-addressability output should be a mark (e.g., black or red) or no mark (e.g., white). Although a threshold has been described as the binarization operation, it will be appreciated that any number of possible techniques may be employed, including forms of halftoning-based thresholding. By averaging the input pixels, the present area 20 mapping operation maintains the average image density for the local region of the image. By employing an interlocked arrangement for the sub-clusters, the area mapping operation not only preserves stroke and line width and position, but also eliminates the potential for objectionable moire as a result of the resolution conversion. A less costly treatment of pixel 102 simply includes it within a 25 neighboring cluster.
Having described one embodiment of the present, attention is now turned to an alternative embodiment of the resolution conversion apparatus and method previously described. In particular, reference is made to Figure 6 which is a block diagram illustrating a system capable of accomplishing the resolution conversion of a plurality 30 of different input resolutions to produce a primary output resolution. The akernative Atty. Dkt. No. D/95497 embodiment preferably substitutes the circuitry represented in Figure 6 for the template map blocks 30 in the embodiment of Figure 1: In particular, the template map blocks take a region of the input pixels and map the values of the pixels to a plurality of output pixels. However the system depicted in Figure 1 requires distinct s channels for each input resolution. The alternative depicted in Figure 6 takes the input image data (M) over a 2 x 4 region (e.g., 8 bits per color plane) on lines 120 and applies the template-based mapping logic at block 124 previously described to produce outputs for a plurality of output pixels (No - N,4) on lines 128 at a higher resolution. The values for each of the output pixels is, for example, determined based l0 upon the mapping technique previously described with respect to Figure S
and all outputs are provided to the selection and buffering block 132. In a simplified representation, block 132 operates to latch or otherwise buffer the signals on lines 128 and then select the outputs to be employed to generate the appropriate number of output pixels for the given resolution conversion, preferably using combinatorial logic.
is Operation of the selection block is accomplished as a result of an input received from selection logic block 136. Selection logic block 136 receives as input the resolution of the input image and produces a combinatorial logic output signal which controls the selection of various signals buffered within block 132. The resultant output from block 132 is a plurality of output pixels that may be further processed as previously 20 described with respect to Figure 1.
To further illustrate the operation of the alternative embodiment, reference may be had to Figure 7 which illustrates an area mapping window for accomplishing an exemplary 240 spi to 600 spi resolution conversion in accordance with the system depicted in Figure 6. In particular, the rectangular input pixel positions are labeled 2s using numerals for the column.row designation as previously described.
Similarly, the output pixel positions use alphabetical column.row notation. As wilt be appreciated from the discussion directed to the embodiment of Figure 1, the state or value for each output pixel or group of output pixels may be determined using a template-based technique, for example those techniques described by Loce et al. in US-A-5,359,423 30 to Loce for a Method for Statistical Generation of Density Preserving Templates for

Claims (9)

1. A method for processing a highlight color digital input image signal representing a highlight color image, comprising the steps of:
quantization slicing the input image signal to produce at least a first binary image with a resolution R1 and a second binary image with a resolution R1;
selecting, from a region of neighboring pixels within the first binary image, a first set of input pixels to be converted;
mapping, using a binary, template-based conversion operation, the first set of input pixels to a first intermediate set of pixels at a high resolution R3, where R3 is greater than R1;
selecting from the first intermediate set of pixels a first set of output pixels to produce an image segment of resolution R2, where R2 is greater than R1 and not greater than R3; wherein the selection is accomplished as a function of the input resolution R1;
selecting, from a region of neighboring pixels within the second binary image, a second set of input pixels to be converted;
mapping the second set of input pixels to a second intermediate set of pixels at a high resolution R3;
selecting from the second intermediate set of pixels a second set of output pixels to produce a second image segment of resolution R2, wherein the selection is accomplished as a function of the input resolution R1;

arbitrating between the first and second image segments to produce an output image; and passing the output image to a lookup table, wherein the lookup table outputs, in response to the output image a digital signal suitable for driving a pulse-width, position modulated marking engine to produce the highlight color image.

2. The method of claim 1, wherein the quantization slicing of the input image signal is accomplished using a process selected from the group comprising:
bit slicing;
and level slicing.

3. The method of claim 1, wherein the mapping step comprises applying a binary, template-based conversion operation to the second set of input pixels, said operation identifying pixel patterns within the second set of input pixels matching predefined template patterns and outputting a plurality of pixels at resolution R3 in response to a match.

4. An apparatus for processing a digital input image having a low resolution R
L
to produce a high resolution output image having a fixed resolution R H
comprising:
windowing means for selecting, from a region of neighboring pixels within the input image, a set of input pixels to be converted;

mapping logic for mapping the set of input pixels to an intermediate set of pixels at a higher resolution R I, where R J is greater than R L and where R I
is not greater than R H;
a buffer for temporarily storing the intermediate set of pixels; and selection logic, generating as a function of the input resolution R L and the fixed output resolution R H a selection signal, said selection signal being used in conjunction with the buffer so as to select from the stored intermediate set of pixels a set of output pixels to produce an image segment of resolution R H, wherein the selection is accomplished as a function of the input resolution R L.

5. The apparatus of claim 4, wherein said mapping logic performs a binary, template-based conversion operation on the set of input pixels.

6. The apparatus of claim 5, wherein said low resolution is one of a plurality of low resolutions that may be processed by the apparatus.

7. The apparatus of claim 6, wherein said high resolution output image has a resolution of at least 600 spots per inch.

8. The apparatus of claim 7, wherein said low resolutions are not greater than 480 spots per inch.

9. The apparatus of claim 8, wherein said low resolution is selected from the set of input of resolutions consisting of:
240, 300, 400 and 480 spots per inch.