CA2223504A1 - Direct sequence frequency ambiguity resolving receiver - Google Patents
Direct sequence frequency ambiguity resolving receiverInfo
- Publication number
- CA2223504A1 CA2223504A1 CA002223504A CA2223504A CA2223504A1 CA 2223504 A1 CA2223504 A1 CA 2223504A1 CA 002223504 A CA002223504 A CA 002223504A CA 2223504 A CA2223504 A CA 2223504A CA 2223504 A1 CA2223504 A1 CA 2223504A1
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- frequency
- chip code
- filter
- level
- signal strength
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7075—Synchronisation aspects with code phase acquisition
- H04B1/70751—Synchronisation aspects with code phase acquisition using partial detection
- H04B1/70752—Partial correlation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7075—Synchronisation aspects with code phase acquisition
- H04B1/70755—Setting of lock conditions, e.g. threshold
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7075—Synchronisation aspects with code phase acquisition
- H04B1/7077—Multi-step acquisition, e.g. multi-dwell, coarse-fine or validation
- H04B1/70775—Multi-dwell schemes, i.e. multiple accumulation times
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7073—Synchronisation aspects
- H04B1/7075—Synchronisation aspects with code phase acquisition
- H04B1/708—Parallel implementation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7097—Interference-related aspects
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
- H04B1/7097—Interference-related aspects
- H04B1/71—Interference-related aspects the interference being narrowband interference
- H04B1/7101—Interference-related aspects the interference being narrowband interference with estimation filters
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Mobile Radio Communication Systems (AREA)
- Radio Transmission System (AREA)
Abstract
A parallel frequency acquisition technique is disclosed for increasing receiver sensitivity and increasing process gain while reducing the necessary preamble duration required for spread spectrum acquisition. In addition, techniques are disclosed for reducing the effects of jamming and impulse noise on the performance of the receiver as well as enhanced antenna diversity approaches. Further, techniques are taught which compensate for chip code alignment drift, providing an associated transmitter maintains carrier and chip code coherence. These techniques allow for the use of lower cost frequency setting crystals in both the receiver and transmitter as well as the operation of the system over a wider temperature range.
Claims (72)
1. A system for receiving direct sequence spread spectrum transmissions with both chip code phase and frequency uncertainty comprising:
means for despreading received signals in a direct sequence spread spectrum system;
a plurality of filter means for filtering the despread signals; and operator means for operating upon the output of at least one of the filter means for resolving frequency uncertainty in the direct sequence spread spectrum transmissions.
means for despreading received signals in a direct sequence spread spectrum system;
a plurality of filter means for filtering the despread signals; and operator means for operating upon the output of at least one of the filter means for resolving frequency uncertainty in the direct sequence spread spectrum transmissions.
2. A system according to Claim 1 wherein the means for despreading received signals employs a chip code reference signal.
3. A system according to Claim 1 wherein the operator means function to select aparticular one of the filter means from which to demodulate at least one of voice or data.
4. A system according to Claim 3 wherein the operator means employs voting techniques to select a particular one of the filter means.
5. A system according to Claim 4 wherein the voting techniques are for selecting a strongest signal level filter bin for decoding data.
6. A system according to Claim 4 wherein the voting techniques utilize an average signal strength or the filter mean and at least one of the highest and the lowest signal strength filter bins are eliminated from the average.
7. A system according to Claim 1 wherein the operator means utilizes output signals from at least two of the filter means for resolving frequency uncertainty in the direct sequence spread spectrum transmissions.
8. A system according to Claim 1 wherein each of the filters of the filter means have a bandwidth less than that of the data bandwidth during the time when a transmitted preamble is being acquired for the spread spectrum communications.
9. A system according to Claim 1 wherein the plurality of filter means is an array of parallel filters.
10. A system according to Claim 1 wherein the filter means employs Fourier transformations to detect the filter bin most likely to yield the transmitted message.
11. A system according to Claim 1 including an envelope shaping means for operating upon the despread signals prior to the filter means for reducing impulse effects on bins adjacent to the-desired bin.
12. A system according to Claim 1 wherein the means for despreading received signals comprises a parallel correlator.
13. A system according to Claim 12 wherein the parallel correlator is clocked at the chipping rate.
14. A system according to Claim 12 wherein, upon an initial correlation output of the parallel correlator, the parallel correlator lock is offset in time by a portion of a chip duration.
15. A system according to Claim 1 wherein the plurality of filter means comprises a plurality of filter banks for receiving the compressed signals in parallel after de-spreading.
16. A receiver for use with a direct sequence spread spectrum system for receiving transmissions with both chip code phase and frequency uncertainty comprising.
compressor means for compressing the bandwidth of signals received in the spread spectrum system using a chip code reference signal;
a plurality of filter bank means for receiving the compressed signals in parallel;
means for detecting a signal parameter provided by each of filter banks in the plurality of filter bank means;
means for identifying at least one of the filter banks which is likely to yield acceptable data; and means for calculating a frequency correction factor based upon the output of the identified filter bank.
compressor means for compressing the bandwidth of signals received in the spread spectrum system using a chip code reference signal;
a plurality of filter bank means for receiving the compressed signals in parallel;
means for detecting a signal parameter provided by each of filter banks in the plurality of filter bank means;
means for identifying at least one of the filter banks which is likely to yield acceptable data; and means for calculating a frequency correction factor based upon the output of the identified filter bank.
17. A receiver according to Claim 16 further including decoder means for decoding at least one of data or voice information from that selected filter.
18. A receiver for use in direct sequence spread spectrum system for receiving transmissions with both chip code phase and frequency uncertainty, comprising:
despreader means for despreading the received spread spectrum signals; and multiple coefficient table means for resolving frequency uncertainty in the despread signals.
despreader means for despreading the received spread spectrum signals; and multiple coefficient table means for resolving frequency uncertainty in the despread signals.
19. A receiver according to Claim 18 wherein the coefficients are the product of a particular chip code sequence and at least one of a particular lowpass characteristic a particular bandpass filter characteristic.
20. A receiver for use in direct sequence spread spectrum system for receiving transmissions with both chip code phase and frequency uncertainty comprising:
hybrid coefficient table means employing at least one of a FIR or IIR coefficient filter that combines a chip code sequence for despreading the received spread spectrum signals and, simultaneously, uses at least one of a lowpass Or bandpass filter for filtering the received spread spectrum signals.
hybrid coefficient table means employing at least one of a FIR or IIR coefficient filter that combines a chip code sequence for despreading the received spread spectrum signals and, simultaneously, uses at least one of a lowpass Or bandpass filter for filtering the received spread spectrum signals.
21. In a direct sequence spread spectrum system, a method for receiving transmissions with both chip code phase and frequency Uncertainty, comprising the following steps:
despreading the signals received in a direct sequence spread spectrum system using a chip code reference signal; and applying multiple tables of coefficients for resolving frequency uncertainty in the despread signals.
despreading the signals received in a direct sequence spread spectrum system using a chip code reference signal; and applying multiple tables of coefficients for resolving frequency uncertainty in the despread signals.
22. In a direct sequence spread spectrum system, a method for receiving transmissions with both chip code phase and frequency uncertainty, comprising the steps of compressing and resolving frequency uncertainty in signals received in a direct sequence spread spectrum system by employing hybrid coefficient tables wherein the coefficients each are the product of a particular chip code sequence and at least one of a particular low pass characteristic and a particular band pass filter characteristic.
23. A method according to Claim 22 further including the steps of determining the chip code phase by at least one of rotation of the hybrid coefficient table and rotation of a sampled IF buffer, and offsetting the pointer into the sampled IF buffer.
24. A method according to Claim 22 further including determining the chip code phase position by identifying a matching hybrid coefficient table, which is calculated based upon a particular chip code sequence phase position and at least one of a particular lowpass or bandpass filter characteristic.
25. In a direct sequence spread spectrum system, a method for receiving transmissions with both chip code phase and frequency uncertainty that provides enhanced acquisition speed or enhanced sensitivity, comprising the following steps:
compressing the bandwidth of signals received in a direct sequence spread spectrum system using a chip code reference signal;
applying the compressed signals to a plurality of filter banks simultaneously, detecting at least one of a) signal strength, b) quieting, c) phase lock or d) signal quality from each of the plurality of filter banks;
from the plurality of filter banks, identifying at least one of the filters which is likely to yield acceptable data; and using the selected filter for decoding data or voice information.
compressing the bandwidth of signals received in a direct sequence spread spectrum system using a chip code reference signal;
applying the compressed signals to a plurality of filter banks simultaneously, detecting at least one of a) signal strength, b) quieting, c) phase lock or d) signal quality from each of the plurality of filter banks;
from the plurality of filter banks, identifying at least one of the filters which is likely to yield acceptable data; and using the selected filter for decoding data or voice information.
26. A method according to Claim 25 wherein the identified filter is identified by detecting at least one of a) signal strength, b) quieting, c) phase lock or d) signal quality from each of the plurality of filter banks.
27. A method according to Claim 25 including the step of pipelining the filter outputs to sample storage buffers.
28. A receiving method employed in a direct sequence spread spectrum system for receiving transmissions with both time and frequency uncertainty, the method comprising:
despreading the signals initially received;
applying the despread signals to a plurality of filter banks simultaneously; andapplying a trip level algorithm to the output of the plurality of filter banks; and demodulating at least one of data and voice once selected by the trip algorithm.29. A receiving method according to Claim 28 wherein each of the filter banks of the plurality of filter banks has a frequency bin, and the trip level algorithm functions such that one or two bins must be higher than the average of the bins by at least a trip level.
despreading the signals initially received;
applying the despread signals to a plurality of filter banks simultaneously; andapplying a trip level algorithm to the output of the plurality of filter banks; and demodulating at least one of data and voice once selected by the trip algorithm.29. A receiving method according to Claim 28 wherein each of the filter banks of the plurality of filter banks has a frequency bin, and the trip level algorithm functions such that one or two bins must be higher than the average of the bins by at least a trip level.
47
30. A receiving method according to Claim 28 wherein each of the filter banks of the plurality of filter banks has a frequency bin and the trip level algorithm functions such that one or two bins must be higher than adjacent bins by at least a trip level.
31. A receiving method according to Claim 1, 16, 18, 20, 25 or 28 wherein each of the filter banks of the plurality of filter banks has a frequency bin and the receiver uses a frequency bin offset from center frequency bin to establish a chip code clock drift correction factor.
32. In a direct sequence spread spectrum receiver that receives transmissions in the presence of background noise and/or impulsive noise or jamming a process for reducing the number of false trips by applying an adaptive trip level algorithm based on a normalization control loop whereby the adaptive trip algorithm adaptively adjusts the trip level.
33. A purpose according to Claim 32 wherein the normalization step is employed for increasing message throughout.
34. A method according to Claims 1, 16, 18 or 22 wherein the step of resolving frequency uncertainty in the despread signals further includes choosing frequency Bin with largest signal strength.
35. A method according to Claims 1, 16, 18 or 22 wherein the step of resolving frequency uncertainty in the despread signals further includes combining all Bins prior to selection of strongest Bins and compare to last chip code alignment.
36. A method according to Claims 1, 16, 18 or 22 wherein the step of resolving frequency uncertainty in the despread signals further adding the .DELTA. signal strength of frequency Bins (the .DELTA. being computed relative to the lowest signal strength frequency Bin) prior to comparing to last chip code alignment.
37. A method for receiving direct sequence spread spectrum transmissions with both chip code phase and frequency uncertainty comprising:
despreading received signals in a direct sequence spread spectrum system;
operating upon the despread signals for correcting frequency uncertainty in the direct sequence spread spectrum transmissions to a selected frequency Bin by the following steps:
measuring the frequency offset of the frequency Bin determined most likely to represent a desired transmission;
determining, based upon the frequency offset measurement, a frequency offset from the selected frequency Bin;
applying the determined frequency offset as a correction factor for correcting the desired transmission to the selected frequency Bin; and demodulating data from the center frequency Bin.
despreading received signals in a direct sequence spread spectrum system;
operating upon the despread signals for correcting frequency uncertainty in the direct sequence spread spectrum transmissions to a selected frequency Bin by the following steps:
measuring the frequency offset of the frequency Bin determined most likely to represent a desired transmission;
determining, based upon the frequency offset measurement, a frequency offset from the selected frequency Bin;
applying the determined frequency offset as a correction factor for correcting the desired transmission to the selected frequency Bin; and demodulating data from the center frequency Bin.
38. The method of Claim 37 wherein the selected frequency bin is the center frequency bin.
39. A method for receiving direct sequence spread spectrum transmissions with both chip code phase and frequency uncertainty comprising:
despreading received signals in a direct sequence spread spectrum system;
operating upon the despread signals for correcting frequency uncertainty in the direct sequence spread spectrum transmissions to a selected frequency Bin by centering the received signal in the passband of a frequency Bin filter by the following steps:
measuring the frequency offset of the frequency Bin determined to most likely, represent a desired transmission;
determining, based upon the frequency measurement a frequency offset correction from the center of the frequency Bin determined most likely to yield a desirable transmission; and selecting, utilizing the determined frequency offset correction factor an alternative frequency Bin filter with a center frequency offset by a portion of a frequency bin bandwidth.
despreading received signals in a direct sequence spread spectrum system;
operating upon the despread signals for correcting frequency uncertainty in the direct sequence spread spectrum transmissions to a selected frequency Bin by centering the received signal in the passband of a frequency Bin filter by the following steps:
measuring the frequency offset of the frequency Bin determined to most likely, represent a desired transmission;
determining, based upon the frequency measurement a frequency offset correction from the center of the frequency Bin determined most likely to yield a desirable transmission; and selecting, utilizing the determined frequency offset correction factor an alternative frequency Bin filter with a center frequency offset by a portion of a frequency bin bandwidth.
40. A method for improving the sensitivity of a receiver during a chip code search in a direct sequence spread spectrum system of the type wherein the receiver searches for chip code reference phase alignment with a desired transmitter in discrete phase increments, the method including the following steps:
a) phase shifting a chip code reference a portion of a chip time;
b) dwelling on that chip phase position for a portion of a bit time;
c) detecting at least one of signal strength, quieting, PLL lock and signal quality as a first signal; and d) phase shifting a chip code reference a portion of a chip time;
e) dwelling on that chip phase position for a portion of a bit time; and f) detecting at least one of signal strength, quieting, PLL lock and signal quality as a second signal;
g) combining the first and the second detected signals; and h) ceasing to search for chip code alignment based upon the combined detected signals.
a) phase shifting a chip code reference a portion of a chip time;
b) dwelling on that chip phase position for a portion of a bit time;
c) detecting at least one of signal strength, quieting, PLL lock and signal quality as a first signal; and d) phase shifting a chip code reference a portion of a chip time;
e) dwelling on that chip phase position for a portion of a bit time; and f) detecting at least one of signal strength, quieting, PLL lock and signal quality as a second signal;
g) combining the first and the second detected signals; and h) ceasing to search for chip code alignment based upon the combined detected signals.
41. The method according to Claim 40 wherein steps a) through g) are repeated one or more times prior to step g. 1.
42. The method according to Claim 41 wherein the step of ceasing to search for chip code alignment is performed with in conjunction with a trip algorithm means.
43. The method according to Claim 1, 16, 18, 22 or 28 further including a method for compensating frequency offset error in a direct sequence receiver equipped with multiple parallel filters, including at least a high frequency filter a center frequency filter and a low frequency filter, comprising the steps of:
a) detecting, during the search for proper preamble chip code phase alignment, signal strength from a low frequency filter as a First Level error output;
b) detecting during the search for proper preamble chip code phase alignment signal strength from a high frequency filter as a Second Level error output;
c) combining the First Level and the Second Level error outputs to step the received frequency control input of the receiver such that the desired transmission becomes available in the center frequency filter; and d) detecting a signal parameter from the center frequency filter; and e) ceasing to search, and thereby dwelling on a particular chip code phase alignment, based upon the detected signal parameter.
a) detecting, during the search for proper preamble chip code phase alignment, signal strength from a low frequency filter as a First Level error output;
b) detecting during the search for proper preamble chip code phase alignment signal strength from a high frequency filter as a Second Level error output;
c) combining the First Level and the Second Level error outputs to step the received frequency control input of the receiver such that the desired transmission becomes available in the center frequency filter; and d) detecting a signal parameter from the center frequency filter; and e) ceasing to search, and thereby dwelling on a particular chip code phase alignment, based upon the detected signal parameter.
44. The method according to Claim 1, 16, 18, 22 or 28 further including a method for compensating frequency of offset error in a direct sequence receiver equipped with multiple parallel filters, including at least a high frequency filter, a center frequency filter and a low frequency filter, comprising the steps of:
a) detecting, during the time data is being demodulated, signal strength from a low frequency filter as a First Level error output;
b) detecting, during the time data is being demodulated, signal strength from a high frequency filter as a Second Level error output;
c) combining the First Level and the Second Level error outputs to step the received frequency control input of the receiver such that the desired transmission becomes centered in the center frequency filter; and d) demodulating data from the signal contained in the center frequency filter.
a) detecting, during the time data is being demodulated, signal strength from a low frequency filter as a First Level error output;
b) detecting, during the time data is being demodulated, signal strength from a high frequency filter as a Second Level error output;
c) combining the First Level and the Second Level error outputs to step the received frequency control input of the receiver such that the desired transmission becomes centered in the center frequency filter; and d) demodulating data from the signal contained in the center frequency filter.
45. The method according to Claim 1, 16, 18, 22 or 28 further including a method for compensating frequency offset error in a direct sequence receiver equipped with multiple parallel filters, including at least a high frequency filter, a center frequency filter and a low frequency filter, comprising the steps of:
a) detecting, during the time data is being demodulated, signal strength from a low frequency filter as a First Level error output;
b) detecting, during the time data is being demodulated, signal strength from a high frequency filter as a Second Level error output;
c) combining the First Level and the Second Level error outputs to step a frequency control input such that the desired transmission becomes centered in any of the multiplicity of frequency Bins and, the, demodulating data from that frequency Bin.
a) detecting, during the time data is being demodulated, signal strength from a low frequency filter as a First Level error output;
b) detecting, during the time data is being demodulated, signal strength from a high frequency filter as a Second Level error output;
c) combining the First Level and the Second Level error outputs to step a frequency control input such that the desired transmission becomes centered in any of the multiplicity of frequency Bins and, the, demodulating data from that frequency Bin.
46. A method to pre-process signal strength prior to Amplitude Shift Keying datademodulation in a receiver with multiple adjacent frequency filters, the steps including:
receiving, with multiple adjacent filters, a transmission with an imperfectly known transmission carrier frequency;
detecting the received signal strength from a plurality of the adjacent filters;combining the detected signal strengths from a plurality of the adjacent filters; and demodulating Amplitude Shift Keyed data from the combined signal strengths.
receiving, with multiple adjacent filters, a transmission with an imperfectly known transmission carrier frequency;
detecting the received signal strength from a plurality of the adjacent filters;combining the detected signal strengths from a plurality of the adjacent filters; and demodulating Amplitude Shift Keyed data from the combined signal strengths.
47. The method according to Claim 1, 16, 18, 20, 21, 22, 25 or 28 wherein the multiple filter Bins are such that the Frequency Bin to Frequency Bin frequency roll-off is set to at least a maximum Trip Level.
48. A method for expanding the CDMA capacity of a direct sequence system spreadspectrum system comprising:
transmitting from an expanded CDMA channel intended transmitter, with a preselected frequency offset, a direct sequence transmission, the transmission having a frequency offset of its carrier at least equal to the frequency uncertainty tolerance of an unintended received last IF filter bandwidth; and receiving, at an intended receiver, the expanded CDMA channel intended transmission, while suppressing receptions from unintended transmissions with a carrier frequency outside of the intended receiver's last IF filter bandwidth.
transmitting from an expanded CDMA channel intended transmitter, with a preselected frequency offset, a direct sequence transmission, the transmission having a frequency offset of its carrier at least equal to the frequency uncertainty tolerance of an unintended received last IF filter bandwidth; and receiving, at an intended receiver, the expanded CDMA channel intended transmission, while suppressing receptions from unintended transmissions with a carrier frequency outside of the intended receiver's last IF filter bandwidth.
49. A method according to Claim 48 further including the steps of slewing the receiver local oscillator in increments for detecting a transmission received with a carrier frequency offset at least equaling the last IF filter bandwidth of the receiver.
50. The receiving method according to Claim 28 wherein the trip level algorithm is applied by:
measuring signal strength from each of a multiplicity of frequency Bins; and Computing an average signal level of the measured frequency Bins; and determining that at least one of the measured signal strengths from a multiplicity of frequency Bins exceeds the computed average by at least a Trip Level.
measuring signal strength from each of a multiplicity of frequency Bins; and Computing an average signal level of the measured frequency Bins; and determining that at least one of the measured signal strengths from a multiplicity of frequency Bins exceeds the computed average by at least a Trip Level.
51. The receiving method according to Claim 28 wherein the trip level algorithm is applied by the steps of:
measuring signal strength from each of a multiplicity of frequency Bins; and verifying, to reduce undesired chip code phase position dwells, that at least one of the measured signal strengths is higher than the adjacent frequency Bins by at least a Trip Level.
measuring signal strength from each of a multiplicity of frequency Bins; and verifying, to reduce undesired chip code phase position dwells, that at least one of the measured signal strengths is higher than the adjacent frequency Bins by at least a Trip Level.
52. The receiving method according to Claim 28, 52, 53 or 54 wherein the trip level is set to a predetermined fixed level.
53. The receiving method according to Claim 28 wherein the Trip Level algorithm is applied by the steps of:
measuring, at least one of the previous chip code alignment, the current chip alignment, the next chip code alignment, the signal strength from a multiplicity of frequency Bins;
comparing at least one of, the measurements from the previous chip code alignment to the measurement of the current chip code alignment, and a measurement of the next chip code alignment to a measurement of the current chip code alignment, and verifying, to reduce false dwells, that the comparison results in a reduction of signal strength in relation to the measurement of the signal strength from the current chip code alignment.
measuring, at least one of the previous chip code alignment, the current chip alignment, the next chip code alignment, the signal strength from a multiplicity of frequency Bins;
comparing at least one of, the measurements from the previous chip code alignment to the measurement of the current chip code alignment, and a measurement of the next chip code alignment to a measurement of the current chip code alignment, and verifying, to reduce false dwells, that the comparison results in a reduction of signal strength in relation to the measurement of the signal strength from the current chip code alignment.
54. In a direct sequence spread spectrum system, a method for reducing the undesirable dwells on chip code phase position not likely to result in the reception of a desired transmission, including the steps of:
stepping the chip code phase position of a receiver's chip code reference; and measuring the resulting received signal strength as a First Level;
disabling the receiver's chip code reference;
measuring the resulting received signal strength as a Second Level;
comparing the First Level to the Second Level; and verifying, to reduce undesirable chip code phase dwells, that the First Level exceeds the Second Level.
stepping the chip code phase position of a receiver's chip code reference; and measuring the resulting received signal strength as a First Level;
disabling the receiver's chip code reference;
measuring the resulting received signal strength as a Second Level;
comparing the First Level to the Second Level; and verifying, to reduce undesirable chip code phase dwells, that the First Level exceeds the Second Level.
55. In a direct sequence spread spectrum system, a method for reducing the undesirable dwells on chip code phase position not likely to result in the reception of a desired transmission, including the steps of: stepping the chip code phase position of a receiver chip code reference; and measuring the resulting received signal strength as a First Level; using an orthogonal chip code sequence as the receiver's chip code reference;
measuring the resulting received signal strength as a Second Level;
comparing the First Level to the Second Level; and verifying, to reduce undesirable chip code phase dwells, that the First Level exceeds the Second Level.
measuring the resulting received signal strength as a Second Level;
comparing the First Level to the Second Level; and verifying, to reduce undesirable chip code phase dwells, that the First Level exceeds the Second Level.
56. In a direct sequence spread spectrum system, a method for reducing the undesirable dwells on chip code phase position not likely to result in the reception of a desired transmission, whereby the receiver's chip code reference is FSK modulated, including the steps of:
stepping the chip code phase position of a receiver FSK modulated chip code reference;
measuring the resulting received signal strength as a First Level;
inverting the FSK chip code reference; and measuring the resulting received signal strength as a Second Level;
comparing the First Level to the Second Level; and verifying, to reduce undesirable chip code phase dwells, that the First Level exceeds the Second Level.
stepping the chip code phase position of a receiver FSK modulated chip code reference;
measuring the resulting received signal strength as a First Level;
inverting the FSK chip code reference; and measuring the resulting received signal strength as a Second Level;
comparing the First Level to the Second Level; and verifying, to reduce undesirable chip code phase dwells, that the First Level exceeds the Second Level.
57. The method according to Claim 1, 16, 18, 20, 21, 22, 25 or 28 including the method of compensating chip code phase alignment drift of the receiver with respect to the transmitter by:
determining a frequency Bin most likely to yield a desired transmission;
measuring a frequency offset of the frequency Bin determined most likely to yield a desired transmission with respect to the center frequency Bin of the receiver;
calculating a chip code phase drift correction factor utilizing the frequency offset measurement; and applying the calculated chip code phase drift correction factor to at lease one of the receiver's chip code reference and the receivers VCO; and demodulating data utilizing the corrected chip code reference.
determining a frequency Bin most likely to yield a desired transmission;
measuring a frequency offset of the frequency Bin determined most likely to yield a desired transmission with respect to the center frequency Bin of the receiver;
calculating a chip code phase drift correction factor utilizing the frequency offset measurement; and applying the calculated chip code phase drift correction factor to at lease one of the receiver's chip code reference and the receivers VCO; and demodulating data utilizing the corrected chip code reference.
58. A receiving method according to Claim 57 including using interpolation for increasing the accuracy of the frequency offset measurement.
59. A receiving method according to Claim 57 including the step of jogging the chip code reference to correct for chip code phase Drift.
60. A method according to Claim 1, 16, 18, 20, 21, 22, 25 or 28 further including a process for receiving direct sequence spread spectrum transmissions with both chip code phase and frequency uncertainty comprising:
detecting signal strength from a multiplicity of filters; comparing the detected signal strength from the filters;
providing a jamming warning when a majority of the filters concurrently contain an elevated signal strength.
detecting signal strength from a multiplicity of filters; comparing the detected signal strength from the filters;
providing a jamming warning when a majority of the filters concurrently contain an elevated signal strength.
61. A receiving method according to Claim 28 wherein undesirable dwells on chip code phase positions are reduced by a false Trip detection algorithm that operates by:
measuring signal strength from each of a multiplicity of frequency Bins; and computing an average signal level of the measured frequency Bins; and verifying to reduce undesired chip code phase dwells that at least one of the measured signal strengths from a multiplicity of frequency Bins exceeds the computed average by at least a Trip Level.
measuring signal strength from each of a multiplicity of frequency Bins; and computing an average signal level of the measured frequency Bins; and verifying to reduce undesired chip code phase dwells that at least one of the measured signal strengths from a multiplicity of frequency Bins exceeds the computed average by at least a Trip Level.
62. A receiving method according to Claim 61 wherein at least one of the highest and the lowest signal strength measurements is eliminated from the computation of the average.
63. A receiving method according to Claim 28 wherein undesirable dwells on chip code phase positions are reduced by a false Trip detection algorithm that operates by:
measuring signal strength from each of a multiplicity of frequency Bins; and comparing the measured signal strength from each of a multiplicity of frequency Bins; and verifying to reduce undesired chip code phase position dwells that at least one of the measured signal strengths is higher than the adjacent frequency Bins by at least a Trip Level.
measuring signal strength from each of a multiplicity of frequency Bins; and comparing the measured signal strength from each of a multiplicity of frequency Bins; and verifying to reduce undesired chip code phase position dwells that at least one of the measured signal strengths is higher than the adjacent frequency Bins by at least a Trip Level.
64. A receiving method according to Claim 63 wherein the lowest signal strength measurement is eliminated from the comparison of the measured signal strengths.
65. A method according to Claim 1, 16, 21, 22 or 28 wherein resistance to signal fading is provided by:
measuring during the reception of a transmitted preamble, the phase of a first antenna, and measuring during the transmitted preamble, the phase of at least one second antenna, and computing using the phase measurements of the first and second antennae, the difference of the two antenna phases as a phase corrections factor; and applying the correction factor to a phase delaying means for constructively combining the signals from the first and second antennae; and demodulating data from the constructively combined antenna signals.
measuring during the reception of a transmitted preamble, the phase of a first antenna, and measuring during the transmitted preamble, the phase of at least one second antenna, and computing using the phase measurements of the first and second antennae, the difference of the two antenna phases as a phase corrections factor; and applying the correction factor to a phase delaying means for constructively combining the signals from the first and second antennae; and demodulating data from the constructively combined antenna signals.
66. A method according to Claim 65 wherein the phase delaying means is placed in one of the antenna signal paths at the front-end of the receiver and wherein both antennas are enabled simultaneously.
67. A method according to Claim 65 wherein the phase delaying means is located within a processor means and wherein the signal from the two antennas are duty cycled each with an appropriate correction factor applied when the respective antenna is enabled.
68. A method according to Claim 1, 16, 21, 22 or 28 wherein additionally, resistance to fading is provided by:
measuring during the reception of the transmitter preamble, the signal strength of a first antenna;
measuring during the reception of the transmitted preamble, the signal strength of at least a second antenna;
comparing the signal strength measurements from the first and second antennae;
determining, upon comparison the strongest signal strength of the first and second antennae;
enabling based upon the determination of signal strength only the strongest of the two antennae; and demodulating data, upon completion of the transmitted preamble, with only the strongest signal strength antenna enabled.
measuring during the reception of the transmitter preamble, the signal strength of a first antenna;
measuring during the reception of the transmitted preamble, the signal strength of at least a second antenna;
comparing the signal strength measurements from the first and second antennae;
determining, upon comparison the strongest signal strength of the first and second antennae;
enabling based upon the determination of signal strength only the strongest of the two antennae; and demodulating data, upon completion of the transmitted preamble, with only the strongest signal strength antenna enabled.
69. A system according to Claim 1, 16, 18, 20, 21, 22, 25 or 28 wherein the receiver includes temperature measurement means for providing a receiver frequency reference correction factor and further including drift correction means for providing a frequency drift correction factor that can be used for reducing the number of parallel filters required to cover the frequency uncertainty between the receiver frequency reference and the transmitter frequency reference.
70. In a direct sequence spread spectrum system a method for receiving transmissions with both time and frequency uncertainty, comprising the steps of:
despreading the signals received in a direct sequence spread spectrum system using a chip code reference signal;
resolving frequency uncertainty in the despread signals; and utilizing the received chip code phase alignment to position the receiver data bit sample clock for improving BER vs. CNR performance at low signal level conditions from reception of transmissions from transmitters with a chip code sequence in fixed time relationship to strength antenna enabled.
despreading the signals received in a direct sequence spread spectrum system using a chip code reference signal;
resolving frequency uncertainty in the despread signals; and utilizing the received chip code phase alignment to position the receiver data bit sample clock for improving BER vs. CNR performance at low signal level conditions from reception of transmissions from transmitters with a chip code sequence in fixed time relationship to strength antenna enabled.
71. A process according to Claim 32 wherein the normalization step is based on a pre-set parameter.
72. A process according to Claim 34 wherein the present parameter is the average number of acceptable false trips.
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| US08/485,007 | 1995-06-07 | ||
| US08/485,007 US6111911A (en) | 1995-06-07 | 1995-06-07 | Direct sequence frequency ambiguity resolving receiver |
| PCT/US1996/009314 WO1996041425A2 (en) | 1995-06-07 | 1996-06-06 | Direct sequence frequency ambiguity resolving receiver |
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| CA2223504A1 true CA2223504A1 (en) | 1996-12-19 |
| CA2223504C CA2223504C (en) | 2012-03-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA2223504A Expired - Lifetime CA2223504C (en) | 1995-06-07 | 1996-06-06 | Direct sequence frequency ambiguity resolving receiver |
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| US (1) | US6111911A (en) |
| EP (1) | EP0872016A4 (en) |
| AU (1) | AU719426B2 (en) |
| CA (1) | CA2223504C (en) |
| WO (1) | WO1996041425A2 (en) |
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| JP2802870B2 (en) * | 1993-03-10 | 1998-09-24 | エヌ・ティ・ティ移動通信網株式会社 | Code division multiplex mobile communication apparatus and cell selection method for code division multiplex mobile communication |
| GB2277853A (en) * | 1993-05-07 | 1994-11-09 | Roke Manor Research | Signal compression signals |
| US5425061A (en) * | 1993-06-07 | 1995-06-13 | Texas Instruments Incorporated | Method and apparatus for bit stream synchronization |
| US5377223A (en) * | 1993-08-30 | 1994-12-27 | Interdigital Technology Corporation | Notch filtering a spread spectrum signal using fourier series coefficients |
| US5377225A (en) * | 1993-10-19 | 1994-12-27 | Hughes Aircraft Company | Multiple-access noise rejection filter for a DS-CDMA system |
| US5440597A (en) * | 1993-11-23 | 1995-08-08 | Nokia Mobile Phones Ltd. | Double dwell maximum likelihood acquisition system with continuous decision making for CDMA and direct spread spectrum system |
| JP2655068B2 (en) * | 1993-12-30 | 1997-09-17 | 日本電気株式会社 | Spread spectrum receiver |
| US5422912A (en) * | 1994-06-23 | 1995-06-06 | Grumman Aerospace Corporation | Adaptive weak signal identification system |
| US5450453A (en) * | 1994-09-28 | 1995-09-12 | Motorola, Inc. | Method, apparatus and system for decoding a non-coherently demodulated signal |
| JPH08213881A (en) * | 1995-02-02 | 1996-08-20 | Fujitsu Ltd | Frequency control circuit |
| US5640431A (en) * | 1995-03-10 | 1997-06-17 | Motorola, Inc. | Method and apparatus for offset frequency estimation for a coherent receiver |
-
1995
- 1995-06-07 US US08/485,007 patent/US6111911A/en not_active Expired - Lifetime
-
1996
- 1996-06-06 EP EP96930486A patent/EP0872016A4/en not_active Withdrawn
- 1996-06-06 CA CA2223504A patent/CA2223504C/en not_active Expired - Lifetime
- 1996-06-06 WO PCT/US1996/009314 patent/WO1996041425A2/en not_active Application Discontinuation
- 1996-06-06 AU AU69502/96A patent/AU719426B2/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| CA2223504C (en) | 2012-03-13 |
| WO1996041425A3 (en) | 1997-02-20 |
| AU6950296A (en) | 1996-12-30 |
| AU719426B2 (en) | 2000-05-11 |
| EP0872016A4 (en) | 2003-04-23 |
| US6111911A (en) | 2000-08-29 |
| EP0872016A2 (en) | 1998-10-21 |
| WO1996041425A2 (en) | 1996-12-19 |
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| EEER | Examination request | ||
| MKEX | Expiry |
Effective date: 20160606 |