CA2241379C - Circuit and method for determining received signal - Google Patents
Circuit and method for determining received signal Download PDFInfo
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- CA2241379C CA2241379C CA002241379A CA2241379A CA2241379C CA 2241379 C CA2241379 C CA 2241379C CA 002241379 A CA002241379 A CA 002241379A CA 2241379 A CA2241379 A CA 2241379A CA 2241379 C CA2241379 C CA 2241379C
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/46—Receiver circuitry for the reception of television signals according to analogue transmission standards for receiving on more than one standard at will
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/015—High-definition television systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/426—Internal components of the client ; Characteristics thereof
- H04N21/42607—Internal components of the client ; Characteristics thereof for processing the incoming bitstream
- H04N21/4263—Internal components of the client ; Characteristics thereof for processing the incoming bitstream involving specific tuning arrangements, e.g. two tuners
- H04N21/42638—Internal components of the client ; Characteristics thereof for processing the incoming bitstream involving specific tuning arrangements, e.g. two tuners involving a hybrid front-end, e.g. analog and digital tuners
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/47—End-user applications
- H04N21/482—End-user interface for program selection
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N11/00—Colour television systems
- H04N11/24—High-definition television systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/426—Internal components of the client ; Characteristics thereof
Abstract
Circuit and method for determining a received signal for a receiver such as a simulcast receiver or an HDTV receiver are provided. The circuit includes a first detector for detecting a first reference signal included in a received signal and outputting a first detection signal, a second detector for detecting a second reference signal included in the received signal and outputting a second detection signal, and a generator for generating a determination signal which indicates that the received signal is an analog broadcasting signal, if the first detection signal is detected, and indicates that the received signal is a high definition signal, if the second detection signal is detected. Therefore, the received signal can be determined correctly, according to channel selection.
Description
CA 0224l379 l998-06-22 CIRCUIT AND METHOD FOR DETERMINING RECEIVED SIGNAL
BACKGROUND OF THE INVENTION
1. Field of the Invention The present invention relates to a receiver, and more particularly, to a circuit for determining whether a received signal is a high-definition television (HDTV) signal or an analog TV signal, and to a method therefor.
BACKGROUND OF THE INVENTION
1. Field of the Invention The present invention relates to a receiver, and more particularly, to a circuit for determining whether a received signal is a high-definition television (HDTV) signal or an analog TV signal, and to a method therefor.
2. Description of Related Art Tests have been completed of a "Grand Alliance" (GA) advanced television (ATV) system, which is a new digital television transmission system standard 10 which can replace the analogue national television system committee (NTSC) broadcasting system. A GA-ATV system (also called GA-HDTV or GA-VSB) is standardized by the advanced television system committee (ATSC), and adopts a vestigial side band (VSB) modulation method for digital transmission.
However, when full-scale HDTV broadcasting starts, it cannot avoid coexistence with an existing analog broadcasting system (here, NTSC). Also, a receiver must allow a viewer to watch either HDTV or NTSC broadcasting at will.
That is, a channel may be for NTSC TV broadcasting in some areas and for HDTV
broadcasting in other areas, so a receiver must have a structure by which either of the two broadcastings can be selected and viewed. Such a simulcast receiver for 20 receiving both HDTV and NTSC TV signals is usually comprised of a tuner, an HDTV signal processor for processing HDTV signals, an NTSC TV signal processor for processing NTSC TV signals, and a display. Accordingly, before an HDTV or NTSC TV signal is selected and displayed on the single display, it must be determined whether the current received signal is an HDTV or NTSC TV signal.
A receiver for receiving the HDTV signal also requires a circuit for determiningwhether the current received signal is an HDTV or NTSC TV signal, in order to display whether a channel selected by a user is an HDTV or NTSC TV channel.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a circuit for correctly determining whether a received signal is an HDTV signal or an analog TV signal upon channel selection in a simulcast receiver.
It is another object of the present invention to provide a circuit for correctlydetermining whether a received signal is an HDTV signal or an analog TV signal in an HDTV receiver.
It is still another object of the present invention to provide a method for correctly determining whether a received signal is an HDTV signal or an analog TV signal.
It is yet another object of the present invention to provide a method for selecting a received signal in order of priority according to selection of channels, when an HDTV signal and an analog ~V signal are simultaneously received.
It is still yet another object of the present invention to provide a method for correctly determining a received signal according to channel selection when an HDTV signal and an analog TV signal are separately processed in a simulcast receiver.
It is further another object of the present invention to provide a method for correctly determining a received signal according to channel selection when an HDTV signal and an analog TV signal are partially processed together in a simulcast receiver.
To accomplish the above objects, there is provided a circuit for determining a received signal, comprising: a first detector for detecting a first reference signal included in a received signal and outputting a first detection signal; a second detector for detecting a second reference signal included in the received signaland outputting a second detection signal; and a generator for generating a determination signal which indicates that the received signal is an analog broadcasting signal, if the first detection signal is detected, and indicates that the received signal is a high definition signal, if the second detection signal is detected.
Also, a method for determining whether a received signal is a high-definition signal having a digital format or an analog broadcasting signal, includes the steps of: detecting a first reference signal included in the received signal and outputting a first detection signal; detecting a second reference signal included in the CA 0224l379 l998-06-22 received signal and outputting a second detection signal; and generating a determination signal which indicates that the received signal is an analog broadcasting signal, if the first detection signal is detected, and indicates that the received signal is a high definition signal, if the second detection signal is detected.
BRIEF DESCRIPTION OF THE DRAWINGS
The above objects and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:
FIG. 1 is a block diagram of a received signal determining circuit in a simulcast receiver according to an embodiment of the present invention;
FIG. 2 is a block diagram of a second signal processor and a second detector shown in FIG. 1;
FIG. 3 is another block diagram of a second signal processor and a second detector shown in FIG. 1;
FIG. 4 is a flowchart illustrating a method for determining a received signal, according to an embodiment of the present invention; and FIG. 5 is a flowchart illustldting a method for determining a received signal according to another embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
Referring to FIG. 1, a simulcast receiver for receiving both HDTV and NTSC
TV signals, according to the present invention, includes a tuner 110, first and second signal processors 120 and 130 for processing NTSC TV and HDTV
signals, respectively, and a display 180. Accordingly, a determination of whether a current received signal is the HDTV or NTSC TV signal must be made to selectively display either the HDTV or NTSC TV signal on a single display 180. Adetermining circuit for performing the above-described determination includes a first detector 140, a second detector 150 and a determination signal generator 160. A selector 170 selects either an NTSC TV signal demodulated by the first signal processor 120 or an HDTV signal demodulated by the second signal processor 130, according to a determination signal generated from the determination circuit.
That is, the first detector 140 of the determination circuit determines the existence or non-existence of the NTSC TV signal according to whether a verticalor horizontal synchronous signal exists, and outputs a first detection signal which is "high" if the synchronous signal exists and "low" if not. Here, the existence or non-existence of the NTSC TV signal can be also determined by a ghost cancellation reference (GCR) signal transmitted for a vertical blanking period to remove ghosting, in addition to using the determination of the synchronous signal.
In this case, a determination of whether the NTSC TV signal exists is made by checking a correlation between the GCR signal and the received signal.
A ghosting phenomenon, where a shadow image is generated on a TV
screen, occurs because an electromagnetic wave emitted from a broadcasting station is reflected by a mountain, a building, etc. In order to remove such a ghosting phenomenon, the broadcas~ing station transmits a predetermined reference signal (here, GCR signal) to allow a receiver to know the characteristics of a transmission channel. Then, the receiver understands the ghosting characteristics of a channel using the reference signal transmitted, and filters a received image signal. A GCR signal for removing the ghosting and a device therefor are disclosed in U.S. Patent "No. 5,389,977" issued to the present applicant.
The second detector 150 detects a field or segment synchronous signal included in the HDTV signal to determine whether the HDTV signal exists. That is, since a field synchronous segment of the HDTV signal is formed in a predetermined pseudo number (PN) sequence, the existence or non-existence of the HDTV signal can be determined by an inspection of the correlation between a received signal and a pre-stored reference signal.
Thus, the second detector 150 also outputs a second detection signal which is "high" if a field or segment synchronous signal exists in a signal output from the second signal processor 130, and is "low" if not. The determination signal generator 160 receives the first and second detection signals from the first andsecond detectors 140 and 150, and outputs a determination signal to the selector 170 to output a proper signal corresponding to a channel selected by determininga received signal as shown in FIG. 4. It is preferable that the existence or non-existence of the HDTV signal is first determined since the HDTV signal is generally transmitted at a lower power than the NTSC TV signal.
FIG. 2 is a block diagram of an example of the second signal processor 130 and a second detector 150. Referring to FIG. 2, elements from a block 131 to an error correction decoder 137 correspond to the second signal processor 130.
The block 131 controls the amplitude of an IF signal output from the tuner 110 shown in FIG. 1, demodulates the IF signal to a base-band signal using a pilot signal included in the IF signal, and converts the demodulated signal into digital data. An NTSC rejection filter (NRF) 132 removes an NTSC component from the output of the block 131 to prevent degradation of the HDTV signal by the NTSC
TV signal. Here, the NRF 132 may be constituted of a comb filter, as a representative example.
An NRF selection controller 133 generates a selection signal for selecting the path having a smaller error out of a path having passed through the NRF 132 and a path having not passed therethrough, and applies the selection signal to afirst selector 134, an adaptive equalizer 135, a phase tracker 136 and the errorcorrection decoder 137. The first selector 134 selects either a signal (15-level) which has passed through the NRF 132 or the output signal (8-level) of the block131 which has not passed through the NRF 132, according to the selection signal.The adaptive equalizer 135, the phase tracker 136 and the error correction decoder 137 are operated to adapt to a selected signal state.
The adaptive equaiizer 135 removes multipath distortion (another name for ghosting) included in the signal selected by the first selector 134. The phase tracker 136 removes a phase error, i.e., phase noise, in the equalized signal output from the adaptive equalizer 135. The error correction decoder 137 error-correction decodes the output of the phase tracker 136.
Meanwhile, a second selector 151 of the second detector 150 shown in FIG. 1 selects either a signal from which co- channel interference has been removed, output from the NRF 132, or a signal output from the phase tracker 136.The signal selected by the second selector 151 is output to a synchronous signal CA 0224l379 l998-06-22 detector 152. Here, the output signal of the phase tracker 136 is a signal from which other interferences, i.e., moving ghosting and phase noise, as well as theco-channel interference, have been removed. The adaptive equalizer 135 and the phase tracker 136 can be called a post-processor.
The synchronous signal detector 152 detects a field or segment synchronous signal included in a signal selected by the second selector 151, andoutputs a first detection signal which is logic "high" signal if the field or segment synchronous signal is detected, and is logic "low" signal if not.
FIG. 3 is a block diagram of another example of the second signal processor 130 and the second detector 150 shown in FIG. 1. Elements from a block 131 through to an error correction decoder 137 constitute the second signal processor 130. A second selector 153, a synchronous signal detector 154, a thirdselector 155, an error rate detector 156 and an AND gate 157 constitute the second detector 150, are omitted from this description. The second detector 150 shown in FIG. 3 determines that a signal exists only when an error rate is lowerthan or equal to a predetermined value, by detecting both a synchronous signal and an error rate.
That is, the synchronous signal detection is performed by the second selector 153 and the synchronous signal detector 154. The error rate detection is performed by the third selector 155 and the error rate detector 156. The third selector 155 selects either the output of the phase tracker 136 or the output of the error correction decoder 137. If the output of the phase tracker 136 is selected by the third selector 155, the error rate detector 156 obtains a symbol error rate by comparing a signal processed by the phase tracker 136 with a known signal (e.g.,a 511PN signal) in a field synchronous segment, since the output signal of the phase tracker 136 exists in a symbol state. The error detector 156 outputs a logic "high" signal if the obtained error rate is less than or equal to a predetermined threshold value, and otherwise outputs a logic"low" signal.
Similarly, if the output of the error correction decoder 137 is selected by the third selector 155, then since a bit error rate (BER) can be estimated using a signal (here, a flag) which indicates the restoration or non-restoration of a bit error-corrected by the error correction decoder 137, the error rate detector 156 CA 0224l379 l998-06-22 accumulates a flag output from the error correction decoder 137 and compares theestimated BER with a predetermined threshold value. Then, a logic "high" is output when the BER is less than or equal to a threshold value, and, otherwise, a logic "low" is output.
An AND gate 157 performs an AND operation on the output signals of the synchronous signal detector 154 and the error rate detector 156, and outputs a second detection signal. When the output signals of the synchronous signal detector 154 and the error rate detector 156 are both logic "high", a second detection signal of logic "high" is output, but otherwise, a second detection signal of logic"low" is output.
FIG. 4 is a flowchart illustrating a method for determining a received signal, according to an embodiment of the present invention. Operation of the first and second signal processors 120 and 130 to process a received signal as shown in FIG. 1 is illustrated by FIG. 4.
Refer,ing to FIG. 4, a received signal is processed simultaneously in the first and second signal processors 120 and 130, in step S101. As described above, it is preferable that the existence of the HDTV signal is first checked since the HDTV signal is transmitted at lower power than the NTSC TV signal.
Accordingly, the second detector 150 detects a synchronous (segment or field synchronous) signal from the HDTV signal processed in the second signal processor 130 and then outputs a second detection signal of logic "high" when the synchronous signal is detected, as shown in FIG. 2, in step S102. Or, the seconddetector 150 performs detections of a synchronous signal and an error rate, and then outputs a second detection signal of logic "high" when the synchronous signal iS detected and the error rate is less than or equal to a threshold value, as shown in FIG. 3, in step S102. The determination signal generator 160 outputs to the selector 170 a determination signal for selecting the output of the second signal processor 130, when the second detection signal is logic "high", in step S103.
If a second detection signal of logic "low" is output from the second detector 150 in step S102, the first detector 140 detects a synchronous (horizontal or vertical synchronous) signal or a GCR signal from the NTSC TV signal processed by the first signal processor 120, and outputs a first detection signal of logic "high"
CA 0224l379 l998-06-22 if the synchronous signal or GCR signal is detected, in step S104. The determination signal generator 160 outputs to the selector 170 a determination signal for selecting the output of the first signal processor 120, if the first detection signal is logic "high", in step S105. If the first detection signal is logic "low" in step S104, the procedure returns to step S101, and then the steps following step S101are repeated.
FIG. 5 is a flowchart illustrating a method for determining a received signal, according to another embodiment of the present invention. The simulcast receivershown in flG. 1 performs a signal processing operation in different ways, separately, but can share a pre-processor such as the block 131 shown in FIG. 2 according to circumstances. Accordingly, the determination method shown in FIG.
5 is proposed.
That is, first, the second signal processor 130 is operated to process a received signal, according to channel selection, in step S201. The second detector 150 detects a synchronous (segment or field synchronous) signal from the HDTV signal processed in the second signal processor 130 and outputs a second detection signal of logic "high" when the synchronous signal is detected,as shown in FIG. 2, in step S202. Or, the second detector 150 detects a synchronous signal and an error rate, and then outputs a second detection signalof logic "high" when the synchronous signal is detected and the error rate is less than or equal to the threshold value, as shown in FIG. 3, in step S202. The determination signal generator 160 outputs to the selector 170 a determination signal for selecting the output of the second signal processor 130, when the second detection signal is logic"high", in step S203.
If a second detection signal of logic "low" is output from the second detector 150 in step S202, the first signal processor 120 operates to process a received signal, in step S204. The first detector 140 detects a synchronous (horizontal or vertical synchronous) signal or a GCR signal from the NTSC TV signal processed by the first signal processor 120, and outputs a first detection signal of logic "high"
if the synchronous signal or GCR signal is detected, in step S205. The determination signal generator 160 outputs to the selector 170 a determination signal for selecting the output of the first signal processor 120, if the first detection signal is logic "high", in step S206. If the first detection signal is also logic "low", in step S205, the procedure returns to step S201, and then the steps following step S201 are repeated.
The present invention can be applied not only to the simulcast receiver for 5 receiving both analog broadcasting (NTSC TV) and HDTV signals, but also to a receiver for receiving a digital terrestrial wave HDTV signal which is scheduled to be broadcasted. That is, the HDTV receiver includes at least a signal processor for demodulating a received HDTV signal having a digital format into a base bandand decoding the result, and a display for displaying caption data indicating 10 whether a channel selected by a user according to a determination HDTV channel or an analog broadcasting TV (NTSC T\/) channel. Also, the HD signal according to the present invention includes a standard definition (SD) signal.
As described above, in a simulcast receiver for receiving both an HDTV
signal and an analog broadcasting signal when an HDTV broadcasting and an existing analog broadcasting coexist, or in an HDTV receiver, the present invention can correctly determine a received signal according to channel selection. Also, in the present invention, since the HDTV signal is transmitted at a lower power than the existing analog broadcasting TV signal, the HDTV signal is detected first todetermine the received signal. Therefore, determination is more reliable.
However, when full-scale HDTV broadcasting starts, it cannot avoid coexistence with an existing analog broadcasting system (here, NTSC). Also, a receiver must allow a viewer to watch either HDTV or NTSC broadcasting at will.
That is, a channel may be for NTSC TV broadcasting in some areas and for HDTV
broadcasting in other areas, so a receiver must have a structure by which either of the two broadcastings can be selected and viewed. Such a simulcast receiver for 20 receiving both HDTV and NTSC TV signals is usually comprised of a tuner, an HDTV signal processor for processing HDTV signals, an NTSC TV signal processor for processing NTSC TV signals, and a display. Accordingly, before an HDTV or NTSC TV signal is selected and displayed on the single display, it must be determined whether the current received signal is an HDTV or NTSC TV signal.
A receiver for receiving the HDTV signal also requires a circuit for determiningwhether the current received signal is an HDTV or NTSC TV signal, in order to display whether a channel selected by a user is an HDTV or NTSC TV channel.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a circuit for correctly determining whether a received signal is an HDTV signal or an analog TV signal upon channel selection in a simulcast receiver.
It is another object of the present invention to provide a circuit for correctlydetermining whether a received signal is an HDTV signal or an analog TV signal in an HDTV receiver.
It is still another object of the present invention to provide a method for correctly determining whether a received signal is an HDTV signal or an analog TV signal.
It is yet another object of the present invention to provide a method for selecting a received signal in order of priority according to selection of channels, when an HDTV signal and an analog ~V signal are simultaneously received.
It is still yet another object of the present invention to provide a method for correctly determining a received signal according to channel selection when an HDTV signal and an analog TV signal are separately processed in a simulcast receiver.
It is further another object of the present invention to provide a method for correctly determining a received signal according to channel selection when an HDTV signal and an analog TV signal are partially processed together in a simulcast receiver.
To accomplish the above objects, there is provided a circuit for determining a received signal, comprising: a first detector for detecting a first reference signal included in a received signal and outputting a first detection signal; a second detector for detecting a second reference signal included in the received signaland outputting a second detection signal; and a generator for generating a determination signal which indicates that the received signal is an analog broadcasting signal, if the first detection signal is detected, and indicates that the received signal is a high definition signal, if the second detection signal is detected.
Also, a method for determining whether a received signal is a high-definition signal having a digital format or an analog broadcasting signal, includes the steps of: detecting a first reference signal included in the received signal and outputting a first detection signal; detecting a second reference signal included in the CA 0224l379 l998-06-22 received signal and outputting a second detection signal; and generating a determination signal which indicates that the received signal is an analog broadcasting signal, if the first detection signal is detected, and indicates that the received signal is a high definition signal, if the second detection signal is detected.
BRIEF DESCRIPTION OF THE DRAWINGS
The above objects and advantages of the present invention will become more apparent by describing in detail preferred embodiments thereof with reference to the attached drawings in which:
FIG. 1 is a block diagram of a received signal determining circuit in a simulcast receiver according to an embodiment of the present invention;
FIG. 2 is a block diagram of a second signal processor and a second detector shown in FIG. 1;
FIG. 3 is another block diagram of a second signal processor and a second detector shown in FIG. 1;
FIG. 4 is a flowchart illustrating a method for determining a received signal, according to an embodiment of the present invention; and FIG. 5 is a flowchart illustldting a method for determining a received signal according to another embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
Referring to FIG. 1, a simulcast receiver for receiving both HDTV and NTSC
TV signals, according to the present invention, includes a tuner 110, first and second signal processors 120 and 130 for processing NTSC TV and HDTV
signals, respectively, and a display 180. Accordingly, a determination of whether a current received signal is the HDTV or NTSC TV signal must be made to selectively display either the HDTV or NTSC TV signal on a single display 180. Adetermining circuit for performing the above-described determination includes a first detector 140, a second detector 150 and a determination signal generator 160. A selector 170 selects either an NTSC TV signal demodulated by the first signal processor 120 or an HDTV signal demodulated by the second signal processor 130, according to a determination signal generated from the determination circuit.
That is, the first detector 140 of the determination circuit determines the existence or non-existence of the NTSC TV signal according to whether a verticalor horizontal synchronous signal exists, and outputs a first detection signal which is "high" if the synchronous signal exists and "low" if not. Here, the existence or non-existence of the NTSC TV signal can be also determined by a ghost cancellation reference (GCR) signal transmitted for a vertical blanking period to remove ghosting, in addition to using the determination of the synchronous signal.
In this case, a determination of whether the NTSC TV signal exists is made by checking a correlation between the GCR signal and the received signal.
A ghosting phenomenon, where a shadow image is generated on a TV
screen, occurs because an electromagnetic wave emitted from a broadcasting station is reflected by a mountain, a building, etc. In order to remove such a ghosting phenomenon, the broadcas~ing station transmits a predetermined reference signal (here, GCR signal) to allow a receiver to know the characteristics of a transmission channel. Then, the receiver understands the ghosting characteristics of a channel using the reference signal transmitted, and filters a received image signal. A GCR signal for removing the ghosting and a device therefor are disclosed in U.S. Patent "No. 5,389,977" issued to the present applicant.
The second detector 150 detects a field or segment synchronous signal included in the HDTV signal to determine whether the HDTV signal exists. That is, since a field synchronous segment of the HDTV signal is formed in a predetermined pseudo number (PN) sequence, the existence or non-existence of the HDTV signal can be determined by an inspection of the correlation between a received signal and a pre-stored reference signal.
Thus, the second detector 150 also outputs a second detection signal which is "high" if a field or segment synchronous signal exists in a signal output from the second signal processor 130, and is "low" if not. The determination signal generator 160 receives the first and second detection signals from the first andsecond detectors 140 and 150, and outputs a determination signal to the selector 170 to output a proper signal corresponding to a channel selected by determininga received signal as shown in FIG. 4. It is preferable that the existence or non-existence of the HDTV signal is first determined since the HDTV signal is generally transmitted at a lower power than the NTSC TV signal.
FIG. 2 is a block diagram of an example of the second signal processor 130 and a second detector 150. Referring to FIG. 2, elements from a block 131 to an error correction decoder 137 correspond to the second signal processor 130.
The block 131 controls the amplitude of an IF signal output from the tuner 110 shown in FIG. 1, demodulates the IF signal to a base-band signal using a pilot signal included in the IF signal, and converts the demodulated signal into digital data. An NTSC rejection filter (NRF) 132 removes an NTSC component from the output of the block 131 to prevent degradation of the HDTV signal by the NTSC
TV signal. Here, the NRF 132 may be constituted of a comb filter, as a representative example.
An NRF selection controller 133 generates a selection signal for selecting the path having a smaller error out of a path having passed through the NRF 132 and a path having not passed therethrough, and applies the selection signal to afirst selector 134, an adaptive equalizer 135, a phase tracker 136 and the errorcorrection decoder 137. The first selector 134 selects either a signal (15-level) which has passed through the NRF 132 or the output signal (8-level) of the block131 which has not passed through the NRF 132, according to the selection signal.The adaptive equalizer 135, the phase tracker 136 and the error correction decoder 137 are operated to adapt to a selected signal state.
The adaptive equaiizer 135 removes multipath distortion (another name for ghosting) included in the signal selected by the first selector 134. The phase tracker 136 removes a phase error, i.e., phase noise, in the equalized signal output from the adaptive equalizer 135. The error correction decoder 137 error-correction decodes the output of the phase tracker 136.
Meanwhile, a second selector 151 of the second detector 150 shown in FIG. 1 selects either a signal from which co- channel interference has been removed, output from the NRF 132, or a signal output from the phase tracker 136.The signal selected by the second selector 151 is output to a synchronous signal CA 0224l379 l998-06-22 detector 152. Here, the output signal of the phase tracker 136 is a signal from which other interferences, i.e., moving ghosting and phase noise, as well as theco-channel interference, have been removed. The adaptive equalizer 135 and the phase tracker 136 can be called a post-processor.
The synchronous signal detector 152 detects a field or segment synchronous signal included in a signal selected by the second selector 151, andoutputs a first detection signal which is logic "high" signal if the field or segment synchronous signal is detected, and is logic "low" signal if not.
FIG. 3 is a block diagram of another example of the second signal processor 130 and the second detector 150 shown in FIG. 1. Elements from a block 131 through to an error correction decoder 137 constitute the second signal processor 130. A second selector 153, a synchronous signal detector 154, a thirdselector 155, an error rate detector 156 and an AND gate 157 constitute the second detector 150, are omitted from this description. The second detector 150 shown in FIG. 3 determines that a signal exists only when an error rate is lowerthan or equal to a predetermined value, by detecting both a synchronous signal and an error rate.
That is, the synchronous signal detection is performed by the second selector 153 and the synchronous signal detector 154. The error rate detection is performed by the third selector 155 and the error rate detector 156. The third selector 155 selects either the output of the phase tracker 136 or the output of the error correction decoder 137. If the output of the phase tracker 136 is selected by the third selector 155, the error rate detector 156 obtains a symbol error rate by comparing a signal processed by the phase tracker 136 with a known signal (e.g.,a 511PN signal) in a field synchronous segment, since the output signal of the phase tracker 136 exists in a symbol state. The error detector 156 outputs a logic "high" signal if the obtained error rate is less than or equal to a predetermined threshold value, and otherwise outputs a logic"low" signal.
Similarly, if the output of the error correction decoder 137 is selected by the third selector 155, then since a bit error rate (BER) can be estimated using a signal (here, a flag) which indicates the restoration or non-restoration of a bit error-corrected by the error correction decoder 137, the error rate detector 156 CA 0224l379 l998-06-22 accumulates a flag output from the error correction decoder 137 and compares theestimated BER with a predetermined threshold value. Then, a logic "high" is output when the BER is less than or equal to a threshold value, and, otherwise, a logic "low" is output.
An AND gate 157 performs an AND operation on the output signals of the synchronous signal detector 154 and the error rate detector 156, and outputs a second detection signal. When the output signals of the synchronous signal detector 154 and the error rate detector 156 are both logic "high", a second detection signal of logic "high" is output, but otherwise, a second detection signal of logic"low" is output.
FIG. 4 is a flowchart illustrating a method for determining a received signal, according to an embodiment of the present invention. Operation of the first and second signal processors 120 and 130 to process a received signal as shown in FIG. 1 is illustrated by FIG. 4.
Refer,ing to FIG. 4, a received signal is processed simultaneously in the first and second signal processors 120 and 130, in step S101. As described above, it is preferable that the existence of the HDTV signal is first checked since the HDTV signal is transmitted at lower power than the NTSC TV signal.
Accordingly, the second detector 150 detects a synchronous (segment or field synchronous) signal from the HDTV signal processed in the second signal processor 130 and then outputs a second detection signal of logic "high" when the synchronous signal is detected, as shown in FIG. 2, in step S102. Or, the seconddetector 150 performs detections of a synchronous signal and an error rate, and then outputs a second detection signal of logic "high" when the synchronous signal iS detected and the error rate is less than or equal to a threshold value, as shown in FIG. 3, in step S102. The determination signal generator 160 outputs to the selector 170 a determination signal for selecting the output of the second signal processor 130, when the second detection signal is logic "high", in step S103.
If a second detection signal of logic "low" is output from the second detector 150 in step S102, the first detector 140 detects a synchronous (horizontal or vertical synchronous) signal or a GCR signal from the NTSC TV signal processed by the first signal processor 120, and outputs a first detection signal of logic "high"
CA 0224l379 l998-06-22 if the synchronous signal or GCR signal is detected, in step S104. The determination signal generator 160 outputs to the selector 170 a determination signal for selecting the output of the first signal processor 120, if the first detection signal is logic "high", in step S105. If the first detection signal is logic "low" in step S104, the procedure returns to step S101, and then the steps following step S101are repeated.
FIG. 5 is a flowchart illustrating a method for determining a received signal, according to another embodiment of the present invention. The simulcast receivershown in flG. 1 performs a signal processing operation in different ways, separately, but can share a pre-processor such as the block 131 shown in FIG. 2 according to circumstances. Accordingly, the determination method shown in FIG.
5 is proposed.
That is, first, the second signal processor 130 is operated to process a received signal, according to channel selection, in step S201. The second detector 150 detects a synchronous (segment or field synchronous) signal from the HDTV signal processed in the second signal processor 130 and outputs a second detection signal of logic "high" when the synchronous signal is detected,as shown in FIG. 2, in step S202. Or, the second detector 150 detects a synchronous signal and an error rate, and then outputs a second detection signalof logic "high" when the synchronous signal is detected and the error rate is less than or equal to the threshold value, as shown in FIG. 3, in step S202. The determination signal generator 160 outputs to the selector 170 a determination signal for selecting the output of the second signal processor 130, when the second detection signal is logic"high", in step S203.
If a second detection signal of logic "low" is output from the second detector 150 in step S202, the first signal processor 120 operates to process a received signal, in step S204. The first detector 140 detects a synchronous (horizontal or vertical synchronous) signal or a GCR signal from the NTSC TV signal processed by the first signal processor 120, and outputs a first detection signal of logic "high"
if the synchronous signal or GCR signal is detected, in step S205. The determination signal generator 160 outputs to the selector 170 a determination signal for selecting the output of the first signal processor 120, if the first detection signal is logic "high", in step S206. If the first detection signal is also logic "low", in step S205, the procedure returns to step S201, and then the steps following step S201 are repeated.
The present invention can be applied not only to the simulcast receiver for 5 receiving both analog broadcasting (NTSC TV) and HDTV signals, but also to a receiver for receiving a digital terrestrial wave HDTV signal which is scheduled to be broadcasted. That is, the HDTV receiver includes at least a signal processor for demodulating a received HDTV signal having a digital format into a base bandand decoding the result, and a display for displaying caption data indicating 10 whether a channel selected by a user according to a determination HDTV channel or an analog broadcasting TV (NTSC T\/) channel. Also, the HD signal according to the present invention includes a standard definition (SD) signal.
As described above, in a simulcast receiver for receiving both an HDTV
signal and an analog broadcasting signal when an HDTV broadcasting and an existing analog broadcasting coexist, or in an HDTV receiver, the present invention can correctly determine a received signal according to channel selection. Also, in the present invention, since the HDTV signal is transmitted at a lower power than the existing analog broadcasting TV signal, the HDTV signal is detected first todetermine the received signal. Therefore, determination is more reliable.
Claims (28)
1. A circuit for determining a received signal, comprising:
a first detector for detecting a first reference signal included in a received signal and outputting a first detection signal;
a second detector for detecting a second reference signal included in the received signal and outputting a second detection signal; and a generator for generating a determination signal which indicates that the received signal is an analog broadcasting signal, if the first detection signal is detected, and indicates that the received signal is a high definition signal, if the second detection signal is detected.
a first detector for detecting a first reference signal included in a received signal and outputting a first detection signal;
a second detector for detecting a second reference signal included in the received signal and outputting a second detection signal; and a generator for generating a determination signal which indicates that the received signal is an analog broadcasting signal, if the first detection signal is detected, and indicates that the received signal is a high definition signal, if the second detection signal is detected.
2. The circuit for determining a received signal as claimed in claim 1, wherein the first reference signal is a horizontal or vertical synchronous signal.
3. The circuit for determining a received signal as claimed in claim 1, wherein the first reference signal is a ghost cancellation reference (GCR) signal.
4. The circuit for determining a received signal as claimed in claim 1, wherein the second reference signal is a segment or field synchronous signal.
5. The circuit for determining a received signal as claimed in claim 1, wherein said second detector further comprises a symbol error rate detector for detecting a symbol error rate of the received signal and outputting the second detection signal if the detected symbol error rate is less than or equal to a predetermined value.
6. The circuit for determining a received signal, as claimed in claim 1, wherein said second detector further comprises a bit error rate detector for detecting a bit error rate of the received signal and outputting the second detection signal if the detected bit error rate is less than or equal to a predetermined value.
7. A circuit for determining a received signal by generating a determination signal, in a simulcast receiver including a tuner for receiving a high-definition Television (HDTV) signal having a digital format and an analog broadcasting TV signal, a first signal processor for demodulating and decoding the analog broadcasting TV signal output from said tuner, a second signal processor for demodulating and decoding the HDTV signal output from said tuner, and a display for displaying one of the output signals of said first and second signalprocessors which is selected according to a determination signal, said circuit comprising:
a first detector for detecting a first reference signal included in the receivedsignal and outputting a first detection signal;
a second detector for detecting a second reference signal included in the received signal and outputting a second detection signal; and a generator for generating a determination signal which indicates that the received signal is an analog broadcasting TV signal, if the first detection signal is detected, and indicates that the received signal is an HDTV signal, if the second detection signal is detected.
a first detector for detecting a first reference signal included in the receivedsignal and outputting a first detection signal;
a second detector for detecting a second reference signal included in the received signal and outputting a second detection signal; and a generator for generating a determination signal which indicates that the received signal is an analog broadcasting TV signal, if the first detection signal is detected, and indicates that the received signal is an HDTV signal, if the second detection signal is detected.
8. The circuit for determining a received signal as claimed in claim 7, wherein the first reference signal is a horizontal or vertical synchronous signal.
9. The circuit for determining a received signal as claimed in claim 7, wherein the first reference signal is a ghost cancellation reference (GCR) signal.
10. The circuit for determining a received signal as claimed in claim 7, wherein said second signal processor comprises:
a demodulator for demodulating the HDTV signal output from said tuner and outputting a first signal;
a co-channel interference remover for removing co- channel interference from the first signal and outputting a second signal;
a first selector for selecting either the first or second signal according to a selection signal and outputting a selected signal;
a post-processor for removing other interferences from the selected signal and outputting a post-processed signal; and a selection controller for determining whether the co- channel interference is included in the post-processed signal, and generating the selection signal, and wherein said second detector comprises:
a second selector for selecting either the first signal or the post-processed signal; and a synchronous signal detector for checking a correlation between a second reference signal included in a signal selected by said second selector and a reference pattern, and outputting a second detection signal.
a demodulator for demodulating the HDTV signal output from said tuner and outputting a first signal;
a co-channel interference remover for removing co- channel interference from the first signal and outputting a second signal;
a first selector for selecting either the first or second signal according to a selection signal and outputting a selected signal;
a post-processor for removing other interferences from the selected signal and outputting a post-processed signal; and a selection controller for determining whether the co- channel interference is included in the post-processed signal, and generating the selection signal, and wherein said second detector comprises:
a second selector for selecting either the first signal or the post-processed signal; and a synchronous signal detector for checking a correlation between a second reference signal included in a signal selected by said second selector and a reference pattern, and outputting a second detection signal.
11. The circuit for determining a received signal as claimed in claim 10, wherein the second reference signal is a segment or field synchronous signal.
12. The circuit for determining a received signal as claimed in claim 10, wherein said second detector further comprises:
a symbol error rate detector for detecting a symbol error rate of the post-processed signal and determining whether the detected symbol error rate is less than or equal to a predetermined value; and a logic circuit for performing an AND operation on the outputs of said synchronous signal detector and said symbol error rate detector and outputting asecond detection signal.
a symbol error rate detector for detecting a symbol error rate of the post-processed signal and determining whether the detected symbol error rate is less than or equal to a predetermined value; and a logic circuit for performing an AND operation on the outputs of said synchronous signal detector and said symbol error rate detector and outputting asecond detection signal.
13. The circuit for determining a received signal as claimed in claim 10, wherein said second signal processor further comprises:
an error correction decoder for error-correction decoding the post-processed signal and outputting an indication signal for indicating whether an error-corrected bit is restored, and wherein said second detector further comprises:
a bit error rate detector for detecting a bit error rate by accumulating the indication signals, and determining whether the detected bit error rate is less than or equal to a predetermined value; and a logic circuit for performing an AND operation on the outputs of said synchronous detector and said bit error rate detector and outputting a second detection signal.
an error correction decoder for error-correction decoding the post-processed signal and outputting an indication signal for indicating whether an error-corrected bit is restored, and wherein said second detector further comprises:
a bit error rate detector for detecting a bit error rate by accumulating the indication signals, and determining whether the detected bit error rate is less than or equal to a predetermined value; and a logic circuit for performing an AND operation on the outputs of said synchronous detector and said bit error rate detector and outputting a second detection signal.
14. A circuit for determining a received signal by generating a determination signal, in a high-definition signal receiver including a signal processor for demodulating and decoding a received high-definition television (HDTV) signal having a digital format, and a display for displaying caption dataindicating whether a channel selected by a user according to the determination signal is a HDTV channel or an analog broadcasting TV channel, said circuit comprising:
a first detector for detecting a first reference signal included in the receivedsignal and outputting a first detection signal;
a second detector for detecting a second reference signal included in the received signal and outputting a second detection signal; and a generator for generating a determination signal which indicates that the received signal is an analog broadcasting TV signal, if the first detection signal is detected, and indicates that the received signal is an HDTV signal, if the second detection signal is detected.
a first detector for detecting a first reference signal included in the receivedsignal and outputting a first detection signal;
a second detector for detecting a second reference signal included in the received signal and outputting a second detection signal; and a generator for generating a determination signal which indicates that the received signal is an analog broadcasting TV signal, if the first detection signal is detected, and indicates that the received signal is an HDTV signal, if the second detection signal is detected.
15. The circuit for determining a received signal as claimed in claim 14, wherein the first reference signal is a horizontal or vertical synchronous signal.
16. The circuit for determining a received signal as claimed in claim 14, wherein the first reference signal is a ghost cancellation reference (GCR) signal.
17. The circuit for determining a received signal as claimed in claim 14, wherein the second reference signal is a segment or field synchronous signal.
18. The circuit for determining a received signal as claimed in claim 14, wherein said second detector further comprises a symbol error rate detector for detecting a symbol error rate of the received signal and outputting the second detection signal if the detected symbol error rate is less than or equal to a predetermined value.
19. The circuit for determining a received signal as claimed in claim 14, wherein said second detector further comprises a bit error rate detector for detecting a bit error rate of the received signal and outputting the second detection signal if the detected bit error rate is less than or equal to a predetermined value.
20. A method for determining whether a received signal is a high-definition signal having a digital format or an analog broadcasting signal,comprising the steps of:
(a) detecting a first reference signal included in the received signal and outputting a first detection signal;
(b) detecting a second reference signal included in the received signal and outputting a second detection signal; and (c) generating a determination signal which indicates that the received signal is an analog broadcasting signal, if the first detection signal is detected, and indicates that the received signal is a high definition signal, if the second detection signal is detected.
(a) detecting a first reference signal included in the received signal and outputting a first detection signal;
(b) detecting a second reference signal included in the received signal and outputting a second detection signal; and (c) generating a determination signal which indicates that the received signal is an analog broadcasting signal, if the first detection signal is detected, and indicates that the received signal is a high definition signal, if the second detection signal is detected.
21. The method for determining a received signal as claimed in claim 20, wherein the first reference signal is one of a horizontal synchronous signal, a vertical synchronous signal and a ghost cancellation reference (GCR) signal.
22. The method for determining a received signal as claimed in claim 21, wherein the second reference signal is a segment or field synchronous signal.
23. A method for determining a received signal by generating a determination signal, in a simulcast receiver including a tuner for receiving a high-definition television (HDTV) signal having a digital format and an analog broadcasting TV signal, a first signal processor for demodulating and decoding the analog broadcasting TV signal output from said tuner to a base band, a second signal processor for demodulating and decoding the HDTV signal output from said tuner, and a display for displaying one of the output signals of said first and second signal processors which is selected according to the determination signal, said method comprising the steps of:
(a) operating said first and second signal processors;
(b) detecting a second reference signal included in a signal processed by said second signal processor and outputting a second detection signal;
(c) generating a determination signal for selecting the HDTV signal, according to the second detection signal;
(d) detecting a first reference signal included in a signal processed by said first signal processor and outputting a first detection signal, if the second detection signal was not detected; and (e) generating a determination signal for selecting the analog broadcasting TV signal, according to the first detection signal.
(a) operating said first and second signal processors;
(b) detecting a second reference signal included in a signal processed by said second signal processor and outputting a second detection signal;
(c) generating a determination signal for selecting the HDTV signal, according to the second detection signal;
(d) detecting a first reference signal included in a signal processed by said first signal processor and outputting a first detection signal, if the second detection signal was not detected; and (e) generating a determination signal for selecting the analog broadcasting TV signal, according to the first detection signal.
24. The method for determining a received signal as claimed in claim 23, wherein the first reference signal is one of a horizontal synchronous signal, a vertical synchronous signal, and a ghost cancellation reference (GCR) signal.
25. The method for determining a received signal as claimed in claim 23, wherein the second reference signal is a segment or field synchronous signal.
26. A method for determining a received signal by generating a determination signal, in a simulcast receiver including a tuner for receiving a high-definition television (HDTV) signal having a digital format and an analog broadcasting TV signal, a preprocessor for demodulating a signal output from said tuner, a first signal processor for decoding the analog broadcasting TV signal output from said preprocessor, a second signal processor for decoding the HDTV
signal output from said preprocessor, and a display for displaying the output signal of one of said first and second signal processors which is selected according to the determination signal, said method comprising the steps of:
(a) operating said second signal processor;
(b) detecting a second reference signal included in a signal processed by said second signal processor and outputting a second detection signal;
(c) generating a determination signal for selecting the HDTV signal, according to the second detection signal;
(d) operating said first signal processor, if the second detection signal was not detected;
(e) detecting a first reference signal included in a signal processed by said first signal processor and outputting a first detection signal; and (f) generating a determination signal for selecting the analog broadcasting TV signal, according to the first detection signal.
signal output from said preprocessor, and a display for displaying the output signal of one of said first and second signal processors which is selected according to the determination signal, said method comprising the steps of:
(a) operating said second signal processor;
(b) detecting a second reference signal included in a signal processed by said second signal processor and outputting a second detection signal;
(c) generating a determination signal for selecting the HDTV signal, according to the second detection signal;
(d) operating said first signal processor, if the second detection signal was not detected;
(e) detecting a first reference signal included in a signal processed by said first signal processor and outputting a first detection signal; and (f) generating a determination signal for selecting the analog broadcasting TV signal, according to the first detection signal.
27. The method for determining a received signal as claimed in claim 26, wherein the first reference signal is one of a horizontal synchronous signal, a vertical synchronous signal, and a ghost cancellation reference (GCR) signal.
28. The method for determining a received signal as claimed in claim 26, wherein the second reference signal is a segment or field synchronous signal.
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|---|---|---|---|
| KR97-36884 | 1997-08-01 | ||
| KR1019970036884A KR100224861B1 (en) | 1997-08-01 | 1997-08-01 | A received signal discrimination circuit and method |
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| CA2241379C true CA2241379C (en) | 2001-11-06 |
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| JP (1) | JP3383220B2 (en) |
| KR (1) | KR100224861B1 (en) |
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| KR100258931B1 (en) * | 1997-06-17 | 2000-06-15 | 윤종용 | A received signal discriminating circuit and method therefor |
| US6606129B1 (en) * | 1998-12-04 | 2003-08-12 | Samsung Electronics Co., Ltd. | Digital filtering of DTV I-F signal to avoid low-end boost of the baseband signal resulting from in-phase synchrodyne |
| US6622308B1 (en) * | 1999-03-23 | 2003-09-16 | Scientific-Atlanta, Inc. | Automatic digital television (DTV) bypass for a CATV converter using a CATV tuner |
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| US6757025B1 (en) | 1999-04-09 | 2004-06-29 | Sony Corporation | Method for switching input terminals based on incoming signal format |
| AU4208600A (en) | 1999-04-09 | 2000-11-14 | Sony Electronics Inc. | Method for switching signal input based on device capability |
| US6826776B1 (en) | 1999-04-09 | 2004-11-30 | Sony Corporation | Method and apparatus for determining signal path |
| US6976267B1 (en) | 1999-04-09 | 2005-12-13 | Sony Corporation | Method and apparatus for controlling connections between devices |
| JP3540242B2 (en) * | 2000-03-30 | 2004-07-07 | 松下電器産業株式会社 | Multi-system receiver |
| US8743285B2 (en) * | 2001-08-31 | 2014-06-03 | Thomson Licensing | Automatic return to a high-definition mode after guide demonstration |
| JP3779215B2 (en) * | 2002-01-28 | 2006-05-24 | 富士通株式会社 | Portable information processing device |
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| JP2004179718A (en) * | 2002-11-25 | 2004-06-24 | Sanyo Electric Co Ltd | Broadcast receiver |
| JP4449382B2 (en) * | 2003-09-19 | 2010-04-14 | 船井電機株式会社 | Receiving device and television apparatus equipped with the same |
| CN1890967B (en) * | 2003-12-08 | 2010-11-17 | 汤姆逊许可公司 | Digital/analog closed caption display system in a television signal receiver |
| JP2008079241A (en) * | 2006-09-25 | 2008-04-03 | Sharp Corp | Detection circuit, modulation mode discrimination circuit, integrated circuit, tuner device, and multi-system compatible receiver |
| US8584173B2 (en) * | 2009-07-10 | 2013-11-12 | EchoStar Technologies, L.L.C. | Automatic selection of video programming channel based on scheduling information |
| US9071799B2 (en) | 2012-02-17 | 2015-06-30 | Echostar Technologies L.L.C. | Channel tuning redirect |
| TW201611620A (en) * | 2014-09-05 | 2016-03-16 | 可取國際股份有限公司 | Digital video recorder and video recording and playback method thereof |
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| JPS6425684A (en) | 1987-07-22 | 1989-01-27 | Olympus Optical Co | Device for recording signal |
| JPH01137890A (en) | 1987-11-25 | 1989-05-30 | Toshiba Corp | Broadcasting system discriminating circuit |
| JPH0748836B2 (en) | 1988-02-04 | 1995-05-24 | 日本放送協会 | Television receiver |
| US5173774A (en) * | 1990-12-18 | 1992-12-22 | Zenith Electronics Corporation | Dual purpose HDTV/NTSC receiver |
| JPH04248782A (en) | 1991-02-04 | 1992-09-04 | Sharp Corp | Side panel system wide aspect television receiver |
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| DE69513699T2 (en) * | 1994-01-24 | 2000-04-06 | Toshiba Kawasaki Kk | TV receiver with a broadcast system discriminator |
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| KR19980076495A (en) * | 1997-04-10 | 1998-11-16 | 윤종용 | HDTV / NTSC receiver and receiving signal selection method |
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1997
- 1997-08-01 KR KR1019970036884A patent/KR100224861B1/en not_active IP Right Cessation
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- 1998-06-22 CA CA002241379A patent/CA2241379C/en not_active Expired - Fee Related
- 1998-06-30 JP JP18486998A patent/JP3383220B2/en not_active Expired - Fee Related
- 1998-07-15 CN CNB981160603A patent/CN1140114C/en not_active Expired - Fee Related
- 1998-07-27 US US09/122,631 patent/US6335762B1/en not_active Expired - Lifetime
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| KR19990015016A (en) | 1999-03-05 |
| JP3383220B2 (en) | 2003-03-04 |
| CN1207636A (en) | 1999-02-10 |
| JPH1175137A (en) | 1999-03-16 |
| CA2241379A1 (en) | 1999-02-01 |
| CN1140114C (en) | 2004-02-25 |
| KR100224861B1 (en) | 1999-10-15 |
| US6335762B1 (en) | 2002-01-01 |
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