CA2247092A1 - Orthogonal signal multiplexing system - Google Patents
Orthogonal signal multiplexing system Download PDFInfo
- Publication number
- CA2247092A1 CA2247092A1 CA002247092A CA2247092A CA2247092A1 CA 2247092 A1 CA2247092 A1 CA 2247092A1 CA 002247092 A CA002247092 A CA 002247092A CA 2247092 A CA2247092 A CA 2247092A CA 2247092 A1 CA2247092 A1 CA 2247092A1
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- signal
- conductors
- disk array
- chassis
- pair
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3058—Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3034—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a storage system, e.g. DASD based or network based
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3041—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is an input/output interface
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3051—Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/409—Mechanical coupling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/20—Arrangements affording multiple use of the transmission path using different combinations of lines, e.g. phantom working
Abstract
A dynamically upgradeable disk array chassis (10), a method for dynamically upgrading a data storage system, diplexed computer communications and a diplexer (50) wherein the diplexer (50) and the diplexed communications may be used in the dynamically upgradeable disk array chassis (10). The dynamically upgradeable disk array chassis (10) includes a serial bus (22) having a first bus for passing data in one direction and a second bus (24) for passing data in the opposite direction. A shunt (40) connects the first (22) and second (24) buses in a normal state. The shunt (40) has a switched state in which each of the first and second buses is coupled to a separate output from the chassis. The chassis (10) includes an environmental monitor (30) connected to a communication path (42). Upon connecting a new disk array chassis to an active disk array chassis, the environmental monitor (30) communicates through the communication path (42) before switching the shunt (40) to connect the serial bus with the serial bus of the new disk array chassis. The disk array chassis (10) may include a diplexer (50) for connecting the communication path (42) to the separate outputs of the shunt (40) and for combining the communicaton path signals with the serial path signals in one direction and for separating these signals in the other direction. The diplexer (50) may include an adder for adding the signals from the communication path with those on the serial path and a subtractor for subtracting signals of one path from the other. The environmental monitor path communications and the serial bus communications can take place over a single twinax cable (18). One signal is differentially coupled onto a first pair of conductors. A second signal is common mode coupled onto the first pair of conductors. In the opposite direction on the twinax cable (18), different signals are also differentially coupled and common mode coupled to the return pair of conductors.
Description
W O 97/32252 PCT~US97/03000 DYNAMICALLY UP&RAD1~ABLE DISK ARRAY SYSTEM AND ORTHOGONAL SMN~L h~tULTI-PLEXING SYSTEM THEREFO~
This invention relates to dynamically adding a disk array chassis to an already operating disk drive array, and communicating with the new disk array chassis over a commL~ni~tion path before the disk drives are interfaced on a high speed path with the S disk drive controller.
Back~round of the Invention Subsystems comprising disk arrays, i.e., groups of small, independent disk drivemodules used to store large quantities of data have been developed and found to possess 10 many advantages over a single large disk drive. For example, the individual modules of a disk array typically take up very little space and typically use less power and cost less than a single large disk drive, yet, when grouped together in an array, provide the same data storage capacity as a single large disk drive. In addition, the small disks of an array retrieve data more quickly than does a single large disk drive because, with a small disk 15 drive~ there is less distance for the actuator to travel and less data per individual disk to search through. The greatest advantage to small disk drives, however, is the boost they give to I10 performance when configured as a disk array subsystem.
A disk array is typically housed in a chassis, which may be an enclosure, for holding a plurality of disk drives. When additional memory storage space is required, it is ~0 desirable to be able to add an additional disk array chassis to the existing system. It is further desirable that one be able to add the new disk array chassis to the existing system without n~e-lin~ to shut down the existing system. In other words, it is desirable to provide a dynamically upgradeable disk array system.
For a system including a disk controller communicating over a loop with a ~5 plurality of disks, it is undesirable to expand that bus by simply adding more disk drives.
There may be a malfunction in any of the new disk drives. Further there may be aproblem with the new connection to the existing loop. While the functional status of the new equipment can be tested by the disk controller after it is connected to the loop, if there is a malfunction. the entire loop (and disk drives~ will be degraded and may be 30 rendered inoperable or inaccessible. Therefore, it is desirable to be able to determine the integrity of the new disk drives and bus before p~rmit~ing interface with the existing system.
W O 97/32252 PCT~US97/~3000 -- 2 --Summary of the Invention In accordance with an embodiment of the present invention, a dynamically upgradeable disk array chassis includes a chassis that contains the disk drives. The disk drives and a disk controller are connected in a loop with a first serial bus for transmitting 5 data from the controller and a second serial bus for passing data back to the controller.
The disk drives are connected to one or the other of the serial busses. A shunt is connected to the first and second busses at the end opposite the controller and has a normal state in which the first bus is connected to the second bus thus completing the loop. The shunt may also assume a state in which each of the first and second serial 10 busses are connected to separate outputs. The separate outputs are used to connect to a new disk array chassis with similar busses and shunting device. Each chassis has an environmental monitor that controls the state of its shunt. A separate serial cl mmunication bus connects to the monitor. When a new disk array chassis is connected to the existing chassis, the existing chassis's environmental monitor may communicate 1~ through its serial communication bus with the serial communication bus and environmental monitor on the new disk array chassis to determine whether conditions are suitable for extending the disk drive loop to include the disks on the new disk array chassis. If no faults are clelected, the existing chassis's environmental monitor switches its shunt to connect the disk drive serial busses of the existing disk array chassis to those 20 of the new disk array chassis. The new chassis's environmental monitor leaves its shunt in the normal state to connect the two disk drive busses and the disk drive loop is again complete.
In accordance with an embodiment of the invention, diplexing is used to provide ehe path for the serial communication bus to the environm~n~l monitor, and the signals 2~ for the disk drive loop over the same wires of a single cable connecting the disk array chassis to one another. Preferably, low frequency signals are used for the communication with the environmental monitor and high frequency signals are used for disk drive loop comml~nications including I/O operations. The low frequency signals may be sirnilar to those of the RS-232 serial data protocol and the high frequency signals may adopt the 30 Fibre Channel Arbitrated Loop signal protocol. The Fibre Channel 8B/IOB signal encoding advantageously guarantees frequent transitions on ehe Fibre Channel signal so that the signal can always be distinguished from the low frequency signals. The Fibre W O 97132252 PCTrUS97/03000 Channel encoding keeps the frequency content of the Fibre Channel signal isolated to l00 MHZ and above by guaranteeing a transition at least every 5 bits.
A diplexer is connected to the environmental monitor serial communication bus and the separate disk drive serial bus outputs of the shunt for combining the high 5 frequency data signals from the disk drive controller and the low frequency data signals from the environmental monitor serial communication bus which are to be sent out from the chassis. The diplexer also includes a configuration for separating the high frequency disk drive serial bus data signals from the low frequency environmPntzll monitor SC8 data signals coming in from the new disk array chassis. By providing a single connector and 1~ diplexing and shunt control in the presently preferred embodiment for both the low and high frequency comrnunication signals, the integrity of the new chassis may be determined over the low frequency environmental monitor communication path without electrically connecting the high frequency path and possibly disrupting operation on the existing disk array system. Only after the integrity of the connection and the operability 15 of the new disk array enclosure is determined will the existing chassis shunt be switched into the state permitting connection or the high frequency data path with the disk drives of the new disk array chassis.
Referring now more particularly to the multiplexing of the two signals, it is noted that a common Fibre Channel (FC) data comml]nic~tions link may be used. In preferred 20 embodiments of the invention, the first signal to be diplexed is a low frequency asynchronous or synchronous RS-232 type serial signal, and the second signal is the standard high frequency Fibre Channel signal. The terms "low frequency" and "high frequency" are used herein as relative to one another. As used herein, a low frequency signal is one that can be separated by filtering from the high frequency signal and vice 25 versa. The low frequency signal, which in preferred embodiments is used to communicate between environmental monitor UARTS, is extremely slow in comparison to the Fibre Channel signal. This signal, preferably tr~n~mitte~l at 9600 baud, has a maximumfilncl~ml~ntal frequency of 4.8 kHz, and a minimllm frequency of DC. The square wave nature of this signal will normally have higher order harmonics which extend to very high 30 frequencies. Consequently, in preferred embodiments of the invention, these harmonics may be limited by low pass filtering without affecting the inforrnation content of the signal, with the intended result of isolating the RS-232 type signal to a low frequency W O 97/32252 PCT~US97/030nO -- 4 --band from DC to about 100 kHz. The high frequency FC signal is limited to 100 ~HZ.
and beyond by the aforementioned 8B/IOB encoding.
In an embodiment of the present invention, the high frequency Fibre Channel, andthe low frequency RS-232 type signal, are frequency division multiplexed into a 5 composite signal which is sent over a single cable. The cable will preferably be a twinax Fibre Channel arbitrated loop standard configuration having two conductor pairs ( 1 pair for each direction) contained within a common shield. Isolation between the two conductor pairs is m~int~ined by locating the two pairs orthogonally in the cable. Each pair will contain a FC signal in differential mode, and a RS-232 signal in common mode.
10 In each conductor pair, one wire conducts a sum of the high frequency FC signal and the low frequency RS-232 type signal and the other wire conducts the difference resulting when the high frequency FC signal is subtracted from the low frequency RS-232 type slgnal.
Brief Description of the Drawin~s The invention may be more readily understood by reference to the following detailed description, taken with the accompanying drawings, in which:
FIG. 1 is a block diagram of a chain of dynarnically upgradeable disk array chassis of the present invention.
FIG. 2 is a flow chart of an upgrading algorithm for use with the present invention.
F~G. 3 is a block diagrarn of a system of interconnected disk array chassis.
FIG. 4 is a block diagram of an environmental monitor for use in the disk array chassis of F~G. 1.
FIG. S is a graph showing the diplex filter frequency response.
2~ FIG. 6 is a figure showing the composite Fibre Channel and RS-232 type signals.
FIG. 7 is a circuit diagram for the differential coupling circuit.
FIG. 8 is a circuit diagram showing the common mode coupling circuit.
FIG. 9 is a functional diagram showing an embodiment of the invention using twin-ax or twisted-pair cable and common mode coupling.
FIG. 10 shows an implementation of the FIG. 9 circuit diagram implemented using transformers.
FIG. 11 is a schematic circuit diagram of the low frequency signal input and output W O 971322~2 PCT~US97/030~0 portions of a diplexer for use in the disk array chassis of 3:;1G. 1.
FIG. 12 is a schematic circuit diagram of the high frequency signal input portion of a diplexer for use in the disk array chassis of FIG. 1.
FIG. 13 is a schematic circuit diagram of the high fre~uency signal output portion, a shunt and an expansion connector for use in the disk array chassis of FIG. 1.
Detailed Description of the Preferred Embo(liments Referring now to the drawings, a disk array chassis 10 is shown in block diagramforrn in F~G. 1. The disk array chassis provides a series of openings into which disk 10 drives 12 may be inserted. The chassis 10 of FIG. 1 is shown capable of housing a specified number of disk drives 12, for example ten. The mechanical chassis may be an open or closed housing or enclosure. Inside the chassis are conventional auxiliary equipment 14 including cooling fans, power supplies and a display card . The display card controls a display on the outside of the housing which may be used to exhibit certain status conditions. Status conditions are determine~ by the environmental monitor.
The disk drives are interconnected by a high speed serial data communication path.
In accordance with the presently preferred embodiment, the commllniczltion path is a loop including a first serial bus 22 directing data in one direction and a second serial bus 24 directing data in a second opposite direction. The preferred data loop is a Fibre Channel arbitrated loop. A series of port bypass circuits 26 are inserted along the loop for making the connection with the disk drives 12. Each port bypass circuit 26is controlled by an environmental monitor 30. The control line between the environmental monitor 30 and the port bypass circuit 26 exists, but is not shown in FIG. 1. When the port bypass circuit is in its bypassed condition, its associated disk drive is shnnted out of the loop. The environmental monitor 30 switches the port bypass circuit 26 into a non-bypassedcondition so that signals on the serial bus are directed to and from the associated disk drive. In order to provide a high availability system, the disk array chassis of the presently ~lc~fGllGd embodiment may include two high speed data commllnic~tion loops and environm~nt~l monitors acting redundantly. Each loop is connected llltim~ely to a disk 30 controller 16. The two disk control processors 16, one for each loop, further serve to provide high availability of the data storage system.
It is desirable that the disk array chassis perrnit dynamic upgrading. In that regard, W O 97/32252 PCT~US97/03000 _ ~ _ a shunt 40 is provided along the Fibre Channel loop. In the presently preferred embodiment, the shunt 40 may be a port bypass circuit. The first serial bus 22 providing data in a first direction is connected to the shunt and the second serial bus 24 providing data in the opposite direction is also connected to the shunt. When the shunt is in its S normally bypassed condition, the Fibre Channel loop ends at the shunt and data passes directly from the first serial bus 22 through the shunt to the second serial bus 24. When the shunt is switched into a non-bypassed state, the f1rst bus 22 is allowed to pass to an expansion connection 52 and the second bus is connected to an incorning signal from the expansion connection. This extends the Fibre Channel loop into the next chassis.The shunt is controlled by the environmental monitor 30. The environm~nt~l monitor 30 is provided with a serial communication path 42 that can lead to an adjacent dislc array chassis. The environmental monitor is a supplier of status signals and other environmental information. The monitor may be any entity that sequences the status signals onto the serial communication path 42. The environmental monitors of the15 presently preferred embodiment are provided with two universal asynchronous receiver tr:~nsmitters 44 (UART) for communicating with a chassis connected at either end of the chassis housing the monitor. While the communication path 42 may be provided forconnection to an adjoining disk array chassis separate from the Fibre Channel loop, in accordance with the presently preferred embodiment of the invention, the cornmunication 20 path 42 is provided as a path for low frequency signals which are diplexed with the high fre~uency Fibre Channel signals for transmission over a single cable 18. Preferably a twinax cable 18 is used. This is a standard cable for Fibre Channel. The presentinvention advantageously adds a low frequency signal to the high frequency FibreChannel signals normally carried by the cable. A twinax cable 18 includes four wire 25 conductors, each divided into two pairs. Each pair transports signals in a single direction so one pair is used for the exiting signals and the other pair of wires in the twinax cable 18 is used for the returning signals.
A diplexer ~() is preferably connected to transmit and receive the low frequencysignals from the environmental monitor 30 and also to transmit and receive high 30 frequency signals from the shunt 40. The other end of the diplexer is connected to a cable connector 52. Regardless of the state of the shunt, communications between disk array chassis environmental monitors are possible over the single twinax cable 18. The disk W O 97/32252 PCTrUS97/03000 array chassis includes a diplexer on both ends of the high frequency drive serial busses, except for the f1rst chassis 110 that houses the disk controller 16 where only one diplexer is required. Comml~nications can thus be m~intzt;ned with the preceding and subse~uent disk array chassis. The environmental monitor communicates with low frec~uency signals 5 that can be separated from the high frequency Fibre Channel signals by filtering in the diplexer. The signals from the diplexed cables can be split with one copy of the signals being high pass filtered while the other copy of the signals is low pass filtered to extract each of the two separate signals. A preferred method of diplexing, however, will be described later herein.
A data storage system is configured by providing l or more disk control processors 16, each in communication with one of the Fibre ~hannel loops and in low frequency communication with the environmental monitors. Disk array chassis are connected to the processors in a continuous chain. The arrangement of the high frequency communication path with two serial busses through each disk array chassis providing cornmunications in 15 each direction permits a high frequency loop. The shunt in each disk array chassis is in the non-bypassed position except for the final active disk array chassis in the chain which remains in the normal bypass condition closing the loop. The disk control processors 16 may be provided in a first chassis 110 along with a disk array. This first chassis 110 in the chain only requires a single diplexer since there is no connection to a prece-ling 20 chassis.
Dynamically upgrading a data storage system of the invention shall now be described. An existing chain of disk storage chassis is provided. The system may include a single chassis enclosing a disk array with the disk controller. Alternatively, the system may include additional disk array chassis connected in a chain to the controller chassis.
25 ~he system is upgraded by connecting an additional disk array chassis to the last disk array chassis in the existing chain. A commllnic~tion cable 18 is connected from the new disk array chassis to the expansion connector 52 on the chassis of the last disk array chassis in the existing chain. This last disk array chassis in the chain has a shunt 40 which is in the normally bypassed condition connecting its first serial bus 22 to the second serial 30 bus 24 and completing the Fibre Channel loop. When the cable 18 is inserted into the connector, the shunt remains in the bypassed condition. The new disk array chassis is now in communication via the low frequency signals conducted over the low frequency W O 97J32252 PCT~US97/03000 -- 8 --serial communication path with the environmental monitor 30. After the connection has been made, the environmental monitor 30 in the existing system can communicate with the environmental monitor 30 in the new disk array chassis. If it is determined that the new disk array chassis is properly connected and operating properly, the shunt ~0 is S switched into the non-bypassed state extending the high frequency communications loop onto the new chassis.
Referring now to FIG. 2, a flow chart of the commllnications conducted along thelow frequency environmental monitor serial comm-lnication path, shall now be described.
In accordance with the presently preferred embodiment, the comm~n-lc supported by the I0 serial protocol along the communication path include a poll, read and write comm~n~l.
These commands are issued by the disk controller 16. The poll command returns the address of each chassis and an indication if that enclosure has changed state since the last poll was issued. The address of a chassis is known to the environmental monitor 30. At present, it is preferred that the address be set by manual switches on the outside of the 1~ chassis. In this manner, a chassis can be given a distinct address different from each of the other chassis that have already been connected to the existing system. Preferably, the user will address the chassis in a numerical order such as 1, 2, 3, 4 .... A read command is directed to a specific chassis address and returns det~iled environmental status about the chassis including its power, cooling and disk drive status. A write comrnand is used by 20 the disk controller to control the operation of the chassis. This command allows the disk controller to turn on or off any port bypass circuit and the shunt 40 of any chassis.
With the shunt of the penultim~te chassis still in the bypass condition, the disk controller is able to monitor and control the newly added last chassis via the diplexed serial communication path 42 without disrupting the ongoing activity on the Fibre 2~ Channel loop. This allows the disk controller to verify the configuration andenvironmental status of the new chassis before enabling the new drives onto the Fibre C~h~nnel loop. As set forth in FIG. 2, the disk controller runs a periodic polling 60 of all the environmental monitors on the system over the low frequency serial communication path 42. The poll command goes out from the disk controller and is received by all of the 30 environmental monitors that are connected to the low frequency serial communication path. Each environmental monitor 30 on the path returns its address and an in~iic~ion of whether there has been any state change since the last poll. If a new chassis is detected 62 W O 97/32252 PCT~US97/03000 _ 9 _ during this periodic polling process, a dynamic upgrading algorithm is initiated. A time delay 64 is imposed to allow for the configuration of the system to settle as the new chassis is powered up.
After completion of the time delay, the disk controller reads the status 68 from5 every environmental monitor 30 along the low frequency serial communication path 42.
The read command produces from each environmental monitor inforrnation about thecabling and address of the chassis 70. This is used to verify that the cabling is properly configured. The address is checked to be sure it is within the range of legally ~csign~hle addresses. The read will also return information as to whether the current chassis is 10 operational 72, i.e., powered and functioning properly. If a problem is found with respect to any of the environmental monitors, the Fibre Channel loop will be terminated at the previous chassis 74, 78 so that only operational chassis are permitted on the Fibre Channel loop. If the chassis is properly connected and operational, processing continues 76 until the new chassis is found 66. ~ the new enclosure is pl~pelly connected and is 15 operational, then it will be set as the last enclosure in the system 76. The shunt 40 of the previous chassis will be switched into a switched state 80 to permit Fibre Channel commlmic~tions with the disks on the new chassis. The Fibre Channel loop may then be instructed to either autom~tiç~lly if it is so set or upon manual indication perform a discovery process to reinitialize the operation on the Fibre Channel loop to include the 20 new disks. This discovery process on the Fibre Channel loop is disruptive to any Fibre Channel activity and may take several seconds to complete. Therefore, it is preferred that the system provide the system ~lminictrator with the option of autom~tic:~lly entering discovery or selecting a manual process that is initiated by a directive from the host system. The discovery process makes the disk drives known to the disk controller's Fibre 25 Channel driver and allows the upper layer protocol drivers (SCSI) to communicate with the disks.
Advantageously, communications with the new disk array chassis along the high ~requency Fibre Channel do not begin until the disk controller has had an opportunity to comml~nicate with the new disk array chassis through the low frequency communication 30 path. This process operates separately and independently through each of the two cables in a reri--n~l~nt system such as that shown in F~G. 3. Thus, a new disk array chassis in the re~ n~ nt system embodiment is added by connecting two cables to the existing chain, W O 97/32252 PCTnJS97103000 -- tO --one for each loop. The connection of each cable operates sepa~ately to enable communications over the respective Fibre Channel loop. FIG. 3 illustrates a chain of disk array chassis. At the bottom of the chain, the chassis l 10 houses a pair of disk controllers as well as a disk array. Each disk controller is in connection with one of the Fib~e 5 Channel loops. The chassis with the disk controller is used for connection to one or more host bus adaptors 112. A host bus adaptor links a host computer with the memory storage provided by the disk arrays. Each of the disk array chassis 10 in the chain is shown with one of two cables connecting each of its recll]ncl~nt loops to the adjoining disk array chassis.
A presently preferred environmental monitor 30 for use in the invention is shownin greater detail in the block diagram of FIG. 4. The monitor program is run on a microcomputer 90. The microcomputer is shown connected to the dual UART's 44. One UART is connected to the input end of the chassis, the other is connected to the expansion end. The UART receives and transmits signals on the low frequency serial 15 commllnic~rion path 42.
The environment~l monitor 30 also includes a number of status ports I00 for monitoring various conditions within the enclosure. One of the status signals is the chassis address (Encl Addr). According to the present embodiment, the address of the chassis is nl~nll~lly set by switches on the outside of the chassis. Thus, a chassis can be 20 m~nll~lly set to have an address different from the already present disk array chassis in the existing chain of chassis. Other status signals include power system status, cooIing status and drive status. The environmental monitor also includes port bypass circuit control latches 102. These control the port bypass circuits 26 for each of the disk drives that may be inserted into the disk array enclosure. Also one of the latches will control the shunt 40.
In preferred embodiments of the invention, low frequency signals and high frequency signals are frequency division multiplexed into a composite signal fortransmission on cables between chassis. They may be simply combined and separated by a dfplex f1lter at each end of the cable, hence use of the term "diplexing." FIG. S shows 30 the diplex filter frequency response. FIG. 6 shows a RS-232 type signal, a FC signal, and the diplexed composite of the two. The diplex filter has three ports, the cable port, a low pass port and a hi"h pass port. The filter is constructed by connecting the output of a hi~sh W O 97t32252 PCT~US97/03000 pass network and a low pass network together. The high pass network will preferably act as an open circuit at low frequency; the simplest form of this high pass network is a capacitor. The low pass network will preferably look like an open circuit to the high frequency Fibre Channel signal; the simplest form of the low pass network is an inductor S or a resistor. The resistor may be used if the system can tolerate the DC resistance;
alternatively, inductors may be used without loss of effectiveness, but they are not ideal devices since achieving broad bandwidth isolation with an inductor is more difficult than with resistors.
Diplexing may be used for cornmunication between a variety of types of computer 10 components. The connection between these components will preferably be with a pair of twinax cables carrying the two Fibre Channel loops. There is also an RS-232 typecommunications channel between environmental monitors. In emboclim~ ntc of the invention, the use of twinax affords two options for coupling the RS-232 type low frequency signal onto the cables. In one embodiment of the invention, the signal may be 15 applied as a differential signal on the twinax cable; in a preferred embodiment of the invention, the signal may be applied as a common mode signal to both sides of the twinax.
A circuit for the first method, differential coupling, is shown in FIG. 7. Coupling the RS-232 type low frequency signal differentially onto the twinax is one possible way to 20 pass the signal from chassis to chassis. This is the same coupling method as that used for the Fibre Channel signals. This method has the highest level of noise immllnity for the low frequency signals. Noise sources such as ground noise and low frequency magnetic fields can be easily rejected using this technique. On the down side, this coupling method will not work if equalized cable assemblies are used ~that's not to say that equalization 25 cannot be done). Another detractor is that any residual coupling of the RS-232 type low frequency signal into the FC signal will be a differential noise source and cause some amount of jitter.
Regarding ground noise, the chassis to chassis twinax-interconnects will preferably be in the range of 0 to 10 meters in length. These connections will be between - 30 chassis within a rack, or between racks in close proximity. There may be a ground voltage potential between two systems in different racks. This ground noise is sul,e~ posed on the cable as a common mode signal. The differential receiver will reject the common CA 02247092 l998-08-20 W O 97/3Z252 PCT~US97/03000 mode noise, and properly receive the differential signal.
Regarding magnetic susceptibility, in an embodiment of the invention, the twinaxcable will preferably be shielded and, in the preferred embodiment of the invention, the shield is connected to chassis ground at both ends. Although this configuration is not the 5 optimal configuration for magnetic shielding, this is required for good high frequency emissions performance. If the cable is brought into an AC magnetic field, a current will be in~ erl to flow through the cable shield, around the ground loop. This current will couple a noise voltage into the internal signals through the mutual inductance between the shield and signal conductors. This noise voltage will be coupled in as a common mode noise 10 source in this configuration, and be rejected by the receiver.
Regarding coupling noise, in an embodiment of the invention, the F;ibre Channel signal is very low amplitude relative to the RS-232 type low frequency signal. With the use of a simple R/C pulse shaping filter, and simple capacitive/resistive diplex filter, there is some residual RS-232 signal coupled into the Fibre C~hannel receiver as shown in FIG.
5. This noise is minimi71~ by making the slew rate of the RS-232 type low frequency signal as slow as possible for the required data rate. The residual noise coupled into the FC receiver is differential noise in this instance, and results in some additive jitter on the received FC signal. This noise is manageable for data rates of 9600 baud and below, while better lowpass filtering may be required for higher data rates.
Regarding external compatibility, in an embodiment of the invention, the rejection of the low frequency signal in the Fibre Channel receiver is accomplished by the AC
coupling circuit at the receiver front end. This coupling circuit uses 1000 pF capacitor and 1~0 ohm termination resistance. If a cable carrying a diplexed signal is plugged into another vendor's equipment, the residual signal coupling, described further below, may be 25 quite severe. The critical factor is the value of the coupling capacitance, as larger values increase the unwanted signal coupling. As there is no standard for this circuit, a preferred embodiment will allow for blocking the diplex signal when connecting to an external host device that cannot safely support the present invention. Preferably, a media converter will be designed to overcome such connection problems. Note, however, that this only applies 30 to JBOD configurations ("just a bunch of disks," i.e. no controller for the disks within the JBOD unit) with DB-9 twinax cables.
Regarding equalizer compatibility, in an embodiment of the invention, the low W O 97/32252 PCTrUS97/03000 frequency signal is coupled onto the twinax cable with lk ohm resistors instead of inductors. This places a high DC resistance in series with the RS-232 type low frequency driver. An equalizer, which would be used for a long twinax cable, will have a fairly low impedance between the differential signals. There will be a voltage divider effect between 5 the equalizer impedance and the coupling resistors which will severely attenuate the low frequency signal. This will be a problem if an equalized cable assembly is used. A
preferred solution to this issue is to use equalizers for the DB-9 twinax cable, and tapping off the low frequency signal before the equalizer. This would allow the DB-9 to DB-9 media converter to contain an equalizer if we want to support twinax links over 10 meters 10 long. Preferred embodiments will not operate with twinax cables which have an equalizer in the cable connector housing.
Regarding crosstalk, in an embodiment of the invention, the invention will utilize twinax having four conductors contained within a common shield (hereinafter twinax4), wherein isolation between the two conductor pairs is m:lint~ined by locating the two pairs 15 orthogonally in the cable. This insures symmetrical coupling from the + and - differential sipn~l~, and the net differential crosstalk between pairs is 0. One pair carries the outgoing signals and the other pin carries the returning signals. For differential coupling of the RS-232 type low frequency signal, there will not be any substantial crosstalk coupling from one pair to the other.
A circuit for the second method, common mode coupling, is shown in FIG. 8.
Preferred embodiments of the invention utilize the fact that the Fibre Channel receiver has common mode rejection to reduce noise coupling from the low frequency signals.
Consequently, since the two cign~ling approaches on the cable are orthogonal, allowing each receiver to reject the signal from the other. The high frequency signal will preferably 25 be driven differentially on the twinax pair, and the low frequency signal will preferably be driven on both signal conductors with the cable shield serving as the signal return path.
The advantages of this method are that it allows potentially higher signaling rates, is compatible with equalized cable assemblies, and is potentially more compatible with host in~Prf~f es The noise rejection and crosstalk performance are worse however.
Regarding ground noise issues, in an embodiment of the invention, any ground potential difference between the transmitter and receiver ends of the cables will couple directly into the common mode low frequency signal as noise. While this is not a new CA 02247092 l998-08-20 W O 97/32252 PCT~US97/03000 problem for RS-232 type links, it is often overcome by running very large signal swings.
A preferred embodiment of the invention would be to keep the swing at 5V peak to peak, or less, which may not be as immllne to this noise as traditional links.
Regarding magnetic susceptibility, in an embodiment of the invention, by running5 the low frequency signal as a common mode signal, the twinax is being used essentially as a coaxial cable. This type of cable configuration allows the shield current induced by an AC magnetic field to impose a noise voltage onto the low frequency signal. This voltage will detract from the signal's noise margin.
Regarding coupling noise, in an embodiment of the invention, coupling of the 10 RS-232 type low frequency signal into the Fibre Channel receiver is now less of a problem because the residual signal coupling is being applied as a common mode noise source. The receiver has very good rejection to low frequency common mode noise, so the noise does not create any jitter on the Fibre Channel signal. This allows the low frequency signal pulse filtering to be relaxed, and higher data rates can be accommodated.The Fibre Channel receiver has a limited common mode rejection range, so the common mode signal must be attenuated before it reaches the receiver. This attenuation is achieved by a voltage divider effect between the Fibre Channel coupling capacitors, and the 150 ohm termination impedance. Preferred embodiments will have termination mode up of two 75 ohm resistors to VBB or some other DC source to provide a common mode 20 termination.
Regarding external compatibility, in an embodiment of the invention, the attenuation of the common mode low frequency signal in the Fibre Channel receiver is accompli~h~d by the AC coupling circuit and termination at the receiver front end. The value of the coupling capacitor is less critical in this configuration, as any additional noise 25 will be rejected. ~rhe critical factor for interoperability is that the termination be common mode. As there is no standard for this circuit, a preferred embodiment will allow for blocking the diplex signal when connecting to an external host device that cannot safely support the present invention. Preferably, a media converter will be designed to overcome such connection problems. Note, however, that this only applies to JBOD configurations 30 with DB-9 twinax cables.
Regarding equali~er compatibility, in an embodiment of the invention, the common mode transmission of the low frequency signal is fully compatible with ~ CA 02247092 1998-08-20 W O 97/32252 PCTrUS97/03000 equalized cable assemblies. The equalizer will act as a low impedance in series with the signal path which will have a minim~l effect.
Regarding crosstalk, the common mode low frequency signal does have a crosstalk issue on the twinax4. The cable has capacitive coupling between the two signal pairs 5 which induces a noise voltage on the other low frequency signal in the cable. This coupling is dependent on ricetime, and is sensitive to cable length. In preferred embodiments of the invention, overall the crosstalk will only be a few percent, and will not significantly degrade the noise margin of the signal.
FIG. g is a simplified diagram of an embodiment of the diplexing of the invention, 10 wherein first and second signals are tr:ln~mitted on a comrnllnic~tion link, and wherein the communication link is preferably twin-ax or twisted pair cable having a tr~n~mi~sion-end and a receiving-end. The communication link has a pair of conductors including a f1rst conductive path and a second conductive path. The first signal to be tr~n~mitte~1 is designated as signal (A), and the second signal is de~ign~tecl as signal (B). Si~snal (A) is 15 sent as a differential mode signal. Signal (B) is sent as a common mode signal. The first conductive path contains the addition of signals (A) + (B). The second conductive path contains the subtraction of (B) - (A). At the receiving-end, the ~lrst and second conductive paths are both sent separately to an adder and a subtractor. At the subtractor, the second conductive path's signal (B)-(A) is subtracted from the first conductive path's signal 20 ~B)+(A), resulting in the (A) signal. At the adder, the second conductive path's signal (B)-(A) is added to the first conductive path's signal (B)+(A), resulting in the (B) signal. A
useful consequence of this embodiment of the invention is that in the subtractor, common mode line noise is efficiently elimin~t~ , and in the adder, differential mode line noise is also elimin~t~l F~G. 10 is a particular implementation of the FIG. 9 embodiment, using transformers.
Referring now to FIGS. 11-13, the common mode coupling embodiment of a ~ diplexer 50 is shown in greater detail. The RS-232 type low fre~uency signal output is provided to an inverter with hysteresis input 120. The signal is then passed through a low 3~1 pass filter 122. The low pass filtered signal is then common mode coupled onto the twinax cable. The return signals are summed at a node 124 where both returning signals are connected. The summed signal is low pass filtered by capacitors 126 connected to W O g7132252 PCT~US97/03000 -- 16 --ground. The summed and filtered signal is provided tO a receiver 128 which in the presently preferred embodiment is an L~ 393 dual comparator.
Referring to FIG. 13, the expansion connector 52 is shown. A DB9 connector is the presently preferred cable connector 52. Signals received on the connector are passed 5 through an equalizer 130. The received signals are then passed to the low frequency input portion of FIG. 11 and the high frequency input portion of FIG. 12 which will now be described. The high frequency input portion passes the received signals through a high pass filter 132. ~ port bypass circuit 134 then acts as a differential receiver. The differential receiver acts as a subtractor looking at the difference between the received 10 signals. The resulting high frequency signals are passed through the port bypass circuit 134 to the shunt 40 and to a signal detector 142. The output of the signal detector 142 may be used to allow the shunt 40 to remain in its normal state when no signals are detected. When a signal is detected the shunt 40 may assume its switched state if authorized by the environmental monitor.
The received signals that are passed through the shunt 40 continue onto the serial bus 24 represented by the FC-SHUNT signals. Outgoing high frequency fibre channel s;gnals are provided by serial bus 22 represented by the FC-LOOP signals. The outgoing signals are driven through the shunt 40. Depending upon the state of the shunt 40, these signals will either loop back to the serial bus 24 on the FC-SHUNT lines or proceed 20 towards the cable connector 52. The signals sent to the cable connector 52 are differentially driven by shunt 40. One signal is inverted and the other noninverted. The inverted and noninverted signals are passed through a high pass filter 138. Thereafter, the fibre channel signals are combined with the low frequency signals from the low frequency output portion of the diplexer to produce a sum of the high and low frequency signals and 25 a difference between the low and high frequency signals. The sum and difference signals may then be passed through an equalizer 140 before they reach the cable connector 52.
This invention relates to dynamically adding a disk array chassis to an already operating disk drive array, and communicating with the new disk array chassis over a commL~ni~tion path before the disk drives are interfaced on a high speed path with the S disk drive controller.
Back~round of the Invention Subsystems comprising disk arrays, i.e., groups of small, independent disk drivemodules used to store large quantities of data have been developed and found to possess 10 many advantages over a single large disk drive. For example, the individual modules of a disk array typically take up very little space and typically use less power and cost less than a single large disk drive, yet, when grouped together in an array, provide the same data storage capacity as a single large disk drive. In addition, the small disks of an array retrieve data more quickly than does a single large disk drive because, with a small disk 15 drive~ there is less distance for the actuator to travel and less data per individual disk to search through. The greatest advantage to small disk drives, however, is the boost they give to I10 performance when configured as a disk array subsystem.
A disk array is typically housed in a chassis, which may be an enclosure, for holding a plurality of disk drives. When additional memory storage space is required, it is ~0 desirable to be able to add an additional disk array chassis to the existing system. It is further desirable that one be able to add the new disk array chassis to the existing system without n~e-lin~ to shut down the existing system. In other words, it is desirable to provide a dynamically upgradeable disk array system.
For a system including a disk controller communicating over a loop with a ~5 plurality of disks, it is undesirable to expand that bus by simply adding more disk drives.
There may be a malfunction in any of the new disk drives. Further there may be aproblem with the new connection to the existing loop. While the functional status of the new equipment can be tested by the disk controller after it is connected to the loop, if there is a malfunction. the entire loop (and disk drives~ will be degraded and may be 30 rendered inoperable or inaccessible. Therefore, it is desirable to be able to determine the integrity of the new disk drives and bus before p~rmit~ing interface with the existing system.
W O 97/32252 PCT~US97/~3000 -- 2 --Summary of the Invention In accordance with an embodiment of the present invention, a dynamically upgradeable disk array chassis includes a chassis that contains the disk drives. The disk drives and a disk controller are connected in a loop with a first serial bus for transmitting 5 data from the controller and a second serial bus for passing data back to the controller.
The disk drives are connected to one or the other of the serial busses. A shunt is connected to the first and second busses at the end opposite the controller and has a normal state in which the first bus is connected to the second bus thus completing the loop. The shunt may also assume a state in which each of the first and second serial 10 busses are connected to separate outputs. The separate outputs are used to connect to a new disk array chassis with similar busses and shunting device. Each chassis has an environmental monitor that controls the state of its shunt. A separate serial cl mmunication bus connects to the monitor. When a new disk array chassis is connected to the existing chassis, the existing chassis's environmental monitor may communicate 1~ through its serial communication bus with the serial communication bus and environmental monitor on the new disk array chassis to determine whether conditions are suitable for extending the disk drive loop to include the disks on the new disk array chassis. If no faults are clelected, the existing chassis's environmental monitor switches its shunt to connect the disk drive serial busses of the existing disk array chassis to those 20 of the new disk array chassis. The new chassis's environmental monitor leaves its shunt in the normal state to connect the two disk drive busses and the disk drive loop is again complete.
In accordance with an embodiment of the invention, diplexing is used to provide ehe path for the serial communication bus to the environm~n~l monitor, and the signals 2~ for the disk drive loop over the same wires of a single cable connecting the disk array chassis to one another. Preferably, low frequency signals are used for the communication with the environmental monitor and high frequency signals are used for disk drive loop comml~nications including I/O operations. The low frequency signals may be sirnilar to those of the RS-232 serial data protocol and the high frequency signals may adopt the 30 Fibre Channel Arbitrated Loop signal protocol. The Fibre Channel 8B/IOB signal encoding advantageously guarantees frequent transitions on ehe Fibre Channel signal so that the signal can always be distinguished from the low frequency signals. The Fibre W O 97132252 PCTrUS97/03000 Channel encoding keeps the frequency content of the Fibre Channel signal isolated to l00 MHZ and above by guaranteeing a transition at least every 5 bits.
A diplexer is connected to the environmental monitor serial communication bus and the separate disk drive serial bus outputs of the shunt for combining the high 5 frequency data signals from the disk drive controller and the low frequency data signals from the environmental monitor serial communication bus which are to be sent out from the chassis. The diplexer also includes a configuration for separating the high frequency disk drive serial bus data signals from the low frequency environmPntzll monitor SC8 data signals coming in from the new disk array chassis. By providing a single connector and 1~ diplexing and shunt control in the presently preferred embodiment for both the low and high frequency comrnunication signals, the integrity of the new chassis may be determined over the low frequency environmental monitor communication path without electrically connecting the high frequency path and possibly disrupting operation on the existing disk array system. Only after the integrity of the connection and the operability 15 of the new disk array enclosure is determined will the existing chassis shunt be switched into the state permitting connection or the high frequency data path with the disk drives of the new disk array chassis.
Referring now more particularly to the multiplexing of the two signals, it is noted that a common Fibre Channel (FC) data comml]nic~tions link may be used. In preferred 20 embodiments of the invention, the first signal to be diplexed is a low frequency asynchronous or synchronous RS-232 type serial signal, and the second signal is the standard high frequency Fibre Channel signal. The terms "low frequency" and "high frequency" are used herein as relative to one another. As used herein, a low frequency signal is one that can be separated by filtering from the high frequency signal and vice 25 versa. The low frequency signal, which in preferred embodiments is used to communicate between environmental monitor UARTS, is extremely slow in comparison to the Fibre Channel signal. This signal, preferably tr~n~mitte~l at 9600 baud, has a maximumfilncl~ml~ntal frequency of 4.8 kHz, and a minimllm frequency of DC. The square wave nature of this signal will normally have higher order harmonics which extend to very high 30 frequencies. Consequently, in preferred embodiments of the invention, these harmonics may be limited by low pass filtering without affecting the inforrnation content of the signal, with the intended result of isolating the RS-232 type signal to a low frequency W O 97/32252 PCT~US97/030nO -- 4 --band from DC to about 100 kHz. The high frequency FC signal is limited to 100 ~HZ.
and beyond by the aforementioned 8B/IOB encoding.
In an embodiment of the present invention, the high frequency Fibre Channel, andthe low frequency RS-232 type signal, are frequency division multiplexed into a 5 composite signal which is sent over a single cable. The cable will preferably be a twinax Fibre Channel arbitrated loop standard configuration having two conductor pairs ( 1 pair for each direction) contained within a common shield. Isolation between the two conductor pairs is m~int~ined by locating the two pairs orthogonally in the cable. Each pair will contain a FC signal in differential mode, and a RS-232 signal in common mode.
10 In each conductor pair, one wire conducts a sum of the high frequency FC signal and the low frequency RS-232 type signal and the other wire conducts the difference resulting when the high frequency FC signal is subtracted from the low frequency RS-232 type slgnal.
Brief Description of the Drawin~s The invention may be more readily understood by reference to the following detailed description, taken with the accompanying drawings, in which:
FIG. 1 is a block diagram of a chain of dynarnically upgradeable disk array chassis of the present invention.
FIG. 2 is a flow chart of an upgrading algorithm for use with the present invention.
F~G. 3 is a block diagrarn of a system of interconnected disk array chassis.
FIG. 4 is a block diagram of an environmental monitor for use in the disk array chassis of F~G. 1.
FIG. S is a graph showing the diplex filter frequency response.
2~ FIG. 6 is a figure showing the composite Fibre Channel and RS-232 type signals.
FIG. 7 is a circuit diagram for the differential coupling circuit.
FIG. 8 is a circuit diagram showing the common mode coupling circuit.
FIG. 9 is a functional diagram showing an embodiment of the invention using twin-ax or twisted-pair cable and common mode coupling.
FIG. 10 shows an implementation of the FIG. 9 circuit diagram implemented using transformers.
FIG. 11 is a schematic circuit diagram of the low frequency signal input and output W O 971322~2 PCT~US97/030~0 portions of a diplexer for use in the disk array chassis of 3:;1G. 1.
FIG. 12 is a schematic circuit diagram of the high frequency signal input portion of a diplexer for use in the disk array chassis of FIG. 1.
FIG. 13 is a schematic circuit diagram of the high fre~uency signal output portion, a shunt and an expansion connector for use in the disk array chassis of FIG. 1.
Detailed Description of the Preferred Embo(liments Referring now to the drawings, a disk array chassis 10 is shown in block diagramforrn in F~G. 1. The disk array chassis provides a series of openings into which disk 10 drives 12 may be inserted. The chassis 10 of FIG. 1 is shown capable of housing a specified number of disk drives 12, for example ten. The mechanical chassis may be an open or closed housing or enclosure. Inside the chassis are conventional auxiliary equipment 14 including cooling fans, power supplies and a display card . The display card controls a display on the outside of the housing which may be used to exhibit certain status conditions. Status conditions are determine~ by the environmental monitor.
The disk drives are interconnected by a high speed serial data communication path.
In accordance with the presently preferred embodiment, the commllniczltion path is a loop including a first serial bus 22 directing data in one direction and a second serial bus 24 directing data in a second opposite direction. The preferred data loop is a Fibre Channel arbitrated loop. A series of port bypass circuits 26 are inserted along the loop for making the connection with the disk drives 12. Each port bypass circuit 26is controlled by an environmental monitor 30. The control line between the environmental monitor 30 and the port bypass circuit 26 exists, but is not shown in FIG. 1. When the port bypass circuit is in its bypassed condition, its associated disk drive is shnnted out of the loop. The environmental monitor 30 switches the port bypass circuit 26 into a non-bypassedcondition so that signals on the serial bus are directed to and from the associated disk drive. In order to provide a high availability system, the disk array chassis of the presently ~lc~fGllGd embodiment may include two high speed data commllnic~tion loops and environm~nt~l monitors acting redundantly. Each loop is connected llltim~ely to a disk 30 controller 16. The two disk control processors 16, one for each loop, further serve to provide high availability of the data storage system.
It is desirable that the disk array chassis perrnit dynamic upgrading. In that regard, W O 97/32252 PCT~US97/03000 _ ~ _ a shunt 40 is provided along the Fibre Channel loop. In the presently preferred embodiment, the shunt 40 may be a port bypass circuit. The first serial bus 22 providing data in a first direction is connected to the shunt and the second serial bus 24 providing data in the opposite direction is also connected to the shunt. When the shunt is in its S normally bypassed condition, the Fibre Channel loop ends at the shunt and data passes directly from the first serial bus 22 through the shunt to the second serial bus 24. When the shunt is switched into a non-bypassed state, the f1rst bus 22 is allowed to pass to an expansion connection 52 and the second bus is connected to an incorning signal from the expansion connection. This extends the Fibre Channel loop into the next chassis.The shunt is controlled by the environmental monitor 30. The environm~nt~l monitor 30 is provided with a serial communication path 42 that can lead to an adjacent dislc array chassis. The environmental monitor is a supplier of status signals and other environmental information. The monitor may be any entity that sequences the status signals onto the serial communication path 42. The environmental monitors of the15 presently preferred embodiment are provided with two universal asynchronous receiver tr:~nsmitters 44 (UART) for communicating with a chassis connected at either end of the chassis housing the monitor. While the communication path 42 may be provided forconnection to an adjoining disk array chassis separate from the Fibre Channel loop, in accordance with the presently preferred embodiment of the invention, the cornmunication 20 path 42 is provided as a path for low frequency signals which are diplexed with the high fre~uency Fibre Channel signals for transmission over a single cable 18. Preferably a twinax cable 18 is used. This is a standard cable for Fibre Channel. The presentinvention advantageously adds a low frequency signal to the high frequency FibreChannel signals normally carried by the cable. A twinax cable 18 includes four wire 25 conductors, each divided into two pairs. Each pair transports signals in a single direction so one pair is used for the exiting signals and the other pair of wires in the twinax cable 18 is used for the returning signals.
A diplexer ~() is preferably connected to transmit and receive the low frequencysignals from the environmental monitor 30 and also to transmit and receive high 30 frequency signals from the shunt 40. The other end of the diplexer is connected to a cable connector 52. Regardless of the state of the shunt, communications between disk array chassis environmental monitors are possible over the single twinax cable 18. The disk W O 97/32252 PCTrUS97/03000 array chassis includes a diplexer on both ends of the high frequency drive serial busses, except for the f1rst chassis 110 that houses the disk controller 16 where only one diplexer is required. Comml~nications can thus be m~intzt;ned with the preceding and subse~uent disk array chassis. The environmental monitor communicates with low frec~uency signals 5 that can be separated from the high frequency Fibre Channel signals by filtering in the diplexer. The signals from the diplexed cables can be split with one copy of the signals being high pass filtered while the other copy of the signals is low pass filtered to extract each of the two separate signals. A preferred method of diplexing, however, will be described later herein.
A data storage system is configured by providing l or more disk control processors 16, each in communication with one of the Fibre ~hannel loops and in low frequency communication with the environmental monitors. Disk array chassis are connected to the processors in a continuous chain. The arrangement of the high frequency communication path with two serial busses through each disk array chassis providing cornmunications in 15 each direction permits a high frequency loop. The shunt in each disk array chassis is in the non-bypassed position except for the final active disk array chassis in the chain which remains in the normal bypass condition closing the loop. The disk control processors 16 may be provided in a first chassis 110 along with a disk array. This first chassis 110 in the chain only requires a single diplexer since there is no connection to a prece-ling 20 chassis.
Dynamically upgrading a data storage system of the invention shall now be described. An existing chain of disk storage chassis is provided. The system may include a single chassis enclosing a disk array with the disk controller. Alternatively, the system may include additional disk array chassis connected in a chain to the controller chassis.
25 ~he system is upgraded by connecting an additional disk array chassis to the last disk array chassis in the existing chain. A commllnic~tion cable 18 is connected from the new disk array chassis to the expansion connector 52 on the chassis of the last disk array chassis in the existing chain. This last disk array chassis in the chain has a shunt 40 which is in the normally bypassed condition connecting its first serial bus 22 to the second serial 30 bus 24 and completing the Fibre Channel loop. When the cable 18 is inserted into the connector, the shunt remains in the bypassed condition. The new disk array chassis is now in communication via the low frequency signals conducted over the low frequency W O 97J32252 PCT~US97/03000 -- 8 --serial communication path with the environmental monitor 30. After the connection has been made, the environmental monitor 30 in the existing system can communicate with the environmental monitor 30 in the new disk array chassis. If it is determined that the new disk array chassis is properly connected and operating properly, the shunt ~0 is S switched into the non-bypassed state extending the high frequency communications loop onto the new chassis.
Referring now to FIG. 2, a flow chart of the commllnications conducted along thelow frequency environmental monitor serial comm-lnication path, shall now be described.
In accordance with the presently preferred embodiment, the comm~n-lc supported by the I0 serial protocol along the communication path include a poll, read and write comm~n~l.
These commands are issued by the disk controller 16. The poll command returns the address of each chassis and an indication if that enclosure has changed state since the last poll was issued. The address of a chassis is known to the environmental monitor 30. At present, it is preferred that the address be set by manual switches on the outside of the 1~ chassis. In this manner, a chassis can be given a distinct address different from each of the other chassis that have already been connected to the existing system. Preferably, the user will address the chassis in a numerical order such as 1, 2, 3, 4 .... A read command is directed to a specific chassis address and returns det~iled environmental status about the chassis including its power, cooling and disk drive status. A write comrnand is used by 20 the disk controller to control the operation of the chassis. This command allows the disk controller to turn on or off any port bypass circuit and the shunt 40 of any chassis.
With the shunt of the penultim~te chassis still in the bypass condition, the disk controller is able to monitor and control the newly added last chassis via the diplexed serial communication path 42 without disrupting the ongoing activity on the Fibre 2~ Channel loop. This allows the disk controller to verify the configuration andenvironmental status of the new chassis before enabling the new drives onto the Fibre C~h~nnel loop. As set forth in FIG. 2, the disk controller runs a periodic polling 60 of all the environmental monitors on the system over the low frequency serial communication path 42. The poll command goes out from the disk controller and is received by all of the 30 environmental monitors that are connected to the low frequency serial communication path. Each environmental monitor 30 on the path returns its address and an in~iic~ion of whether there has been any state change since the last poll. If a new chassis is detected 62 W O 97/32252 PCT~US97/03000 _ 9 _ during this periodic polling process, a dynamic upgrading algorithm is initiated. A time delay 64 is imposed to allow for the configuration of the system to settle as the new chassis is powered up.
After completion of the time delay, the disk controller reads the status 68 from5 every environmental monitor 30 along the low frequency serial communication path 42.
The read command produces from each environmental monitor inforrnation about thecabling and address of the chassis 70. This is used to verify that the cabling is properly configured. The address is checked to be sure it is within the range of legally ~csign~hle addresses. The read will also return information as to whether the current chassis is 10 operational 72, i.e., powered and functioning properly. If a problem is found with respect to any of the environmental monitors, the Fibre Channel loop will be terminated at the previous chassis 74, 78 so that only operational chassis are permitted on the Fibre Channel loop. If the chassis is properly connected and operational, processing continues 76 until the new chassis is found 66. ~ the new enclosure is pl~pelly connected and is 15 operational, then it will be set as the last enclosure in the system 76. The shunt 40 of the previous chassis will be switched into a switched state 80 to permit Fibre Channel commlmic~tions with the disks on the new chassis. The Fibre Channel loop may then be instructed to either autom~tiç~lly if it is so set or upon manual indication perform a discovery process to reinitialize the operation on the Fibre Channel loop to include the 20 new disks. This discovery process on the Fibre Channel loop is disruptive to any Fibre Channel activity and may take several seconds to complete. Therefore, it is preferred that the system provide the system ~lminictrator with the option of autom~tic:~lly entering discovery or selecting a manual process that is initiated by a directive from the host system. The discovery process makes the disk drives known to the disk controller's Fibre 25 Channel driver and allows the upper layer protocol drivers (SCSI) to communicate with the disks.
Advantageously, communications with the new disk array chassis along the high ~requency Fibre Channel do not begin until the disk controller has had an opportunity to comml~nicate with the new disk array chassis through the low frequency communication 30 path. This process operates separately and independently through each of the two cables in a reri--n~l~nt system such as that shown in F~G. 3. Thus, a new disk array chassis in the re~ n~ nt system embodiment is added by connecting two cables to the existing chain, W O 97/32252 PCTnJS97103000 -- tO --one for each loop. The connection of each cable operates sepa~ately to enable communications over the respective Fibre Channel loop. FIG. 3 illustrates a chain of disk array chassis. At the bottom of the chain, the chassis l 10 houses a pair of disk controllers as well as a disk array. Each disk controller is in connection with one of the Fib~e 5 Channel loops. The chassis with the disk controller is used for connection to one or more host bus adaptors 112. A host bus adaptor links a host computer with the memory storage provided by the disk arrays. Each of the disk array chassis 10 in the chain is shown with one of two cables connecting each of its recll]ncl~nt loops to the adjoining disk array chassis.
A presently preferred environmental monitor 30 for use in the invention is shownin greater detail in the block diagram of FIG. 4. The monitor program is run on a microcomputer 90. The microcomputer is shown connected to the dual UART's 44. One UART is connected to the input end of the chassis, the other is connected to the expansion end. The UART receives and transmits signals on the low frequency serial 15 commllnic~rion path 42.
The environment~l monitor 30 also includes a number of status ports I00 for monitoring various conditions within the enclosure. One of the status signals is the chassis address (Encl Addr). According to the present embodiment, the address of the chassis is nl~nll~lly set by switches on the outside of the chassis. Thus, a chassis can be 20 m~nll~lly set to have an address different from the already present disk array chassis in the existing chain of chassis. Other status signals include power system status, cooIing status and drive status. The environmental monitor also includes port bypass circuit control latches 102. These control the port bypass circuits 26 for each of the disk drives that may be inserted into the disk array enclosure. Also one of the latches will control the shunt 40.
In preferred embodiments of the invention, low frequency signals and high frequency signals are frequency division multiplexed into a composite signal fortransmission on cables between chassis. They may be simply combined and separated by a dfplex f1lter at each end of the cable, hence use of the term "diplexing." FIG. S shows 30 the diplex filter frequency response. FIG. 6 shows a RS-232 type signal, a FC signal, and the diplexed composite of the two. The diplex filter has three ports, the cable port, a low pass port and a hi"h pass port. The filter is constructed by connecting the output of a hi~sh W O 97t32252 PCT~US97/03000 pass network and a low pass network together. The high pass network will preferably act as an open circuit at low frequency; the simplest form of this high pass network is a capacitor. The low pass network will preferably look like an open circuit to the high frequency Fibre Channel signal; the simplest form of the low pass network is an inductor S or a resistor. The resistor may be used if the system can tolerate the DC resistance;
alternatively, inductors may be used without loss of effectiveness, but they are not ideal devices since achieving broad bandwidth isolation with an inductor is more difficult than with resistors.
Diplexing may be used for cornmunication between a variety of types of computer 10 components. The connection between these components will preferably be with a pair of twinax cables carrying the two Fibre Channel loops. There is also an RS-232 typecommunications channel between environmental monitors. In emboclim~ ntc of the invention, the use of twinax affords two options for coupling the RS-232 type low frequency signal onto the cables. In one embodiment of the invention, the signal may be 15 applied as a differential signal on the twinax cable; in a preferred embodiment of the invention, the signal may be applied as a common mode signal to both sides of the twinax.
A circuit for the first method, differential coupling, is shown in FIG. 7. Coupling the RS-232 type low frequency signal differentially onto the twinax is one possible way to 20 pass the signal from chassis to chassis. This is the same coupling method as that used for the Fibre Channel signals. This method has the highest level of noise immllnity for the low frequency signals. Noise sources such as ground noise and low frequency magnetic fields can be easily rejected using this technique. On the down side, this coupling method will not work if equalized cable assemblies are used ~that's not to say that equalization 25 cannot be done). Another detractor is that any residual coupling of the RS-232 type low frequency signal into the FC signal will be a differential noise source and cause some amount of jitter.
Regarding ground noise, the chassis to chassis twinax-interconnects will preferably be in the range of 0 to 10 meters in length. These connections will be between - 30 chassis within a rack, or between racks in close proximity. There may be a ground voltage potential between two systems in different racks. This ground noise is sul,e~ posed on the cable as a common mode signal. The differential receiver will reject the common CA 02247092 l998-08-20 W O 97/3Z252 PCT~US97/03000 mode noise, and properly receive the differential signal.
Regarding magnetic susceptibility, in an embodiment of the invention, the twinaxcable will preferably be shielded and, in the preferred embodiment of the invention, the shield is connected to chassis ground at both ends. Although this configuration is not the 5 optimal configuration for magnetic shielding, this is required for good high frequency emissions performance. If the cable is brought into an AC magnetic field, a current will be in~ erl to flow through the cable shield, around the ground loop. This current will couple a noise voltage into the internal signals through the mutual inductance between the shield and signal conductors. This noise voltage will be coupled in as a common mode noise 10 source in this configuration, and be rejected by the receiver.
Regarding coupling noise, in an embodiment of the invention, the F;ibre Channel signal is very low amplitude relative to the RS-232 type low frequency signal. With the use of a simple R/C pulse shaping filter, and simple capacitive/resistive diplex filter, there is some residual RS-232 signal coupled into the Fibre C~hannel receiver as shown in FIG.
5. This noise is minimi71~ by making the slew rate of the RS-232 type low frequency signal as slow as possible for the required data rate. The residual noise coupled into the FC receiver is differential noise in this instance, and results in some additive jitter on the received FC signal. This noise is manageable for data rates of 9600 baud and below, while better lowpass filtering may be required for higher data rates.
Regarding external compatibility, in an embodiment of the invention, the rejection of the low frequency signal in the Fibre Channel receiver is accomplished by the AC
coupling circuit at the receiver front end. This coupling circuit uses 1000 pF capacitor and 1~0 ohm termination resistance. If a cable carrying a diplexed signal is plugged into another vendor's equipment, the residual signal coupling, described further below, may be 25 quite severe. The critical factor is the value of the coupling capacitance, as larger values increase the unwanted signal coupling. As there is no standard for this circuit, a preferred embodiment will allow for blocking the diplex signal when connecting to an external host device that cannot safely support the present invention. Preferably, a media converter will be designed to overcome such connection problems. Note, however, that this only applies 30 to JBOD configurations ("just a bunch of disks," i.e. no controller for the disks within the JBOD unit) with DB-9 twinax cables.
Regarding equalizer compatibility, in an embodiment of the invention, the low W O 97/32252 PCTrUS97/03000 frequency signal is coupled onto the twinax cable with lk ohm resistors instead of inductors. This places a high DC resistance in series with the RS-232 type low frequency driver. An equalizer, which would be used for a long twinax cable, will have a fairly low impedance between the differential signals. There will be a voltage divider effect between 5 the equalizer impedance and the coupling resistors which will severely attenuate the low frequency signal. This will be a problem if an equalized cable assembly is used. A
preferred solution to this issue is to use equalizers for the DB-9 twinax cable, and tapping off the low frequency signal before the equalizer. This would allow the DB-9 to DB-9 media converter to contain an equalizer if we want to support twinax links over 10 meters 10 long. Preferred embodiments will not operate with twinax cables which have an equalizer in the cable connector housing.
Regarding crosstalk, in an embodiment of the invention, the invention will utilize twinax having four conductors contained within a common shield (hereinafter twinax4), wherein isolation between the two conductor pairs is m:lint~ined by locating the two pairs 15 orthogonally in the cable. This insures symmetrical coupling from the + and - differential sipn~l~, and the net differential crosstalk between pairs is 0. One pair carries the outgoing signals and the other pin carries the returning signals. For differential coupling of the RS-232 type low frequency signal, there will not be any substantial crosstalk coupling from one pair to the other.
A circuit for the second method, common mode coupling, is shown in FIG. 8.
Preferred embodiments of the invention utilize the fact that the Fibre Channel receiver has common mode rejection to reduce noise coupling from the low frequency signals.
Consequently, since the two cign~ling approaches on the cable are orthogonal, allowing each receiver to reject the signal from the other. The high frequency signal will preferably 25 be driven differentially on the twinax pair, and the low frequency signal will preferably be driven on both signal conductors with the cable shield serving as the signal return path.
The advantages of this method are that it allows potentially higher signaling rates, is compatible with equalized cable assemblies, and is potentially more compatible with host in~Prf~f es The noise rejection and crosstalk performance are worse however.
Regarding ground noise issues, in an embodiment of the invention, any ground potential difference between the transmitter and receiver ends of the cables will couple directly into the common mode low frequency signal as noise. While this is not a new CA 02247092 l998-08-20 W O 97/32252 PCT~US97/03000 problem for RS-232 type links, it is often overcome by running very large signal swings.
A preferred embodiment of the invention would be to keep the swing at 5V peak to peak, or less, which may not be as immllne to this noise as traditional links.
Regarding magnetic susceptibility, in an embodiment of the invention, by running5 the low frequency signal as a common mode signal, the twinax is being used essentially as a coaxial cable. This type of cable configuration allows the shield current induced by an AC magnetic field to impose a noise voltage onto the low frequency signal. This voltage will detract from the signal's noise margin.
Regarding coupling noise, in an embodiment of the invention, coupling of the 10 RS-232 type low frequency signal into the Fibre Channel receiver is now less of a problem because the residual signal coupling is being applied as a common mode noise source. The receiver has very good rejection to low frequency common mode noise, so the noise does not create any jitter on the Fibre Channel signal. This allows the low frequency signal pulse filtering to be relaxed, and higher data rates can be accommodated.The Fibre Channel receiver has a limited common mode rejection range, so the common mode signal must be attenuated before it reaches the receiver. This attenuation is achieved by a voltage divider effect between the Fibre Channel coupling capacitors, and the 150 ohm termination impedance. Preferred embodiments will have termination mode up of two 75 ohm resistors to VBB or some other DC source to provide a common mode 20 termination.
Regarding external compatibility, in an embodiment of the invention, the attenuation of the common mode low frequency signal in the Fibre Channel receiver is accompli~h~d by the AC coupling circuit and termination at the receiver front end. The value of the coupling capacitor is less critical in this configuration, as any additional noise 25 will be rejected. ~rhe critical factor for interoperability is that the termination be common mode. As there is no standard for this circuit, a preferred embodiment will allow for blocking the diplex signal when connecting to an external host device that cannot safely support the present invention. Preferably, a media converter will be designed to overcome such connection problems. Note, however, that this only applies to JBOD configurations 30 with DB-9 twinax cables.
Regarding equali~er compatibility, in an embodiment of the invention, the common mode transmission of the low frequency signal is fully compatible with ~ CA 02247092 1998-08-20 W O 97/32252 PCTrUS97/03000 equalized cable assemblies. The equalizer will act as a low impedance in series with the signal path which will have a minim~l effect.
Regarding crosstalk, the common mode low frequency signal does have a crosstalk issue on the twinax4. The cable has capacitive coupling between the two signal pairs 5 which induces a noise voltage on the other low frequency signal in the cable. This coupling is dependent on ricetime, and is sensitive to cable length. In preferred embodiments of the invention, overall the crosstalk will only be a few percent, and will not significantly degrade the noise margin of the signal.
FIG. g is a simplified diagram of an embodiment of the diplexing of the invention, 10 wherein first and second signals are tr:ln~mitted on a comrnllnic~tion link, and wherein the communication link is preferably twin-ax or twisted pair cable having a tr~n~mi~sion-end and a receiving-end. The communication link has a pair of conductors including a f1rst conductive path and a second conductive path. The first signal to be tr~n~mitte~1 is designated as signal (A), and the second signal is de~ign~tecl as signal (B). Si~snal (A) is 15 sent as a differential mode signal. Signal (B) is sent as a common mode signal. The first conductive path contains the addition of signals (A) + (B). The second conductive path contains the subtraction of (B) - (A). At the receiving-end, the ~lrst and second conductive paths are both sent separately to an adder and a subtractor. At the subtractor, the second conductive path's signal (B)-(A) is subtracted from the first conductive path's signal 20 ~B)+(A), resulting in the (A) signal. At the adder, the second conductive path's signal (B)-(A) is added to the first conductive path's signal (B)+(A), resulting in the (B) signal. A
useful consequence of this embodiment of the invention is that in the subtractor, common mode line noise is efficiently elimin~t~ , and in the adder, differential mode line noise is also elimin~t~l F~G. 10 is a particular implementation of the FIG. 9 embodiment, using transformers.
Referring now to FIGS. 11-13, the common mode coupling embodiment of a ~ diplexer 50 is shown in greater detail. The RS-232 type low fre~uency signal output is provided to an inverter with hysteresis input 120. The signal is then passed through a low 3~1 pass filter 122. The low pass filtered signal is then common mode coupled onto the twinax cable. The return signals are summed at a node 124 where both returning signals are connected. The summed signal is low pass filtered by capacitors 126 connected to W O g7132252 PCT~US97/03000 -- 16 --ground. The summed and filtered signal is provided tO a receiver 128 which in the presently preferred embodiment is an L~ 393 dual comparator.
Referring to FIG. 13, the expansion connector 52 is shown. A DB9 connector is the presently preferred cable connector 52. Signals received on the connector are passed 5 through an equalizer 130. The received signals are then passed to the low frequency input portion of FIG. 11 and the high frequency input portion of FIG. 12 which will now be described. The high frequency input portion passes the received signals through a high pass filter 132. ~ port bypass circuit 134 then acts as a differential receiver. The differential receiver acts as a subtractor looking at the difference between the received 10 signals. The resulting high frequency signals are passed through the port bypass circuit 134 to the shunt 40 and to a signal detector 142. The output of the signal detector 142 may be used to allow the shunt 40 to remain in its normal state when no signals are detected. When a signal is detected the shunt 40 may assume its switched state if authorized by the environmental monitor.
The received signals that are passed through the shunt 40 continue onto the serial bus 24 represented by the FC-SHUNT signals. Outgoing high frequency fibre channel s;gnals are provided by serial bus 22 represented by the FC-LOOP signals. The outgoing signals are driven through the shunt 40. Depending upon the state of the shunt 40, these signals will either loop back to the serial bus 24 on the FC-SHUNT lines or proceed 20 towards the cable connector 52. The signals sent to the cable connector 52 are differentially driven by shunt 40. One signal is inverted and the other noninverted. The inverted and noninverted signals are passed through a high pass filter 138. Thereafter, the fibre channel signals are combined with the low frequency signals from the low frequency output portion of the diplexer to produce a sum of the high and low frequency signals and 25 a difference between the low and high frequency signals. The sum and difference signals may then be passed through an equalizer 140 before they reach the cable connector 52.
Claims (41)
1. A dynamically upgradeable disk array chassis comprising:
a chassis;
a plurality of ports within said chassis that make connection with a plurality of data storage devices;
serial bus means for interconnecting said plurality of data storage devices, said bus means including a first bus for passing data in one direction and a second bus for passing data in a second direction;
a shunt connected to the first bus and the second bus and having a normal state in which the first bus is connected to the second bus across said shunt and a switched state in which each of the first bus and the second bus is connected to a separate output;
an environmental monitor connected to said shunt to control the state of said shunt;
a communication path connected to said monitor, connection means, on the chassis coupled to said communication path and to said shunt, for making data communication connection with a communication path and a serial bus from a new disk array chassis, wherein said environmental monitor communicates through said communication path with the new disk array chassis before switching said shunt to the switched state to connect said serial bus means with the serial bus on the new disk array chassis.
a chassis;
a plurality of ports within said chassis that make connection with a plurality of data storage devices;
serial bus means for interconnecting said plurality of data storage devices, said bus means including a first bus for passing data in one direction and a second bus for passing data in a second direction;
a shunt connected to the first bus and the second bus and having a normal state in which the first bus is connected to the second bus across said shunt and a switched state in which each of the first bus and the second bus is connected to a separate output;
an environmental monitor connected to said shunt to control the state of said shunt;
a communication path connected to said monitor, connection means, on the chassis coupled to said communication path and to said shunt, for making data communication connection with a communication path and a serial bus from a new disk array chassis, wherein said environmental monitor communicates through said communication path with the new disk array chassis before switching said shunt to the switched state to connect said serial bus means with the serial bus on the new disk array chassis.
2. The disk array chassis of claim 1 further comprising a second serial bus means, a second environmental monitor, a second shunt, a second communication path and a second connection means so as to provide a redundant communication path with the plurality of storage devices.
3. The disk array chassis of claim 1 wherein said serial bus means carries high frequency data signals and said communication path carries low frequency data signals.
4. The disk array chassis of claim 3 further comprising a diplexer, connected between said connection means and both said shunt and said communication path, for adding the high frequency data signal to the low frequency data signal to produce a sum signal and for subtracting the high frequency data signal from the low frequency data signal to produce a difference signal.
5. The disk array chassis of claim 3 further comprising a diplexer connected to said connection means for receiving a sum signal and a difference signal from the new disk array chassis and including an adder and a subtractor for extracting a high frequency data signal and a low frequency data signal from the new disk array chassis.
6. The disk array chassis of claim 3 wherein said connection means comprises a twinax cable connector.
7. The disk array chassis of claim 6 further comprising a diplexer connected to said shunt and said communication path to provide a combination of the high frequency data signals to said twinax cable connector.
8. A dynamically upgradeable disk array chassis comprising:
a chassis;
a plurality of ports within said chassis that make connection with a plurality of data storage devices;
serial bus means, interconnecting said plurality of data storage devices, for carrying high frequency data signals;
an environmental monitor connected to said plurality of data storage devices to detect status of a plurality of conditions within said disk array chasses;
a communication path connected to said monitor for carrying low frequency data signals;
a connector accessible outside said chassis to allow communication therethrough with a low frequency communication path and a high frequency serial bus from a new disk array chassis;
a shunt, connected to said serial bus means and having a normal state in which said serial bus means is disconnected from said connector and a switched state in which said serial bus means is in communication, through said connector, with the highfrequency serial bus from the new disk array chassis; and wherein said environmental monitor communicates by low frequency signals through said communication path with the new disk array chassis and afterwards causes said shunt to switch to the switched state.
a chassis;
a plurality of ports within said chassis that make connection with a plurality of data storage devices;
serial bus means, interconnecting said plurality of data storage devices, for carrying high frequency data signals;
an environmental monitor connected to said plurality of data storage devices to detect status of a plurality of conditions within said disk array chasses;
a communication path connected to said monitor for carrying low frequency data signals;
a connector accessible outside said chassis to allow communication therethrough with a low frequency communication path and a high frequency serial bus from a new disk array chassis;
a shunt, connected to said serial bus means and having a normal state in which said serial bus means is disconnected from said connector and a switched state in which said serial bus means is in communication, through said connector, with the highfrequency serial bus from the new disk array chassis; and wherein said environmental monitor communicates by low frequency signals through said communication path with the new disk array chassis and afterwards causes said shunt to switch to the switched state.
9. The disk array chassis of claim 8 further comprising a diplexer connected to said communication path and to said shunt for combining high frequency data signals and low frequency data signals in one direction and for separating high frequency data signals from low frequency data signals in a second direction.
10. The disk array chassis of claim 9 wherein said diplexer combines by adding the high frequency data signals to the low frequency data signals to produce a sum signal and by subtracting the high frequency data signals from the low frequency data signals to produce a difference signal.
11. The disk array chassis of claim 9 wherein said diplexer includes an adder and a subtractor for separating the high frequency data signals from the low frequency data signals in the second direction.
12. The disk array chassis of claim 8 further comprising a second serial bus means, a second environmental monitor, a second shunt, a second communication path and a second connector so as to provide a redundant communication path with the plurality of storage devices.
13. The disk array chassis of claim 8 wherein said connector is a twinax cable connector and wherein the high frequency data signals and the low frequency data signals travel through said connector when said shunt is in the switched state.
14. A dynamically upgradeable disk array chassis comprising:
a chassis;
a plurality of ports within said chassis that make connection with a plurality of data storage devices;
serial bus means for interconnecting said plurality of data storage devices, said serial bus means including a first bus for carrying high frequency data signals in one direction and a second bus for carrying the high frequency data signals in a second direction;
a shunt connected to the first bus and the second bus and having a normal bypassstate in which the first bus is connected to the second bus across said shunt and a switched state in which each of the first bus and the second bus is connected to a separate output;
an environmental monitor connected to said shunt to control the state of said shunt;
a communication path connected to said monitor for carrying low frequency data signals;
a diplexer connected to said communication path and to the separate outputs of said shunt for combining the high frequency data signals and the low frequency data signals in the one direction and for separating a high frequency data signal from a low frequency data signal in the second direction; and a connector, connected to said diplexer, accessible outside said chassis to makedata communication connection with a low frequency communication path and a highfrequency serial bus from a new disk array chassis, wherein said environmental monitor communicates with low frequency signals through said communication path with the new disk array chassis before switching said shunt to the switched state to connect said serial bus means to the high frequency serial bus on the new disk array chassis.
a chassis;
a plurality of ports within said chassis that make connection with a plurality of data storage devices;
serial bus means for interconnecting said plurality of data storage devices, said serial bus means including a first bus for carrying high frequency data signals in one direction and a second bus for carrying the high frequency data signals in a second direction;
a shunt connected to the first bus and the second bus and having a normal bypassstate in which the first bus is connected to the second bus across said shunt and a switched state in which each of the first bus and the second bus is connected to a separate output;
an environmental monitor connected to said shunt to control the state of said shunt;
a communication path connected to said monitor for carrying low frequency data signals;
a diplexer connected to said communication path and to the separate outputs of said shunt for combining the high frequency data signals and the low frequency data signals in the one direction and for separating a high frequency data signal from a low frequency data signal in the second direction; and a connector, connected to said diplexer, accessible outside said chassis to makedata communication connection with a low frequency communication path and a highfrequency serial bus from a new disk array chassis, wherein said environmental monitor communicates with low frequency signals through said communication path with the new disk array chassis before switching said shunt to the switched state to connect said serial bus means to the high frequency serial bus on the new disk array chassis.
15. The disk array chassis of claim 14 wherein said diplexer combines by adding the high frequency data signals to the low frequency data signals to produce a sum signal and by subtracting the high frequency data signals from the low frequency data signals to produce a difference signal.
16. The disk array chassis of claim 14 wherein said diplexer includes an adder and a subtractor for separating the high frequency data signals from the low frequency data signals in the second direction.
17. The disk array chassis of claim 14 further comprising a second serial bus means, a second environmental monitor, a second shunt, a second communication path, a second diplexer and a second connector so as to provide a redundant communication path with the plurality of storage devices.
18. The disk array chassis of claim 14 wherein said connector is a twinax cable connector and wherein the high frequency data signals and the low frequency data signals travel through said connector when said shunt is in the switched state.
19. A method for dynamically upgrading a data storage system comprising:
providing a disk array chassis having a plurality of data storage devices interconnected by a high frequency data bus, an environmental monitor connected to a low frequency communication serial and a diplexer for combining high frequency signals from the high frequency data path with low frequency signals from the low frequency communication path;
connecting a cable between the diplexer of said disk array chassis and a connector on said data storage system;
communicating with said disk array chassis with low frequency signals through said cable and said communication bus; and switching a shunt in the data storage system to permit high frequency signals tocommunicate between said data storage system and said disk array chassis.
providing a disk array chassis having a plurality of data storage devices interconnected by a high frequency data bus, an environmental monitor connected to a low frequency communication serial and a diplexer for combining high frequency signals from the high frequency data path with low frequency signals from the low frequency communication path;
connecting a cable between the diplexer of said disk array chassis and a connector on said data storage system;
communicating with said disk array chassis with low frequency signals through said cable and said communication bus; and switching a shunt in the data storage system to permit high frequency signals tocommunicate between said data storage system and said disk array chassis.
20. A method for communicating between computer components comprising:
differential coupling a Fibre Channel 8B/10B encoded signal in a first computer component onto a first pair of conductors within a grounded sheath;
coupling a low frequency signal in the first computer component onto the first pair of conductors; and filtering out one of the Fibre Channel signal and the low frequency signal from the first pair of conductors in a second computer component so as to retrieve the other one of the Fibre Channel signal and the low frequency signal.
differential coupling a Fibre Channel 8B/10B encoded signal in a first computer component onto a first pair of conductors within a grounded sheath;
coupling a low frequency signal in the first computer component onto the first pair of conductors; and filtering out one of the Fibre Channel signal and the low frequency signal from the first pair of conductors in a second computer component so as to retrieve the other one of the Fibre Channel signal and the low frequency signal.
21. The method of claim 20 further comprising providing a twinax cable connected between the first computer component and the second computer component, the twinax cable including the first pair of conductors and a second pair of conductors arranged orthogonal to the first pair of conductors wherein signals are transmitted along the second pair of conductors from the second computer component to the first computer component.
22. The method of claim 20 wherein the step of coupling a low frequency signal in the first computer component comprises common mode coupling.
23. The method of claim 22 wherein said step of filtering out includes adding together signals received on each of the conductors in the first pair of conductors so as to retrieve the low frequency signal.
24. The method of claim 22 wherein said step of filtering out includes subtracting signals received on one of the conductors in the first pair of conductors from signals received on the other of the conductors in the first pair of conductors so as to retrieve the Fibre Channel signal.
25. The method of claim 20 wherein the step of coupling a low frequency signal in the first computer component comprises differential coupling.
26. A method for communicating in full duplex on a twinax cable comprising:
providing a twinax cable with a first pair of conductors, a second pair of conductors and a ground;
differential coupling a first signal onto the first pair of conductors in a first direction;
common mode coupling a second signal onto the first pair of conductors in the first direction, differential coupling a third signal onto the second pair of conductors in a second direction opposite to the first direction; and common mode coupling a fourth signal onto the second pair of conductors in the second direction.
providing a twinax cable with a first pair of conductors, a second pair of conductors and a ground;
differential coupling a first signal onto the first pair of conductors in a first direction;
common mode coupling a second signal onto the first pair of conductors in the first direction, differential coupling a third signal onto the second pair of conductors in a second direction opposite to the first direction; and common mode coupling a fourth signal onto the second pair of conductors in the second direction.
27. The method of claim 26 further comprising adding together signals received on each of the conductors in the first pair of conductors to retrieve the second signal.
28. The method of claim 26 further comprising subtracting signals received on one of the conductors in the first pair of conductors from signals received on the other of the conductors in the first pair of conductors so as to retrieve the first signal.
29. A computer communication link comprising:
a first computer component including means for differentially coupling a Fibre Channel signal onto a first pair of conductors;
a cable including said first pair of conductors therein;
a second computer component further including an environmental monitor to detect status of a plurality of conditions within said second computer component; and a communication path passing through said cable for connection to said environmental monitor so that proper connection of said cable and thereby said first pair of conductors to said second computer component can be determined from signals on said communication path.
a first computer component including means for differentially coupling a Fibre Channel signal onto a first pair of conductors;
a cable including said first pair of conductors therein;
a second computer component further including an environmental monitor to detect status of a plurality of conditions within said second computer component; and a communication path passing through said cable for connection to said environmental monitor so that proper connection of said cable and thereby said first pair of conductors to said second computer component can be determined from signals on said communication path.
30. The computer communication link of claim 29 wherein said communication path comprises common mode coupled signals on said first pair of conductors and wherein said cable includes a grounded sheath.
31. The computer communication link of claim 29 wherein said communication path is carried on at least one conductor within said cable separate from the first pair of conductors.
32. A diplexed computer communication link comprising:
a first computer component including means for differentially coupling a first signal onto a first pair of conductors;
a grounded sheath having said first pair of conductors pass therethrough;
said first computer component further including means for common mode coupling a second signal onto the first pair of conductors; and a second computer component including a diplexer coupled to the first pair of conductors for separately extracting the first signal and the second signal from the first pair of conductors.
a first computer component including means for differentially coupling a first signal onto a first pair of conductors;
a grounded sheath having said first pair of conductors pass therethrough;
said first computer component further including means for common mode coupling a second signal onto the first pair of conductors; and a second computer component including a diplexer coupled to the first pair of conductors for separately extracting the first signal and the second signal from the first pair of conductors.
33. The computer communication link of claim 32 wherein the first signal comprises a Fibre Channel signal.
34. The computer communication link of claim 32 wherein the diplexer includes an adder for retrieving the second signal.
35. The computer communication link of claim 32 wherein the diplexer includes a subtractor for retrieving the first signal.
36. The computer communication link of claim 32 further comprising a second pair of conductors within said grounded sheath and wherein said second computer component includes means for differentially coupling a third signal onto the second pair of conductors and means for common mode coupling a fourth signal onto the second pair of conductors.
37. The computer communication link of claim 36 wherein the first pair of conductors and the second pair of conductors are arranged orthogonal to one another.
38. The computer communication link of claim 36 wherein said first computer component includes a diplexer coupled to the second pair of conductors for separately extracting the third signal and the fourth signal from the second pair of conductors.
39. A diplexer comprising:
a first conductor;
a second conductor;
an adder connected to said first conductor and said second conductor for adding signals received over said first and second conductors; and a subtractor connected to said first conductor and said second conductor for subtracting signals received over said second conductor from signals received over said first conductor.
a first conductor;
a second conductor;
an adder connected to said first conductor and said second conductor for adding signals received over said first and second conductors; and a subtractor connected to said first conductor and said second conductor for subtracting signals received over said second conductor from signals received over said first conductor.
40. The diplexer of claim 39 further comprising a low pass filter connected to receive signals from said adder.
41. The diplexer of claim 39 wherein said subtractor comprises a differential receiver.
Applications Claiming Priority (6)
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| US1235896P | 1996-02-27 | 1996-02-27 | |
| US60/012,358 | 1996-02-27 | ||
| US748,884 | 1996-11-14 | ||
| US08/748,884 US5890214A (en) | 1996-02-27 | 1996-11-14 | Dynamically upgradeable disk array chassis and method for dynamically upgrading a data storage system utilizing a selectively switchable shunt |
| US801,603 | 1997-02-13 | ||
| US08/801,603 US5901151A (en) | 1996-02-27 | 1997-02-13 | System for orthogonal signal multiplexing |
Publications (1)
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|---|---|
| CA2247092A1 true CA2247092A1 (en) | 1997-09-04 |
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|---|---|---|---|
| CA002247092A Abandoned CA2247092A1 (en) | 1996-02-27 | 1997-02-25 | Orthogonal signal multiplexing system |
Country Status (6)
| Country | Link |
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| US (1) | US5901151A (en) |
| EP (1) | EP0883845B1 (en) |
| JP (1) | JP3204985B2 (en) |
| CA (1) | CA2247092A1 (en) |
| DE (1) | DE69730593T2 (en) |
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|---|---|---|---|---|
| US6266379B1 (en) * | 1997-06-20 | 2001-07-24 | Massachusetts Institute Of Technology | Digital transmitter with equalization |
| US6209023B1 (en) | 1998-04-24 | 2001-03-27 | Compaq Computer Corporation | Supporting a SCSI device on a non-SCSI transport medium of a network |
| US6418121B1 (en) * | 1998-11-25 | 2002-07-09 | The Whitaker Corporation | Transceiver circuitry for a GBIC module |
| US6295323B1 (en) * | 1998-12-28 | 2001-09-25 | Agere Systems Guardian Corp. | Method and system of data transmission using differential and common mode data signaling |
| US6167463A (en) * | 1999-04-08 | 2000-12-26 | Hewlett-Packard Company | Firm addressing for devices on a fibre channel arbitrated loop |
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| US4335464A (en) * | 1980-01-24 | 1982-06-15 | Paradyne Corporation | Dual multipoint data transmission system modem |
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| GB8628046D0 (en) * | 1986-11-24 | 1986-12-31 | British Telecomm | Transmission system |
| JP2686392B2 (en) * | 1992-01-27 | 1997-12-08 | 富士通株式会社 | Modem |
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| US6153411A (en) * | 1998-10-30 | 2000-11-28 | American Water Works Company, Inc. | Methods and kits for detection of Cryptosporidium parvum using immunomagnetic separation and amplification |
-
1997
- 1997-02-13 US US08/801,603 patent/US5901151A/en not_active Expired - Lifetime
- 1997-02-25 DE DE69730593T patent/DE69730593T2/en not_active Expired - Lifetime
- 1997-02-25 EP EP97907877A patent/EP0883845B1/en not_active Expired - Lifetime
- 1997-02-25 WO PCT/US1997/003000 patent/WO1997032252A1/en active IP Right Grant
- 1997-02-25 JP JP53107997A patent/JP3204985B2/en not_active Expired - Fee Related
- 1997-02-25 CA CA002247092A patent/CA2247092A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| JP3204985B2 (en) | 2001-09-04 |
| JP2000509172A (en) | 2000-07-18 |
| DE69730593T2 (en) | 2005-10-06 |
| EP0883845B1 (en) | 2004-09-08 |
| DE69730593D1 (en) | 2004-10-14 |
| EP0883845A1 (en) | 1998-12-16 |
| US5901151A (en) | 1999-05-04 |
| WO1997032252A1 (en) | 1997-09-04 |
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| Date | Code | Title | Description |
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| EEER | Examination request | ||
| FZDE | Discontinued |