CA2253488A1 - A method and device to convert an analog current to a digital signal - Google Patents
A method and device to convert an analog current to a digital signal Download PDFInfo
- Publication number
- CA2253488A1 CA2253488A1 CA002253488A CA2253488A CA2253488A1 CA 2253488 A1 CA2253488 A1 CA 2253488A1 CA 002253488 A CA002253488 A CA 002253488A CA 2253488 A CA2253488 A CA 2253488A CA 2253488 A1 CA2253488 A1 CA 2253488A1
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- Prior art keywords
- current
- converter
- circuit
- pipelined
- stage
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
- H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
- H03M1/167—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters
- H03M1/168—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters and delivering the same number of bits
Abstract
To convert an analog current to a digital signal using a high-speed pipelined analog-to-digital (A/D) converter, the A/D converter may comprise a current sample- and hold (S/H) circuit at the input and several identical pipelined stages, where each stage contains a current S/H circuit, a current interstage low-resolution A/D converter and current references. To improve the speed of pipelined current-mode A/D converters the capacitive load seen by the output of every stage will be reduced. By adjusting the reference currents the power consumption will also be reduced. It is possible to achieve about 100 Msamples/s conversion rate and to reduce the power consumption by several times compared with existing designs. To increase the operation speed and to provide means to reduce the power consumption the pipelined current-mode A/D
converter may comprise an S/H circuit (7) as the input and N pipelined stages (8), each of which contains an internal low-resolution A/D converter (9), a D/A converter (10), an S/H circuit (11), a reference current source (12) and an adder/subtractor (13). The most distinguishing features of the invented architecture are: 1) the inputs to the internal A/D converter and the interstage S/H circuit are timeinterleaved; and 2) the reference current to the D/A converter in every stage can be different.
converter may comprise an S/H circuit (7) as the input and N pipelined stages (8), each of which contains an internal low-resolution A/D converter (9), a D/A converter (10), an S/H circuit (11), a reference current source (12) and an adder/subtractor (13). The most distinguishing features of the invented architecture are: 1) the inputs to the internal A/D converter and the interstage S/H circuit are timeinterleaved; and 2) the reference current to the D/A converter in every stage can be different.
Description
CA 022~3488 1998-11-03 A METHOD AND DEVICE TO CONVERT AN ANALOG CURRENT TO A DIGITAL
SIGNAL
TECHNICAL FIELD
The present invention relates to a method and a device to convert an analog current to a digital signal; more particularly this invention relates to the design of high-speed pipelined analog-to-digital (A/D) converters, where the input analog signal is a current.
R~Kr.ROUND OF THE INVENTION
Traditionally CMOS A/D converters have been designed by using switched-capacitor technique. But these kind of A/D converters usually call for linear capacitors. In a digital CMOS process, there is only one poly layer available. To create linear capacitors in the digital CMOS process, extra process steps are needed, which would increase the cost. It is therefore of interest to design CMOS A/D converters in the digital CMOS
process. This can be accomplished by using the current mode approach, see for example: "Analog IC Design: the Current-Mode Approach", C. Toumazou, F.J. Lidgey and D.G. Haig (Eds), Peter Peregrinus Ltd., 1990 and "Switched-Currents: an Analogue Technique for Digital Technology", C. Toumazou, J.B. Hughes and N.C Bettersby (Eds), Peter Peregrinus Ltd., 1993.
A high-speed pipelined A/D converter was presented in "A CMOS
transistor - only 8-b 4.5 - Ms/s pipelined analog-to-digital converter using fully-differential current-mode curcuit techniques" C.-Y. Wu, C.-C. Chen and J.-J. Cho, IEEE J. Solid -25 State Circuits, May 1995 pp. 522-532. In figure 1 there is shown a 1-bit-per-stage architecture. The A/D converter consists of a current sample-and-hold (S/H) circuit 1 at the input and 8 identical 1-bit pipelined stages 2. Each stage 2 contains a ., . , ._.
CA 022~3488 1998-11-03 .
current S/H 3 circuit, an inter stage current amplifier/adder 4, a current comparator 5 and current references 6.
If the input current Ij is positive, the output of the current comparator is ONE and the residual current to the next stage is (2Ij - Iref). If the input current Ij is negative, the output of the current comparator is ZERO and the residual current to the next stage is (2Ij + Iref). The residual current Ij+1 is then sent to the next stage to determine next bit. The sampled input currents can therefore be pipelined to determine its digital codes sequentially.
In practical realization the function of multiplication by 2 can be realized in the S/H circuit by using a current mirror as in the reference "A CMOS transistor - only 8-b 4.5-Ms/s pipelined analog-to-digital converter using fully-differential current-mode circuit techni~ues". However, the current mirrors includeextra capacitive load to the S/H circuit, which limits the speed. Another drawback is that every stage is treated equally and therefore the power consumtion cannot be optimized.
In US-A-4894657: "Pipelined analog-to-digital architecture with parallel-autozero analog signal processing" the invention relates to an A/D converter for converting analog signals to digital signals and in particular to a pipelined A/D converter having a cascade connection of A/D-D/A sub-blocks respectively for determining partial bits of a conversion output. The cited invention is based on the tradit~onal voltage-mode approach, and therefore is not in the scope of the invention where a current mode approach is used.
CA 022~3488 1998-11-03 SUMMARY OF T~E I~V~N1-10N
To improve the speed of pipelined current-mode A/D converters the present invention reduces the capacitive load seen by the output of every stage. By adjusting the reference currents, the method and the device according to the invention also reduces the power consumption. It is possible to achieve about l00 Msamples/s conversion rate and to reduce the power consumption by several times compared with existing designs, when using the invented architectures.
DESCRIPTION OF THE DRAWINGS
Figure l shows the prior art architecture for a pipelined current-mode analog-to-digital converter.
Figure 2 shows a pipelined current-mode A/D converter architecture according to the invention.
Figure 3 shows the stages generating LSBs to reduce the spread of reference currents in figure 2.
Figure 4 shows a simplified cicuit diagram of one stage corresponding to the architecture of figure 2.
Figure 5 shows a simplified circuit diagram of current sample-and-hold circuit.
Figure 6 shows a simplified circuit diagram of the l-bit current quantizer.
Figure 7 shows a simplified circuit diagram of the l-bit D/A
converter.
CA 022~3488 1998-11-03 DETAILED DESCRIPTION OF THE I~V~N110N
To increase the operation speed and to provide means to reduce the power consumption, a pipelined current-mode A/D converter architecture is proposed as shown in figure 2.
The invented architecture consists of an S/H circuit 7 at the input and N pipelined stages 8. Every stage 8 contains an inter-nal low-resolution A/D converter 9, a D/A converter 10, an S/H
circuit 11, a reference current source 12 and a current adder/subtractor 13. Every stage 8 does not have to be identical to any other stage. The most distinguishing features of the invented architecture are: 1) the inputs to the internal A/D
converter (it can be only a current comparator) and to the interstage S/H circuit are time-interleaved; 2) the reference current to the D/A converter (it can be only a 1-bit converter) in every stage can be different. The converter only needs two clock phases. The operations of three successive stages are illustrated in Table 1, where the auto-zeroing of the internal A/D converter is optional.
phase 1 phase 2 stage j - 1 S/H circuit sample hold A~D converter auto-zero quantization D/A converter change output hold output stage j S/H circuit hold sample A/D converter quantization auto-zero D/A converter hold output change output stage j + 1 S/H circuit sample hold A/D converter auto-zero quantization D/A converter change output hold output CA 022~3488 1998-11-03 Table 1: The operations of three successive stages.
The input current is first fed to the internal A/D converter 9, which usually has a low resolution, then the input current is switched to the S/H circuit 11 and at the same time the internal D/A converter 10 outputs the current to the current adder/subtractor 13. The output of the current adder/subtractor 13 is sent to the next stage. Therefore the output current is the summation of the output current of the D/A converter 10 and the output current of the S/H circuit 11. It is given by Ii+~ ((bl+2-b2---+2 i bh,)-Ijref) where the internal A/D converter 9 has kj output bits.
In order to realize the proper quantization, the reference current of the following stage should be scaled, i.e., Ijrel (j+l)r(!J 2kj In the new architecture, we do not need to realize the multiplication by the factor of 2, reducing the settling time.
The accuracy is mainly determined by the matching of the reference current sources, which is comparable to other structures where accuracy is determined by the matching of current sources and realization of coefficients.
In the new architecture, the settings of the D/A converter 10 and S/H circuit 11 of the preceding stage are directly coupled with the settling of the A/D converter 9 of the current stage, limiting the operation speed. The settling time of a well-designed A/D converter (having a low resolution) is usually only1/5~1/10 of the settling time of an S/H circuit, and the D/A
CA 022~3488 1998-11-03 converter settles usually much faster than other circuits.
Compared with the circuits in the prior art, the capacitive load of the S/H circuits ll in the new structure is much less.
Therefore, the invented A/D converter can operate much faster than the existing ones. A data rate of about lO0 Msamples/s is possible, according to transistor-level simulation.
Due to the scaling of the reference current sources, the maximum current swing decreases throughout the pipelined stages.
Therefore, bias currents can be reduced successively throughout the pipelined stages. Power consumption can thus be reduced dramatically.
The scaling does not have a negative effect on the performance in that the first stage needs highest resolution ~equivalent to the resolution of the whole pipelined A/D converter) and the following stages need lower and lower resolution throughout the pipeline. For example, the second stage only needs a bit resolution (resolution specified in the num~er of bits) equivalent to the bit resolution of the whole A/D converter minus the bit resolution of the first stage.
To reduce the spread of reference currents, we can introduce multiplication in the S/H circuit of the stages generating the last significant bits (LSBs). They can take two forms as shown in figure 3.
The output current is given by Ii+l=2k' Ij--((bl + 2 ~ b2 +. . ~+2ki-' ~ bk ) Ijre~ ) In this case, the following stage has the same reference value Iiref -.
CA 022~3488 1998-11-03 Due to the extra capacitive load, the settling time increases.
However, the stages generating LSBs do not have the same accuracy requirement and relatively large settling error is acceptable.
The invented architecture has been implemented in the in-house CMOS process. In this section a simplified circuit solution is presented. In figure 4 the simplified circuit diagram of one stage is shown corresponding to figure 2. The input current Iin is fed into the current sample-and-hold circuit S_HO on the odd clock phase Clk_o through switch transistor M7, and is fed into the current quantizer Quantizer_I on the even clock phase Clk_e through transistor M6. The output of the current quantizer Quantizer_I is inverted by an inverter and then latched by a flip-flop resettable by the signal Set_b. The digital output Out_Dig is used to control the D/A converter DAO_lb. The input current to the next stage is Iout, generated by wiring together the output of the sample-and-hold circuit S_HO and that of the D/A converter DAO_lb. Notice the subtraction in figure 2 is implicitly implemented in the D/A converter by properly setting the reference current directions. VbiasO 2 are the bias voltages for the analog blocks S_HO and DACO_lb.
In figure 5, the simplified circuit diagram of the current sample-and-hold circuit is shown. The current sample-and-hold circuit is basically a cascode current mirror with a control switch. Transistors MO and Ml6 provide bias currents for the input and output, respectively. Transistors Ml and Ml5 are cascode transistors to increase the output impedance of current sources. Transistors Ml7 and M5, together with cascode transistors M3 and M4, realize the current mirroring. Transistor M6 is used as a switch controlled by the digital input Clk_S.
CA 022~3488 1998-11-03 Iin and Iout are the input and output currents, respectively, and VbiasO-2 are the bias voltages.
When the digital input Clk_S is high, the output current Iout is equal to the input current Iin, due to the same gate-source 5 voltage for transistors M17 and M5. When Clk_S goes low, the gate of transistor M5 is isolated and therefore the output current Iout is held constant. For different stages, the bias current can be scaled.
In figure 6 the simplified circuit diagram of the 1-bit current quantizer is shown. The 1-bit current quantizer used is a low-impedance quantizer. Transistors MO and M1 are the input transistors. Transistors M2 and M3 form an amplifier. When the input current Iin changes direction, any small potential change is amplified by the amplifier to make the change at the gates of MO and M1 considerably large. This large voltage change is further amplified by another amplifier consisting of transistors M4 and M5, and an inverter is used to drive the output.To realize a multi-bit current quantizer, only reference current at the input will need to be provided.
In figure 7, the simplified circuit diagram of the 1-bit D/A
converter is shown. The D/A converter is basically a cascode current source consisting of transistor M22 and M20, and their cascode transistors M23, M21 respectively. The branch consistiny of transistor MO, M1, M10 and M18 is only used to provide the bias voltage for transistor M20 to guarantee that the drain current in M20 is equal to the drain current in M22. Transistors M31, M50, M36, M37 are used as switches. Depending on the digital input In-Dig, either the current in M22 or the current in M20 is switched to the output. At the same time, the other current, which is not switched to the output is switched to a CA 022~3488 l998-ll-03 load to avoid drastic voltage change when a current source is open circuited. The load is only a current mirror providing a low impedance at its input. VbiasO~2 are the bias voltages.
While the foregoing description includes numerous details and specificities, it is to be understood that these are merely illustrative of the present invention, and are not to be construed as limitations. Many modifications will be readily apparent to those skilled in the art which do not depart from the spirit and scope of the invention, as defined by the appended claims and their legal equivalents.
SIGNAL
TECHNICAL FIELD
The present invention relates to a method and a device to convert an analog current to a digital signal; more particularly this invention relates to the design of high-speed pipelined analog-to-digital (A/D) converters, where the input analog signal is a current.
R~Kr.ROUND OF THE INVENTION
Traditionally CMOS A/D converters have been designed by using switched-capacitor technique. But these kind of A/D converters usually call for linear capacitors. In a digital CMOS process, there is only one poly layer available. To create linear capacitors in the digital CMOS process, extra process steps are needed, which would increase the cost. It is therefore of interest to design CMOS A/D converters in the digital CMOS
process. This can be accomplished by using the current mode approach, see for example: "Analog IC Design: the Current-Mode Approach", C. Toumazou, F.J. Lidgey and D.G. Haig (Eds), Peter Peregrinus Ltd., 1990 and "Switched-Currents: an Analogue Technique for Digital Technology", C. Toumazou, J.B. Hughes and N.C Bettersby (Eds), Peter Peregrinus Ltd., 1993.
A high-speed pipelined A/D converter was presented in "A CMOS
transistor - only 8-b 4.5 - Ms/s pipelined analog-to-digital converter using fully-differential current-mode curcuit techniques" C.-Y. Wu, C.-C. Chen and J.-J. Cho, IEEE J. Solid -25 State Circuits, May 1995 pp. 522-532. In figure 1 there is shown a 1-bit-per-stage architecture. The A/D converter consists of a current sample-and-hold (S/H) circuit 1 at the input and 8 identical 1-bit pipelined stages 2. Each stage 2 contains a ., . , ._.
CA 022~3488 1998-11-03 .
current S/H 3 circuit, an inter stage current amplifier/adder 4, a current comparator 5 and current references 6.
If the input current Ij is positive, the output of the current comparator is ONE and the residual current to the next stage is (2Ij - Iref). If the input current Ij is negative, the output of the current comparator is ZERO and the residual current to the next stage is (2Ij + Iref). The residual current Ij+1 is then sent to the next stage to determine next bit. The sampled input currents can therefore be pipelined to determine its digital codes sequentially.
In practical realization the function of multiplication by 2 can be realized in the S/H circuit by using a current mirror as in the reference "A CMOS transistor - only 8-b 4.5-Ms/s pipelined analog-to-digital converter using fully-differential current-mode circuit techni~ues". However, the current mirrors includeextra capacitive load to the S/H circuit, which limits the speed. Another drawback is that every stage is treated equally and therefore the power consumtion cannot be optimized.
In US-A-4894657: "Pipelined analog-to-digital architecture with parallel-autozero analog signal processing" the invention relates to an A/D converter for converting analog signals to digital signals and in particular to a pipelined A/D converter having a cascade connection of A/D-D/A sub-blocks respectively for determining partial bits of a conversion output. The cited invention is based on the tradit~onal voltage-mode approach, and therefore is not in the scope of the invention where a current mode approach is used.
CA 022~3488 1998-11-03 SUMMARY OF T~E I~V~N1-10N
To improve the speed of pipelined current-mode A/D converters the present invention reduces the capacitive load seen by the output of every stage. By adjusting the reference currents, the method and the device according to the invention also reduces the power consumption. It is possible to achieve about l00 Msamples/s conversion rate and to reduce the power consumption by several times compared with existing designs, when using the invented architectures.
DESCRIPTION OF THE DRAWINGS
Figure l shows the prior art architecture for a pipelined current-mode analog-to-digital converter.
Figure 2 shows a pipelined current-mode A/D converter architecture according to the invention.
Figure 3 shows the stages generating LSBs to reduce the spread of reference currents in figure 2.
Figure 4 shows a simplified cicuit diagram of one stage corresponding to the architecture of figure 2.
Figure 5 shows a simplified circuit diagram of current sample-and-hold circuit.
Figure 6 shows a simplified circuit diagram of the l-bit current quantizer.
Figure 7 shows a simplified circuit diagram of the l-bit D/A
converter.
CA 022~3488 1998-11-03 DETAILED DESCRIPTION OF THE I~V~N110N
To increase the operation speed and to provide means to reduce the power consumption, a pipelined current-mode A/D converter architecture is proposed as shown in figure 2.
The invented architecture consists of an S/H circuit 7 at the input and N pipelined stages 8. Every stage 8 contains an inter-nal low-resolution A/D converter 9, a D/A converter 10, an S/H
circuit 11, a reference current source 12 and a current adder/subtractor 13. Every stage 8 does not have to be identical to any other stage. The most distinguishing features of the invented architecture are: 1) the inputs to the internal A/D
converter (it can be only a current comparator) and to the interstage S/H circuit are time-interleaved; 2) the reference current to the D/A converter (it can be only a 1-bit converter) in every stage can be different. The converter only needs two clock phases. The operations of three successive stages are illustrated in Table 1, where the auto-zeroing of the internal A/D converter is optional.
phase 1 phase 2 stage j - 1 S/H circuit sample hold A~D converter auto-zero quantization D/A converter change output hold output stage j S/H circuit hold sample A/D converter quantization auto-zero D/A converter hold output change output stage j + 1 S/H circuit sample hold A/D converter auto-zero quantization D/A converter change output hold output CA 022~3488 1998-11-03 Table 1: The operations of three successive stages.
The input current is first fed to the internal A/D converter 9, which usually has a low resolution, then the input current is switched to the S/H circuit 11 and at the same time the internal D/A converter 10 outputs the current to the current adder/subtractor 13. The output of the current adder/subtractor 13 is sent to the next stage. Therefore the output current is the summation of the output current of the D/A converter 10 and the output current of the S/H circuit 11. It is given by Ii+~ ((bl+2-b2---+2 i bh,)-Ijref) where the internal A/D converter 9 has kj output bits.
In order to realize the proper quantization, the reference current of the following stage should be scaled, i.e., Ijrel (j+l)r(!J 2kj In the new architecture, we do not need to realize the multiplication by the factor of 2, reducing the settling time.
The accuracy is mainly determined by the matching of the reference current sources, which is comparable to other structures where accuracy is determined by the matching of current sources and realization of coefficients.
In the new architecture, the settings of the D/A converter 10 and S/H circuit 11 of the preceding stage are directly coupled with the settling of the A/D converter 9 of the current stage, limiting the operation speed. The settling time of a well-designed A/D converter (having a low resolution) is usually only1/5~1/10 of the settling time of an S/H circuit, and the D/A
CA 022~3488 1998-11-03 converter settles usually much faster than other circuits.
Compared with the circuits in the prior art, the capacitive load of the S/H circuits ll in the new structure is much less.
Therefore, the invented A/D converter can operate much faster than the existing ones. A data rate of about lO0 Msamples/s is possible, according to transistor-level simulation.
Due to the scaling of the reference current sources, the maximum current swing decreases throughout the pipelined stages.
Therefore, bias currents can be reduced successively throughout the pipelined stages. Power consumption can thus be reduced dramatically.
The scaling does not have a negative effect on the performance in that the first stage needs highest resolution ~equivalent to the resolution of the whole pipelined A/D converter) and the following stages need lower and lower resolution throughout the pipeline. For example, the second stage only needs a bit resolution (resolution specified in the num~er of bits) equivalent to the bit resolution of the whole A/D converter minus the bit resolution of the first stage.
To reduce the spread of reference currents, we can introduce multiplication in the S/H circuit of the stages generating the last significant bits (LSBs). They can take two forms as shown in figure 3.
The output current is given by Ii+l=2k' Ij--((bl + 2 ~ b2 +. . ~+2ki-' ~ bk ) Ijre~ ) In this case, the following stage has the same reference value Iiref -.
CA 022~3488 1998-11-03 Due to the extra capacitive load, the settling time increases.
However, the stages generating LSBs do not have the same accuracy requirement and relatively large settling error is acceptable.
The invented architecture has been implemented in the in-house CMOS process. In this section a simplified circuit solution is presented. In figure 4 the simplified circuit diagram of one stage is shown corresponding to figure 2. The input current Iin is fed into the current sample-and-hold circuit S_HO on the odd clock phase Clk_o through switch transistor M7, and is fed into the current quantizer Quantizer_I on the even clock phase Clk_e through transistor M6. The output of the current quantizer Quantizer_I is inverted by an inverter and then latched by a flip-flop resettable by the signal Set_b. The digital output Out_Dig is used to control the D/A converter DAO_lb. The input current to the next stage is Iout, generated by wiring together the output of the sample-and-hold circuit S_HO and that of the D/A converter DAO_lb. Notice the subtraction in figure 2 is implicitly implemented in the D/A converter by properly setting the reference current directions. VbiasO 2 are the bias voltages for the analog blocks S_HO and DACO_lb.
In figure 5, the simplified circuit diagram of the current sample-and-hold circuit is shown. The current sample-and-hold circuit is basically a cascode current mirror with a control switch. Transistors MO and Ml6 provide bias currents for the input and output, respectively. Transistors Ml and Ml5 are cascode transistors to increase the output impedance of current sources. Transistors Ml7 and M5, together with cascode transistors M3 and M4, realize the current mirroring. Transistor M6 is used as a switch controlled by the digital input Clk_S.
CA 022~3488 1998-11-03 Iin and Iout are the input and output currents, respectively, and VbiasO-2 are the bias voltages.
When the digital input Clk_S is high, the output current Iout is equal to the input current Iin, due to the same gate-source 5 voltage for transistors M17 and M5. When Clk_S goes low, the gate of transistor M5 is isolated and therefore the output current Iout is held constant. For different stages, the bias current can be scaled.
In figure 6 the simplified circuit diagram of the 1-bit current quantizer is shown. The 1-bit current quantizer used is a low-impedance quantizer. Transistors MO and M1 are the input transistors. Transistors M2 and M3 form an amplifier. When the input current Iin changes direction, any small potential change is amplified by the amplifier to make the change at the gates of MO and M1 considerably large. This large voltage change is further amplified by another amplifier consisting of transistors M4 and M5, and an inverter is used to drive the output.To realize a multi-bit current quantizer, only reference current at the input will need to be provided.
In figure 7, the simplified circuit diagram of the 1-bit D/A
converter is shown. The D/A converter is basically a cascode current source consisting of transistor M22 and M20, and their cascode transistors M23, M21 respectively. The branch consistiny of transistor MO, M1, M10 and M18 is only used to provide the bias voltage for transistor M20 to guarantee that the drain current in M20 is equal to the drain current in M22. Transistors M31, M50, M36, M37 are used as switches. Depending on the digital input In-Dig, either the current in M22 or the current in M20 is switched to the output. At the same time, the other current, which is not switched to the output is switched to a CA 022~3488 l998-ll-03 load to avoid drastic voltage change when a current source is open circuited. The load is only a current mirror providing a low impedance at its input. VbiasO~2 are the bias voltages.
While the foregoing description includes numerous details and specificities, it is to be understood that these are merely illustrative of the present invention, and are not to be construed as limitations. Many modifications will be readily apparent to those skilled in the art which do not depart from the spirit and scope of the invention, as defined by the appended claims and their legal equivalents.
Claims (4)
1. A method to convert an analog current to a digital signal particularly, where the method relates to high-speed pipelined analog-to-digital (A/D) converters, comprising an S/H circuit at an input and N pipelined stages, each of them comprising an internal low resolution A/D converter, a D/A converter, an S/H
circuit, a reference current source and an adder/subtractor, wherein every stage does not have to be identical to any other, characterized by reducing capacitive load by timeinterleaving the inter stage A/D
converter and the S/H circuit in the N pipelined stages, wherein the capacitive load is to be reduced in order to have high speed and by adjusting reference currents the method also reduces the power consumption.
circuit, a reference current source and an adder/subtractor, wherein every stage does not have to be identical to any other, characterized by reducing capacitive load by timeinterleaving the inter stage A/D
converter and the S/H circuit in the N pipelined stages, wherein the capacitive load is to be reduced in order to have high speed and by adjusting reference currents the method also reduces the power consumption.
2. A device to convert an analog current to a digital signal particularly, where the device relates to the design of high-speed pipelined analog-to-digital (A/D) converters, comprising an S/H circuit at an input and N
pipelined stages, each of them comprising an internal low resolution A/D converter, a D/A converter, an S/H
circuit, a reference current source and an adder/subtractor, wherein every stage does not have to be identical to any other, characterized by, in the N
pipelined stages (8), the inter stage A/D converter (9) and the S/H circuit (11) are timeinterleaved to reduce capacitive load in order to have high speed.
pipelined stages, each of them comprising an internal low resolution A/D converter, a D/A converter, an S/H
circuit, a reference current source and an adder/subtractor, wherein every stage does not have to be identical to any other, characterized by, in the N
pipelined stages (8), the inter stage A/D converter (9) and the S/H circuit (11) are timeinterleaved to reduce capacitive load in order to have high speed.
3. A device according to claim 2, characterized by, in the N pipelined stages (8), a scaling of reference currents is provided for resulting in scaling of bias currents for every stage in order to reduce power consumption.
4. A device according to claim 2, characterized by the use of LSBs stages to reduce the spread of reference currents.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE9601747-0 | 1996-05-07 | ||
| SE9601747A SE516675C2 (en) | 1996-05-07 | 1996-05-07 | Method and apparatus for converting an analog current to a digital signal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2253488A1 true CA2253488A1 (en) | 1997-11-13 |
Family
ID=20402492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002253488A Abandoned CA2253488A1 (en) | 1996-05-07 | 1997-04-29 | A method and device to convert an analog current to a digital signal |
Country Status (11)
| Country | Link |
|---|---|
| US (1) | US5990820A (en) |
| EP (1) | EP0976198B1 (en) |
| JP (1) | JP2000509925A (en) |
| KR (1) | KR20000010717A (en) |
| CN (1) | CN1106712C (en) |
| AU (1) | AU2797197A (en) |
| CA (1) | CA2253488A1 (en) |
| DE (1) | DE69726613T2 (en) |
| SE (1) | SE516675C2 (en) |
| TW (1) | TW330356B (en) |
| WO (1) | WO1997042712A1 (en) |
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| KR100404180B1 (en) * | 1999-07-06 | 2003-11-03 | 엘지전자 주식회사 | Base Station Signal Demodulation Device in Communication System |
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| EP1079528B1 (en) * | 1999-08-25 | 2005-01-12 | Alcatel | Current mode asynchronous decision A/D converter |
| US6255978B1 (en) * | 1999-09-14 | 2001-07-03 | Industrial Technology Research Institute | Serial pipeline DAC with Gamma correction function |
| US6532370B1 (en) * | 1999-09-30 | 2003-03-11 | Skyworks Solutions, Inc. | Cellular handset with adjustable analog to digital conversion |
| US6396429B2 (en) * | 2000-01-07 | 2002-05-28 | Analog Devices, Inc. | Front-end sampling for analog-to-digital conversion |
| FR2809247A1 (en) * | 2000-05-16 | 2001-11-23 | France Telecom | PIPELINE ANALOG-TO-DIGITAL CONVERTER WITH NOISE SHAPING |
| KR100506190B1 (en) * | 2000-05-31 | 2005-08-04 | 매그나칩 반도체 유한회사 | Pipeline Analog-to-Digital Converter |
| US6448192B1 (en) | 2001-04-16 | 2002-09-10 | Motorola, Inc. | Method for forming a high dielectric constant material |
| GB0216897D0 (en) * | 2002-07-20 | 2002-08-28 | Koninkl Philips Electronics Nv | Switched-current analogue-to-digital converter |
| JP4039928B2 (en) * | 2002-10-03 | 2008-01-30 | 三洋電機株式会社 | Analog-digital conversion circuit |
| TW569545B (en) * | 2002-10-24 | 2004-01-01 | Endpoints Technology Corp | Analog/digital converter |
| US6756929B1 (en) * | 2003-03-27 | 2004-06-29 | Analog Devices, Inc. | Methods and structures for interleavably processing data and error signals in pipelined analog-to-digital converter systems |
| US7068203B2 (en) * | 2003-12-31 | 2006-06-27 | Texas Instruments Incorporated | Switched-capacitor circuits with reduced finite-gain effect |
| JP4529007B2 (en) * | 2004-09-02 | 2010-08-25 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit device |
| US7015842B1 (en) * | 2005-01-12 | 2006-03-21 | Teranetics, Inc. | High-speed sampling architectures |
| US7075471B1 (en) * | 2005-02-11 | 2006-07-11 | Teranetics, Inc. | Double-sampled, time-interleaved analog to digital converter |
| DE102005015429B3 (en) * | 2005-04-04 | 2006-10-19 | Infineon Technologies Ag | Clock generation for a time-shifted analog-to-digital converter |
| US7714762B2 (en) * | 2005-04-12 | 2010-05-11 | Massachusetts Institute Of Technology | Method and apparatus for current-mode ADC |
| CN100440734C (en) * | 2005-05-25 | 2008-12-03 | 晨星半导体股份有限公司 | Dynamic accelerating method and device of analogue/digital converter |
| US7773945B2 (en) * | 2005-06-27 | 2010-08-10 | Thingmagic, Inc. | RFID reader front end |
| US7706764B2 (en) * | 2006-06-03 | 2010-04-27 | Thingmagic, Inc. | Systems and methods for active noise cancellation in an RFID tag reader |
| US7683780B2 (en) * | 2006-07-24 | 2010-03-23 | Thingmagic, Inc. | Methods and apparatus for RFID tag placement |
| US7382307B2 (en) * | 2006-10-03 | 2008-06-03 | Atmel Corpporation | Pipelined analog-to-digital converter having a power optimized programmable data rate |
| US8022814B2 (en) * | 2006-11-13 | 2011-09-20 | Trimble Navigation Limited | Systems and methods for slot classification |
| US8081063B2 (en) * | 2006-11-13 | 2011-12-20 | Trimble Navigation Limited | Systems and methods for Q value determination |
| US7839318B2 (en) * | 2006-11-17 | 2010-11-23 | Siflare, Inc | Current mode pipelined analog-to-digital converter |
| US8242946B2 (en) * | 2006-11-17 | 2012-08-14 | Crest Semiconductors, Inc. | Pipelined analog-to-digital converter |
| TWI379526B (en) * | 2007-04-16 | 2012-12-11 | Realtek Semiconductor Corp | Apparatus and method for interference cancellation in receiver of communication system |
| US7733254B2 (en) * | 2007-06-28 | 2010-06-08 | Slicex, Inc. | Sample and hold circuit for a current mode pipelined analog-to-digital converter |
| JP4739395B2 (en) * | 2008-11-14 | 2011-08-03 | 富士通セミコンダクター株式会社 | A / D conversion circuit |
| JP5279521B2 (en) * | 2009-01-20 | 2013-09-04 | 三菱電機株式会社 | Current mode AD converter |
| ATE543259T1 (en) * | 2009-01-26 | 2012-02-15 | Fujitsu Semiconductor Ltd | SCAN |
| CN101635571B (en) * | 2009-08-26 | 2011-07-27 | 余浩 | High-speed production line analog-to-digital converter and clock adjusting method thereof |
| US8436760B1 (en) * | 2009-09-25 | 2013-05-07 | Marvell International Ltd. | Low power current-voltage mixed ADC architecture |
| WO2012009796A1 (en) * | 2010-07-20 | 2012-01-26 | Kapik Inc. | System and method for high speed analog to digital data acquisition |
| US9503119B2 (en) * | 2014-05-29 | 2016-11-22 | Texas Instruments Incorporated | Common mode sampling mechanism for residue amplifier in switched current pipeline analog-to-digital converters |
| KR101986938B1 (en) * | 2017-10-26 | 2019-06-07 | 고려대학교 세종산학협력단 | High-speed, Low-power pipelined ADC utilizing a dynamic reference voltage and 2-stage sample-and-hold |
| US10868557B2 (en) | 2018-03-30 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd | Analog to digital converter with current steering stage |
| US10797718B1 (en) | 2018-04-17 | 2020-10-06 | Ali Tasdighi Far | Tiny low power current mode analog to digital converters for artificial intelligence |
| US10581448B1 (en) | 2018-05-28 | 2020-03-03 | Ali Tasdighi Far | Thermometer current mode analog to digital converter |
| US10862495B1 (en) | 2018-04-17 | 2020-12-08 | Ali Tasdighi Far | Glitch free current mode analog to digital converters for artificial intelligence |
| US10833692B1 (en) | 2018-04-17 | 2020-11-10 | Ali Tasdighi Far | Small low glitch current mode analog to digital converters for artificial intelligence |
| US10720934B1 (en) * | 2019-02-28 | 2020-07-21 | Nxp Usa, Inc. | MDAC based time-interleaved analog-to-digital converters and related methods |
| CN117278031A (en) * | 2023-09-26 | 2023-12-22 | 成都信息工程大学 | ADC system noise model circuit based on time interleaving assembly line |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4684924A (en) * | 1982-09-30 | 1987-08-04 | Wood Lawson A | Analog/digital converter using remainder signals |
| US4894657A (en) * | 1988-11-25 | 1990-01-16 | General Electric Company | Pipelined analog-to-digital architecture with parallel-autozero analog signal processing |
| US5043732A (en) * | 1989-09-26 | 1991-08-27 | Analog Devices, Inc. | Analog-to-digital converter employing a pipeline multi-stage architecture |
-
1996
- 1996-05-07 SE SE9601747A patent/SE516675C2/en not_active IP Right Cessation
-
1997
- 1997-04-29 US US08/848,248 patent/US5990820A/en not_active Expired - Lifetime
- 1997-04-29 CN CN97194404A patent/CN1106712C/en not_active Expired - Lifetime
- 1997-04-29 DE DE69726613T patent/DE69726613T2/en not_active Expired - Lifetime
- 1997-04-29 WO PCT/SE1997/000724 patent/WO1997042712A1/en not_active Application Discontinuation
- 1997-04-29 JP JP9539837A patent/JP2000509925A/en active Pending
- 1997-04-29 TW TW086105659A patent/TW330356B/en active
- 1997-04-29 CA CA002253488A patent/CA2253488A1/en not_active Abandoned
- 1997-04-29 KR KR1019980708819A patent/KR20000010717A/en not_active Application Discontinuation
- 1997-04-29 EP EP97922254A patent/EP0976198B1/en not_active Expired - Lifetime
- 1997-04-29 AU AU27971/97A patent/AU2797197A/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| SE9601747L (en) | 1997-11-08 |
| DE69726613D1 (en) | 2004-01-15 |
| EP0976198B1 (en) | 2003-12-03 |
| CN1217836A (en) | 1999-05-26 |
| SE516675C2 (en) | 2002-02-12 |
| WO1997042712A1 (en) | 1997-11-13 |
| CN1106712C (en) | 2003-04-23 |
| KR20000010717A (en) | 2000-02-25 |
| AU2797197A (en) | 1997-11-26 |
| TW330356B (en) | 1998-04-21 |
| EP0976198A1 (en) | 2000-02-02 |
| SE9601747D0 (en) | 1996-05-07 |
| US5990820A (en) | 1999-11-23 |
| JP2000509925A (en) | 2000-08-02 |
| DE69726613T2 (en) | 2004-10-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Discontinued |