CA2255634A1 - Parallel processor with redundancy of processor pairs - Google Patents

Parallel processor with redundancy of processor pairs

Info

Publication number
CA2255634A1
CA2255634A1 CA002255634A CA2255634A CA2255634A1 CA 2255634 A1 CA2255634 A1 CA 2255634A1 CA 002255634 A CA002255634 A CA 002255634A CA 2255634 A CA2255634 A CA 2255634A CA 2255634 A1 CA2255634 A1 CA 2255634A1
Authority
CA
Canada
Prior art keywords
bus
processor
pairs
migrant
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CA002255634A
Other languages
French (fr)
Other versions
CA2255634C (en
Inventor
Antonio Esposito
Rosario Esposito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of CA2255634A1 publication Critical patent/CA2255634A1/en
Application granted granted Critical
Publication of CA2255634C publication Critical patent/CA2255634C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8023—Two dimensional arrays, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2038—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant with a single idle spare processing component

Abstract

General purpose parallel computer, latency reduction MIMD, with multiple processors and multiple memory address spaces, wherein processors (SPU) are redundantly replicated on each memory (M) bus (C-BUS) and, formed/connected as either master-active or slave-inactive of the bus and to interface a suitable communication structure (A-S) for transferring among themselves the process context and the bus control, in such a way to execute in turn a unique migrant sequential process per bus (C-BUS), and wherein each processor is also directly and tightly coupled with devoted private buses (P-P) to one corresponding processor of another one bus (C-BUS) in a way to form, between distinct buses (C-BUS), biprocessor pairs (DPU) capable of allowing communication and synchronization of the parallel migrant processes.
CA002255634A 1996-05-30 1997-05-28 Parallel processor with redundancy of processor pairs Expired - Fee Related CA2255634C (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
IT96NA000032A IT1288076B1 (en) 1996-05-30 1996-05-30 ELECTRONIC NUMERICAL MULTIPROCESSOR PARALLEL MULTIPROCESSOR WITH REDUNDANCY OF COUPLED PROCESSORS
ITNA96A000032 1996-05-30
PCT/IT1997/000121 WO1997045795A1 (en) 1996-05-30 1997-05-28 Parallel processor with redundancy of processor pairs

Publications (2)

Publication Number Publication Date
CA2255634A1 true CA2255634A1 (en) 1997-12-04
CA2255634C CA2255634C (en) 2002-02-12

Family

ID=11387885

Family Applications (1)

Application Number Title Priority Date Filing Date
CA002255634A Expired - Fee Related CA2255634C (en) 1996-05-30 1997-05-28 Parallel processor with redundancy of processor pairs

Country Status (8)

Country Link
US (1) US6363453B1 (en)
EP (1) EP0901659B1 (en)
JP (1) JP2000511309A (en)
AU (1) AU714681B2 (en)
CA (1) CA2255634C (en)
DE (1) DE69701802T2 (en)
IT (1) IT1288076B1 (en)
WO (1) WO1997045795A1 (en)

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US6738845B1 (en) * 1999-11-05 2004-05-18 Analog Devices, Inc. Bus architecture and shared bus arbitration method for a communication device
US7191310B2 (en) * 2000-01-19 2007-03-13 Ricoh Company, Ltd. Parallel processor and image processing apparatus adapted for nonlinear processing through selection via processor element numbers
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JP2002297556A (en) * 2001-03-29 2002-10-11 Fujitsu Ltd Multiprocessor system, control method and program for multiprocessor, and computer readable recording medium with the program recorded thereon
US20020161453A1 (en) * 2001-04-25 2002-10-31 Peltier Michael G. Collective memory network for parallel processing and method therefor
DE60124324T2 (en) * 2001-09-07 2007-05-24 Nokia Corp. METHOD AND DEVICE FOR SERVICE-QUALITY-BASED DIMENSIONING OF THE CAPACITY OF A CELL
US20060218556A1 (en) * 2001-09-28 2006-09-28 Nemirovsky Mario D Mechanism for managing resource locking in a multi-threaded environment
EP1436724A4 (en) * 2001-09-28 2007-10-03 Consentry Networks Inc Multi-threaded packet processing engine for stateful packet pro cessing
FI20021287A0 (en) * 2002-06-28 2002-06-28 Nokia Corp Balancing load in telecommunication systems
US7634640B2 (en) * 2002-08-30 2009-12-15 Infineon Technologies Ag Data processing apparatus having program counter sensor
DE10319903B4 (en) * 2003-04-29 2007-05-31 Siemens Ag Intrinsically safe computer arrangement
GB0425860D0 (en) * 2004-11-25 2004-12-29 Ibm A method for ensuring the quality of a service in a distributed computing environment
US8279886B2 (en) * 2004-12-30 2012-10-02 Intel Corporation Dataport and methods thereof
US20060200278A1 (en) * 2005-03-02 2006-09-07 Honeywell International Inc. Generic software fault mitigation
US8527741B2 (en) * 2005-07-05 2013-09-03 Viasat, Inc. System for selectively synchronizing high-assurance software tasks on multiple processors at a software routine level
US8190877B2 (en) * 2005-07-05 2012-05-29 Viasat, Inc. Trusted cryptographic processor
ES2303742B1 (en) * 2005-08-01 2009-08-25 Universidad De Cordoba COMMUNICATIONS SYSTEM TO EXECUTE PARALLEL TASKS BY PERSONAL COMPUTERS.
US7739470B1 (en) * 2006-10-20 2010-06-15 Emc Corporation Limit algorithm using queue depth to control application performance
FR2918190B1 (en) 2007-06-26 2009-09-18 Thales Sa ADDRESSING DEVICE FOR PARALLEL PROCESSOR.
US20110179255A1 (en) * 2010-01-21 2011-07-21 Arm Limited Data processing reset operations
US8051323B2 (en) * 2010-01-21 2011-11-01 Arm Limited Auxiliary circuit structure in a split-lock dual processor system
US8108730B2 (en) * 2010-01-21 2012-01-31 Arm Limited Debugging a multiprocessor system that switches between a locked mode and a split mode
US9525647B2 (en) 2010-07-06 2016-12-20 Nicira, Inc. Network control apparatus and method for creating and modifying logical switching elements
US8817621B2 (en) 2010-07-06 2014-08-26 Nicira, Inc. Network virtualization apparatus
US9465670B2 (en) 2011-12-16 2016-10-11 Intel Corporation Generational thread scheduler using reservations for fair scheduling
EP3662474B1 (en) 2017-07-30 2023-02-22 NeuroBlade Ltd. A memory-based distributed processor architecture
EP3966936B1 (en) * 2019-05-07 2023-09-13 Silicon Mobility SAS Spatial segregation of flexible logic hardware
US11789896B2 (en) * 2019-12-30 2023-10-17 Star Ally International Limited Processor for configurable parallel computations

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US4358823A (en) * 1977-03-25 1982-11-09 Trw, Inc. Double redundant processor
JPS60229160A (en) * 1984-04-26 1985-11-14 Toshiba Corp Multiprocessor system
JP2834122B2 (en) 1987-07-08 1998-12-09 株式会社日立製作所 Control device
GB2251964B (en) * 1991-01-15 1994-09-14 Sony Corp Processor arrays

Also Published As

Publication number Publication date
DE69701802T2 (en) 2000-11-16
AU3047197A (en) 1998-01-05
EP0901659A1 (en) 1999-03-17
US6363453B1 (en) 2002-03-26
JP2000511309A (en) 2000-08-29
WO1997045795A1 (en) 1997-12-04
CA2255634C (en) 2002-02-12
AU714681B2 (en) 2000-01-06
EP0901659B1 (en) 2000-04-26
ITNA960032A0 (en) 1996-05-30
DE69701802D1 (en) 2000-05-31
IT1288076B1 (en) 1998-09-10
ITNA960032A1 (en) 1997-11-30

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