CA2256169A1 - Circuit for reproducing bit timing and method of reproducing bit timing - Google Patents
Circuit for reproducing bit timing and method of reproducing bit timing Download PDFInfo
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- CA2256169A1 CA2256169A1 CA002256169A CA2256169A CA2256169A1 CA 2256169 A1 CA2256169 A1 CA 2256169A1 CA 002256169 A CA002256169 A CA 002256169A CA 2256169 A CA2256169 A CA 2256169A CA 2256169 A1 CA2256169 A1 CA 2256169A1
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- circuit
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/233—Demodulator circuits; Receiver circuits using non-coherent demodulation
- H04L27/2332—Demodulator circuits; Receiver circuits using non-coherent demodulation using a non-coherent carrier
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/0033—Correction by delay
- H04L7/0037—Delay of clock signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
- H04L7/002—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation
- H04L7/0029—Arrangements for synchronising receiver with transmitter correction of synchronization errors correction by interpolation interpolation of received data signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence
Abstract
There is provided a circuit for reproducing bit timing, including (a) a first analog-digital converter for converting a real part signal of a complex modulation signal into a real part digital signal, the complex modulation signalhaving a base band frequency band and obtained from a received modulation signal modulated into a digital phase, (b) a second analog-digital converter forconverting an imaginary part signal of the complex modulation signal into an imaginary part digital signal, (c) a first detector for receiving the real part digital signal and the imaginary part digital signal, detecting a phase angle of the complex modulation signal on a complex plane, and transmitting a first signal indicative of the phase angle, (d) a delay circuit for delaying the first signal by a symbol interval, (e) a second detector for detecting a difference in phase on the complex plane between the complex modulation signals in the symbol interval, (f)a third detector for detecting a timing gap between a sampling clock and an optimum sampling point, based on the difference in phase, detected by the seconddetector, and transmitting a second signal indicative of the timing gap, and (g) a signal converter for converting each of the real part digital signal and the imaginary part digital signal into a signal associated with the optimum samplingpoint, based on the second signal. The circuit is hardly influenced by noises and non-linear strains, and is capable of reducing power consumption and accomplishing maintenance free.
Description
CA 022~6169 1998-12-1~
CIRCUIT FOR REPRODUCING BIT TIMING
AND
METHOD OF REPRODUCING BIT TIMING
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a circuit for reproducing bit timing, and more particularly to such a circuit for detecting a timing gap between a sampling clock and an optimal sampling clock, based on a real part digital signal and an 10 im~gin~ry part digital signal obtained by digitizing a real part and an im~gin~ry part of a complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase.
DESCRIPTION OF THE RELATED ART
An apparatus for demodulating burst ~ign~l~ having been modulated into a digital phase is often provided at an input stage thereof with an automatic gain control circuit (hereinafter, referred to simply as "AGC") in order to suppress fluctuation in received .~ign~l~ in a tr~n~mi.~sion path. It is necessary to use a preamble in order to converge AGC.
As is well known, a preamble is a signal indicating that data to be transmitted from a transmitter to a receiver at any time has been transmitted to a receiver, and establi~hing synchronization between a transmitter and a receiver.A burst signal having been modulated into a digital phase is designed to have a preamble at the head thereof for reproducing bit timing, to thereby 25 establish synchronization.
Bit timing of quadrature phase shift keying (QPSK) is usually reproduced through the use of a preamble pattern in which ~ign~l~ existing on a diagonal line are repeatedly transmitted in such an arrangement of signal pointsas an arrangement illustrated in Fig. 3, which is a signal phase diagram, and has CA 022~6169 1998-12-1~
I-axis as an axis of abscissa and Q-axis as an axis of ordinate.
The above-mentioned reproduction of bit timing is controlled, for instance, by zero-cross detection in which timing at which a signal passes an origin is detected.
In zero-cross detection, there is used sampling data having a small amplitude around an origin. However, sampling data having a small amplitude is accompanied with a problem of being readily influenced by noises and non-linear strains to thereby generate errors.
In burst transmission system m~king use of digital phase modulation, 10 it is necessary to rapidly carry out bit synchronization and demodulation such as reproduction of a carrier wave. To this end, a burst signal is provided at a head thereof with a preamble.
In order to enhance a tr~n.~mi~sion rate, it is preferable to shorten a preamble to thereby rapidly establish bit synchronization.
For instance, Japanese Unex~min~?d Patent Publication No. 5-211532 has suggested a rapid bit synchronization system in which a 1r /2-shifted BPSK
signal or a 1r /4-shifted QPSK signal is employed, and needs to have a zero- 1r /
CIRCUIT FOR REPRODUCING BIT TIMING
AND
METHOD OF REPRODUCING BIT TIMING
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a circuit for reproducing bit timing, and more particularly to such a circuit for detecting a timing gap between a sampling clock and an optimal sampling clock, based on a real part digital signal and an 10 im~gin~ry part digital signal obtained by digitizing a real part and an im~gin~ry part of a complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase.
DESCRIPTION OF THE RELATED ART
An apparatus for demodulating burst ~ign~l~ having been modulated into a digital phase is often provided at an input stage thereof with an automatic gain control circuit (hereinafter, referred to simply as "AGC") in order to suppress fluctuation in received .~ign~l~ in a tr~n~mi.~sion path. It is necessary to use a preamble in order to converge AGC.
As is well known, a preamble is a signal indicating that data to be transmitted from a transmitter to a receiver at any time has been transmitted to a receiver, and establi~hing synchronization between a transmitter and a receiver.A burst signal having been modulated into a digital phase is designed to have a preamble at the head thereof for reproducing bit timing, to thereby 25 establish synchronization.
Bit timing of quadrature phase shift keying (QPSK) is usually reproduced through the use of a preamble pattern in which ~ign~l~ existing on a diagonal line are repeatedly transmitted in such an arrangement of signal pointsas an arrangement illustrated in Fig. 3, which is a signal phase diagram, and has CA 022~6169 1998-12-1~
I-axis as an axis of abscissa and Q-axis as an axis of ordinate.
The above-mentioned reproduction of bit timing is controlled, for instance, by zero-cross detection in which timing at which a signal passes an origin is detected.
In zero-cross detection, there is used sampling data having a small amplitude around an origin. However, sampling data having a small amplitude is accompanied with a problem of being readily influenced by noises and non-linear strains to thereby generate errors.
In burst transmission system m~king use of digital phase modulation, 10 it is necessary to rapidly carry out bit synchronization and demodulation such as reproduction of a carrier wave. To this end, a burst signal is provided at a head thereof with a preamble.
In order to enhance a tr~n.~mi~sion rate, it is preferable to shorten a preamble to thereby rapidly establish bit synchronization.
For instance, Japanese Unex~min~?d Patent Publication No. 5-211532 has suggested a rapid bit synchronization system in which a 1r /2-shifted BPSK
signal or a 1r /4-shifted QPSK signal is employed, and needs to have a zero- 1r /
2 modulated preamble or a zero-3 7r /4 modulated preamble, respectively.
A signal obtained by detecting a ~T /2-shifted BPSK signal or a 1r /4-shifted QPSK signal in quasi-synchronization is digitally quantized into one bitsignal by means of an analog-digital converter through the use of clock ~ign~l~
transmitted from an oscillator, and then, variation in phase is detected by a phase-variation detector.
A complex sine wave generator generates a complex sine wave having a frequency of N/2 in response to a clock signal transmitted from an oscillator. Amultiplier multiplies the thus generated complex sine wave by the variation in phase detected by the phase-variation detector to thereby calculate a relation in phase between a frequency component of 1/2 bit and the complex sine wave.
The result of calculation is averaged through a low-pass filter, and then, a reverse CA 022~6169 1998-12-1~
tangent of an output transmitted from the low-pass filter is calculated by a reverse tangent calculator.
The reverse tangent calculator transmits its output at a timing which is represented within + 7r under a two-bit interval. In order to covert a bit timing 5 of an output timing of the reverse tangent calculator into a bit timing represented within + ~T under a one-bit interval, the reverse tangent is doubled by means ofa doubling device, and a remainder is calculated when the thus doubled reverse tangent is divided by 2 ~T .
An output transmitted from an analog-digital converter is sampled or 10 interpolated by a sampler or an interpolator at a bit timing at which the doubling device generates an output.
Japanese Unex~min~d Patent Publication No. 5-260107 has suggested a perpendicular modulator for demodulating n-PSK wave ~ign~l~, wherein n indicates phase modulation. The suggested perpendicular modulator 15 interpolates sampled n-PSK wave ~ign~l~ when n-PSK wave ~ign~l~ are digitally sampled and perpendicularly detected.
The suggested perpendicular modulator is designed to include two analog-digital converters for sampling n-PSK wave ~ign~ at a constant interval to thereby reproduce base band .~ign~ . Then, the thus reproduced base band 20 ~ign~l~ are interpolated by means of an interpolation circuit. A re-timing device carries out re-timing treatment to the thus interpolated base band signals in response to a bit timing signal. Then, a detector detects the thus re-timed baseband .cign~l~ to thereby reproduce data sequence. Then, a bit timing reproducer generates a bit timing signal, based on a timing of the thus reproduced data 25 sequence.
Japanese Unexamined Patent Publication No. 6-284159 has suggested a digital demodulator including a clock synchronization circuit which extracts aphase component of received clocks, and control a phase of a timing clock.
In accordance with the suggested digital demodulator, a base band CA 022~6169 1998-12-1~
signal having been modulated under four-value digital modulation is sampled at arate twice greater than a modulation rate to thereby convert the base band signal into digital data. Detection data detected by a delay detection circuit is judged by a judgement circuit with judgement timing clocks, and then, is transmitted to a 5 limiter circuit having a function of interpolation.
The limiter circuit interpolates one or more of adjacent two sampling values of detected outputs, puts the thus interpolated value into a limiter, andtransmits one-bit interpolated data to a digital band pass filter.
In response to tr~n~mi~sion of an output from the digital band pass 10 filter, a circuit for detecting an error in phase detects an error in phase in a timing clock. Then, the circuit for detecting an error in phase transmits a signal indicative of an error in phase to a circuit for reproducing a clock, in accordance with the result of comparison in phase between the thus detected error in phase and a current timing clock. Then, the circuit for reproducing a clock 15 compensates for a phase of a timing clock.
Japanese Unexamined Patent Publication No. 7-50700 has suggested a circuit for reproducing a carrier wave for detecting a phase of preamble.
In the suggested circuit, first and second multipliers each multiplies an offset QPSK modulation wave by a reproduced carrier wave having a phase 20 shifted by 7r /2 from a phase of the offset QPSK modulation wave. An output transmitted from the first multiplier is delayed by a half interval of symbol rate relative to an output transmitted from the second multiplier, by means of a delay circuit. Then, a phase comparator for reproducing a bit timing converts outputs transmitted from the delay circuit and the second multiplier into a signal having a 25 phase including two phase-stable points.
Japanese Unex~min~?d Patent Publication No. 7-212419 has suggested an apparatus for extracting a clock for detecting a phase of preamble.
In this apparatus, a relative phase of a carrier wave of a 1r /4-shifted QPSK is input into a relative phase detector. The relative phase detector CA 022~6169 1998-12-1~
includes first and second counters each of which counts qign~l.q having a frequency equal to a M times multiplied sum of a frequency of a carrier wave of a 7r /4-shifted QPSK signal transmitted from an oscillator and a shifted frequency.
The relative phase detector includes an amplitude limiter. The amplitude limiter slides an amplitude of the carrier wave to thereby transmit a rectangular wave as a carrier wave. A rise-up detecting circuit detects rise-up of the carrier wave, and resets the first counter. Then, a circuit for subtraction subtracts an output transmitted from the first counter from an output transmitted from the second counter to thereby transmit a relative phase of the 10 carrier wave of the ~r /4-shifted QPSK signal.
Then, the subtraction circuit calculates a difference between the relative phase and a phase prior to the relative phase by a half symbol. When a phase difference detector detects that the thus calculated difference becomes equal to a predetermined value, a reference signal generator transmits a 15 reference signal.
On the other hand, a demodulator may be designed to include a limiter amplifier for suppressing fluctuation in an input level to be introduced to the demodulator. The limiter amplifier keeps an output level transmitted from the demodulator constant regardless of an input level. As a result, it is no longer 20 necessary to use a preamble for AGC, which ensures a shorter preamble.
However, the use of a limiter amplifier is accompanied with a problem that performances of the demodulator is much deteriorated due to non-linear strain which is caused by the limiter amplifier. Hence, the demodulator is necessary to be provided with a countermeasure against such non-linear strain All of the above-mentioned conventional apparatuses or circuits are not provided with a countermeasure to avoid influences due to non-linear strain and/or an error caused by noises, and hence, are accompanied with a problem of deterioration of performances due to non-linear strain.
CA 022~6169 1998-12-1~
SUMMARY OF THE INVENTION
In view of the above-mentioned problem, it is an object of the present invention to provide a circuit for reproducing a bit timing and a method of doing the same both of which are hardly influenced by noises and errors caused by non-linear strain, and are capable of fabricating a semiconductor device in a smaller size to thereby reduce power consumption.
In one aspect of the present invention, there is provided a circuit for reproducing bit timing, including (a) a first analog-digital converter for converting a real part signal of a complex modulation signal into a real part digital signal, 10 the complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase, (b) a second analog-digital converter for converting an im~gin~ry part signal of the complex modulation signal into an im~gin~ry part digital signal, (c) a first detector for receiving the real part digital signal and the im~gin~ry part digital signal, 15 detecting a phase angle of the complex modulation signal on a complex plane, and transmitting a first signal indicative of the phase angle, (d) a delay circuit for delaying the first signal by a symbol interval, (e) a second detector for detecting a difference in phase on the complex plane between the complex modulation ~ign~l~
in the symbol interval, (f) a third detector for detecting a timing gap between a 20 sampling clock and an optimum sampling point, based on the difference in phase, detected by the second detector, and transmitting a second signal indicative of the timing gap, and (g) a signal converter for converting each of the real part digital signal and the im~gin~ry part digital signal into a signal associated with the optimum sampling point, based on the second signal.
In accordance with the above-mentioned circuit, the first analog-digital converter converts a real part signal of a complex modulation signal, which has a base band frequency band and is obtained from a received modulation signal having been modulated into a digital phase, into a real part digital signal, and the second analog-digital converter converts an im~gin~ry part signal of the complex CA 022~6169 1998-12-1~
modulation signal into an imaginary part digital signal. The thus obtained real part digital signal and im~gin~ry part digital signal are input into the first detector.
The first detector having received the real part digital signal and the im~gin~ry part digital signal detects a phase angle of the complex modulation signal on a complex plane, and then, transmits the first signal indicative of the phase angle, to both the delay circuit and the second detector. The delay circuit delays the first signal by a symbol interval, and then, transmits the delayed first signal to the second detector. The second detector makes subtraction between lo the first signal and an output signal transmitted from the delay circuit to thereby detect a difference in phase on the complex plane between the complex modulation .qignz~l.q in the symbol interval. A signal indicative of the thus detected difference in phase is transmitted to the third detector.
The third detector detects a timing gap between a sampling clock and 15 an optimum sampling point, based on the difference in phase detected by the second detector, and transmits the second signal indicative of the timing gap tothe signal converter.
The signal converter converts each of the real part digital signal and the im~gin~ry part digital signal into a signal associated with the optimum 20 sampling point, based on the second signal.
The circuit in accordance with the invention is hardly influenced by noises and errors caused by non-linear strain, and makes it possible to fabricate a semiconductor device in a smaller size, reduce power consumption, and accomplish maintenance free.
It is preferable that the above-mentioned circuit further includes a clock oscillator transmitting fixed clock qign~lq, in which case, the first analog-digital converter samples and quantizes the real part signal with the fixed clock qign~lq to thereby convert the real part signal into the real part digital signal.
It is also preferable that the above-mentioned circuit further includes a CA 022~6169 1998-12-1~
clock oscillator transmitting fixed clock qign~l.q, in which case, the second analog-digital converter samples and quantizes the im~gin~ry part signal with the fixedclock .qignz31q to thereby convert the im~gin71ry part signal into the im~gin~ry part digital signal.
For instance, the second detector may be comprised of a subtracter for making subtraction between the first signal and an output signal transmitted from the delay circuit.
There is further provided a circuit for reproducing bit timing, including (a) a first analog-digital converter for converting a real part signal of a complex lo modulation signal into a real part digital signal, the complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase, (b) a second analog-digital converter forconverting an im~gin~ry part signal of the complex modulation signal into an im~gin~ry part digital signal, (c) a first detector for receiving the real part digital 15 signal and the im~gin~ry part digital signal, detecting a phase angle of the complex modulation signal on a complex plane, and transmitting a first signal indicative of the phase angle, (d) a delay circuit for delaying the first signal by a symbol interval, (e) a second detector for detecting a difference in phase on the complex plane between the complex modulation .qign~lq in the symbol interval, (f) 20 a third detector for detecting a timing gap between a sampling clock and an optimum sampling point, based on the difference in phase, detected by the seconddetector, and transmitting a second signal indicative of the timing gap, (g) a first interpolating filter for converting the real part digital signal into a signal associated with an optimum sampling point, based on the second signal, and (h) a25 second interpolating filter for converting the im~gin~ry part digital signal into a signal associated with an optimum sampling point, based on the second signal.
There is still further provided a circuit for reproducing bit timing, including (a) a first analog-digital converter for converting a real part signal of a complex modulation signal into a real part digital signal, the complex modulation CA 022~6169 1998-12-1~
signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase, (b) a second analog-digital converter for converting an im~gin~ry part signal of the complex modulation signal into an im~gin~ry part digital signal, (c) a first detector for receiving the 5 real part digital signal and the im~gin~ry part digital signal, detecting a phase angle of the complex modulation signal on a complex plane, and transmitting a first signal indicative of the phase angle, (d) a delay circuit for delaying the first signal by a symbol interval, (e) a second detector for detecting a difference inphase on the complex plane between the complex modulation ~ign~ in the 10 symbol interval, (f) a third detector for detecting a timing gap between a sampling clock and an optimum sampling point, based on the difference in phase, detected by the second detector, and transmitting a second signal indicative of the timing gap, (g) a clock oscillator for transmitting fixed clock .qign~l~, and (h) a progr~mm.qhle phase shifter for ~hifting a phase of the fixed clock .~ign~ , based 15 on the second signal.
In another aspect of the present invention, there is provided a method of reproducing bit timing, including the steps of (a) converting a real part signal of a complex modulation signal into a real part digital signal, the complex modulation signal having a base band frequency band and obtained from a 20 received modulation signal modulated into a digital phase, (b) converting an im~gin~ry part signal of the complex modulation signal into an im~gin~ry part digital signal, (c) detecting a phase angle of the complex modulation signal on a complex plane, based on the real part digital signal and the im?~gins~ry part digital signal, and transmitting a first signal indicative of the thus detected phase angle, 25 (d) delaying the first signal by a symbol interval, (e) detecting a difference in phase on the complex plane between the complex modulation ~ign~l.s in the symbol interval, (f) detecting a timing gap between a sampling clock and an optimum sampling point, based on the difference in phase, and (g) converting each of the real part digital signal and the im~gin~ry part digital signal into a signal . . . , _ , CA 022~6169 1998-12-1~
associated with the optimum sampling point, based on the timing gap.
It is preferable that the real part signal is sampled and quantized with fixed clock ~sign~l~ to thereby be converted into the real part digital signal in the step (a).
6 It is also preferable that the im~gin~ry part signal is sampled andquantized with fixed clock ~ign~l~ to thereby be converted into the im~gin~ry part digital signal in step (b).
For instance, the difference in phase may be detected by m~king subtraction between the complex modulation ~ign~ in the symbol interval in the step (e).
There is further provided a method of reproducing bit timing, including the steps of (a) converting a real part signal of a complex modulation signal into a real part digital signal, the complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase, (b) converting an im~gin~ry part signal of the complex modulationsignal into an im~gin~ry part digital signal, (c) detecting a phase angle of thecomplex modulation signal on a complex plane, based on the real part digital signal and the im~ginz~ry part digital signal, and transmitting a first signal indicative of the thus detected phase angle, (d) delaying the first signal by a symbol interval, (e) detecting a difference in phase on the complex plane between the complex modulation ~ign~l.q in the symbol interval, (f) detecting a timing gap between a sampling clock and an optimum sampling point, based on the difference in phase, and (g) shifting a phase of fixed clock sign~ , based on the timing gap.
In the specification, BPSK is an acronym of "Binary Phase Shift Keying", QPSK is an acronym of "Quadrature Phase Shift Keying", MSK is an acronym of "Minimum Shift Keying", and GMSK is an acronym of "Gaussian filtered Minimum Phase Shift Keying".
The above and other objects and advantageous features of the present invention will be made apparent from the following description made with .. , . , .. ~ . . ..
CA 022~6169 1998-12-1~
reference to the accompanying drawings, in which like reference characters designate the same or ~imil~r parts throughout the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram illustrating a circuit for reproducing bit timing, in accordance with the first embodiment of the present invention.
Fig. 2 is a block diagram of a demodulator including the circuit illustrated in Fig. 1.
Fig. 3 is a view illustrating signal phases in the circuit illustrated in Fig.
10 1.
Fig. 4 is a view illustrating a relation between a timing at which a modulation signal is sampled and a phase angle of a modulation signal in the circuit illustrated in Fig. 1.
Fig. 5 is a view illustrating interpolation of sampled data by means of 15 an interpolating filter in the circuit illustrated in Fig. 1.
Fig. 6 is a block diagram illustrating a circuit for reproducing bit timing, in accordance with the second embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Fig. 1 is a block diagram illustrating a circuit for reproducing bit timing, in accordance with the first embodiment. In order to make it easy to understand the circuit illustrated in Fig. 1, a demodulator including the circuit illustrated in Fig. 1 is first explained hereinbelow with reference to Fig. 2.
With reference to Fig. 2, a received modulation signal having been 25 modulated into a digital phase is input into a limiter amplifier 1 from a radio receiver 21. Even if the radio receiver 21 receives radio ~ign~l~ having been fluctuated in level in a tr~n.~mi~sion path, the limiter amplifier 1 smoothes the level fluctuation of the received radio ~ign~l~ when the received radio .~ign~l~ are input into the demodulator.
.. . . .
CA 022~6169 1998-12-1~
The limiter amplifier 1 transmits its output to a band pass filter 2.
The band pass filter 2 removes an unnecessary wave caused by non-linear strain accompanied with an operation of smoothing the level fluctuation in the receivedmodulation signal, carried out by the limiter amplifier 1, and then, transmits the 5 received modulation signal into a distributor 3 constituting a part of a perpendicular quasi-synchronization detector 101.
The distributor 3 bifurcates the received modulation signal, and transmits the bifurcated .qign~l.s into each of first input ports of a first multiplier 4 and a second multiplier 5. The first multiplier 4 further receives at a second 10 input port thereof a local signal approximately identical with a carrier wave of a modulation signal transmitted from an oscillator 6.
The first multiplier 4 multiplies the local signal by the bifurcated modulation signal transmitted from the distributor 3, to thereby generate a realpart signal of a complex modulation signal having a base band frequency band.
15 The thus generated real part signal is transmitted into a first low pass filter 8.
The local signal is transmitted further to a 7r /2-phase shifter 7 from the oscillator 6. The 7r /2-phase shifted local signal is transmitted to a second input port of the second multiplier 5 from the ~r /2-phase shifter 7.
Then, the second multiplier 5 multiplies the 7r/2-phase shifted local 20 signal by the bifurcated modulation signal tr~n.~mitted from the distributor 3, to thereby generate an im~gin~ry part signal of a complex modulation signal having a base band frequency band. The thus generated im~gin~ry part signal is transmitted into a second low pass filter 9.
The first low pass filter 8 removes unnecessary high-frequency waves 25 out of the real part signal of the complex modulation signal, and then, transmits the real part signal to a first analog-digital (A/D) converter 10.
Similarly, the second low pass filter 9 removes unnecessary high-frequency waves out of the imaginary part signal of the complex modulation signal, and then, transmits the im~gin~ry part signal to a second analog-digital (A
CA 022~6169 1998-12-1~
/D) converter 11.
A clock oscillator 12 tr~n.~mits fixed clocks to the first and second analog-digital converters 10 and 11. The first analog-digital converter 10 samples and quantizes the received real part signal of the complex modulation 5 signal in response to the fixed clocks received from the oscillator 12, to thereby convert the real part signal into a real part digital signal. Similarly, the second analog-digital converter 11 samples and quantizes the received im~gin~ry part signal of the complex modulation signal in response to the fixed clocks receivedfrom the oscillator 12, to thereby convert the im~gin~ry part signal into an lo im~gin~ry part digital signal.
Both the real part digital signal transmitted from the first analog-digital converter 10 and the im~gin~ry part digital signal transmitted from the second analog-digital converter 11 are introduced into a circuit 102 for reproducing bit timing, in accordance with the first embodiment, and converted 5 into ~ign~l~ associated with optimal sampling points by the circuit 102.
The real part digital signal and the im~in~ry part digital signal having been converted into sign~l~ associated with optimal sampling points are input into a delay detecting circuit 13. The real part digital signal and the im~gin~ry part digital signal are delayed and detected in the delay detecting circuit 13, and 20 resultingly, the delay detecting circuit 13 outputs I-ch~nnel demodulation signal and Q-channel demodulation signal.
Hereinbelow is explained a structure of the circuit 102 for reproducing bit timing, with reference to Fig. 1.
Both the real part digital signal transmitted from the first analog-25 digital converter 10 and the im~gin~ry part digital signal transmitted from thesecond analog-digital converter 11 are introduced into a circuit 14 for detecting a phase of a modulation signal.
The real part digital signal transmitted from the first analog-digital converter 10 is introduced further into the delay detecting circuit 13 through a CA 022~6169 1998-12-1~
first interpolation circuit 18, and qimil~rly, the im~gin~ry part digital signaltransmitted from the second analog-digital converter 11 is introduced further into the delay detecting circuit 13 through a second interpolation circuit 19.
The circuit 14 for detecting a phase of a modulation signal receives the 5 real part digital signal and the im~gin~qry part digital signal to thereby detect a phase angle of the complex modulation signal on a complex plane, and transmits afirst signal Sa indicative of the thus detected phase angle to both a first input port of a subtracter 15 and an input port of a delay circuit 16.
The delay circuit 16 delays the first signal Sa received from the circuit lo 14, by a symbol interval Ts, and transmits the thus delayed signal to a second input port of the subtracter 15.
The subtracter 15 makes subtraction between the first signal Sa and the delayed signal to thereby detect a difference in phase on a complex plane among the modulation qign~lq in the symbol interval Ts.
The difference in phase detected by the subtracter 15 is transmitted into a circuit 17 for detecting a clock phase. The circuit 17 for detecting a clock phase detects a timing gap between a sampling clock and an optimal sampling point, based on the received difference in phase, and transmits the detection result, that is, a second signal Sb indicative of the thus detected timing gap to 20 both the first interpolation circuit 18 and the second interpolation circuit 19.
The first interpolation circuit 18 and the second interpolation circuit 19 cooperates with each other to thereby constitute a signal converter 200 which converts the real part digital signal transmitted from the first analog-digital converter 10, into a signal associated with an optimal sampling point, and 25 converts the im~gin~ry part digital signal tr~mqmitted from the second analog-digital converter 11, into a signal associated with an optimal sampling point, based on the second signal Sb indicative of the timing gap.
Outputs transmitted from the first and second interpolation circuits 18 and 19 are introduced into the delay detecting circuit 13.
CA 022~6169 1998-12-1~
The circuit 102 for reproducing bit timing has such a structure as mentioned so far.
Hereinbelow is explained an operation of the circuit for reproducing bit timing, in accordance with the first embodiment.
As mentioned earlier, the first low pass filter 8 removes unnecessary high-frequency waves out of the real part signal of the complex modulation signal, and transmits the real part signal to the first analog-digital converter 10. In the same way, the second low pass filter 9 removes unnecessary high-frequency waves out of the imzlgin~ry part signal of the complex modulation signal, and transmits 10 the im~gin~ry part signal to the second analog-digital converter 11.
The first analog-digital converter 10 receives fixed clocks from the clock oscillator 12, and samples the real part signal of the complex modulation signal in response to the fixed clocks, to thereby convert the real part signal to the real part digital signal. Similarly, the second analog-digital converter 11 receives fixed15 clocks from the clock oscillator 12, and samples the im~gin~ry part signal of the complex modulation signal in response to the fixed clocks, to thereby convert the im~gin~ry part signal to the im~gin~ry part digital signal.
The thus produced real part digital signal and im~gin~ry part digital signal are transmitted into the circuit 14 for detecting a phase of a modulation20 signal.
The circuit 14 for detecting a phase of a modulation signal receives the real part digital signal and the im~gin~ry part digital signal to thereby detect a phase angle of the complex modulation signal on a complex plane, and transmits the first signal Sa indicative of the thus detected phase angle to both a first input 25 port of the subtracter 15 and the delay circuit 16.
The delay circuit 16 produces a signal delayed by the symbol interval Ts from the second signal Sb, and transmits the thus produced, delayed signal to a second input port of the subtracter 15.
The subtracter 15 subtracts the first signal Sa received from the circuit CA 022~6169 1998-12-1~
14 from the delayed signal received from the delay circuit 16 to thereby detect a difference in phase of those .qi~n~lq on a complex plane in the symbol interval Ts.
Then, the subtracter 15 transmits a signal Sd indicative of the thus detected difference in phase to the circuit 17 for detecting a phase of clocks.
In accordance with the above-mentioned first embodiment, synchronization is established by means of a preamble arranged at a head of a burst signal and used for reproducing bit timing. Herein, it is assumed that a clock is sufficiently stable, and synchronization is kept established in a burst until the burst ends, even if a control through the use of clocks is ceased, after 10 synchronization has been once established by means of a preamble.
For instance, it is assumed that a preamble to be used in QPSK
modulation system has a pattern wherein two .qign~lq S1 and S2, bridged by an arrow Yl in Fig. 3, a signal phase diagram, is alternately repeated.
Assuming one of the .qi~n~lq Sl and S2 is considered as a standard, a 15 phase angle of a modulation signal would have a pattern comprised of repeated waveforms, as illustrated in Fig. 4.
It is assumed in Fig. 4 that a timing gap between a sampling clock and an optimal sampling point tl is represented by ~T, and a phase difference between modulation qign~lq in a symbol interval Ts is represented by ~ . Under 20 the assumption, a relation between the timing gap l~ T and the phase different 0 is represented as follows.
0 =90~ x (1--2x~T/Ts) .-. ~ T/Ts = (1/2--0 /180~
In accordance with the above-mentioned equation, it is possible to 25 detect the timing gap between a sampling clock and an optimal sampling point tl, represented by ~ T/Ts, can be calculated based on the phase difference ~ on a complex plane between the modulation .qi~n~lq in the symbol interval Ts.
The circuit 17 for detecting a clock phase detects a timing gap between a sampling clock between an optimal sampling point in the above-mentioned CA 022~6169 1998-12-1~
manner, averages the timing gap in a preamble, and transmits a second signal Sb indicative of the thus detected timing gap to the first and second interpolationfilters 18 and 19.
The first interpolation filter 18 receives the second signal Sb from the circuit 17, and converts the real part digital signal received from the first analog-digital converter 10, into a signal associated with an optimal sampling point, based on the second signal Sb indicative of the timing gap.
Similarly, the second interpolation filter 19 receives the second signal Sb from the circuit 17, and converts the im~gin~ry part digital signal received 10 from the second analog-digital converter 11, into a signal associated with anoptimal sampling point, based on the second signal Sb indicative of the timing gap.
For instance, when sample data Dl, D2, and D3 having an interval equal to Ts/2 among one another are input for converting the real or im~gin~ry 15 part digital signal into an optimal signal, as illustrated in Fig. 5, data SD is presumed by interpolation. Herein, data SD is data delayed by the timing gap T from the sample data D2.
The operation of the first and second interpolation filters 18 and 19 is described in "Burst Mode All-Digitized High-Speed Clock Reproducing Circuit", by20 Matsumoto, Morikura, and Kato, Electronic Data Communication Institute Articles, Vol. J75--B--II, June 1992, No. 6.
An interpolation filter requires data sampled at a speed at least twice greater than a symbol speed, whereas the circuit 17 for detecting a clock phase requires data sampled at a speed equal to a symbol speed.
The real part digital signal having been converted into the signal associated with an optimal sampling point by means of the first interpolation filter 18 is transmitted to the delay detecting circuit 13, and the im~gin~ry digital signal having been converted into the signal associated with an optimal samplingpoint by means of the second interpolation filter 19 is transmitted also to the .. . .
CA 022~6169 1998-12-1~
delay detecting circuit 13.
The delay detecting circuit 13 delays the thus received real and im~gin~ry part digital ~ign~l~, and transmits I-ch~nnel and Q-ch~3nnel demodulation sign~ as output ~ign~
The circuit 102 for reproducing bit timing, in accordance with the first embodiment, uses a preamble which does not pass an origin of a complex plane of a modulation signal, as illustrated in Fig. 3.
Thus, the circuit 102 detects a phase of a sampling clock without using sampling data located in the vicinity of the origin and having a small amplitude.
10 Accordingly, the circuit 102 is hardly influenced by noises and errors caused by non-linear strain.
In order to detect a clock phase, a sampling speed twice greater than a symbol speed has been conventionally required, but the circuit 102 for reproducing bit timing, in accordance with the first embodiment, can operate at a 15 symbol speed.
Accordingly, the circuit 102 in accordance with the first embodiment is resistant to non-linear strain, and is capable of reducing power consumption, fabricating a semiconductor device in a smaller size in the form of LSI, and accompli.ching maintenance free.
Fig. 6 is a block diagram illustrating a circuit for reproducing bit timing, in accordance with the second embodiment. Parts or elements that correspond to those of the first embodiment illustrated in Figs. 1 and 2 have been provided with the same reference numerals.
As would be obvious from comparison of Fig. 6 with Fig. 1, a circuit 103 25 for reproducing bit timing, in accordance with the second embodiment, is provided with a signal converter 201 having a different structure from a structure of thesignal converter 200 of the circuit 102 for reproducing bit timing, in accordance with the first embodiment.
That is, the signal converter 200 in the first embodiment is comprised of ... . .
CA 022~6169 1998-12-1~
the first interpolation filter 18 and the second interpolation filter 19, whereas the signal converter 201 in the second embodiment is comprised of a progr~mm~hle phase shifter 20.
In the circuit 103 in accordance with the second embodiment, the 5 second signal Sb indicative of the timing gap, transmitted from the circuit 17 for detecting a clock phase, is input into the progr~mm~hle phase shifter 20, which shifts a phase of fixed clocks transmitted from the clock oscillator 12, based on the second signal Sb. In the second embodiment, a phase of fixed clocks transmitted from the clock oscillator 12 is shifted unlike the first embodiment.
In accordance with clocks transmitted from the clock oscillator 12 and phase-shifted by the progr~mm~hle phase shifter 20, the first analog-digital converter 10 samples and quantizes a real part signal of a complex modulation signal to thereby convert the real part signal into a real part digital signal, which is transmitted to both the circuit 14 for detecting a phase of a modulation signal 15 and the delay detecting circuit 13.
Similarly, in accordance with clocks transmitted from the clock oscillator 12 and phase-shifted by the progr~mm~hle phase shifter 20, the secondanalog-digital converter 11 samples and quantizes an im~in~ry part signal of a complex modulation signal to thereby convert the im~gin~ry part signal into an 20 im~in~3ry part digital signal, which is transmitted to both the circuit 14 for detecting a phase of a modulation signal and the delay detecting circuit 13.
The other operation is the same as the operation carried out by the circuit 102 in accordance with the first embodiment.
The progr~mm~hle phase shifter 20 is described, for instance, in 25 "Development of Digitally Controlled Clock Oscillator for DDL", by Takakusaki, Electronic Data Communication Institute, Communication Society Conference, B-371, 1996.
All parts constituting the circuit 103 in accordance with the second embodiment, including the first and second analog-digital converters 10 and 11, CA 022~6169 1998-12-1~
operate at a symbol speed.
In addition, since the circuit 103 for reproducing bit timing, in accordance with the second embodiment, uses a preamble which does not pass an origin of a complex plane of a modulation signal, as illustrated in Fig. 3, the 5 circuit 103 can be applied to modulation system in which a modulation signal does not pass an origin of a complex plane, such as 7r/4--shifted QPSK, MSK, or GMSK.
While the present invention has been described in connection with certain preferred embodiments, it is to be understood that the subject matter 10 encompassed by way of the present invention is not to be limited to those specific embodiments. On the contrary, it is intended for the subject matter of the invention to include all alternatives, modifications and equivalents as can be included within the spirit and scope of the following claims.
The entire disclosure of Japanese Patent Application No. 9-363522 filed on December 16, 1997 including specification, claims, drawings and sllmmz~ry is incorporated herein by reference in its entirety.
A signal obtained by detecting a ~T /2-shifted BPSK signal or a 1r /4-shifted QPSK signal in quasi-synchronization is digitally quantized into one bitsignal by means of an analog-digital converter through the use of clock ~ign~l~
transmitted from an oscillator, and then, variation in phase is detected by a phase-variation detector.
A complex sine wave generator generates a complex sine wave having a frequency of N/2 in response to a clock signal transmitted from an oscillator. Amultiplier multiplies the thus generated complex sine wave by the variation in phase detected by the phase-variation detector to thereby calculate a relation in phase between a frequency component of 1/2 bit and the complex sine wave.
The result of calculation is averaged through a low-pass filter, and then, a reverse CA 022~6169 1998-12-1~
tangent of an output transmitted from the low-pass filter is calculated by a reverse tangent calculator.
The reverse tangent calculator transmits its output at a timing which is represented within + 7r under a two-bit interval. In order to covert a bit timing 5 of an output timing of the reverse tangent calculator into a bit timing represented within + ~T under a one-bit interval, the reverse tangent is doubled by means ofa doubling device, and a remainder is calculated when the thus doubled reverse tangent is divided by 2 ~T .
An output transmitted from an analog-digital converter is sampled or 10 interpolated by a sampler or an interpolator at a bit timing at which the doubling device generates an output.
Japanese Unex~min~d Patent Publication No. 5-260107 has suggested a perpendicular modulator for demodulating n-PSK wave ~ign~l~, wherein n indicates phase modulation. The suggested perpendicular modulator 15 interpolates sampled n-PSK wave ~ign~l~ when n-PSK wave ~ign~l~ are digitally sampled and perpendicularly detected.
The suggested perpendicular modulator is designed to include two analog-digital converters for sampling n-PSK wave ~ign~ at a constant interval to thereby reproduce base band .~ign~ . Then, the thus reproduced base band 20 ~ign~l~ are interpolated by means of an interpolation circuit. A re-timing device carries out re-timing treatment to the thus interpolated base band signals in response to a bit timing signal. Then, a detector detects the thus re-timed baseband .cign~l~ to thereby reproduce data sequence. Then, a bit timing reproducer generates a bit timing signal, based on a timing of the thus reproduced data 25 sequence.
Japanese Unexamined Patent Publication No. 6-284159 has suggested a digital demodulator including a clock synchronization circuit which extracts aphase component of received clocks, and control a phase of a timing clock.
In accordance with the suggested digital demodulator, a base band CA 022~6169 1998-12-1~
signal having been modulated under four-value digital modulation is sampled at arate twice greater than a modulation rate to thereby convert the base band signal into digital data. Detection data detected by a delay detection circuit is judged by a judgement circuit with judgement timing clocks, and then, is transmitted to a 5 limiter circuit having a function of interpolation.
The limiter circuit interpolates one or more of adjacent two sampling values of detected outputs, puts the thus interpolated value into a limiter, andtransmits one-bit interpolated data to a digital band pass filter.
In response to tr~n~mi~sion of an output from the digital band pass 10 filter, a circuit for detecting an error in phase detects an error in phase in a timing clock. Then, the circuit for detecting an error in phase transmits a signal indicative of an error in phase to a circuit for reproducing a clock, in accordance with the result of comparison in phase between the thus detected error in phase and a current timing clock. Then, the circuit for reproducing a clock 15 compensates for a phase of a timing clock.
Japanese Unexamined Patent Publication No. 7-50700 has suggested a circuit for reproducing a carrier wave for detecting a phase of preamble.
In the suggested circuit, first and second multipliers each multiplies an offset QPSK modulation wave by a reproduced carrier wave having a phase 20 shifted by 7r /2 from a phase of the offset QPSK modulation wave. An output transmitted from the first multiplier is delayed by a half interval of symbol rate relative to an output transmitted from the second multiplier, by means of a delay circuit. Then, a phase comparator for reproducing a bit timing converts outputs transmitted from the delay circuit and the second multiplier into a signal having a 25 phase including two phase-stable points.
Japanese Unex~min~?d Patent Publication No. 7-212419 has suggested an apparatus for extracting a clock for detecting a phase of preamble.
In this apparatus, a relative phase of a carrier wave of a 1r /4-shifted QPSK is input into a relative phase detector. The relative phase detector CA 022~6169 1998-12-1~
includes first and second counters each of which counts qign~l.q having a frequency equal to a M times multiplied sum of a frequency of a carrier wave of a 7r /4-shifted QPSK signal transmitted from an oscillator and a shifted frequency.
The relative phase detector includes an amplitude limiter. The amplitude limiter slides an amplitude of the carrier wave to thereby transmit a rectangular wave as a carrier wave. A rise-up detecting circuit detects rise-up of the carrier wave, and resets the first counter. Then, a circuit for subtraction subtracts an output transmitted from the first counter from an output transmitted from the second counter to thereby transmit a relative phase of the 10 carrier wave of the ~r /4-shifted QPSK signal.
Then, the subtraction circuit calculates a difference between the relative phase and a phase prior to the relative phase by a half symbol. When a phase difference detector detects that the thus calculated difference becomes equal to a predetermined value, a reference signal generator transmits a 15 reference signal.
On the other hand, a demodulator may be designed to include a limiter amplifier for suppressing fluctuation in an input level to be introduced to the demodulator. The limiter amplifier keeps an output level transmitted from the demodulator constant regardless of an input level. As a result, it is no longer 20 necessary to use a preamble for AGC, which ensures a shorter preamble.
However, the use of a limiter amplifier is accompanied with a problem that performances of the demodulator is much deteriorated due to non-linear strain which is caused by the limiter amplifier. Hence, the demodulator is necessary to be provided with a countermeasure against such non-linear strain All of the above-mentioned conventional apparatuses or circuits are not provided with a countermeasure to avoid influences due to non-linear strain and/or an error caused by noises, and hence, are accompanied with a problem of deterioration of performances due to non-linear strain.
CA 022~6169 1998-12-1~
SUMMARY OF THE INVENTION
In view of the above-mentioned problem, it is an object of the present invention to provide a circuit for reproducing a bit timing and a method of doing the same both of which are hardly influenced by noises and errors caused by non-linear strain, and are capable of fabricating a semiconductor device in a smaller size to thereby reduce power consumption.
In one aspect of the present invention, there is provided a circuit for reproducing bit timing, including (a) a first analog-digital converter for converting a real part signal of a complex modulation signal into a real part digital signal, 10 the complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase, (b) a second analog-digital converter for converting an im~gin~ry part signal of the complex modulation signal into an im~gin~ry part digital signal, (c) a first detector for receiving the real part digital signal and the im~gin~ry part digital signal, 15 detecting a phase angle of the complex modulation signal on a complex plane, and transmitting a first signal indicative of the phase angle, (d) a delay circuit for delaying the first signal by a symbol interval, (e) a second detector for detecting a difference in phase on the complex plane between the complex modulation ~ign~l~
in the symbol interval, (f) a third detector for detecting a timing gap between a 20 sampling clock and an optimum sampling point, based on the difference in phase, detected by the second detector, and transmitting a second signal indicative of the timing gap, and (g) a signal converter for converting each of the real part digital signal and the im~gin~ry part digital signal into a signal associated with the optimum sampling point, based on the second signal.
In accordance with the above-mentioned circuit, the first analog-digital converter converts a real part signal of a complex modulation signal, which has a base band frequency band and is obtained from a received modulation signal having been modulated into a digital phase, into a real part digital signal, and the second analog-digital converter converts an im~gin~ry part signal of the complex CA 022~6169 1998-12-1~
modulation signal into an imaginary part digital signal. The thus obtained real part digital signal and im~gin~ry part digital signal are input into the first detector.
The first detector having received the real part digital signal and the im~gin~ry part digital signal detects a phase angle of the complex modulation signal on a complex plane, and then, transmits the first signal indicative of the phase angle, to both the delay circuit and the second detector. The delay circuit delays the first signal by a symbol interval, and then, transmits the delayed first signal to the second detector. The second detector makes subtraction between lo the first signal and an output signal transmitted from the delay circuit to thereby detect a difference in phase on the complex plane between the complex modulation .qignz~l.q in the symbol interval. A signal indicative of the thus detected difference in phase is transmitted to the third detector.
The third detector detects a timing gap between a sampling clock and 15 an optimum sampling point, based on the difference in phase detected by the second detector, and transmits the second signal indicative of the timing gap tothe signal converter.
The signal converter converts each of the real part digital signal and the im~gin~ry part digital signal into a signal associated with the optimum 20 sampling point, based on the second signal.
The circuit in accordance with the invention is hardly influenced by noises and errors caused by non-linear strain, and makes it possible to fabricate a semiconductor device in a smaller size, reduce power consumption, and accomplish maintenance free.
It is preferable that the above-mentioned circuit further includes a clock oscillator transmitting fixed clock qign~lq, in which case, the first analog-digital converter samples and quantizes the real part signal with the fixed clock qign~lq to thereby convert the real part signal into the real part digital signal.
It is also preferable that the above-mentioned circuit further includes a CA 022~6169 1998-12-1~
clock oscillator transmitting fixed clock qign~l.q, in which case, the second analog-digital converter samples and quantizes the im~gin~ry part signal with the fixedclock .qignz31q to thereby convert the im~gin71ry part signal into the im~gin~ry part digital signal.
For instance, the second detector may be comprised of a subtracter for making subtraction between the first signal and an output signal transmitted from the delay circuit.
There is further provided a circuit for reproducing bit timing, including (a) a first analog-digital converter for converting a real part signal of a complex lo modulation signal into a real part digital signal, the complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase, (b) a second analog-digital converter forconverting an im~gin~ry part signal of the complex modulation signal into an im~gin~ry part digital signal, (c) a first detector for receiving the real part digital 15 signal and the im~gin~ry part digital signal, detecting a phase angle of the complex modulation signal on a complex plane, and transmitting a first signal indicative of the phase angle, (d) a delay circuit for delaying the first signal by a symbol interval, (e) a second detector for detecting a difference in phase on the complex plane between the complex modulation .qign~lq in the symbol interval, (f) 20 a third detector for detecting a timing gap between a sampling clock and an optimum sampling point, based on the difference in phase, detected by the seconddetector, and transmitting a second signal indicative of the timing gap, (g) a first interpolating filter for converting the real part digital signal into a signal associated with an optimum sampling point, based on the second signal, and (h) a25 second interpolating filter for converting the im~gin~ry part digital signal into a signal associated with an optimum sampling point, based on the second signal.
There is still further provided a circuit for reproducing bit timing, including (a) a first analog-digital converter for converting a real part signal of a complex modulation signal into a real part digital signal, the complex modulation CA 022~6169 1998-12-1~
signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase, (b) a second analog-digital converter for converting an im~gin~ry part signal of the complex modulation signal into an im~gin~ry part digital signal, (c) a first detector for receiving the 5 real part digital signal and the im~gin~ry part digital signal, detecting a phase angle of the complex modulation signal on a complex plane, and transmitting a first signal indicative of the phase angle, (d) a delay circuit for delaying the first signal by a symbol interval, (e) a second detector for detecting a difference inphase on the complex plane between the complex modulation ~ign~ in the 10 symbol interval, (f) a third detector for detecting a timing gap between a sampling clock and an optimum sampling point, based on the difference in phase, detected by the second detector, and transmitting a second signal indicative of the timing gap, (g) a clock oscillator for transmitting fixed clock .qign~l~, and (h) a progr~mm.qhle phase shifter for ~hifting a phase of the fixed clock .~ign~ , based 15 on the second signal.
In another aspect of the present invention, there is provided a method of reproducing bit timing, including the steps of (a) converting a real part signal of a complex modulation signal into a real part digital signal, the complex modulation signal having a base band frequency band and obtained from a 20 received modulation signal modulated into a digital phase, (b) converting an im~gin~ry part signal of the complex modulation signal into an im~gin~ry part digital signal, (c) detecting a phase angle of the complex modulation signal on a complex plane, based on the real part digital signal and the im?~gins~ry part digital signal, and transmitting a first signal indicative of the thus detected phase angle, 25 (d) delaying the first signal by a symbol interval, (e) detecting a difference in phase on the complex plane between the complex modulation ~ign~l.s in the symbol interval, (f) detecting a timing gap between a sampling clock and an optimum sampling point, based on the difference in phase, and (g) converting each of the real part digital signal and the im~gin~ry part digital signal into a signal . . . , _ , CA 022~6169 1998-12-1~
associated with the optimum sampling point, based on the timing gap.
It is preferable that the real part signal is sampled and quantized with fixed clock ~sign~l~ to thereby be converted into the real part digital signal in the step (a).
6 It is also preferable that the im~gin~ry part signal is sampled andquantized with fixed clock ~ign~l~ to thereby be converted into the im~gin~ry part digital signal in step (b).
For instance, the difference in phase may be detected by m~king subtraction between the complex modulation ~ign~ in the symbol interval in the step (e).
There is further provided a method of reproducing bit timing, including the steps of (a) converting a real part signal of a complex modulation signal into a real part digital signal, the complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase, (b) converting an im~gin~ry part signal of the complex modulationsignal into an im~gin~ry part digital signal, (c) detecting a phase angle of thecomplex modulation signal on a complex plane, based on the real part digital signal and the im~ginz~ry part digital signal, and transmitting a first signal indicative of the thus detected phase angle, (d) delaying the first signal by a symbol interval, (e) detecting a difference in phase on the complex plane between the complex modulation ~ign~l.q in the symbol interval, (f) detecting a timing gap between a sampling clock and an optimum sampling point, based on the difference in phase, and (g) shifting a phase of fixed clock sign~ , based on the timing gap.
In the specification, BPSK is an acronym of "Binary Phase Shift Keying", QPSK is an acronym of "Quadrature Phase Shift Keying", MSK is an acronym of "Minimum Shift Keying", and GMSK is an acronym of "Gaussian filtered Minimum Phase Shift Keying".
The above and other objects and advantageous features of the present invention will be made apparent from the following description made with .. , . , .. ~ . . ..
CA 022~6169 1998-12-1~
reference to the accompanying drawings, in which like reference characters designate the same or ~imil~r parts throughout the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a block diagram illustrating a circuit for reproducing bit timing, in accordance with the first embodiment of the present invention.
Fig. 2 is a block diagram of a demodulator including the circuit illustrated in Fig. 1.
Fig. 3 is a view illustrating signal phases in the circuit illustrated in Fig.
10 1.
Fig. 4 is a view illustrating a relation between a timing at which a modulation signal is sampled and a phase angle of a modulation signal in the circuit illustrated in Fig. 1.
Fig. 5 is a view illustrating interpolation of sampled data by means of 15 an interpolating filter in the circuit illustrated in Fig. 1.
Fig. 6 is a block diagram illustrating a circuit for reproducing bit timing, in accordance with the second embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Fig. 1 is a block diagram illustrating a circuit for reproducing bit timing, in accordance with the first embodiment. In order to make it easy to understand the circuit illustrated in Fig. 1, a demodulator including the circuit illustrated in Fig. 1 is first explained hereinbelow with reference to Fig. 2.
With reference to Fig. 2, a received modulation signal having been 25 modulated into a digital phase is input into a limiter amplifier 1 from a radio receiver 21. Even if the radio receiver 21 receives radio ~ign~l~ having been fluctuated in level in a tr~n.~mi~sion path, the limiter amplifier 1 smoothes the level fluctuation of the received radio ~ign~l~ when the received radio .~ign~l~ are input into the demodulator.
.. . . .
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The limiter amplifier 1 transmits its output to a band pass filter 2.
The band pass filter 2 removes an unnecessary wave caused by non-linear strain accompanied with an operation of smoothing the level fluctuation in the receivedmodulation signal, carried out by the limiter amplifier 1, and then, transmits the 5 received modulation signal into a distributor 3 constituting a part of a perpendicular quasi-synchronization detector 101.
The distributor 3 bifurcates the received modulation signal, and transmits the bifurcated .qign~l.s into each of first input ports of a first multiplier 4 and a second multiplier 5. The first multiplier 4 further receives at a second 10 input port thereof a local signal approximately identical with a carrier wave of a modulation signal transmitted from an oscillator 6.
The first multiplier 4 multiplies the local signal by the bifurcated modulation signal transmitted from the distributor 3, to thereby generate a realpart signal of a complex modulation signal having a base band frequency band.
15 The thus generated real part signal is transmitted into a first low pass filter 8.
The local signal is transmitted further to a 7r /2-phase shifter 7 from the oscillator 6. The 7r /2-phase shifted local signal is transmitted to a second input port of the second multiplier 5 from the ~r /2-phase shifter 7.
Then, the second multiplier 5 multiplies the 7r/2-phase shifted local 20 signal by the bifurcated modulation signal tr~n.~mitted from the distributor 3, to thereby generate an im~gin~ry part signal of a complex modulation signal having a base band frequency band. The thus generated im~gin~ry part signal is transmitted into a second low pass filter 9.
The first low pass filter 8 removes unnecessary high-frequency waves 25 out of the real part signal of the complex modulation signal, and then, transmits the real part signal to a first analog-digital (A/D) converter 10.
Similarly, the second low pass filter 9 removes unnecessary high-frequency waves out of the imaginary part signal of the complex modulation signal, and then, transmits the im~gin~ry part signal to a second analog-digital (A
CA 022~6169 1998-12-1~
/D) converter 11.
A clock oscillator 12 tr~n.~mits fixed clocks to the first and second analog-digital converters 10 and 11. The first analog-digital converter 10 samples and quantizes the received real part signal of the complex modulation 5 signal in response to the fixed clocks received from the oscillator 12, to thereby convert the real part signal into a real part digital signal. Similarly, the second analog-digital converter 11 samples and quantizes the received im~gin~ry part signal of the complex modulation signal in response to the fixed clocks receivedfrom the oscillator 12, to thereby convert the im~gin~ry part signal into an lo im~gin~ry part digital signal.
Both the real part digital signal transmitted from the first analog-digital converter 10 and the im~gin~ry part digital signal transmitted from the second analog-digital converter 11 are introduced into a circuit 102 for reproducing bit timing, in accordance with the first embodiment, and converted 5 into ~ign~l~ associated with optimal sampling points by the circuit 102.
The real part digital signal and the im~in~ry part digital signal having been converted into sign~l~ associated with optimal sampling points are input into a delay detecting circuit 13. The real part digital signal and the im~gin~ry part digital signal are delayed and detected in the delay detecting circuit 13, and 20 resultingly, the delay detecting circuit 13 outputs I-ch~nnel demodulation signal and Q-channel demodulation signal.
Hereinbelow is explained a structure of the circuit 102 for reproducing bit timing, with reference to Fig. 1.
Both the real part digital signal transmitted from the first analog-25 digital converter 10 and the im~gin~ry part digital signal transmitted from thesecond analog-digital converter 11 are introduced into a circuit 14 for detecting a phase of a modulation signal.
The real part digital signal transmitted from the first analog-digital converter 10 is introduced further into the delay detecting circuit 13 through a CA 022~6169 1998-12-1~
first interpolation circuit 18, and qimil~rly, the im~gin~ry part digital signaltransmitted from the second analog-digital converter 11 is introduced further into the delay detecting circuit 13 through a second interpolation circuit 19.
The circuit 14 for detecting a phase of a modulation signal receives the 5 real part digital signal and the im~gin~qry part digital signal to thereby detect a phase angle of the complex modulation signal on a complex plane, and transmits afirst signal Sa indicative of the thus detected phase angle to both a first input port of a subtracter 15 and an input port of a delay circuit 16.
The delay circuit 16 delays the first signal Sa received from the circuit lo 14, by a symbol interval Ts, and transmits the thus delayed signal to a second input port of the subtracter 15.
The subtracter 15 makes subtraction between the first signal Sa and the delayed signal to thereby detect a difference in phase on a complex plane among the modulation qign~lq in the symbol interval Ts.
The difference in phase detected by the subtracter 15 is transmitted into a circuit 17 for detecting a clock phase. The circuit 17 for detecting a clock phase detects a timing gap between a sampling clock and an optimal sampling point, based on the received difference in phase, and transmits the detection result, that is, a second signal Sb indicative of the thus detected timing gap to 20 both the first interpolation circuit 18 and the second interpolation circuit 19.
The first interpolation circuit 18 and the second interpolation circuit 19 cooperates with each other to thereby constitute a signal converter 200 which converts the real part digital signal transmitted from the first analog-digital converter 10, into a signal associated with an optimal sampling point, and 25 converts the im~gin~ry part digital signal tr~mqmitted from the second analog-digital converter 11, into a signal associated with an optimal sampling point, based on the second signal Sb indicative of the timing gap.
Outputs transmitted from the first and second interpolation circuits 18 and 19 are introduced into the delay detecting circuit 13.
CA 022~6169 1998-12-1~
The circuit 102 for reproducing bit timing has such a structure as mentioned so far.
Hereinbelow is explained an operation of the circuit for reproducing bit timing, in accordance with the first embodiment.
As mentioned earlier, the first low pass filter 8 removes unnecessary high-frequency waves out of the real part signal of the complex modulation signal, and transmits the real part signal to the first analog-digital converter 10. In the same way, the second low pass filter 9 removes unnecessary high-frequency waves out of the imzlgin~ry part signal of the complex modulation signal, and transmits 10 the im~gin~ry part signal to the second analog-digital converter 11.
The first analog-digital converter 10 receives fixed clocks from the clock oscillator 12, and samples the real part signal of the complex modulation signal in response to the fixed clocks, to thereby convert the real part signal to the real part digital signal. Similarly, the second analog-digital converter 11 receives fixed15 clocks from the clock oscillator 12, and samples the im~gin~ry part signal of the complex modulation signal in response to the fixed clocks, to thereby convert the im~gin~ry part signal to the im~gin~ry part digital signal.
The thus produced real part digital signal and im~gin~ry part digital signal are transmitted into the circuit 14 for detecting a phase of a modulation20 signal.
The circuit 14 for detecting a phase of a modulation signal receives the real part digital signal and the im~gin~ry part digital signal to thereby detect a phase angle of the complex modulation signal on a complex plane, and transmits the first signal Sa indicative of the thus detected phase angle to both a first input 25 port of the subtracter 15 and the delay circuit 16.
The delay circuit 16 produces a signal delayed by the symbol interval Ts from the second signal Sb, and transmits the thus produced, delayed signal to a second input port of the subtracter 15.
The subtracter 15 subtracts the first signal Sa received from the circuit CA 022~6169 1998-12-1~
14 from the delayed signal received from the delay circuit 16 to thereby detect a difference in phase of those .qi~n~lq on a complex plane in the symbol interval Ts.
Then, the subtracter 15 transmits a signal Sd indicative of the thus detected difference in phase to the circuit 17 for detecting a phase of clocks.
In accordance with the above-mentioned first embodiment, synchronization is established by means of a preamble arranged at a head of a burst signal and used for reproducing bit timing. Herein, it is assumed that a clock is sufficiently stable, and synchronization is kept established in a burst until the burst ends, even if a control through the use of clocks is ceased, after 10 synchronization has been once established by means of a preamble.
For instance, it is assumed that a preamble to be used in QPSK
modulation system has a pattern wherein two .qign~lq S1 and S2, bridged by an arrow Yl in Fig. 3, a signal phase diagram, is alternately repeated.
Assuming one of the .qi~n~lq Sl and S2 is considered as a standard, a 15 phase angle of a modulation signal would have a pattern comprised of repeated waveforms, as illustrated in Fig. 4.
It is assumed in Fig. 4 that a timing gap between a sampling clock and an optimal sampling point tl is represented by ~T, and a phase difference between modulation qign~lq in a symbol interval Ts is represented by ~ . Under 20 the assumption, a relation between the timing gap l~ T and the phase different 0 is represented as follows.
0 =90~ x (1--2x~T/Ts) .-. ~ T/Ts = (1/2--0 /180~
In accordance with the above-mentioned equation, it is possible to 25 detect the timing gap between a sampling clock and an optimal sampling point tl, represented by ~ T/Ts, can be calculated based on the phase difference ~ on a complex plane between the modulation .qi~n~lq in the symbol interval Ts.
The circuit 17 for detecting a clock phase detects a timing gap between a sampling clock between an optimal sampling point in the above-mentioned CA 022~6169 1998-12-1~
manner, averages the timing gap in a preamble, and transmits a second signal Sb indicative of the thus detected timing gap to the first and second interpolationfilters 18 and 19.
The first interpolation filter 18 receives the second signal Sb from the circuit 17, and converts the real part digital signal received from the first analog-digital converter 10, into a signal associated with an optimal sampling point, based on the second signal Sb indicative of the timing gap.
Similarly, the second interpolation filter 19 receives the second signal Sb from the circuit 17, and converts the im~gin~ry part digital signal received 10 from the second analog-digital converter 11, into a signal associated with anoptimal sampling point, based on the second signal Sb indicative of the timing gap.
For instance, when sample data Dl, D2, and D3 having an interval equal to Ts/2 among one another are input for converting the real or im~gin~ry 15 part digital signal into an optimal signal, as illustrated in Fig. 5, data SD is presumed by interpolation. Herein, data SD is data delayed by the timing gap T from the sample data D2.
The operation of the first and second interpolation filters 18 and 19 is described in "Burst Mode All-Digitized High-Speed Clock Reproducing Circuit", by20 Matsumoto, Morikura, and Kato, Electronic Data Communication Institute Articles, Vol. J75--B--II, June 1992, No. 6.
An interpolation filter requires data sampled at a speed at least twice greater than a symbol speed, whereas the circuit 17 for detecting a clock phase requires data sampled at a speed equal to a symbol speed.
The real part digital signal having been converted into the signal associated with an optimal sampling point by means of the first interpolation filter 18 is transmitted to the delay detecting circuit 13, and the im~gin~ry digital signal having been converted into the signal associated with an optimal samplingpoint by means of the second interpolation filter 19 is transmitted also to the .. . .
CA 022~6169 1998-12-1~
delay detecting circuit 13.
The delay detecting circuit 13 delays the thus received real and im~gin~ry part digital ~ign~l~, and transmits I-ch~nnel and Q-ch~3nnel demodulation sign~ as output ~ign~
The circuit 102 for reproducing bit timing, in accordance with the first embodiment, uses a preamble which does not pass an origin of a complex plane of a modulation signal, as illustrated in Fig. 3.
Thus, the circuit 102 detects a phase of a sampling clock without using sampling data located in the vicinity of the origin and having a small amplitude.
10 Accordingly, the circuit 102 is hardly influenced by noises and errors caused by non-linear strain.
In order to detect a clock phase, a sampling speed twice greater than a symbol speed has been conventionally required, but the circuit 102 for reproducing bit timing, in accordance with the first embodiment, can operate at a 15 symbol speed.
Accordingly, the circuit 102 in accordance with the first embodiment is resistant to non-linear strain, and is capable of reducing power consumption, fabricating a semiconductor device in a smaller size in the form of LSI, and accompli.ching maintenance free.
Fig. 6 is a block diagram illustrating a circuit for reproducing bit timing, in accordance with the second embodiment. Parts or elements that correspond to those of the first embodiment illustrated in Figs. 1 and 2 have been provided with the same reference numerals.
As would be obvious from comparison of Fig. 6 with Fig. 1, a circuit 103 25 for reproducing bit timing, in accordance with the second embodiment, is provided with a signal converter 201 having a different structure from a structure of thesignal converter 200 of the circuit 102 for reproducing bit timing, in accordance with the first embodiment.
That is, the signal converter 200 in the first embodiment is comprised of ... . .
CA 022~6169 1998-12-1~
the first interpolation filter 18 and the second interpolation filter 19, whereas the signal converter 201 in the second embodiment is comprised of a progr~mm~hle phase shifter 20.
In the circuit 103 in accordance with the second embodiment, the 5 second signal Sb indicative of the timing gap, transmitted from the circuit 17 for detecting a clock phase, is input into the progr~mm~hle phase shifter 20, which shifts a phase of fixed clocks transmitted from the clock oscillator 12, based on the second signal Sb. In the second embodiment, a phase of fixed clocks transmitted from the clock oscillator 12 is shifted unlike the first embodiment.
In accordance with clocks transmitted from the clock oscillator 12 and phase-shifted by the progr~mm~hle phase shifter 20, the first analog-digital converter 10 samples and quantizes a real part signal of a complex modulation signal to thereby convert the real part signal into a real part digital signal, which is transmitted to both the circuit 14 for detecting a phase of a modulation signal 15 and the delay detecting circuit 13.
Similarly, in accordance with clocks transmitted from the clock oscillator 12 and phase-shifted by the progr~mm~hle phase shifter 20, the secondanalog-digital converter 11 samples and quantizes an im~in~ry part signal of a complex modulation signal to thereby convert the im~gin~ry part signal into an 20 im~in~3ry part digital signal, which is transmitted to both the circuit 14 for detecting a phase of a modulation signal and the delay detecting circuit 13.
The other operation is the same as the operation carried out by the circuit 102 in accordance with the first embodiment.
The progr~mm~hle phase shifter 20 is described, for instance, in 25 "Development of Digitally Controlled Clock Oscillator for DDL", by Takakusaki, Electronic Data Communication Institute, Communication Society Conference, B-371, 1996.
All parts constituting the circuit 103 in accordance with the second embodiment, including the first and second analog-digital converters 10 and 11, CA 022~6169 1998-12-1~
operate at a symbol speed.
In addition, since the circuit 103 for reproducing bit timing, in accordance with the second embodiment, uses a preamble which does not pass an origin of a complex plane of a modulation signal, as illustrated in Fig. 3, the 5 circuit 103 can be applied to modulation system in which a modulation signal does not pass an origin of a complex plane, such as 7r/4--shifted QPSK, MSK, or GMSK.
While the present invention has been described in connection with certain preferred embodiments, it is to be understood that the subject matter 10 encompassed by way of the present invention is not to be limited to those specific embodiments. On the contrary, it is intended for the subject matter of the invention to include all alternatives, modifications and equivalents as can be included within the spirit and scope of the following claims.
The entire disclosure of Japanese Patent Application No. 9-363522 filed on December 16, 1997 including specification, claims, drawings and sllmmz~ry is incorporated herein by reference in its entirety.
Claims (20)
1. A circuit for reproducing bit timing, comprising:
(a) a first analog-digital converter for converting a real part signal of a complex modulation signal into a real part digital signal, said complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase;
(b) a second analog-digital converter for converting an imaginary part signal of said complex modulation signal into an imaginary part digital signal;
(c) a first detector for receiving said real part digital signal and said imaginary part digital signal, detecting a phase angle of said complex modulation signal on a complex plane, and transmitting a first signal indicative of said phase angle;
(d) a delay circuit for delaying said first signal by a symbol interval;
(e) a second detector for detecting a difference in phase on said complex plane between said complex modulation signals in said symbol interval;
(f) a third detector for detecting a timing gap between a sampling clock and an optimum sampling point, based on said difference in phase, detected by said second detector, and transmitting a second signal indicative of said timing gap;and (g) a signal converter for converting each of said real part digital signal and said imaginary part digital signal into a signal associated with said optimum sampling point, based on said second signal.
(a) a first analog-digital converter for converting a real part signal of a complex modulation signal into a real part digital signal, said complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase;
(b) a second analog-digital converter for converting an imaginary part signal of said complex modulation signal into an imaginary part digital signal;
(c) a first detector for receiving said real part digital signal and said imaginary part digital signal, detecting a phase angle of said complex modulation signal on a complex plane, and transmitting a first signal indicative of said phase angle;
(d) a delay circuit for delaying said first signal by a symbol interval;
(e) a second detector for detecting a difference in phase on said complex plane between said complex modulation signals in said symbol interval;
(f) a third detector for detecting a timing gap between a sampling clock and an optimum sampling point, based on said difference in phase, detected by said second detector, and transmitting a second signal indicative of said timing gap;and (g) a signal converter for converting each of said real part digital signal and said imaginary part digital signal into a signal associated with said optimum sampling point, based on said second signal.
2. The circuit as set forth in claim 1, further comprising a clock oscillator transmitting fixed clock signals, and wherein said first analog-digital converter samples and quantizes said real part signal with said fixed clock signals to thereby convert said real part signal into said real part digital signal.
3. The circuit as set forth in claim 1, further comprising a clock oscillator transmitting fixed clock signals, and wherein said second analog-digital converter samples and quantizes said imaginary part signal with said fixed clock signals to thereby convert said imaginary part signal into said imaginary part digital signal.
4. The circuit as set forth in claim 1, wherein said second detector is comprised of a subtracter for making subtraction between said first signal and an output signal transmitted from said delay circuit.
5. A circuit for reproducing bit timing, comprising:
(a) a first analog-digital converter for converting a real part signal of a complex modulation signal into a real part digital signal, said complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase;
(b) a second analog-digital converter for converting an imaginary part signal of said complex modulation signal into an imaginary part digital signal;
(c) a first detector for receiving said real part digital signal and said imaginary part digital signal, detecting a phase angle of said complex modulation signal on a complex plane, and transmitting a first signal indicative of said phase angle;
(d) a delay circuit for delaying said first signal by a symbol interval;
(e) a second detector for detecting a difference in phase on said complex plane between said complex modulation signals in said symbol interval;
(f) a third detector for detecting a timing gap between a sampling clock and an optimum sampling point, based on said difference in phase, detected by said second detector, and transmitting a second signal indicative of said timing gap;(g) a first interpolating filter for converting said real part digital signal into a signal associated with an optimum sampling point, based on said second signal;
and (h) a second interpolating filter for converting said imaginary part digital signal into a signal associated with an optimum sampling point, based on said second signal.
(a) a first analog-digital converter for converting a real part signal of a complex modulation signal into a real part digital signal, said complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase;
(b) a second analog-digital converter for converting an imaginary part signal of said complex modulation signal into an imaginary part digital signal;
(c) a first detector for receiving said real part digital signal and said imaginary part digital signal, detecting a phase angle of said complex modulation signal on a complex plane, and transmitting a first signal indicative of said phase angle;
(d) a delay circuit for delaying said first signal by a symbol interval;
(e) a second detector for detecting a difference in phase on said complex plane between said complex modulation signals in said symbol interval;
(f) a third detector for detecting a timing gap between a sampling clock and an optimum sampling point, based on said difference in phase, detected by said second detector, and transmitting a second signal indicative of said timing gap;(g) a first interpolating filter for converting said real part digital signal into a signal associated with an optimum sampling point, based on said second signal;
and (h) a second interpolating filter for converting said imaginary part digital signal into a signal associated with an optimum sampling point, based on said second signal.
6. The circuit as set forth in claim 5, further comprising a clock oscillator transmitting fixed clock signals, and wherein said first analog-digital converter samples and quantizes said real part signal with said fixed clock signals to thereby convert said real part signal into said real part digital signal.
7. The circuit as set forth in claim 5, further comprising a clock oscillator transmitting fixed clock signals, and wherein said second analog-digital converter samples and quantizes said imaginary part signal with said fixed clock signals to thereby convert said imaginary part signal into said imaginary part digital signal.
8. The circuit as set forth in claim 5, wherein said second detector is comprised of a subtracter for making subtraction between said first signal and an output signal transmitted from said delay circuit.
9. A circuit for reproducing bit timing, comprising:
(a) a first analog-digital converter for converting a real part signal of a complex modulation signal into a real part digital signal, said complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase;
(b) a second analog-digital converter for converting an imaginary part signal of said complex modulation signal into an imaginary part digital signal;
(c) a first detector for receiving said real part digital signal and said imaginary part digital signal, detecting a phase angle of said complex modulation signal on a complex plane, and transmitting a first signal indicative of said phase angle;
(d) a delay circuit for delaying said first signal by a symbol interval;
(e) a second detector for detecting a difference in phase on said complex plane between said complex modulation signals in said symbol interval;
(f) a third detector for detecting a timing gap between a sampling clock and an optimum sampling point, based on said difference in phase, detected by said second detector, and transmitting a second signal indicative of said timing gap; (g) a clock oscillator for transmitting fixed clock signals; and (h) a programmable phase shifter for shifting a phase of said fixed clock signals, based on said second signal.
(a) a first analog-digital converter for converting a real part signal of a complex modulation signal into a real part digital signal, said complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase;
(b) a second analog-digital converter for converting an imaginary part signal of said complex modulation signal into an imaginary part digital signal;
(c) a first detector for receiving said real part digital signal and said imaginary part digital signal, detecting a phase angle of said complex modulation signal on a complex plane, and transmitting a first signal indicative of said phase angle;
(d) a delay circuit for delaying said first signal by a symbol interval;
(e) a second detector for detecting a difference in phase on said complex plane between said complex modulation signals in said symbol interval;
(f) a third detector for detecting a timing gap between a sampling clock and an optimum sampling point, based on said difference in phase, detected by said second detector, and transmitting a second signal indicative of said timing gap; (g) a clock oscillator for transmitting fixed clock signals; and (h) a programmable phase shifter for shifting a phase of said fixed clock signals, based on said second signal.
10. The circuit as set forth in claim 9, wherein said first analog-digital converter samples and quantizes said real part signal with the phase-shifted clock signals to thereby convert said real part signal into said real part digital signal.
11. The circuit as set forth in claim 9, further comprising a clock oscillator transmitting fixed clock signals, and wherein said second analog-digital converter samples and quantizes said imaginary part signal with the phase-shifted clock signals to thereby convert said imaginary part signal into said imaginary part digital signal.
12. The circuit as set forth in claim 9, wherein said second detector is comprised of a subtracter for making subtraction between said first signal and an output signal transmitted from said delay circuit.
13. A method of reproducing bit timing, comprising the steps of:
(a) converting a real part signal of a complex modulation signal into a real part digital signal, said complex modulation signal having a base band frequencyband and obtained from a received modulation signal modulated into a digital phase;
(b) converting an imaginary part signal of said complex modulation signal into an imaginary part digital signal;
(c) detecting a phase angle of said complex modulation signal on a complex plane, based on said real part digital signal and said imaginary part digital signal, and transmitting a first signal indicative of the thus detected phase angle;
(d) delaying said first signal by a symbol interval;
(e) detecting a difference in phase on said complex plane between said complex modulation signals in said symbol interval;
(f) detecting a timing gap between a sampling clock and an optimum sampling point, based on said difference in phase; and (g) converting each of said real part digital signal and said imaginary part digital signal into a signal associated with said optimum sampling point, based on said timing gap.
(a) converting a real part signal of a complex modulation signal into a real part digital signal, said complex modulation signal having a base band frequencyband and obtained from a received modulation signal modulated into a digital phase;
(b) converting an imaginary part signal of said complex modulation signal into an imaginary part digital signal;
(c) detecting a phase angle of said complex modulation signal on a complex plane, based on said real part digital signal and said imaginary part digital signal, and transmitting a first signal indicative of the thus detected phase angle;
(d) delaying said first signal by a symbol interval;
(e) detecting a difference in phase on said complex plane between said complex modulation signals in said symbol interval;
(f) detecting a timing gap between a sampling clock and an optimum sampling point, based on said difference in phase; and (g) converting each of said real part digital signal and said imaginary part digital signal into a signal associated with said optimum sampling point, based on said timing gap.
14. The method as set forth in claim 13, wherein said real part signal is sampled and quantized with fixed clock signals to thereby be converted into saidreal part digital signal in said step (a).
15. The method as set forth in claim 13, wherein said imaginary part signal is sampled and quantized with fixed clock signals to thereby be converted into said imaginary part digital signal in step (b).
16. The method as set forth in claim 13, wherein said difference in phase is detected by making subtraction between said complex modulation signals in said symbol interval in said step (e).
17. A method of reproducing bit timing, comprising the steps of:
(a) converting a real part signal of a complex modulation signal into a real part digital signal, said complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase;
(b) converting an imaginary part signal of said complex modulation signal into an imaginary part digital signal;
(c) detecting a phase angle of said complex modulation signal on a complex plane, based on said real part digital signal and said imaginary part digital signal, and transmitting a first signal indicative of the thus detected phase angle;
(d) delaying said first signal by a symbol interval;
(e) detecting a difference in phase on said complex plane between said complex modulation signals in said symbol interval;
(f) detecting a timing gap between a sampling clock and an optimum sampling point, based on said difference in phase; and (g) shifting a phase of fixed clock signals, based on said timing gap.
(a) converting a real part signal of a complex modulation signal into a real part digital signal, said complex modulation signal having a base band frequency band and obtained from a received modulation signal modulated into a digital phase;
(b) converting an imaginary part signal of said complex modulation signal into an imaginary part digital signal;
(c) detecting a phase angle of said complex modulation signal on a complex plane, based on said real part digital signal and said imaginary part digital signal, and transmitting a first signal indicative of the thus detected phase angle;
(d) delaying said first signal by a symbol interval;
(e) detecting a difference in phase on said complex plane between said complex modulation signals in said symbol interval;
(f) detecting a timing gap between a sampling clock and an optimum sampling point, based on said difference in phase; and (g) shifting a phase of fixed clock signals, based on said timing gap.
18. The method as set forth in claim 17, wherein said real part signal is sampled and quantized with the phase-shifted clock signals to thereby be converted into said real part digital signal in said step (a).
19. The method as set forth in claim 17, wherein said imaginary part signal is sampled and quantized with the phase-shifted clock signals to thereby be converted into said imaginary part digital signal in step (b).
20. The method as set forth in claim 17, wherein said difference in phase is detected by making subtraction between said complex modulation signals in said symbol interval in said step (e).
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9-363522 | 1997-12-15 | ||
| JP36352297A JPH11177644A (en) | 1997-12-15 | 1997-12-15 | Bit timing reproducing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA2256169A1 true CA2256169A1 (en) | 1999-06-15 |
Family
ID=18479524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA002256169A Abandoned CA2256169A1 (en) | 1997-12-15 | 1998-12-15 | Circuit for reproducing bit timing and method of reproducing bit timing |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6377634B1 (en) |
| EP (1) | EP0924892A3 (en) |
| JP (1) | JPH11177644A (en) |
| AU (1) | AU9708098A (en) |
| CA (1) | CA2256169A1 (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19732894C2 (en) * | 1997-07-30 | 1999-11-11 | Siemens Ag | Methods and arrangements for quickly synchronizing two carrier signals |
| US6553087B1 (en) * | 2000-05-04 | 2003-04-22 | 2Wire, Inc. | Interpolating bandpass filter for packet-data receiver synchronization |
| JP4489922B2 (en) * | 2000-09-22 | 2010-06-23 | 株式会社日立国際電気 | Demodulation method |
| JP3419397B2 (en) * | 2001-01-18 | 2003-06-23 | 日本電気株式会社 | Clock synchronization circuit and clock synchronization method |
| US20050201490A1 (en) * | 2004-02-20 | 2005-09-15 | Tobias Scholand | Zero-crossing detector for receivers |
| FR2877787A1 (en) * | 2004-11-09 | 2006-05-12 | St Microelectronics Sa | CADENCE CORRECTION LOOP ERROR ESTIMATING DEVICE FOR DIGITAL DEMODULATOR |
| US20060274874A1 (en) * | 2005-06-01 | 2006-12-07 | Arvind Kumar | Clock and data timing compensation for receiver |
| JP4717557B2 (en) * | 2005-08-30 | 2011-07-06 | 三菱電機株式会社 | Communication system and transmitter / receiver |
| US7831004B2 (en) * | 2006-06-13 | 2010-11-09 | Panasonic Corporation | Synchronous detecting circuit |
| JP2009010754A (en) * | 2007-06-28 | 2009-01-15 | Naoki Suehiro | Parallel sampling apparatus, parallel sampling method, receiving apparatus, and receiving method |
| US20100111229A1 (en) * | 2008-08-08 | 2010-05-06 | Assaf Kasher | Method and apparatus of generating packet preamble |
| GB2520650B (en) | 2009-07-23 | 2015-11-04 | Coreoptics Inc | Clock recovery for optical transmission systems |
| KR101423111B1 (en) * | 2010-08-10 | 2014-07-30 | 창원대학교 산학협력단 | Band pass sampling receiver |
| EP2615769B1 (en) * | 2011-12-15 | 2018-04-18 | Cisco Technology, Inc. | Clock recovery through digital techniques in a coherent receiver |
| EP2940916B1 (en) * | 2014-05-02 | 2017-03-22 | Nxp B.V. | A symbol clock recovery circuit |
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| CA1288878C (en) * | 1988-08-15 | 1991-09-10 | John D. Mcnicol | Timing and carrier recovery in tdma without preamable sequence |
| US4941155A (en) | 1989-11-16 | 1990-07-10 | Bell Communications Research, Inc. | Method and circuitry for symbol timing and frequency offset estimation in time division multiple access radio systems |
| JP2841985B2 (en) | 1991-12-25 | 1998-12-24 | 日本電気株式会社 | Bit synchronization system and burst demodulator |
| CA2090367C (en) * | 1992-02-27 | 1997-09-30 | Toshifumi Sato | Data demodulator |
| JPH05260107A (en) | 1992-03-13 | 1993-10-08 | Fujitsu Ltd | Orthogonal detector |
| JPH0614070A (en) | 1992-06-26 | 1994-01-21 | Sanyo Electric Co Ltd | Digital demodulator |
| JP3003826B2 (en) * | 1992-12-11 | 2000-01-31 | 三菱電機株式会社 | Clock recovery circuit |
| US5590158A (en) * | 1993-01-28 | 1996-12-31 | Advantest Corporation | Method and apparatus for estimating PSK modulated signals |
| JPH06284159A (en) | 1993-03-29 | 1994-10-07 | Toshiba Corp | Digital demodulator |
| JP2797916B2 (en) * | 1993-08-05 | 1998-09-17 | 日本電気株式会社 | Carrier recovery circuit |
| JPH07212419A (en) | 1994-01-13 | 1995-08-11 | Pioneer Electron Corp | Clock extraction device |
| JP3377858B2 (en) | 1994-04-07 | 2003-02-17 | 富士通株式会社 | Clock recovery circuit and demodulator using the same |
| JPH0879323A (en) | 1994-08-31 | 1996-03-22 | Nippon Telegr & Teleph Corp <Ntt> | Clock phase detection circuit |
| JPH08149173A (en) | 1994-11-16 | 1996-06-07 | Kokusai Electric Co Ltd | Absolute phase detection circuit |
| US5588025A (en) * | 1995-03-15 | 1996-12-24 | David Sarnoff Research Center, Inc. | Single oscillator compressed digital information receiver |
| US5671257A (en) * | 1995-06-06 | 1997-09-23 | Sicom, Inc. | Symbol timing recovery based on complex sample magnitude |
| JP3350290B2 (en) | 1995-06-15 | 2002-11-25 | 株式会社日立製作所 | Receiver |
| FR2736231A1 (en) | 1995-06-28 | 1997-01-03 | Trt Telecom Radio Electr | DIGITAL COMMUNICATION SYSTEM COMPRISING A RECEIVER HAVING A RHYTHM RECOVERY DEVICE |
| JPH0926649A (en) | 1995-07-13 | 1997-01-28 | Fuji Photo Film Co Ltd | Film unit with lens and photographic data management system |
| JP3130773B2 (en) * | 1995-10-16 | 2001-01-31 | 日本電気株式会社 | Demodulator for wireless data communication |
| US5654989A (en) * | 1995-11-03 | 1997-08-05 | Motorola, Inc. | Method and apparatus for symbol timing tracking |
| KR0178750B1 (en) * | 1996-02-13 | 1999-05-15 | 김광호 | Full digital symbol timing recovery apparatus |
| GB2331210A (en) * | 1997-09-12 | 1999-05-12 | Daewoo Electronics Co Ltd | Timing recovery in vestigial sideband modulation |
-
1997
- 1997-12-15 JP JP36352297A patent/JPH11177644A/en active Pending
-
1998
- 1998-12-14 AU AU97080/98A patent/AU9708098A/en not_active Abandoned
- 1998-12-14 EP EP98310248A patent/EP0924892A3/en not_active Withdrawn
- 1998-12-15 CA CA002256169A patent/CA2256169A1/en not_active Abandoned
- 1998-12-15 US US09/210,932 patent/US6377634B1/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US6377634B1 (en) | 2002-04-23 |
| EP0924892A2 (en) | 1999-06-23 |
| EP0924892A3 (en) | 2003-12-10 |
| AU9708098A (en) | 1999-07-01 |
| JPH11177644A (en) | 1999-07-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EEER | Examination request | ||
| FZDE | Discontinued |