CA2265794A1 - Address allocation method for records of values representing various parameters - Google Patents

Abstract

Disclosed is an address allocation method for records of values representing various parameters whereby data related to the respective records of values can be stored. The described method is characterized by the fact that all of the allocated addresses are formed by chaining the address components representing the individual values of each record of values, whereby the magnitude of each address component and/or the order of each address component in the chain is individually variable depending on the configuration parameters influencing the parameter value ranges.

Description

CA 02265794 l999-03- 16GR 96 P 2101SpecificationMETHOD BY WHICH SETS OF VALUES REPRESENTING VARIOUS PARAMETERSCAN BE ALLOCATED TO ADDRESSESThe present invention relates to a method as genericallydefined by the preamble to claim 1, that is, a method by whichsets of values representing various parameters can beallocated to addresses, at which addresses data pertaining tothe various value sets can be stored in memory.One such method can be employed in the switching method knownas ATM, among others, a method that is used in so-calledbroadband ISDN or B—ISDN, for instance.The Consultative Committee for International Telephony andTelegraphy (CCITT) already called on the switching methodknown as Asynchronous Transfer Mode (ATM) in May 1990 as astandard for so-called data packet switching in B—ISDN. Itdefines ATM as follows: “A switching method in which theinformation is bunched in cells; the method is asynchronous inthe sense that the cells need not necessarily be exchangedperiodically between the transmitter and the receiver”.One possible embodiment for performing the ATM method is shownin Fig. 4.The system shown there includes a switching station 1, whichoutputs data packets (ATM cells) received over first lines 21-24 correspondingly to the respective destination site oversecond lines 41-44, and vice versa.CA 02265794 l999-03- 16The lines 21-24 are glass fiber cables terminated bytermination units 31-34. The termination units 31-34 are thepractical embodiment of so-called PHYS (physical ports).The lines 41-44, which are also embodied as glass fibercables, are terminated by termination units 51-54. Like thetermination units 31-34, the termination units 51-54 are thepractical embodiment of so-called phys (physical ports).The switching station 1 includes a first ATM unit 11 (shown onthe left in Fig. 4), a second ATM unit 13 (shown on the rightin Fig. 4), and a coupling network 12 disposed between them.The termination units 31-34 are connected to the first ATMunit 11, and the termination units 51-54 are connected to thesecond ATM unit 13.The ATM cells arriving in the switching station 1, or moreprecisely in the ATM units thereof, have a cell header inwhich, among other information, the destination site or thereceiver of the particular ATM cell is defined in a 28-bitaddress field.The 28-bit address has two components, namely a 16-bit VCIpart and a 12-bit VPI part. VCI stands for Virtual ChannelIdentifier and designates the connection end point to whichthe useful data contained in the applicable ATM cell are to beswitched. VPI stands for Virtual Path Identifier anddesignates a subscriber system that includes many connectionend points, to which system the useful data contained in theapplicable ATM cell are to be switched.The ATM units 11 and 13 include a connection statusinformation memory (not shown in Fig. 4), in which for eachCA 02265794 l999-03- 16connection, or more precisely for each VPC (Virtual PathConnection) and for each VCC (Virtual Channel Connection),which is made via the switching station 1, certain data(connection status information) are stored. The data to bestored include approximately 200 bytes per connection, andthus are relatively extensive.The 28 bits in the header region of each ATM cell reserved forspecifying the receiver of a given ATM cell make it possibleto establish 2” different connections. If a memory regionlarge enough to enable storing the aforementioned connectionstatus information in it were to be reserved for each of theconnections in this enormous number of possible connections,this would require the provision of a memory with a hugestorage capacity.A memory with such a large storage capacity is practicallyfeasible only at the greatest possible technological effortand expense, since in practice only an extremely smallfraction of the theoretically possible number of connectionsis or can be made at the same time and each is used for onlyan extraordinarily small fraction of the time.It is therefore preferable to use a memory whose storagecapacity is oriented “only” to the maximum number ofconnections that can be made simultaneously. In that case,however, the memory can no longer be addressed directlythrough the 28-bit address in the header region of the ATMcells. Instead, it requires address conversion or a specialaddress allocation. More precisely, it requires the use of amethod by which sets of values representing various parameterscan be assigned to addresses at which data pertaining to thevarious value sets can be stored; the various parameters inthe example here are VPI, VCI, and possibly also PN (PhysicalCA 02265794 l999-03- 16Port Number) and which is the number of termination unit orline over which the applicable ATM cell was received. Theaddress to be assigned to the various value sets willhereinafter be called the LCI (for Logical ChannelIdentifier).In performing such allocations, it is known to make use of an(auxiliary) memory which is preoccupied with values in such away that the address (LCI) to be allocated to a given valueset (VPI, VCI, PN) is either— the address of that memory region whose contents correspondto the value set, or- the contents of the memory region that can be addressedusing the value set as an address.The first of these cases is practically feasible by using aso- called cam (for content addressable memory) as the(auxiliary) memory. In cams, a comparator is provided foreach memory region, and by this comparator data (value sets)applied to the memory can each be compared with the contentsstored in the applicable memory region. This comparison isperformed simultaneously for all the memory regions by thecomparators assigned to the various memory regions and istherefore done very quickly. As a result, the address of therow in which the data corresponding to the value set arestored is obtained; this row address is at the same time theaddress LCI to be assigned to the value set. It can beappreciated that this kind of practical embodiment of theaddress allocation is relatively complicated, because of thelarge number of comparators that must be provided and operatedsimultaneously.CA 02265794 l999-03- 16The second case above can be embodied by a “normal”(auxiliary) memory, which is preferably subdividedhierarchically into a plurality of memory units. Such asystem is shown in Fig. 5. It includes a first memory unit14, a second memory unit 15, and a. third memory unit 16. Thefirst memory unit 14 is addressed by the physical port numberPN; the second memory unit 15 is addressed on the basis of thevirtual path identifier VPI, or more precisely by a baseaddress PVH + VPI obtained from the first memory unit 14, andthe third memory unit 15 is addressed on the basis of thevirtual channel identifier VCI, or more precisely by a baseaddress PWH + VCI obtained from the second memory unit 15.The data stored at the various addresses of the individualmemory units are either directly the addresses (LCI) to beallocated to the applicable Value sets, or are pointers P,which point to the beginning of an assigned memory region ofthe respectively lower—ranking memory unit. For among otherreasons because of the fact that the LCI values to beascertained and allocated in real time are obtained by anintrinsically slow, multistage method, this kind of practicalrealization of address allocation again proves to berelatively complex.This kind of multistage mention for ascertaining an addresswith a reduced number of bits is known from US Patent5,481,687.It is also known from US Patent 5,557,609 to extract an ATMcell from the 28-bit address in the header region by shiftingthe VPI and VCI parts bit by bit. By subsequently shorteningthe VPI and VCI values, an address with a reduced number ofbits is generated for addressing a memory that containsconversion data.Amended page 5aCA 02265794 l999-03- 16The above-described methods, however, require not only complexhardware, that is, high-speed and/or extensive hardware, butalso — for instance when the system configuration is expandedand/or changed - because of the (auxiliary) memory expansionor expansions then required and/or the change in memorycontents then required, can be adapted to the alteredconditions only at relatively major effort and expense.It is therefore the object of the present invention to refinethe method defined by the preamble to claim 1 in such a wayAmended page SbCA 02265794 l999-03- 16that the address allocation sought is always feasible in asimple way and at minimal effort and expense.According to the invention, this object is attained by thecharacteristics claimed in the body of claim l.It is accordingly provided that the allocated addresses areeach formed by a concatenation of address componentsrepresenting the individual values of a given set of values,and the scope of the various address components and/or theorder of the various address components in their concatenationcan be varied individually as a function of configurationparameters that have an influence on the ranges of values ofthe parameters.The address to be allocated to a given set of values isaccordingly no longer, as was the case previously obtained byusing an association table realizable by means of an(auxiliary) memory or the like, but instead by means of aconcatenation of address components representing the values ofthe applicable value set in a way adapted to given conditions.The few circumstances (configuration parameters) on which thegeneration of the address to be allocated depends, and the fewand slight effects thereof on address forming (change in thelength and order of the concatenated address components) areadvantageous in two respects: First, the hardware to befurnished for performing the method can be of low complexityand structured simply, and on the other for adaptation of themethod to changed circumstances, all that is required is tomodify a few parameters representing the applicablecircumstances.CA 02265794 l999-03- 16Accordingly, a method has been discovered through which thesought address allocation can always be realized simply and atminimal expense.Advantageous refinements are the subject of the dependentclaims.The invention is described below in further detail in terms ofan exemplary embodiment with reference to the drawing.Shown are:Fig. 1, an illustration of the forming of an address to beallocated to a set of values;Fig. 2, an illustration of the forming of an address to beallocated to another set of values;Fig. 3, an apparatus for performing the method of theinvention;Fig. 4, a system in which both conventional address allocationmethods and the address allocation method of the invention canbe employed; andFig. 5, an illustration to explain a conventional addressallocation method.The exemplary embodiment on the basis of which the method ofthe invention will be described in detail below relates to theaddress conversion to be performed in an ATM switchingstation, or more precisely the method by which addresses canbe assigned to values representing sets of various parameters(VPI, VCI, PN), at which addresses data (connection statusCA 02265794 l999-03- 16information) pertaining to the various value sets can bestored.However, the method of the invention can be used not only inATM switching technology but also quite generally anywherethat arbitrary sets of values representing arbitraryparameters are to be assigned addresses at which datapertaining to the various value sets can be stored. The useof the method of the invention proves to be especiallyadvantageous in cases where the capacity of a memory intendedfor data storage is not sufficient to be addressed directlyvia the set of values.The basic outlines of the ATM switching method have alreadybeen described extensively at the outset above with referenceto Fig. 4. The basic layout of the system shown in Fig. 4 isunchanged by the use of the method of the invention; thecomments in this respect already made are therefore fullyvalid below unless expressly stated otherwise.The first ATM unit 11 of the switching station 1 receives datapackets in the form of ATM cells over the lines 21-24 and thetermination units 31-34; these data packets are to be switchedto the lines 41-44 via the coupling network 12, the second ATMunit 13, and the termination units 51-54. Conversely, thesecond ATM unit 13 of the switching station 1, over the lines41-44 and the termination units 51-54, receive data packets inthe form of ATM cells that are to be switched to the lines 21-24 via the coupling network 12, the first ATM unit 11, and thetermination units 31-34.The intended destination of the various ATM cells is definedin their header, in the form of a 28-bit address. By means ofthis 28-bit address, 22*’ destination sites can be defined.CA 02265794 l999-03- 16However, the number of possible destination sites is not alsoequal to the number of connections that can be made(maintained) via a switching station and for whichcorresponding connection status information is to be stored.The maximum number of connections that can be made at the sametime is assumed to be 16 K, in the example shown in Fig. 4.This value is drawn from an officially announcedrecommendation, which says that over a line by which a dataquantity of 150 MBits/s can be transmitted, as in the case ofthe glass fiber cables 21-24 and 41-44 shown in Fig. 4, nomore than 4 K connections are to be made; it does not matterwhether the connections are the VPCS (virtual pathconnections) already mentioned, or the VCCS (Virtual ChannelConnections), also already mentioned above.Clearly, the memory that must be furnished for storingconnection status information for 16 K connections cannot beaddressed directly via the 28-bit address in the header of theATM cells. This is especially true for the case where theaddress at which the data pertaining to a particularconnection are to be stored is supposed to be madeadditionally dependent on which of the lines or terminationunits have been used for receiving the ATM cell to beswitched.The address that is generated for addressing the connectionstatus information memory is the LCI (Logical ChannelIdentifier) value already mentioned at the outset. If it isto be able to represent 16 K different addresses, the LCIvalue must include 14 bits.In the present example, the LCI value, used as a reducedaddress, includes precisely the aforementioned 14 bits; itsCA 02265794 l999-03- 16contents depend on the (l2—bit) VPI value, the (16-bit) VCIvalue, and the (in this case) six—bit PN value. For the sakeof completeness, it should be pointed out again here that theVPI (Virtual Path Identifier) value and the VCI (VirtualChannel Identifier) value jointly form the 28-bit address inthe header of the ATM cells, and that the pn (Physical PortNumber) value represents the number of the line or terminationunit from which the applicable ATM cell has been received.The aforementioned LCI Value is obtained from a concatenationof the address components, of which the first addresscomponent is based on the PN value, the second addresscomponent is based on the VCI value, and the third addresscomponent is based on the VPI value.The size and order of the arrangement of the addresscomponents encompassing a total of l4 bits depends, amongother factors, on whether the VPI value of the applicable ATMcell is less than a value of 2V, or not. 2V is the number ofthe first VPC (Virtual Path Connection) in the switchingstation, among the VPCs numbered sequentially from zero upwardby the VPIs, that is not resolved, or in other words that isswitched onward as is. V is a first configuration parameter,which is obtained from the (user-settable) configuration ofthe system and which must be known in order to perform theaddress allocation described.For the sake of better comprehension, it is important to knowwhich kinds of connections there are, and how they are to behandled by the switching station. The connections that can bemade by an ATM switching station can be grouped, as alreadyindicated several times above, in two classes, namely VCCs(Virtual Channel Connections) and VPCs (Virtual PathConnections). The VCCs are single connections made_lO...CA 02265794 l999-03- 16individually to quite specific subscriber terminals at thetime; the VPCs are collective connections (for instance,between switching stations or to subscriber systems thatinclude a plurality of subscriber terminals), in each of whichan entire bunch of VCCS that can be manipulated uniformly canbe combined. To enable the VCCs combined in them to beswitched onward individually (to take separate paths), VPCscan be resolved in a switching station; as a result, from oneVPC, many VCCs can be created. However, VPCs can also beswitched onward as is, in other words without being resolved.By suitable system configuration before the system is put intooperation, it is defined how many of the theoreticallypossible 2” VPCs in the applicable switching station are to beresolved, and which individual VPCs these will be. The VPCSare assigned numbers by the VPIS, and VPIs from O to 2V—l areassigned to those VPCs that are to be resolved in theapplicable switching station, while the VPCs that are notresolved in the switching station are identified by thenumbers that are greater than 2V—l.In other words, the way in which the applicable LCI value isgenerated depends, among other factors, on whether theapplicable VPC is resolved in the switching station or isretained as is. This can be ascertained, as already mentionedabove, by checking whethera) VPI < 2V orb) VPI 2V.The procedure for case a) above, that is, the case in whichthe applicable VPC is resolved in the switching station, isshown in Fig. 1. Fig. 1 schematically shows a VPI value-11..CA 02265794 l999-03- 16including 12 bits (bits 0 through 11), a VCI value including16 bits (bits 0 through 15), and a PN value including 6 bits(bits 0 through 5), as well as an LCI value including 14 bits(bits 0 through 13).portions of the VPI value, the VCI value, and the PN value:The LCI value is composed as follows of1) The low-order P bits of the LCI Value are the lowest—orderP bits of the PN value.2) The highest—order 14—M bits of the LCI value are thelowest— order 14—M bits of the VPI value.3) The intervening M-P bits of the LCI value are the lowest-order M—P bits of the VCI value.The aforementioned value P is a second configurationparameter, which represents the number of lines or terminationunits (PHYS) with which the applicable ATM unit is connected.In the example in question, 2? is equal to the number of linesor termination units connected to the applicable ATM unit.The value to be defined for P is obtained from the (user-determinable) configuration of the system and in the examplein question must be known in order to perform the addressallocation described.Shortening the originally six—bit PN value to P bits (in theexamples shown in Figs. 1 and 2, P = 3) does not mean any lossof information, since the (highest—order) bits of the pn valuethat are left out in the LCI value were already equal to zero,as can be seen from the applicable configuration.The aforementioned value M is a third configuration parameter,which represents the number of blocks into which connectionstatus information memory to be addressed by the LCI value is_l2_CA 02265794 l999-03- 16subdivided. In the example in question, 2” is equal to thenumber of these blocks of the connection status informationmemory. The number of blocks into which the connection statusinformation memory is to be divided is obtained from thenumber of VPCS that are not to be resolved in the switchingstation but instead are to be switched onward as is. All theitems of connection status information pertaining to theseVPCs (and only these items of information) must be given spacein the topmost of the blocks of the connection statusinformation memory, for reasons that will be addressed infurther detail below. The value to be defined for M isobtained from the (user- determinable) configuration of thesystem and in this example must be known, if the method of theinvention is to be performed.Shortening the originally 12-bit VPI value to 14—M bits (14-M,in the examples shown in Figs. 1 and 2 equals 4) does not meanany information loss, because the (highest—order) bits of theVPI value left out in the LCI value were already always equalto zero in the applicable configuration.Shortening the originally 16-bit VCI value to M—P bits1 and 2,(in thealso means nobits of theexamples shown in Figs. M—P equals 7)loss of information, because the (highest—order)VCI value left out in the LCI value were already always equalto zero in the applicable configuration.The fact that no loss of information can ensue fromconcatenating the address components representing the VPI, VCIand PN values can also be seen from the fact that the 14 bitsof the LCI values, composed as described, suffice precisely toenable representing the maximum required 16 K addresses forstoring the connection status information._l3_CA 02265794 l999-03- 16The composition of the PCT values in case b), that is, wherethe applicable VPC is not resolved in the switching station,similarly to Fig. 1,schematically shows a VPI value including 12 bitsa pn value including six bits (0 through 5),(bits 0- 13).is shown in Fig. 2. Fig. 2,and an LCI valueincluding 14 bits The LCI is composed of partsof the VPI value, VCI value, and PN value, as follows:1) The lower—order P bits of the LCI value are the lowest-order P bits of the PN value.2) The highest-order 14—M bits of the LCI value are occupiedby ones.3) The intervening M—P bits of the LCI value are the lowest-order M—P bits of the VPI value.P and M are the(second and third) configuration parametersalready defined at length above.The LCI values generated for cases a) and b) differ in termsof the highest-order 14-M bits and the M-P bits below them.The highest-order 14—M bits are used to select one of theblocks into which the connection status information memory isdivided.In case b), which pertains to the VPCS that are not resolvedin the switching station, the block address is set fixedly at1 ... 1, that is, the maximum possible value. As a result,the topmost block of the blocks of the connection statusinformation memory is addressed. This is also desired,because the connection status information pertaining to theVPCS that are not to be resolved is to be stored, as alreadymentioned above, precisely there and only there. Since only_l4_(bits O-ll),CA 02265794 l999-03- 16those items of connection status information that pertain toVPCs not to be resolved in the switching station are to bestored in the topmost block of the blocks of the connectionstatus information memory, they can be addressed only via theVPI values stored in the middle portion of the LCI value; VCIvalues are needed because of the lack of resolution of theVPCs, and so logically they continue not to be taken intoaccount in case b).In case a), which pertains to the VPCs that are to be resolvedin the switching station, the block address represented by thehighest-oriented 14-M bits is equal to the applicable VPIvalue that in case a) can never represent the topmost block ofthe blocks of the connection status information memory. Thisis also desired, because the connection status informationpertaining to the VPCS to be resolved is meant to be depositedin the lower blocks, or more specifically in all the blocksexcept for the topmost block. Because only those items ofconnection status information that pertain to VPCs to beresolved in the switching station are to be stored in all theblocks except the topmost block of the connection statusinformation memory, they are meant to be addressedadditionally via the VCI values stored in the middle portionof the LCI value; the address component representing the VCIvalue, because of the many VCCs that can be combined in oneVPC, is the largest of the address components from which theLCI value is composed. As already mentioned above, the(highest—order) bits of the VPI, VCI and PN values that havebeen left out in the formation of the LCI value contain onlyzeroes in each case, so that no information loss ensues. Toassure that this is indeed the case, it may be provided thatthis be checked in each case. If in such a check it is foundthat one or more of the bits that are to be left out in theindividual values are not equal to zero, then this is an-15-CA 02265794 l999-03- 16indication of an error, which requires special handling. Thespecial handling may for instance be that the affected ATMcell is not switched. This makes it possible at least toprevent to already existing connections from being impeded.In conclusion, with reference to Fig. 3, an apparatus forperforming the method of the invention will be explained.The method described above is performed in an addressallocation unit 100 shown in Fig. 3. The set of values towhich the LCI value to be generated is to be allocated, and aseries of configuration parameters, are input as input signalsinto this address allocation unit 100.The aforementioned set of values includes the 12-bit VPI value(from the header of the ATM cell), the 16-bit VCI value (alsofrom the header of the ATM cell), and the 6-bit pn value.The aforementioned configuration parameters include the first,second and third configuration parameters already explainedabove, more precisely a four-bit V value, a three—bit P value,and a four-bit M value.An address at which data (connection status information)pertaining to the value set can be stored in a connectionstatus information memory is allocated to the set of VPI, VCIand PN values, taking the configuration parameters intoaccount. The way in which this address is formed is done hasbeen described above at length with reference to Figs. 1 and2.This address is output from the address allocation unit 100 inthe form of a 14-bit LCI Value.-16..CA 02265794 l999-03- 16The configuration parameters V, P and M input into the addressallocation unit 100 are “only” representatives of the actualconfiguration parameters 2V, 2? and 2M. Inputting theconfiguration parameters in the form of exponents to the base2 makes it possible on the one hand to keep the number ofterminals provided for inputting the configuration parametersinto the address allocation unit low, and on the other toenable further processing of the thus—input values directly,that is, without additional preprocessing. Nevertheless,naturally it is also possible to provide that theconfiguration parameters are input in full, rather than in theform of exponents as proposed. Nor is there any restrictionregarding inputting the configuration parameters in the form.of exponents to the base 2; the base value may be anyarbitrary other value instead.Nor is there any restriction that the individual configurationparameters represent precisely those variables indicated inthe above description. Alternatives that at least in part aremore or less equivalent are conceivable. For instance, thefirst configuration parameter V can represent the size,instead of the number, of the applicable blocks of theconnection status information memory.In summary, it can be stated that with the method of theinvention, a method has been discovered by which the addressallocation sought can always be achieved simply and at minimaleffort and expense._]_'7_

Claims (8)

New claim 1

1. A method by which sets of values (14-M bits, M-P bits, P
(VPI, VCI, PN) that each represent various parameters can be allocated to addresses (LCI), at which addresses data pertaining to the various value sets (VPI, VCI, PN) can be stored in memory, characterized in that the allocated addresses (LCI) are each formed of address components (14-M bits, M-P bits, P bits) that are formed by concatenation of individual values (14-M bits, M-P bits, P
bits) of a value set (VPI, VCI, PN), and the scope of the various address components and/or the order of the various address components in their concatenation can be varied individually as a function of configuration parameters that have an influence on the ranges of values of the parameters.

Claims:

2. The method of claim 1, characterized in that the method can be used in an ATM unit of a B-ISDN system, to enable addressing a connection status information memory.

3. The method of claim 2, characterized in that the values of the value set include a VPI value, a VCI value, and a PN value; the VPI value and the VCI value designate the intended location of an ATM cell, and the PN value designates its site of origin.

4. The method of claim 2 or 3, characterized in that a first one of the configuration parameters is selected in accordance with the capability of determining from it whether a VPC in the applicable switching station should or should not be resolved.

5. The method of one of claims 2-4, characterized in that a second one of the configuration parameters is selected in accordance with the capability of determining from it the maximum range of values of the pn value.

6. The method of one of claims 2-5, characterized in that a second one of the configuration parameters is selected in accordance with the capability of determining from it the maximum range of values of the VPI value.

7. The method of one of the foregoing claims, characterized in that the configuration parameters are furnished in the form of exponents to a predetermined base.

8. The method of one of claims 2-7, characterized in that the address components correspond to the values of a given set, but elements of no significance for address forming are cancelled without replacement and/or are replaced by others.